1261171 / 玖、發明說明： 【發明所屬之技術領域】 本發明係有關於快速周邊元件互連(Peripheral component Interconnect Express，簡稱PCI Express，或簡稱快速Ρα)介面卡，特別 有關於快速PCI介面卡上PCI周邊裝置控制器之超頻方法及其相關裝 置。 ’ 【先前技術】 個人電腦之周邊裝置所使用之標準匯流排，由早期之ISA介面、 EISA介面、PCI33介面、不斷演進到PCI66介面以及PCI133介面，尤 其是PCI系列之標準介面更是近幾年以來最為盛行之周邊裝置之標準 連接介面。 圖一顯示典型PCI匯流排之示意圖，PCI匯流排10〇為一共享匯流 排(shared bus)，圖一顯示PCI匯流排1〇〇掛置有PCI周邊裝置11〇、12〇、 以及130 ’另外’ PCI匯流排需要時脈源140供PCI周邊裝置之參考； 而PCI周邊裝置110、120、以及130，藉由PCI匯流排1〇〇上之PCI_66 硬體訊號與各PCI周邊裝置之内部暫存器來區別定義不同之硬體運作 速度，如PCI33、PCI66、或者PCI133，由於PCI匯流排100為共享匯 流排，因此時脈源140之運作係依照pci-66硬體訊號與各PCI周邊裝 置之内部暫存器來決定與PCI匯流排1〇〇耦接之諸多pCI周邊裝置 110、120、以及130中所能承受之適當時脈訊號；因此，唯有所有與 pci匯流排1〇〇耦接之諸多PCI周邊裝置皆能運作於PCI133或者更快 之速度，方能使其確實運作於pCI133。 快速周邊元件互連介面，極有希望成為下一世代之標準介面；快 速PCI採用點對點傳輸，而對每個端點而言，每個快速ρα之通道(lane) 分別具有傳送訊號對和接收訊號對，以目前已知之規格來說，快速pCI 差動訊號傳輸速度達2.5Gbps，就傳收資料而言僅需四根實體訊號，其 他共用之控制訊號則不予贅述，相較於PCI，快速PCI可以較少之硬體 腳位實現更高之傳輸速率。快速PCI亦規範了單通道、四通道、八通 1261171 道、十六通道、以及三十二通料不同硬體規格，以符合不同周邊裝 置應用之頻寬需求，舉_言，_卡需要極大之傳輸職，適合以 二十二通道之快速PCI介面實現；快速PCI介面在主機板上可以實施 於北橋晶片或者南橋晶片。 快速PCI規格規範了接收器(receiver)與傳送器⑽職汾啦線端 (termination)，^ ^(impedancem m〇de 讀age)等等。快速PCI規格規範了兩種通道順序··正通道順序㈣福 lane order)以及反通道順序(reverse丨咖_Γ);當四通道之快速ra裝 置以[通道0、通道1、通道2、通道3]對應麵接另一個四通道之快速 PCI裝置之[通道3、通道2、通道1、通道〇]，稱為反通道順序輕接； 另一種硬體輕接方式則為將四通道之快速PCI裝置之[通道〇、通道卜 通道2、通道3]依序對應耦接另一個四通道之快速ρα襞置之[通道〇、 通道1、通道2、通道3]，兩種快速PCI通道之耦接方式皆可為快速ρα 規格所接受。 【發明内容】 本發明揭示一種快速周邊元件互連介面卡之超頻方法，包含下列 步驟：複製快速周邊元件互連介面卡上PCI周邊裝置控制器之規劃暫 存器之内容，以將規劃暫存器之内容複製到主機端之主記憶體中；存 取及比對規劃暫存器之内容以決定PCI周邊裝置控制器之最高工作頻 率；回復規劃暫存器之内容；以及進行熱插拔以使PCI周邊裝置控制 器運作於最高工作頻率，藉由改變快速周邊元件互連介面卡之快速周 邊元件互連介面之終端狀態以重新初始化快速周邊元件互連介面卡， 舉例而言，改變快速周邊元件互連介面卡之快速周邊元件互連介面上 之共模電壓或阻抗’使其斷線後’再重新初始化快速周邊元件互連介 面卡。 本發明亦揭示一種快速PCI與PCI橋接控制器，包含:pci匯流排， 用以耦接PCI周邊裝置控制器；快速PCI匯流排，用以耦接主機端； 以及鎖相迴路電路，用以耗接一振盪器，以產生一時脈訊號給該pci 1261171 pci周邊裝置控制器 ’其中’ _α與ρα橋接控制器藉由存取及比對 pci周邊裝·繼之賴暫翻之内容以決定 之最高工作頻。 _ίΓΓ步揭示—種快賴邊元件互連介面卡，包含：具有規 祕子η之CI周邊裝置控制器；具有鎖相迴路電路、快速PCI匯流 排以及PCI ®流排之快速PCI與PCI橋接控制器，用以經由ρα匯流 =接PCI周邊裝置控制器及經由快速PCI帛流排祕至主機端，·振 盪器，输快速PCI與PCI橋接控制器，用以經由該鎖相迴路電路產 生時脈訊號供PCI周邊裝置控制器運作；其中，快速PCI與PCI橋接 控制器藉由存取及比對規劃暫存器之内容以決定該PCI周邊裝置控制 器之最面工作頻率。 為使對本發明之有最佳之瞭解，以下兹列舉若干具體實施例，並 配合佐以圖式作說明，其中： 【實施方式】 圖一顯示根據本發明之一具體實施例之快速pCI超頻裝置之方塊 圖，用以對PCI周邊裝置控制器200進行超頻運作；快速ρα超頻裝 置包含PCI周邊裝置控制器200、快速pCI與pci橋接控制器22〇、以 及時脈源240，PCI周邊裝置控制器200透過PCI匯流排26〇耦接快速 PCI與PCI橋接控制器220，快速PCI與PCI橋接控制器220耦接時脈 源240以提供PCI周邊裝置控制器200之運作時脈，快速PCI與pci 橋接控制器220提供快速PCI通道280搞接主機端(host);典型地，舉 例來說’ PCI周邊裝置控制器200與快速pci與pci橋接控制器220 皆為獨立晶片’而時脈源240為石英振盘器(cryStai)、陶竞振盪器 (ceramic resonator)、或時脈產生器(d〇ck generator)，而以上諸多元件適 合被置於同一塊電腦介面卡片上，該電腦介面卡具有快速PCI介面， 以耦接於電腦主機端，因此可以更少之硬體接腳提供更大之傳輸頻 寬，每個快速PCI通道至少可以提供2.5Gbps之雙向傳輸頻寬，由時脈 源240振盪出之頻率訊號給快速PCI與PCI橋接控制器220，經由其内 1261171 部之鎖相迴路(phase lock loop，簡稱Pll，未示），而產生適當之工作 頻率，甚至透過PCI匯流排260提供給PCI周邊裝置控制器2〇〇工作 時脈33/66/133MHz(l〇6赫茲）；舉例來說，以ρα周邊裝置控制器2〇〇 為10/100/1000之PCI乙太網路控制器為例，該電腦介面卡便成為具有 快速PCI介面之乙太網路介面卡，如此之優點在於，ρα介面已是多年 以來之主流技術，目前大多數家庭裡面的電腦皆有ρα介面擴充插槽， 將來pci周邊裝置㈣n仍有其市場與需求，而且，快速ρα之技術 門檻頗高，對於某賴邊裝置控之生產廠商而言，無法於一時之 間發展完成，另一方面，同樣的周邊裝置控制器無須同時設計生產pci 介面與快速PCI介面兩種產品，利用快速PCI與PCI橋接控制器22〇 就可以將同一種PCI周邊裝置控制器發展成PCI介面或快速PCI介面 兩種產品。 PCI周邊裝置控制器200内部具有規劃暫存器(c〇nggurau⑽ register)202，其記錄有有關PCI周邊裝置控制器2〇〇硬體本身之重要資 訊，包括有該PCI周邊裝置控制器2〇〇所支援之PCI匯流排運作速度 攔位；進一步地，舉例來說，規劃暫存器位址全部範圍為〇〇至FFh(h 代表16進位制），其中一部分是可以被存取的，舉例來說，位址範圍為 00至3Fh是可以被存取的。應注意到，本發明之快速PCI與PCI橋接 控制器220可利用時脈源240振盪出除了標準ρα工作時脈 33/66/133MHZ之外的其他ρα工作時脈給ρα匯流排26〇，例如 50/80/100/150/200MHZ，也就是說本發明之快速ρα與ρα橋接控制器 220可利用時脈源24〇振盪出33/50/66/80/100/133/150/200MHZ之複數 種PCI工作時脈33/66/133MHz;於電腦剛開機之初始化過程中，快速 PCI與PCI橋接控制器220可以藉由PCI匯流排26〇上ρα_66硬體訊 號與規劃暫存II 2〇2判斷出PCI周邊裝置控制器2⑼所支援之基本運 作頻率’舉例來說，66MHZ，由主機端配置出一塊可以讀寫之記憶體， 將規劃暫存器202巾之内容複製到所配置之記憶體中暫存，然後由快 速PCI與PCI橋接控制器220提昇PCI工作時脈至80MHz、100MHz 1261171 v"· ‘ .,w:.U 5 .奶·11:¾ : Μ1261171 / 玖, invention description: [Technical field of the invention] The present invention relates to a Peripheral Component Interconnect Express (PCI Express, or simply referred to as a fast Ρα) interface card, particularly on a PCI interface card Overclocking method of PCI peripheral device controller and related devices. [Prior Art] The standard bus used by peripheral devices of personal computers, from the early ISA interface, EISA interface, PCI33 interface, continually evolved to PCI66 interface and PCI133 interface, especially the standard interface of PCI series is in recent years. The standard connection interface for the most popular peripheral devices. Figure 1 shows a schematic diagram of a typical PCI bus, PCI bus 10 is a shared bus, Figure 1 shows PCI bus 1 with PCI peripherals 11〇, 12〇, and 130 ' The PCI bus requires the clock source 140 for reference to the PCI peripheral device; and the PCI peripheral devices 110, 120, and 130, through the PCI_66 hardware signal on the PCI bus and the internal temporary storage of each PCI peripheral device Differentiate the different hardware operating speeds, such as PCI33, PCI66, or PCI133. Since the PCI bus 100 is a shared bus, the clock source 140 operates according to the pci-66 hardware signal and each PCI peripheral device. The internal register determines the appropriate clock signals that can be received by the plurality of pCI peripheral devices 110, 120, and 130 coupled to the PCI bus 1; therefore, only all of them are coupled to the pci bus 1 Many of the PCI peripherals can operate at PCI133 or faster to be able to operate on the pCI133. The fast peripheral component interconnect interface is promising as the standard interface for the next generation; fast PCI uses point-to-point transmission, and for each endpoint, each fast ρα lane has a transmit signal pair and a receive signal, respectively. For the currently known specifications, the fast pCI differential signal transmission speed is 2.5 Gbps. For the transmission of data, only four physical signals are required. Other shared control signals are not described here. Compared with PCI, it is fast. PCI can achieve higher transmission rates with fewer hardware pins. Fast PCI also regulates single-channel, four-channel, eight-pass 12611171 channels, sixteen channels, and thirty-two materials in different hardware specifications to meet the bandwidth requirements of different peripheral device applications. The transmission function is suitable for the 22-channel fast PCI interface; the fast PCI interface can be implemented on the north bridge chip or the south bridge chip on the motherboard. The fast PCI specification regulates the receiver and transmitter (10), the termination, ^ ^ (impedancem m〇de read), and so on. The fast PCI specification specifies two channel sequences: • positive channel order (four) fulan order) and reverse channel order (reverse 丨 _ Γ); when four channels of fast ra device with [channel 0, channel 1, channel 2, channel 3] The corresponding channel is connected to another four-channel PCI device [Channel 3, Channel 2, Channel 1, Channel 〇], which is called reverse channel sequential light connection; another hardware light connection method is to make the four channels fast. The [channel 〇, channel 卜 channel 2, channel 3] of the PCI device are sequentially coupled to the other four channels of fast ρα, [channel 〇, channel 1, channel 2, channel 3], and two fast PCI channels. The coupling method can be accepted by the fast ρα specification. SUMMARY OF THE INVENTION The present invention discloses an overclocking method for a fast peripheral component interconnection interface card, which includes the following steps: copying the contents of a planning register of a PCI peripheral device controller on a fast peripheral component interconnection interface card to temporarily store the plan The contents of the device are copied to the main memory of the host; access and compare the contents of the plan register to determine the maximum operating frequency of the PCI peripheral device controller; reply to the contents of the plan register; and hot swap Having the PCI peripheral device controller operate at the highest operating frequency, re-initializing the fast peripheral component interconnect interface card by changing the terminal state of the fast peripheral component interconnect interface of the fast peripheral component interconnect interface card, for example, changing the fast perimeter The common-mode voltage or impedance of the component interconnect interface card's fast peripheral component interconnect interface 'after disconnection' re-initializes the fast peripheral component interconnect interface card. The invention also discloses a fast PCI and PCI bridge controller, comprising: a pci bus bar for coupling to a PCI peripheral device controller; a fast PCI bus bar for coupling to the host end; and a phase locked loop circuit for consuming Connect an oscillator to generate a clock signal to the pci 1261171 pci peripheral device controller 'where' _α and ρα bridge controller to determine the highest by accessing and comparing the contents of the pci peripheral Working frequency. _ ΓΓ 揭示 — - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - For communicating via the ρα convergence to the PCI peripheral device controller and via the fast PCI bus to the host side, the oscillator, and the fast PCI and PCI bridge controller for generating the clock via the phase locked loop circuit The signal is for the PCI peripheral device controller; wherein the PCI and PCI bridge controllers determine the maximum operating frequency of the PCI peripheral device controller by accessing and comparing the contents of the plan register. In order to make the best understanding of the present invention, several specific embodiments are listed below, and are illustrated with reference to the drawings, in which: FIG. 1 shows a fast pCI overclocking device according to an embodiment of the present invention. Block diagram for overclocking the PCI peripheral device controller 200; the fast ρα overclocking device includes a PCI peripheral device controller 200, a fast pCI and pci bridge controller 22A, and a clock source 240, a PCI peripheral device controller The PCI bus and the PCI bridge controller 220 are coupled to the fast PCI and PCI bridge controller 220. The fast PCI and PCI bridge controller 220 is coupled to the clock source 240 to provide the operating clock of the PCI peripheral device controller 200, and the fast PCI and pci bridge. The controller 220 provides a fast PCI channel 280 to engage the host; typically, for example, the 'PCI peripheral device controller 200 and the fast pci and pci bridge controller 220 are separate chips' and the clock source 240 is quartz. A flashing device (cryStai), a ceramic resonator, or a clock generator, and the above components are suitable for being placed on the same computer interface card. The interface card has a fast PCI interface to be coupled to the host computer, so that it can provide a larger transmission bandwidth with fewer hardware pins. Each fast PCI channel can provide at least 2.5Gbps bidirectional transmission bandwidth. The frequency signal oscillated by the pulse source 240 is sent to the fast PCI and PCI bridge controller 220, and the phase lock loop (Pll, not shown) of the 1261117 is generated to generate an appropriate working frequency, even through the PCI convergence. The row 260 is provided to the PCI peripheral device controller 2 〇〇 working clock 33/66/133 MHz (10 〇 6 Hz); for example, the ρα peripheral device controller 2 is 10/100/1000 PCI Ethernet For example, the network controller is an Ethernet interface card with a fast PCI interface. The advantage of this is that the ρα interface has been the mainstream technology for many years. Currently, most computers in the home have ρα. The interface expansion slot, in the future, the peripheral device (4) of the pci still has its market and demand, and the technical threshold of the fast ρα is quite high, and it is impossible for the manufacturer of a certain device to develop to complete the development at one time. On the other hand, the same peripheral device controller does not need to design and produce both the pci interface and the fast PCI interface. The PCI and PCI bridge controllers can be used to develop the same PCI peripheral controller into a PCI interface or fast. PCI interface two products. The PCI peripheral device controller 200 internally has a planning register (c〇nggurau(10) register) 202, which records important information about the PCI peripheral device controller 2 itself, including the PCI peripheral device controller. Supported PCI bus operation speed block; further, for example, the plan register address is in the range of 〇〇 to FFh (h stands for hexadecimal system), some of which can be accessed, for example Said that the address range of 00 to 3Fh can be accessed. It should be noted that the fast PCI and PCI bridge controller 220 of the present invention can utilize the clock source 240 to oscillate other ρα working clocks other than the standard ρα operating clock 33/66/133 MHz to the ρα bus bar 26〇, for example 50/80/100/150/200MHZ, that is to say, the fast ρα and ρα bridge controller 220 of the present invention can oscillate a plurality of 33/50/66/80/100/133/150/200 MHZ by using the clock source 24〇. PCI working clock 33/66/133MHz; during the initialization process of the computer just started, the fast PCI and PCI bridge controller 220 can be judged by the PCI bus 26 on the ρα_66 hardware signal and the planning temporary storage II 2〇2 The basic operating frequency supported by the PCI peripheral device controller 2 (9), for example, 66 MHz, the host side configures a readable and writable memory, and copies the contents of the plan register 202 to the configured memory. Temporary storage, then the PCI PCI clock is upgraded by the PCI Express and PCI Bridge Controller 220 to 80MHz, 100MHz 1261171 v"· ' ., w:.U 5 . Milk 11:3⁄4 : Μ
Λ ，：U ,i 广\ 二 * .- 或更亦，…對涵暫存！ 2〇2中可被存取之部分進行指定資料之讀寫以 確定根據較高頻率之PCI工作時脈是否可以對規劃暫存器2〇2 =行正 確之讀寫動作，以決定該PCI周邊裝置控制器200所能運作^最二工 作頻率，將被暫存之規劃暫存器202中之内容回填至規割暫存器3 中，然後再使該ρα 裝置控制器200細根據此最高工作頻率運 作，以達到對該PCI周邊裝置控制器200進行超頻之目的。 圖二顯示根據本發明之一具體實施例之快速PCI超頻流程圖，亦 請配合圖二以方便進行解說，圖三自步驟300開始，首先於步驟310 複製PCI周邊裝置控制器200之規劃暫存器202中之内容；步驟32〇 i 藉由存取及比對規劃暫存器202之内容，決定該pci周邊裝置控制器 2〇〇所能運作之最高工作頻率，舉例來說，由快速pci與ρα橋接控制 器220於不同PCI工作時脈至80MHz、1〇〇MHz或更高，對規劃^存 器2〇2中可存取部份，全面進行資料〇或資料i之穿插讀寫，根據頻 率80MHz時進行資料〇之寫入，再將其讀出比對，若比對結果正確， 則決定PCI周邊裝置控制器200可進一步支援到頻率8〇MHz之運作， 接者，根據頻率100MHz時進行資料1之寫入，再將其讀出比對，根 據比對結果正確，決定PCI周邊裝置控制器2〇〇是否可支援頻率 100MHz之運作，藉由進行資料〇或資料丨之穿插讀寫確保讀寫資料之 轉態(toggle)，也可以對每個頻率進行更複雜之資料樣態讀寫或者增加 其讀寫次數，以確保將來系統之穩定性；步驟33〇，回復規劃暫存器 202之内容；步驟340，進行熱插拔(hot plug)使PCI周邊裝置控制器2〇〇 運作於最高工作頻率。 應注意到，圖三所揭示之流程圖可以不同方式實施之，舉例而言， 圖二揭示之快速PCI介面卡可以藉由修改基本輸出入系統(basic input/output system，簡稱BIOS) ’實施於電腦開機初始化過程中以及將 相關於圖二之快速PCI介面卡之驅動程式載入之前，由基本輪出入系 統於電腦開機初始化過程中為每一個快速PCI介面卡配置一塊記憶 體，較佳地為主記憶體中1M以下之傳統記憶區之一部分，以供各快速 1261171 pci介面卡將其PCI周邊裝置控制器200之規劃暫存器2〇2中之内容進 行複製以及讀寫，並供稍候之回復；舉例而言，圖三所揭示之流程可 以實施於由作業系統將驅動程式載入之初始化階段，此階段作業系統 會為各驅動程式配置適當之記憶體空間，而無須修改基本輸出入系 統，便可利用配置給驅動程式專屬之記憶體空間供快速PCI介面卡將 其PCI周邊裝置控制器200之規劃暫存器2〇2中之内容進行複製以及 讀寫。 另一方面，圖三之步驟340,揭示進行熱插拔以使PCI周邊裝置控 制器200運作於最高工作頻率終端狀態，可以由快速ρα與ρα橋接 控制器220改變與主機端間耦接之終端狀態，包括由快速pci與 橋接控制器220改變阻抗或共模電壓，使主機端認為快速ρα與ρα 橋接控制器220斷線(disconnect)，並由快速PCI與PCI橋接控制器220 重新設定PCI周邊裝置控制器200及供應其新PCI工作頻率後，再重 新與主機端進行連接程序，使PCI胃邊裝置控制器2〇〇正確工作於新 pci工作頻率；或者，於快速PCI與ρα橋接控制器22〇内之ρα端 增a又PCI之熱插拔控制單元(未示），藉由於ρα匯流排上之主張(肪_ 重置訊號，使pci周邊裝置控制器2⑻進行重置，並供應其新ρα工 作頻率後，使PCI周邊裝置控制器200正確工作於新pCI工作頻率。 應注意到，技藝人士當可根據以上揭示做出可能之變化，舉例而 δ ’利用電腦之硬碟供快速PCI介面卡將其ρα周邊裝置控制器2〇〇 之規劃暫存器202中之内容進行複製以及讀寫。 、縱上所述，本發明揭示一種快速周邊元件互連介面卡之超頻方 法’口包含下列步驟··複製快速周邊元件互連介面卡上ρα周邊裝置控 制器之規簡存H之内容，崎規_翻之内容複_主機端之主 記憶，中；存取及比對_暫柿之内容以決定pQ贿裝置控制器 之最同工作鮮，回復_暫存器之魄；以及進行熱插拔以使 周邊裝置控糖運作於最高卫作鱗，藉由改變快速周邊元件互連介 面卡之快速贿元件互連介蚊終端麟以飾初始滅速周邊元件 10 1261171 互連介面卡，舉例而言，改變快速周邊元件互連介面卡之快速周邊元 件互連介面上之共模電壓或阻抗，使其斷線後，再重新初始化快速周 邊元件互連介面卡。 本發明亦揭示一種快速PCI與PCI橋接控制器，包含:PCI匯流排， 用以麵接PCI周邊裝置控制器；快速PCI匯流排，用以耦接主機端； 以及鎖相迴路電路，用以耦接一振盪器，以產生一時脈訊號給該PCI 周邊裝置控制器，其中，快速代^與代^橋接控制器藉由存取及比對 pci周邊裝置控制器之規劃暫存器之内容以決定ρα周邊裝置控制器 之最高工作頻。 本發明進一步揭示一種快速周邊元件互連介面卡，包含：具有規 劃暫存器之PCI周邊裝置控制器；具有鎖相迴路電路、快速PCI匯流 排以及PCI ®流排之快速PCI與PCI橋接控制器，用以經由ρα匯流 排搞接PCI周邊裝置控制器及經由快速PCI匯流排搞接至主機端；振 盪器，耦接快速PCI與PCI橋接控制器，用以經由該鎖相迴路電路產 生時脈訊號供PCI周邊裝置控制||運作；其中，快速ρα與ρα橋接 控制器藉由存取及比對賴暫存||之内容以決定該PCI周邊裝置控制 Is之最南工作頻率。 ，以上所揭示之具體實酬之_及圖式，係缺關明本發明之 技術内容及技術手段，並不欲祕本發明之紗。舉凡__切針對本發 明之結構細部修_、變更，或者是元件之等效替代、置換，當不脫離 本發明之發明精神及範其範圍將由以下之申請專利範圍來界定之。 【圖式簡單說明】 圖一係顯示顯示典型PCI匯流排之示意圖； 圖二係顯示根據本發明之一具體實施例之快速PCI超頻裝置之方 塊圖；以及 圖一係根據本發明之一具體實施例之快速超頻流程圖。 【元件符號簡單說明】 110、120、130 PCI 周邊裝置 100 PCI匯流排 1261171 140 時脈源 200 PCI周邊裝置控制器 202規劃暫存器 220快速PCI與PCI橋接控制器240 時脈源 260 PCI匯流排 280 快速PCI通道Λ , : U , i 广 \ 二 * .- or more, ... cum for the culvert! The part that can be accessed in 2〇2 reads and writes the specified data to determine whether the PCI working clock according to the higher frequency can correct the read/write action of the plan register 2〇2= to determine the PCI periphery. The device controller 200 can operate the second working frequency, backfill the contents of the temporarily stored planning register 202 into the processing register 3, and then cause the ρα device controller 200 to work according to the highest level. The frequency operates to achieve the purpose of overclocking the PCI peripheral device controller 200. FIG. 2 shows a fast PCI overclocking flowchart according to an embodiment of the present invention. Please also refer to FIG. 2 for convenient explanation. FIG. 3 starts from step 300, and firstly, in step 310, the planning of the PCI peripheral device controller 200 is temporarily stored. The content of the device 202; step 32〇i determines the maximum operating frequency of the pci peripheral device controller 2 by accessing and comparing the contents of the plan register 202, for example, by fast pci And the ρα bridge controller 220 operates at different PCI operating clocks to 80 MHz, 1 〇〇 MHz or higher, and accesses the read/write of the data or the data i to the accessible portion of the plan memory 2〇2. According to the frequency of 80MHz, the data is written and then read and compared. If the comparison result is correct, it is determined that the PCI peripheral device controller 200 can further support the operation to the frequency of 8 〇 MHz, according to the frequency of 100 MHz. When the data 1 is written, and then read and compared, according to the correct comparison result, it is determined whether the PCI peripheral device controller 2 can support the operation of the frequency of 100 MHz, and the data or data is interspersed. Write guarantee By writing a data toggle, you can also read and read more complex data patterns for each frequency or increase the number of reads and writes to ensure the stability of the system in the future; Step 33, reply to the planning register 202 Contents; Step 340, performing a hot plug to operate the PCI peripheral device controller 2 at the highest operating frequency. It should be noted that the flowchart disclosed in FIG. 3 can be implemented in different manners. For example, the fast PCI interface card disclosed in FIG. 2 can be implemented by modifying a basic input/output system (BIOS). Before the computer boot initialization process and before loading the driver of the fast PCI interface card related to FIG. 2, the basic wheel access system configures a memory for each PCI interface card during the initialization process of the computer, preferably One part of the traditional memory area below 1M in the main memory, for each fast 1261171 pci interface card to copy and read the contents of the planning register 2〇2 of the PCI peripheral device controller 200, and for later reading For example, the process disclosed in FIG. 3 can be implemented in an initialization phase in which the driver loads the driver, and the operating system configures the appropriate memory space for each driver without modifying the basic input and output. System, you can use the memory space dedicated to the driver for the PCI interface controller 200 2〇2 in the register designated content replication and to read and write. On the other hand, in step 340 of FIG. 3, it is disclosed that the hot plugging is performed to enable the PCI peripheral device controller 200 to operate in the highest operating frequency terminal state, and the terminal coupled to the host end may be changed by the fast ρα and ρα bridge controller 220. The state includes changing the impedance or common mode voltage by the fast pci and the bridge controller 220, causing the host to consider the fast ρα and ρα bridge controller 220 disconnected, and resetting the PCI perimeter by the fast PCI and PCI bridge controller 220. After the device controller 200 and its new PCI operating frequency are supplied, the connection procedure is again performed with the host to enable the PCI stomach device controller 2 to operate correctly at the new PCI operating frequency; or, in the PCI and ρα bridge controllers. The ρα terminal in 22〇 is increased by a PCI hot-swap control unit (not shown), and the pci peripheral device controller 2 (8) is reset and supplied by the claim on the ρα bus bar (the fat_reset signal) After the new ρα operating frequency, the PCI peripheral device controller 200 is correctly operated at the new pCI operating frequency. It should be noted that the skilled person can make possible changes according to the above disclosure, for example, δ The hard disk of the computer is used for the PCI interface card to copy and read the contents of the planning register 202 of the ρα peripheral device controller. In the above, the present invention discloses a fast peripheral component interconnection. The overclocking method of the interface card's port includes the following steps: · Copying the contents of the ρα peripheral device controller on the fast peripheral component interconnection interface card, the content of the stipulation _ 翻 翻 翻 翻 _ _ host memory, the main memory; Access and comparison _ temporary persimmon content to determine the pQ bribe device controller's best work, reply _ temporary storage; and hot swap to enable peripheral devices to control sugar operation in the highest guard scale, borrow The quick bribe element that changes the fast peripheral component interconnect interface card interconnects the mosquito terminal to decorate the initial peripheral component 10 1261171 interconnect interface card, for example, to change the fast peripheral components of the fast peripheral component interconnect interface card The common mode voltage or impedance on the interface is re-initialized after the wire is disconnected, and the fast peripheral component interconnect interface card is re-initialized. The invention also discloses a fast PCI and PCI bridge controller, including: PCI bus The PCI peripheral device controller is connected to the PCI peripheral device; the fast PCI bus bar is coupled to the host terminal; and the phase locked loop circuit is coupled to the oscillator to generate a clock signal to the PCI peripheral device controller, wherein The fast generation and the bridge controller determine the highest operating frequency of the ρα peripheral device controller by accessing and comparing the contents of the planning register of the pci peripheral device controller. The present invention further discloses a fast peripheral component mutual The interface card includes: a PCI peripheral device controller with a planning register; a PCI and PCI bridge controller with a phase locked loop circuit, a fast PCI bus, and a PCI® bus bar for interfacing via the ρα bus bar The PCI peripheral device controller is connected to the host terminal via a fast PCI bus; the oscillator is coupled to the fast PCI and PCI bridge controller for generating a clock signal via the phase-locked loop circuit for control by the PCI peripheral device|| Wherein, the fast ρα and ρα bridge controller determines the southernmost operating frequency of the PCI peripheral device control Is by accessing and comparing the contents of the temporary storage ||. The specific details of the disclosure and the drawings disclosed above are not intended to reveal the technical contents and technical means of the present invention. The invention is not limited to the spirit of the invention and the scope of the invention is defined by the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a typical PCI bus bar; FIG. 2 is a block diagram showing a PCI PCI overclocking device according to an embodiment of the present invention; and FIG. 1 is a specific implementation according to the present invention. Example of a fast overclocking flowchart. [Simplified description of component symbols] 110, 120, 130 PCI peripheral device 100 PCI bus 1261171 140 clock source 200 PCI peripheral device controller 202 planning register 220 fast PCI and PCI bridge controller 240 clock source 260 PCI bus 280 Fast PCI Channel
1212