TWI261165B - Memory module storing therein boot codes and method and device for locating same - Google Patents

Abstract

A memory module storing therein boot codes, a core logic device capable of distinguishing such memory module from the other memory modules of the same module specification, and a method for realizing the boot codes from the memory module storing therein the boot codes are disclosed. All the memory modules are electrically connected to the core logic device via respective signal pins, but the memory module storing therein boot codes outputs an identifying signal different from the identifying signals outputted by the other memory modules in a booting process. Therefore, the core logic device can locate the memory module storing therein the boot codes, and the host device can accomplish the booting process by reading the boot codes from the specific memory module.

Description

1261165 V. INSTRUCTION DESCRIPTION (i) Field of the Invention The present invention discloses a memory module storing a boot code, a core logic device having a memory module identification capability, and a boot code reading method, especially for a computer system. A memory module storing a boot code, a core logic device having a memory module identification capability, and a boot code reading method. BACKGROUND OF THE INVENTION In a computer system booting process, a microprocessor usually has to Non-volatile memory (Ν ο η - v ο 1 ati 1 emem 〇ry ) in the section of the boot program line system from the boot action system (B asic basic output flash memory please refer to 1 1 , South Bridge out, basically so micro The code can be retrieved. In addition to the code (boot codes) and executed, this includes performing the test work and reading the basic settings of the system, etc., and the boot code is generally called the basic output. Input Output System (BIOS), and non-volatile memory with input system code (currently mostly Into) the basic input-output system is called a wafer. See the first figure, which is a schematic diagram of the conventional architecture of the microprocessor 1 and the north bridge wafer wafer. It can be clearly seen that the output input system chip 13 is connected to the south bridge wafer 1 2, the processor 1 The 0 system must pass through the north bridge chip 1 1 and the south bridge chip 1 2 , and the basic output input system chip 13 is stored in the boot program. The basic output is input to the system chip 1 3 memory body, the computer system

Page 6 1261165 V. Description of the Invention (2) A plurality of other memories 14 electrically connected to the Northbridge wafer 1 1 are also included. These ̄ ̄ ̄ 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 However, one of the technologies developed by Micron Technology, Inc. (^1&}1〇;: flash memory can use the same bus as DRAM, and the same] memory The controller is executed. Therefore, a SyncFlah flash memory can now be used as one of the memories 14. In this case, a SyncFlash double-sided pin is used to define the memory module (SyncFlash Dual).

The In-line Memory Module (SyncFlash DIMM) is used as a basic output for storing the boot code, and is inserted into the slot used for the memory 14. In this way, the microprocessor can quickly retrieve the boot code through the north bridge chip 1 1 . However, since the above-mentioned Sync F 1 ash double-sided pin definition memory module has the same module specifications as the general DRAM double-sided pin definition memory module and is also inserted into the memory connected to the north bridge wafer 1 1 In the body socket, the Sync F 1 ash memory module and the DRA Μ memory module seen by the north bridge chip 1 1 are both the same double-sided pin definition memory module, and cannot be performed. The Sy ncF 1 ash memory module carrying the boot code is directly identified during the boot operation, and how to propose a quick-recognition and practical solution is the main purpose of the development of the case. SUMMARY OF THE INVENTION The first aspect of the present invention is a memory module electrically connected to

Page 7 1261165 One of the required ones of the computer system is stored in the group. The memory module is electrically connected to the computer system for an identification signal for providing a computer system for determining the storage code of the computer system. Select nab 1 e to include the output one including one out of the south module system and one north bridge system. For a non-volatile memory module, for example, the fifth description of the invention (3) in the brain system, the memory model code is characterized in that one of the signal pins is outputted and read, thereby making the computer system At the office. The memory module is electrically connected to the pair of signal pins, such as a crystal clock enable pin (C 1 〇 ck E , the memory module is preferably electrically connected to the pull-down resistor, and the memory module can also be connected Preferably, the memory core logic device, particularly preferably, the computer system signal pin outputs the memory module is preferably a Sync F 1 ash memory phantom The second aspect of the present invention is to one of a plurality of memory modules, one of the specific memory modules, and the one of the signal pins is divided to determine the memory modules. The signal pin is preferably a Chip Select pin or a pin. The pull pin is a low-level digital identification signal. Or a pull-up resistor, this signal pin is the digital identification signal of the potential level. Electrically connected to one of the wafers in the computer system. During the booting process, the core logic device is electrically connected to a plurality of signal pins, and the core logic device required in the booting process of the memory module is stored in the booting program. Do not read the corresponding identification signal, so that in the group, which is stored in the boot code

Page 8 1261165 V. Inventive Note (4) The specific memory is better, such as wafer selection (Clock is in the foot system (pu 1 1 - E nab 1 - the implementation is connected to the down r connected to it and the electrical resistance (pull-up number. In another real pin system pul 1 is electrically connected up res to other electrical connection P and (pul 1-down number. One of the other modules accesses the face-to-face pin as a dynamic core logic Outside the North Bridge, the non-volatile memory is better, and the randomized random body module is defined. The signal pins that are electrically connected to the memory modules are pin-connected (C hip S e 1 ec ΐ pins ) or clock In the example, the signal connected to the specific memory module is connected to a pull-down resistor esist 〇r in the specific memory module and read into a low level. The digital identification signal, the signal pin of the memory module is electrically connected to a pull-up resistor, and is read into a high-level digital identification signal embodiment, and is electrically connected to the signal of the specific memory module to One of the pull-up resistors in the particular memory module Ist 〇r) and reading a digital identification signal of a high level, and the signal pin of the memory module is electrically connected to the lower power sensor, and the digital identification device for reading a low level can be A chip set, especially a chip set. The specific memory module can be a memory memory module such as S y n c F 1 a s h, and the other memory modules can be a follow-up module, such as a dynamic random access memory module. The S y n c F 1 a s h memory module is a S y n c F 1 a s h double memory module, and the dynamic random access memory module accesses the double-sided pin definition memory module.

Page 9 1261165 V. Description of the invention (5) The third aspect of the present invention is a boot code reading method applied between a core logic device and a plurality of memory modules, the core logic device having an electrical connection to The plurality of signal pins of the memory modules, wherein one of the memory modules stores a boot code required in the boot process, and the read method includes the following steps: In the booting process, the core logic device reads the corresponding identification signal from the signal pins respectively, thereby determining the specific memory module storing the boot code; and the specific memory The boot code I is bought in the module. A brief description of the case The following drawings and detailed descriptions can be used to obtain a more in-depth understanding: The first figure: It is a schematic diagram of the conventional architecture of the current microprocessor, Northbridge chip, and Southbridge chip. Second figure: It is a functional block diagram of the first preferred embodiment of the present invention. The third figure is a functional block diagram of the second preferred embodiment of the present invention. Fourth (a) and (b): This is not intended to be a resistor composed of a MOS transistor. The components included in the diagram of this case are listed as follows: Microprocessor 1 0 North Bridge Chip 1 1

Page 10 1261165 V. Invention Description (6) South Bridge Chip 1 2 Memory 1 4 North Bridge Chip 2 1 Pull-up Resistor 213, 214 S ync F 1 ash Memory Module 2 3 Microprocessor 3 晶片 Chip Select Pin 3 1 1 , 3 1 2 DRA Μ Memory Module 3 2 Pull-up Resistor 3 3 1 Basic Output Input System Chip 1 3 Microprocessor 2 0 Chip Select Pin 211, 212 DRA Μ Memory Module 2 2 Pull-down Resistor 2 3 1 North Bridge Wafer 3 1 Pull-down Resistor 313, 314 S ync F 1 ash Memory Module 3 3 For a description of the preferred embodiment, please refer to the second figure, which is a functional block diagram of the first preferred embodiment of the present invention. The chip selection pins (C hip S e 1 ectpi η, CS for short) 2 1 1 and 2 1 2 of the north bridge chip 2 are individually connected to a pull-up resistor 213, 214. The voltage on it is pulled to the south level V cc . Therefore, in order to enable the Sync F 1 ash memory module 2 3 storing the boot code to be recognized by the north bridge chip 2 1 from other DRAM memory modules 2 2, we are in the Sync F 1 ash memory. The chip select pin (CS) of the body module 2 3 is connected to the pull-down resistor 231 to ground, and the resistance value of the pull-down resistor 2 3 1 can be set to be much smaller than the pull-up resistor 2 1 3 The resistance value, in turn, forms a strong pull-down and weak pull-up potential state. And because the resistance value of the pull-down resistor 231 is much smaller than the resistance of the pull-up resistor 213

Page 11 1261165 5, invention description (7) value, so the North Bridge chip 2 1 during the boot process (or reset procedure) - can read the chip select pin (CS) 2 1 1 , 2 1 2 operation of the voltage level signal, and by detecting the low level signal, the north bridge chip 2 1 can determine which is the chip selection pin connected to the Sync F 1 ash memory module 2 3 Further, the microprocessor 20 can pass through the north bridge chip 2 1 and the boot code is retrieved from the Sync F 1 ash memory module 2 3, thereby completing: a subsequent boot process (or reset procedure) . Please refer to the third figure, which is a functional block/schematic diagram of the second preferred embodiment of the present invention. In this example, the wafer selection pins (CS) 3 1 1 and 3 1 2 of the north bridge chip 31 are individually connected. Pull the resistors 3 1 3, 3 1 4 to the ground point and pull them to the low level. Therefore, in order to enable the _Sync F1 ash memory module 3 3 storing the boot code to be recognized by the north bridge chip 3 1 from other DRA Μ memory modules 3 2, we are connected to Sync F 1 A pull-up resistor 3 3 1 to a voltage source V cc is connected to the chip select pin (CS) of the ash memory module 3 3 , and the resistance value of the pull-up resistor 3 3 1 can be set to be much smaller than the pull-down resistor. The resistance value of 3 1 3, which in turn forms a strong pull-up and weak pull-down potential state. Since the resistance value of the pull-up resistor 331 is much smaller than the resistance value of the pull-down resistor 313, the north bridge chip 31 can read the chip selection pins (CS) during the boot process (or reset procedure). 3 1 1 , 3 1 2 on the voltage level signal action, and in the way of detecting the high level signal, the north bridge chip 3 1 can determine which is connected to the Sync F 1 ash memory module 3 3 The chip selects the _ pin, and further enables the microprocessor 30 to pass through the north bridge chip 3 1 and capture the boot code from the Sync F 1 ash memory module 3 3 , thereby completing

Page 12 1261165 V. Description of the invention (8) Follow-up procedure (or reset procedure). In the above description, the technical means of the present invention can accurately and quickly identify in the plurality of memory modules inserted in the memory slot, which is the Sync F 1 ash memory module storing the boot code. It did achieve the main purpose of developing the case. In addition to the above-mentioned chip select pin (CS), the technical means of the present invention can be applied to any point-to-point signal pin between the north bridge chip and the memory module, for example, a clock-enabled pin (C 1 〇ck) E nab 1 e pin, referred to as CKE). In order to be highly integrated into the integrated circuit process, the above-mentioned pull-up resistor and pull-down resistor can be used as shown in the fourth figure (a) (b), the resistor composed of MOS transistor. carry out. Of course, this case can also be applied to any similar hardware environment of the core logic (c 〇re 1 〇gic) device, so the invention of this case can be modified by people who are familiar with the art, but none of them Remove as intended from the scope of the patent application.

Page 13 1261165 Brief Description of the Diagram First: It is a schematic diagram of the conventional architecture of the current microprocessor, Northbridge, and Southbridge. Second figure: It is a functional block diagram of the first preferred embodiment of the present invention. The third figure is a functional block diagram of the second preferred embodiment of the present invention. Fig. 4 (a) and (b) are not intended to constitute a resistor by a MOS transistor.

Page 14

Claims (1)

I; case number 蚶]^ every 65 1 > month __ L—.?Γ, ▼ read 莼羽读围^'- ' ' 1. A memory module, electrically connected to one of the computer systems The core logic device 'the memory module stores one of the boot code required for the computer system' is characterized in that the memory module is electrically connected to a point-to-point signal pin of the computer system and outputs an identification The signal is used to provide reading by the core logic device, so that the computer system can determine where the boot code is stored. 2. The memory module of claim 1, wherein the point-to-point signal pin is selected from a chip select pin (Chip Select pi η) or a clock enable pin (C 1 ο ck Ε η ab 1 e ρ i η ). 3. The memory module of claim 1, further comprising a pull-down resistor, the point-to-point signal pin being electrically connected to the pull-down resistor to output a low-level digital identification signal. 4. The memory module of claim 1, further comprising a pull-up resistor, the point-to-point signal pin being electrically coupled to a pull-up resistor to output a high-level digital identification signal. 5. The memory module of claim 1, wherein the core logic device is electrically connected to a north bridge wafer. 6. The memory module of claim 1, wherein the computer system reads the identification signal output by the point-to-point signal pin during a boot process. 7. The memory module of claim 1, wherein the memory module is a non-volatile memory module. 8. A core logic device having a plurality of point-to-point signal pins electrically connected to a plurality of memory modules, one of the memory modules Page 15 1261165 The core module stores a host open code', and the core logic device is read into the corresponding memory module of the 5th and the like, respectively, and is the memory module. One of the required programs in the machine program, in the booting process, the point-to-point identification signal is used to determine that the specific code stored in the boot code is as described in item 8 of the patent application scope. The core logic device, wherein the point signal pin is selected from a chip select pin (Chlp Select ph or a Clock Enable pin). I 0 · core logic as described in claim 8 The device, wherein the electrical connection $ to the point-to-point signal pin of the specific memory module is resis; the 1^1 item enters a low-level digital identification signal, and the point-to-point signal pin electrically connected to the other memory group is electrically Connected to a pull-up resistor called res is tor) and read in the digital identification signal of a high level. II. The core logic device of claim 8, wherein the point-to-point signal pin electrically connected to the specific memory module is electrically connected to one of the pull-up resistors (puU) located in the specific memory module. -up resist〇r) and read the digital identification signal of a high level, and the point-to-point signal pin electrically connected to other memory modules is electrically connected to the pull-up resistor (pul i_d〇wn resistor) and read into one Low level digital identification signal. 1 2 The core logic device of claim 8 is a chip set. ^ 1 3 · The core logic device as described in claim 8 is a north bridge wafer in a chip set. 1261165 --1^_91104465 years ~, apply for full-time® 1 * __ 1 4 · The core logical memory module of the application scope is the non-volatile memory module: upper = module For the - random access memory module. And its ... body 1 5. A boot code reading method, applied to - 桉, a plurality of memory modules, the core logic device is set up and so on, a plurality of signal connections of the memory module The foot, the record; the J槿 group φ to, the specific memory module stores one of the two in the boot program... ρ ^ one code 'sub-includes one of the corresponding signal pin connections - two The method of fetching comprises the following steps: Private 1 In the booting process, the core logic device reads the corresponding identification signal by 誃, wherein only 1 work;::: J: one of the specific identification signal systems Located at the first level: Sa this: Second, the specific memory module storing the boot code; and: the decision to store the boot code from the specific memory module. 2: The patent code of the 15th patent range is as follows: the signal connection from the core logic device of the eight-in-one is connected to the signal pins such as the memory. ~,, ' ^ 1 7 · The method of reading the boot code described in the '16 patent scope, wherein the point-to-point signal pins are selected from Chip Select pins or clocks. Can be pin (ci0Ck Enable pins). 1 8 . The method of reading a boot code according to claim 15 , wherein a signal pin electrically connected to the specific memory module is electrically connected to one of the specific memory modules. Resistor (pul 1-down resistor) causes the core logic device to read in a low level digital identification η Page 17 曰Revision>: The scope of the patent is Ling, and the signal pin that is electrically connected to other memory modules is electrically connected to 170 / 1 η — ιΤϊή 彳 ancient and modern female J·7, 、, rn» . Case No. 91104465 s D The sighing hole u ^ ~ ~ A ww electrically presses the pull-up resistor to cause the core logic device to read the digital identification signal of the j Q high level. The method of reading the boot code as described in item 5 of the patent application scope, the signal pin connected to the specific memory module is electrically connected to the bit; and one of the specific memory modules is read. Pull-up resistor (3i〇2 causes the core logic device to read in a high-level digital identification signal, and the signal pin electrically connected to other memory modules is electrically connected to the pull-up resistor (pull a digital identification device, wherein the core logic device reads a low-level digital identification signal, as described in claim 15, wherein the core logic device is Is a chip set. @ 彳' 2 1 · The boot code # 4 * ^ code reading method as described in claim 15 wherein the core logic device is in a chip set, τ ^ a ^ #1%片. 22· As shown in the patent application, item 15 and 5, the same memory module is a non-volatile code method, and its memory module is a random access memory module n group