TWI248199B - Conductive plug and method of making the same - Google Patents
Conductive plug and method of making the same Download PDFInfo
- Publication number
- TWI248199B TWI248199B TW94108023A TW94108023A TWI248199B TW I248199 B TWI248199 B TW I248199B TW 94108023 A TW94108023 A TW 94108023A TW 94108023 A TW94108023 A TW 94108023A TW I248199 B TWI248199 B TW I248199B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- conductive plug
- conductive
- angstroms
- thickness
- Prior art date
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
1248199 五、發明說明(1) 【發明所屬之技術領域】 本發明係有關於一種 於一種導電插塞及其製造 【先前技術】 傳統的半導體製程如 Random Access Memory ; 方法包括··在一基底上形 述絕緣層以形成一接觸孔 學機械研磨以形成表面舆 塞。然後利用一般的沉積 一二氧化矽層。接著,形 矽層上,並進行圖案化及 行儀刻步驟,以選擇性地 層’並去除光阻圖案而形 導電材料,以當作導線元 上述習知技術中,由 表面等高,再著,鎢插塞 矽層,在進行蝕刻步驟時 梦層未被完全移除,導致 不良,亦即存在著開路或 種改良之導電插塞的製造 【發明内容】 有鑑於此,本發明之 製造方法,不但解決了斷 半導體 方法。 動態隨 DRAM ) 成一絕 ,接著 上述絕 方法依 成一光 的製程技術,且特別有關 機存取 製程中 緣層, w積鎢 緣層略 序形成 阻層於 顯影以形成光 去除上述二氧 成一開 件間的 於鎢插 表面覆 經常會 鎢插塞 者斷路 方法。 ϋ,接 導線。 基的表 蓋有氮 發生鎢 與後續 的問題 記憶體 ’導電 然後選 金屬, 為等高 一氮氧 上述基 阻圖案 化碎層 著,在 (Dynamic 插塞的製造 擇性韻刻上 其次施以化 的鶴金屬插 化石夕層以及 底之二氧化 。之後,進 及氮氧化矽 此開口填入 面通常與絕緣層的 氧化石夕層及二氧化 插塞上方之氮氧化 形成的導線之接觸 ,因此業界亟需一 目的在於提供一種導電插塞及其 路的問題’同時也使得導電插夷 0548-A50295TWf(5.0) ; 93021 ; Forever769.ptd 第8頁 1248199 五、發明說明(2) 之間的接觸面積增加,而接觸阻抗得以降低。 - αΙΠϊ成第一介電層、一抗反射層、-犧牲層於 # ^ 後定義一介層窗穿過上述犧牲層、上述抗反 射層及上述第一介愈爲^ 仇久 g^ 罘;丨電層,並於上述犧牲層上沉積一導電声 形層窗内’·最後去除介層窗以外之導電層,: 電闲且凹敍至少部分之上述犧牲層’使上述導 、f其二大八周圍之表面。最後,沉積一第二介電層於上 蓋上述導電插塞;以及形成-導線穿過上述 出之邱八勺紅基接觸。其中,上述導電插塞突 比上’且上述導線與部分之上 述上=面及上述侧壁均形成接觸。 之上 述犧ί:對it亡述凹,步驟係利用上述抗反射層及上 α1=ηρ Λ :…(Di iuted Hydr〇f-a 刻速率差異的特性,以去除部分之卜、+. 犧牲層而使導電插塞較复 矛、[刀之上述 後續㈣製程所需钱刻的之犬出,因而間接縮短 沒有上述抗反射層覆i的::度;另:!; t於導電插塞之上 避免了存在於習知技術中由:進:J續钱,,程時,便 引起之斷路的問題。 几十層如氮氧化矽層所 又,上述導電插塞突出之部分包 壁,且上述導線與部分 上表面與一侧 觸。使得導電插塞之間沾; 及上述側壁均形成接 接觸阻抗得以降低。、1面積較習知技術的增加,而 和優點能更明 為讓本發明之上述和其他目的、特徵 第9頁 0548-A50295TWf(5.0) ; 93021 ; Forever769.ptd 1248199 ' 五、發明說明(3) 顯易懂,下文特舉出較佳實施例,並配合所附圖式,作詳 細說明如下: 【實施方式】 依照本發明一較佳實施例,第1圖表示一基底2,其具 有一導電區域7。第2圖說明疊層結構5的形成方法,上述 方法係於一基底2依序形成第一介電層10、抗反射層2〇、 以及犧牲層3 0。上述疊層結構5的形成方法可以包括同一 反應室内同步進行之化學氣相沉積法。其中,第一介電層 10例如導入TEOS及02KLPCVD的反應室之中,以5 0 0至70 0 °C 〇的溫度形成厚度介於2 0 0 0至30 0 0埃之間的二氧化矽 (Si〇2 )層,然後導入SiH4、NH3及队0等氣體於同一反應室 中’以形成當作抗反射層2 〇的氮氧化石夕(S i Ο N )層,其厚 度大抵介於3 0 0至4 0 0埃;接著,再導入TEOS&〇2sLPCVI)反 -應室之中以形成當作犧牲層3 〇的二氧化矽層,其厚度大抵 介於2 0 0 0至3000埃,較佳之厚度大抵介於5()()至1()〇()埃。 依照本發明一較佳實施例,第3至6用於說明介層窗5〇 的形成方法。上述方法係可以利用傳統的微影技術,先於 犧牲層30上形成一光阻層35,如第3圖所示。然後微影形 |成一光阻圖案4 0,如第4圖所示。再經後續的蝕刻步驟, 例如導入合氟氣體如CF4、CHF3、C4F8於反應性離子蝕刻機 台,以蝕刻未被光阻圖案4〇保護之犧牲層3〇、抗反射層 20、以及部分的介電層丨〇,如第5圖所示。最後,移除光 阻圖案40而形成介層窗5〇,此介層窗5〇露出上述導電區域 7,如第6圖所不。其中,介層窗5〇之深度大抵介於丨了㈣至1248199 V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a conductive plug and a manufacturing method thereof [Prior Art] A conventional semiconductor process such as a Random Access Memory; the method includes: The insulating layer is patterned to form a contact hole mechanical grinding to form a surface choking. A general deposition of a cerium oxide layer is then utilized. Next, on the shape layer, and performing a patterning and engraving step to selectively layer and remove the photoresist pattern to form a conductive material to be used as a wire element in the above-mentioned prior art, by surface contours, and then, a tungsten plug layer, the dream layer is not completely removed during the etching step, resulting in defects, that is, the manufacture of an open circuit or an improved conductive plug. [Invention] In view of this, the manufacturing method of the present invention, Not only solved the semiconductor method. Dynamic with DRAM) becomes a must, then the above-mentioned absolute method is based on a light process technology, and especially related to the middle edge layer of the machine access process, the w-stacked tungsten edge layer forms a resist layer in development to form light to remove the above-mentioned two oxygen. The tungsten plug surface between the pieces is often broken by the tungsten plug. ϋ, connect the wires. The base cover has a tungsten-generating tungsten and a subsequent problem memory 'conducting and then selecting a metal, which is patterned by the above-mentioned base resistance of the contour nitrous oxide, and is applied secondly to the manufacturing rhyme of the dynamic plug. The corrugated metal is intercalated with the phosphatide layer and the bottom of the oxidized layer. Thereafter, the opening of the yttrium oxide is usually in contact with the oxidized oxide layer of the insulating layer and the wire formed by the oxidation of nitrogen above the oxidized plug. Therefore, there is an urgent need in the industry to provide a problem of a conductive plug and its path. At the same time, it also makes conductive interleaving 0548-A50295TWf (5.0); 93021; Forever769.ptd page 8 1248199 V. Between the invention description (2) The contact area is increased, and the contact resistance is reduced. - α is formed into the first dielectric layer, an anti-reflection layer, and the sacrificial layer is defined by #^, and a via is defined through the sacrificial layer, the anti-reflection layer, and the first dielectric layer. The more ^ ^ 久久 g ^ 罘; 丨 electric layer, and deposited on the sacrificial layer a conductive acoustic layer window '· finally remove the conductive layer outside the via window,: electric idle and concave at least part of the above sacrifice The layer 'sends the surface around the two major eight. Finally, depositing a second dielectric layer on the upper cover of the conductive plug; and forming a wire through the above-mentioned eight-spoon red base contact. The conductive plug has a protrusion ratio and the conductor is in contact with the upper surface and the sidewall of the portion. The above-mentioned sacrifice: the recess is reversed, and the step is to use the anti-reflection layer and the upper α1=ηρ Λ : ...(Di iuted Hydr〇fa The characteristics of the difference in the rate of the engraving, in order to remove the part of the Bu, +. Sacrificial layer and make the conductive plug more than the spear, [the knife of the above-mentioned follow-up (four) process required for the dog, and thus indirectly Shortening the absence of the above-mentioned anti-reflection layer covering i::degree; another:!; t avoiding the problem of the open circuit caused by the conventional technology in the conventional technology: a plurality of layers, such as a layer of ruthenium oxynitride, wherein a portion of the conductive plug protrudes from the wall, and the wire is in contact with a portion of the upper surface and one side, so that the conductive plugs are in contact with each other; and the sidewalls are formed to have contact resistance Can be reduced. 1 area is more than the increase of conventional technology, and The above and other objects and features of the present invention will become more apparent. Page 9 0548-A50295TWf (5.0); 93021; Forever 769.ptd 1248199 ' V. Invention Description (3) It is easy to understand, and the following is a preferred embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In accordance with a preferred embodiment of the present invention, Figure 1 shows a substrate 2 having a conductive region 7. Figure 2 illustrates a laminate structure 5. In the method of forming the first dielectric layer 10, the anti-reflection layer 2, and the sacrificial layer 30, a method is sequentially formed on a substrate 2. The above-described method of forming the laminated structure 5 may include a chemical vapor deposition method in which the same reaction chamber is simultaneously performed. Wherein, the first dielectric layer 10 is introduced into a reaction chamber of TEOS and 02KLPCVD, for example, to form a cerium oxide having a thickness of between 200 and 300 angstroms at a temperature of 50,000 to 70 ° C 〇. (Si〇2) layer, then introduce SiH4, NH3, and team 0 gas in the same reaction chamber to form a layer of oxynitride (S i Ο N ) as anti-reflective layer 2 ,, the thickness of which is large 3 0 0 to 400 angstroms; then, into the TEOS & 〇 2sLPCVI) counter-reaction chamber to form a cerium oxide layer as a sacrificial layer 3 ,, the thickness of which is between 2,000 and 3,000 angstroms Preferably, the thickness is between 5 () () and 1 () 〇 () angstroms. In accordance with a preferred embodiment of the present invention, the third to sixth embodiments are used to explain the formation of the via 5 〇. The above method can form a photoresist layer 35 on the sacrificial layer 30 by using conventional lithography techniques, as shown in Fig. 3. Then lithography | into a photoresist pattern 40, as shown in Figure 4. Then, through a subsequent etching step, for example, introducing a fluorine-containing gas such as CF4, CHF3, or C4F8 to the reactive ion etching machine to etch the sacrificial layer 3, the anti-reflection layer 20, and the portion not protected by the photoresist pattern 4? Dielectric layer 丨〇, as shown in Figure 5. Finally, the photoresist pattern 40 is removed to form a via 5 〇 which exposes the conductive region 7, as shown in Fig. 6. Among them, the depth of the via window 5大 is probably between 四 (4) to
12481991248199
2 3 Ο 0 埃。 —依妝本杳明一較佳實施例,第7及8圖用於說明導電插 基7 〇的^/成方& i述方法係、先於介層窗5 Q之底部及侧壁 表面利用沉積法形成阻障層6〇,士口第7圖所示。上述阻障 層60例如利用LPCVD法形成氮化鈦(ΤιΝ)層,其厚度大抵 介於2〇〇至_埃及利用PVD法形成一鈦(Tl)層,盆厚度一 大抵介於200至3 00埃。 ’、 、之後進打一退火製程,溫度大抵大於400 °C ;利用CVD 法(導入WFe及Si扎或I等氣體)於犧牲層3〇上沉積一導電 層,如鎢金屬層且填入介層窗5〇内,其中導電層將介層窗 50,滿。然後,去除介層窗5〇以外之導電層,以形成導電 插塞70-,亦即施以平坦化步驟,以形成導電插塞7〇,如第 8圖所不。上述去除介層窗5〇以外之導電層的方法包括化 學機械研磨法。上述導電插塞7〇之厚度大抵介於3〇⑽至 4 0 0 0埃之間。 最後,凹蝕至少部分之犧牲層3 〇,並留下部分的犧牲 層30a,使導電插塞70突出其周圍之表面,如第9圖所示。 =上述導電插塞70突出其周圍之表面大抵2〇〇至3〇〇埃,本 實施例中導電插塞7〇的上表面高於犧牲層3〇a的上表面。 上述凹银步驟係利用稀釋之氫氟酸(Di luted2 3 Ο 0 angstroms. - In accordance with a preferred embodiment of the present invention, Figures 7 and 8 are used to illustrate the method of the conductive interposer 7 成, the method of the method, the bottom of the via 5 Q and the sidewall surface. The barrier layer 6 is formed by a deposition method, as shown in Fig. 7 of Shikou. The barrier layer 60 is formed, for example, by a LPCVD method to form a titanium nitride layer having a thickness of about 2 〇〇 to _ Egypt. A titanium (Tl) layer is formed by a PVD method, and the thickness of the basin is substantially between 200 and 30,000. Ai. ', and then an annealing process, the temperature is greater than 400 °C; CVD method (introduction of WFe and Si or I gas) deposited a conductive layer on the sacrificial layer 3, such as tungsten metal layer and filled in The layer window 5 is inside, wherein the conductive layer will be filled with the via 50. Then, the conductive layer other than the via 5 去除 is removed to form a conductive plug 70-, i.e., a planarization step is applied to form the conductive plug 7 〇 as shown in Fig. 8. The above method of removing the conductive layer other than the via 5 包括 includes a chemical mechanical polishing method. The thickness of the conductive plug 7 is substantially between 3 〇 (10) and 400 Å. Finally, at least a portion of the sacrificial layer 3 is recessed and a portion of the sacrificial layer 30a is left to cause the conductive plug 70 to protrude from the surface around it, as shown in FIG. = The above-mentioned conductive plug 70 protrudes from the surface around it by about 2 〇〇 to 3 〇〇, and the upper surface of the conductive plug 7 本 in the present embodiment is higher than the upper surface of the sacrificial layer 3 〇 a. The above concave silver step utilizes diluted hydrofluoric acid (Di luted
Hydrofluoric Acid ;DHF)以濕蝕刻部分之犧牲層⑽。其 中,抗反射層及上述犧牲層對DHF之蝕刻速率為1 : 8。依、 照本發明另一較佳實施例,上述凹蝕步驟包括去除所有又之 上述犧牲層3 0,直到露出上述抗反射層2 〇為止。Hydrofluoric Acid; DHF) wet-etched a portion of the sacrificial layer (10). The etch rate of the anti-reflective layer and the sacrificial layer to DHF is 1:8. According to another preferred embodiment of the present invention, the etching step includes removing all of the sacrificial layers 30 until the anti-reflective layer 2 露出 is exposed.
1248199 五、發明說明(5)1248199 V. Description of invention (5)
依照本發明一較佳實施例,第丨〇至丨2圖用於說明導線 90的形成方法,包括:沉積第二介電層8〇於上述基底上且 覆蓋上述導電插塞70,如第1〇圖所示。接著,在上述第二 介電層80形成一開口 85,如第11圖所示。然後,在上述開 口 85形成一導線90,並與上述導電插塞7〇接觸。其中,上 述導電插塞70突出之部分包括一上表面10Q與侧壁11〇,且 上述導線90與部分之上述上表面1()()及上述侧壁丨1()均形成 ,觸,如第12圖所示。其中,上述第二介電層8〇包括一二 氧化矽層,其厚度大抵介於2Q00至3〇〇〇埃。 依照本發明一較佳實施例 ,塞,包括:一基底2、一導電區域7、第一介電層i、一 几反射層20、一犧牲層3〇a、一阻障層60、一導電插塞7〇 犧it介矣電層二、以及一導線9〇。其中,導電插塞〜"交 Ξ導f:/::人之部分包括-上表面100與側壁11〇, ^線90貝牙弟二介電層8〇盥上述 均形成接觸。 /、上边之上表面100及側壁110 雖然本發明已以數個較佳實施例 用以限定本發日月,任何熟習 :、其亚非 精神和範圍内,當可作任音之不脫離本發明之 保護範圍當視後附之申請;部,因此本發明之 T明寻利耗圍所界定者為準。In accordance with a preferred embodiment of the present invention, the second to fourth figures are for explaining a method of forming a wire 90, comprising: depositing a second dielectric layer 8 on the substrate and covering the conductive plug 70, such as the first This picture shows. Next, an opening 85 is formed in the second dielectric layer 80 as shown in Fig. 11. Then, a wire 90 is formed at the opening 85 and is in contact with the above-mentioned conductive plug 7A. The protruding portion of the conductive plug 70 includes an upper surface 10Q and a sidewall 11〇, and the conductive wire 90 and the upper surface 1() of the portion and the sidewall 丨1 are formed, such as Figure 12 shows. Wherein, the second dielectric layer 8 includes a germanium dioxide layer, and the thickness thereof is substantially between 2Q00 and 3 〇〇〇. According to a preferred embodiment of the present invention, the plug includes a substrate 2, a conductive region 7, a first dielectric layer i, a reflective layer 20, a sacrificial layer 3A, a barrier layer 60, and a conductive layer. The plug 7 it it 矣 矣 矣 矣 electrical layer 2, and a wire 9 〇. Wherein, the conductive plug ~ " cross-lead f: /:: the human part includes - the upper surface 100 and the side wall 11 〇, ^ line 90 牙 弟 二 2 dielectric layer 8 〇盥 all of the above contact. / upper upper surface 100 and side wall 110 Although the present invention has been used in several preferred embodiments to define the date of the present invention, any familiarity: its sub-ethnic spirit and scope, The scope of protection of the invention is to be determined by the appended claims; therefore, the invention is defined by the scope of the invention.
1248199 圖式簡單說明 第1至1 2圖為一系列剖面圖,用以說明本發明一較佳 實施例製作導電插塞的流程。1248199 BRIEF DESCRIPTION OF THE DRAWINGS Figures 1 through 2 2 are a series of cross-sectional views for illustrating the flow of a conductive plug in accordance with a preferred embodiment of the present invention.
件底電 元基導 , 产·-rc 《《《((( 要~ ~ 0000500000 J271233345678 主 rL 明 說 weu !# 符 域 區 層; 電層 介射 - 層 層圖窗層插介 反牲t4i阻阻層障電二 第抗犧彳光光介阻導第 案 •, 層 塞電 8 5〜開口 ; 9 0〜導線; 100〜導電插塞之上表面; 11 0〜導電插塞之側壁。The bottom element of the unit is the base conductor, the production ·-rc "" (((~(~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The layer barrier electric second resistance to sacrificial light and light blocking guide case •, layer plug electric 8 5 ~ opening; 9 0 ~ wire; 100 ~ conductive plug upper surface; 11 0 ~ conductive plug side wall.
0548-A50295TWf(5.0) ; 93021 ; Forever769.ptd 第13頁0548-A50295TWf(5.0) ; 93021 ; Forever769.ptd Page 13
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW94108023A TWI248199B (en) | 2005-03-16 | 2005-03-16 | Conductive plug and method of making the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW94108023A TWI248199B (en) | 2005-03-16 | 2005-03-16 | Conductive plug and method of making the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TWI248199B true TWI248199B (en) | 2006-01-21 |
| TW200635032A TW200635032A (en) | 2006-10-01 |
Family
ID=37400765
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW94108023A TWI248199B (en) | 2005-03-16 | 2005-03-16 | Conductive plug and method of making the same |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI248199B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12272561B2 (en) | 2022-06-01 | 2025-04-08 | Nanya Technology Corporation | Method for manufacturing semiconductor device |
| US12315734B2 (en) | 2022-06-01 | 2025-05-27 | Nanya Technology Corporation | Method for manufacturing semiconductor device |
| TWI841057B (en) * | 2022-06-01 | 2024-05-01 | 南亞科技股份有限公司 | Method for manufacturing semiconductor device |
-
2005
- 2005-03-16 TW TW94108023A patent/TWI248199B/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| TW200635032A (en) | 2006-10-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4152276B2 (en) | Semiconductor device using nitride film formed by low temperature atomic layer deposition as an etching stop layer and method for manufacturing the same | |
| US7741222B2 (en) | Etch stop structure and method of manufacture, and semiconductor device and method of manufacture | |
| TWI270178B (en) | Ferroelectric random access memory capacitor and method for manufacturing the same | |
| CN101587860B (en) | Method for fabricating semiconductor device | |
| TWI271799B (en) | An innovation method to resolve arcing problem | |
| TW201742285A (en) | Method for forming integrated circuit and capacitor | |
| TWI237871B (en) | Method of forming contacts for memory device | |
| JP2005136414A (en) | CAPACITOR, SEMICONDUCTOR ELEMENT HAVING SAME, AND METHOD FOR MANUFACTURING SAME | |
| TW201203518A (en) | Method for fabricating bottom electrode of capacitors of DRAM | |
| KR100413606B1 (en) | Method for fabricating capacitor | |
| JP4282616B2 (en) | Manufacturing method of semiconductor device | |
| CN100524753C (en) | Semiconductor device and method for fabricating the same | |
| WO2022147986A1 (en) | Semiconductor structure and manufacturing method therefor | |
| TWI248199B (en) | Conductive plug and method of making the same | |
| US6977418B2 (en) | Low resistance semiconductor process and structures | |
| JP2006114896A (en) | Method for manufacturing semiconductor device, method for forming etching stop layer having resistance to wet etching, and semiconductor device | |
| KR100555505B1 (en) | Connected contact formation method that realizes an extended open line width at the bottom of contact hole by depositing and removing silicide layer | |
| CN108364953B (en) | Three-dimensional memory device and device protection method in its manufacturing process | |
| KR20100093925A (en) | Method for fabricating cylinder type capacitor in semicondutor device | |
| US7776707B2 (en) | Method for manufacturing dielectric memory | |
| TWI875329B (en) | Semiconductor structure and manufacturing method thereof | |
| JP2006191053A (en) | Manufacturing method of semiconductor memory device | |
| TWI351736B (en) | Methods for forming a semiconductor device | |
| TWI336930B (en) | Methods for forming a bit line contact | |
| TW200919638A (en) | Metal line in semiconductor device and fabricating method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MK4A | Expiration of patent term of an invention patent |