1247433 15379twf.doc/g 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體元件及其製作方法，且特 別是有關於一種薄膜電晶體及其製作方法。 【先前技術】 薄膜電晶體(TFT)—般包括閘極、閘絕緣層、通道層 與源極/汲極，其通常在顯示器中，例如是如液晶顯示器 (LCDj，是作為開關元件之用。通常，薄膜電晶體的形成 方法是在基底上依序形成閘極、閘絕緣層、a_Si通道層與 源極/没極。閘極是由銘、絡、鎢、组、鈦等的單一金属層 或是由複數金屬層所組成。 然而，导以單一層的上述金屬形成閘極時，膜層表面 容易被做，且料魏反應而形成金射…物，因而導 ^在後續的似|燦程中紐有效地進行侧。另一方面， 二閘極是域層金屬層所組柄，其例如為鉬(施)辅目， 二和侵姓的問題。但是形成數層金屬層的製程 材以及、㈤為此製程需要超過—個以上的減鑛輕 源極此外，上制題㈣齡射在形成 【發明内容】 電阻5電3=提出—種薄膜電晶體，其具有較低接觸 %阻次、、泉電阻的閘極與源極/汲極。 本發明另提出一種薄膜電晶體的形成方法， 和抗侵崎梢細細極和咖極/汲極。 1247433 15379twf.doc/g 本發明係提出-種薄膜電晶體，此薄膜電晶體包括間 極、閘絕緣層、半導體層以及源極/汲極。閘鋪配置於基 底上，'其中，閘極包括至少—層氮化她合金。閘絕緣層 係形成於基底上以覆蓋祕。半導體層係配置於基底上之 閘絶緣層上。源極/>及極係配置於半導體層上。 本發明另提出一種薄膜電晶體‘，此薄曰膜電晶體包括閘 極、閘絕緣層、半導體相及源極/汲極。祕係配置於基 底上。_緣層係形成於基底上哺蓋·。半導體層係 配置於基底上n緣層上。雜/ & _配置於半導體層 上’其中’源極/沒極包括至少一層氮化紹紀合金。 尸在本發明-實施例中，上述之間極係由錄合金層與 氮化鋁纪合金層所組成。 入在本發明一實施例中，上述之問極係由第一氣化細乙 &金層、她合金層與第二氮化她合金層所組成。 f本發明一實施例中，上述之源極/汲極係由她合金 層與氮化紹紀合金層所組成。 在本购—實施射，上述之齡織極係由第-氮化 航合金層、減合金層與第二氮化诚合金層所組成。 本發明另提出「_膜.電晶體的形成方法，此方法先 ^基底上形成閘極。其中’閘極包括至少—層氮化減合 =°然後’於基底上形賴絕緣層以覆蓋閘極。之後，於 基底上的_緣層上配置半導體層^下來，於半導體層 上配置源極/汲極。 本發明又提出一種_電晶體的形成方法，此方法係 1247433 15379twf.doc/g $於基底上形成閘極。接著，於基底上形成閘絕緣層以覆 蓋閘極。之後，於基底上的閘絕緣層上形成半導體層。接 下來，於半導體層上形成源極/汲極。其中，源極/汲極包 括至少一層氮化鋁釔合金。 在本發明-實施例中，上述之閘極和(或)源極/汲極係 以下述之步驟形成。首先於基底上形成鋁釔合金層。並且 • ，鋁釔合金層進行氮化步驟，以形成氮化鋁釔合金層。接 • 著將氮化鋁釔合金層圖案化以形成閘極和（或)源極/汲極。 /在本發明之-實施例中，上述之閘極和(或)源極/沒極 係以下述之步成。首先於基底上形成第—射乙合金 層^後於第-減合金層上形成第二減合金層。並且 , 對第，1祕合金層進行氮化步驟，⑽第—減合金層上 形成氮化她合金層。之後將氮化紹紀合金層與第一紹紀 合金層圖案化以形成閘極和（或)源極/汲極。 /林發明之-實施例中，上述之閘極和(或)源極/汲極 #、以下述之步_成。首先，於基底上軸第—減合金 擊 @。並且，對第-減合金層進行第—氮化步驟，以形成 ' ^氮化她合金層。接著，於第—氮化減合金層上形 • iU二減合金層。之後，於第二氮化減合金層上形成 弟三減合金層。並且，對第三她合金層進行第二氮化 步，’以於第二合金層上形成第二氮化減合金層。 接著，將第二氮化減合金層、第二銘紀合金層與第一氮 化她合金層®案化，以形成_和⑷雜/汲極。 ' 本發明之薄膜電晶體的電極(閘極和（或)源極/没極）包 1247433 15379twf.doc/g 比較起來 佳的抵抗性 一二層氮化鋁釔合金，其因為在鋁釔合金的表面上有 一I:，保護薄膜，所以與習知技術中使用的金屬合金 • ° "，較為穩定，以致於電極對於氧化與侵蝕具有較 為縣發明之上述和其他目的、特徵和優點能更明顯 紅’下文特舉較佳實闕，並配合賴㈣，作詳細說 %如下。 【實施方式】 圖二繪不為依照本發明一較佳實施例之薄膜電晶體的 二面不意圖。請參照圖1，薄膜電晶體包括閘極102、閘絕 酉層104、半導體層105以及源極/汲極110。閘極102係 配置於基底1〇〇上，而閘絕緣層1〇4係配置於基底1㈨上 方以覆夢間極102。間絕緣層1〇4例如是由氧化石夕層、氮 匕矽層或氧化矽層與氮化矽層的組合層所構成。半導體層 W5係配置於閘極1〇2上方的閘絕緣層ι〇4上。汲 U0係配置於半導體層1〇5上。在本實施例中，半導體層 105例如包括形成於閘絕緣層104上的通道層106與形成 於通道層106和源極/汲極11〇之間的歐姆接觸層丨〇8。 I特別是，依照本發明之一較佳實施例，閘極1〇2包括 至J 一層氮化鋁釔合金。換句話說，閘極1〇2可以是單層 =氮化鋁釔合金或包括至少一層氮化鋁釔合金的複合層。 右閘極102為單層，則閘極1〇2係由氮化鋁釔合金層所組 成。在本實施例中，形成單層之閘極1〇2的方法如以下步 里取 ， ^首先’在錢鑛製程室、蒸鍍製程室或其他習知的沈積 1247433 15379twf.doc/g 至中，於基底100上形成一層鋁釔合金層。並且，對鋁釔 合金層進行氮化步驟，以形成氮化鋁釔合金層。其中，上 述之氮化步驟例如是在形成鋁記合金層之後，於沈積室中 通入氮氣即可。或者是，於形成鋁釔合金層的同時通入氮 氣至’尤積至中，以形成氮化銘紀合金層。之後，利用微影 製私與钱刻製程將氮化紹紀合金層圖案化，以形成閘極 102 〇 右間極102為雙層結構’則間極1 〇2係由铭紀合金層 102a與氮化鋁釔合金層i〇2b所組成。請參照圖2A，在本 例中’形成雙層閘極102的方法如以下步驟。首先，於基 底100上形成第一铭紀合金層l〇2a。然後，於第一铭紀合 金層102a上形成第二鋁釔合金層（未繪示）。並且，對第二 紹紀合金層進行氮化反應步驟，以形成氮化鋁釔合金層 102b。之後，將氮化鋁釔合金層1〇2b與第一鋁釔合金層 102a圖案化，以形成閘極1〇2。第一鋁紀合金層i〇2a與第 一紹紀合金層係以先前所述的方法所形成，而氮化反應步 驟也是以先前所述的相同方法進行。 若閘極102為三層結構，則閘極102係由第一氮化鋁 妃合金層102c、鋁纪合金層l〇2d以及第二氮化鋁紀合金 層102e所組成，請參照圖3A。在本實施例中，形成三層 之閘極102的方法如以下步驟。首先，於基底1〇〇上形成 第一鋁釔合金層（未繪示）。並且，對第一鋁釔合金層進行 如上述之氮化步驟，以形成第一氮化鋁纪合金層l〇2c。然 後，於第一氮化鋁釔合金層l〇2c上形成第二鋁釔合金層 1247433 15379twf.doc/g 102d。接著，於第二鋁釔合金層102d上形成第三鋁釔合金 層（未繪示）。並且，對第三鋁釔合金層進行如上述之氮化 步驟，以形成第二氮化鋁釔合金層1〇2e。然後，將第二氮 化銘紀合金層l〇2e、第二鋁釔合金層i〇2d以及第一氮化 紹釔合金層l〇2c圖案化，以形成閘極1〇2。 在另一貫加例中’源極/>及極110包括至少一層氮化銘 名乙合金’凊參照圖1。換句話說，源極/j；及極1可以是單 . 層的氮化紹紀合金或包括至少一層氮化銘記合金的複合 層。若源極/汲極110為單層，則源極/汲極11()係由氮化 鋁釔合金層所組成。同樣地，形成單層源極/汲極11()的方 法如以下步驟。首先，在濺鍍製程室、蒸鍍製程室或其他 熟知的沈積室中，於閘絕緣層104上形成鋁釔合金層，以 覆蓋半導體層105。並且，對鋁釔合金層進行氮化步驟， 以形成氮化鋁釔合金層，其中，上述之氮化步驟例如是在 形成鋁釔合金層之後，於沈積室中通入氮氣即可。或者是， 於形成紹紀合金層的同時通入氮氣至沈積室中，以形成氮 ►化鋁釔合金層。之後'，將氮化鋁釔合金層圖案化，以形成 源極/汲極110。 若源極/汲極110為雙層結構，則源極/汲極11〇係由 銘紀合金層110a與氮化鋁釔合金層110b所組成，請參照 圖2B。同樣地，形成雙層之源極/汲極11()的方法如以下 步驟。首先，於閘絕緣層104上形成第一鋁釔合金層n〇a， 以覆蓋半導體層105。然後，於第一鋁紀合金層n〇a上形 成第二鋁釔合金層（未繪示）。並且，對第二鋁釔合金層進 1247433 15379twf.doc/g 行氮化步驟，以形成氮化鋁釔合金層110b。之後，將氮化 鋁釔合金層ll〇b與第一鋁釔合金層ii〇a圖案化，以形成 源極/汲極110。第一紹纪合金層ll〇a與第二紹紀合金層係 以先前所述的方法所形成，而氮化步驟也是以先前所述的 相同方法進行。 當源極/汲極110為三層結構，則源極/汲極U0係由 八 第一氮化鋁釔合金層110c、鋁釔合金層ii〇d以及第二氮 φ 化鋁釔合金層110e所組成，請參照圖3B。相同地，形成 三層之源極/汲極110的方法如以下步驟。首先，於閘絕緣 層104上形成第一鋁釔合金層（未繪示），以覆蓋半導體層 105。並且，對第一鋁釔合金層進行如上述之氮化步驟，以 形成第一氮化鋁釔合金層ll〇c。然後，於第一氮化鋁釔合 金層110c上形成第二鋁釔合金層11〇d。接著，於第二鋁 釔，金層110d上形成第三鋁釔合金層（未繪示）。並且，對 第三銘紀合金層進行如上述之氮化步驟，以形成第二氮化 铭紀合金層ll〇e。然後，將第二氮化鋁釔合金層u〇e、第 • 二尬合金層UGd以及第-氮化減合金層llGc圖案 - 化，以形成源極/汲極110。 、在，貝知例中，閘極102與源極/汲極110皆包括至 J 一層氮化魏合金層。換句話說，閘極1()2與源極/汲極 =皆可=是單層的氮化銘齡金或包括至少-層氮化紹 人爲金的複^層。上述包括至少一層氮化鋁釔合金層的複 〇 &可以疋雙層結構或三層結構，請參照圖2A、圖2B、 圖3A以及圖2B。 11BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor device and a method of fabricating the same, and in particular to a thin film transistor and a method of fabricating the same. [Prior Art] A thin film transistor (TFT) generally includes a gate, a gate insulating layer, a channel layer, and a source/drain, which is usually used in a display such as, for example, a liquid crystal display (LCDj) as a switching element. Generally, a thin film transistor is formed by sequentially forming a gate, a gate insulating layer, an a_Si channel layer, and a source/danopole on a substrate. The gate is a single metal layer of Ming, Luo, Tung, Titanium, etc. Or consisting of a plurality of metal layers. However, when a single layer of the above-mentioned metal is used to form a gate, the surface of the film layer is easily made, and the material reacts to form a gold-emitting object, and thus the lead is in the subsequent Cheng Zhongxin effectively performs the side. On the other hand, the two gates are the handles of the domain metal layer, which are, for example, the molybdenum (application) auxiliary, the second and the invading problem. However, the process material for forming several metal layers is formed. And (5) for this process, more than one or more of the ore-reducing light source is required. In addition, the above-mentioned problem (four) age is formed. [Inventive content] Resistor 5 electricity 3 = proposed thin film transistor with lower contact % resistance The gate of the secondary, spring resistance and the source/drain. The present invention A method for forming a thin film transistor, and an anti-aggression fine pole and a coffee pole/dip pole are proposed. 1247433 15379twf.doc/g The present invention proposes a thin film transistor including a interlayer electrode and a gate insulating layer. a layer, a semiconductor layer, and a source/drain. The gate is disposed on the substrate, wherein the gate includes at least a layer of nitrided alloy. The gate insulating layer is formed on the substrate to cover the secret. The semiconductor layer is disposed on the substrate. On the insulating layer of the upper gate, the source/> and the pole are disposed on the semiconductor layer. The present invention further provides a thin film transistor which includes a gate, a gate insulating layer, a semiconductor phase and a source /Bunge. The secret system is disposed on the substrate. The edge layer is formed on the substrate. The semiconductor layer is disposed on the n-edge layer on the substrate. The impurity / & _ is disposed on the semiconductor layer 'where the source / immersing comprises at least one layer of nitriding alloy. In the present invention - the embodiment, the intermediate layer is composed of a recorded alloy layer and an aluminum nitride alloy layer. In an embodiment of the invention, The first line is made of the first gasified fine B & gold layer The alloy layer and the second nitrided alloy layer are composed of the same. In an embodiment of the invention, the source/drainage system is composed of a layer of the alloy and a nitrided alloy layer. The above-mentioned age is composed of a first-nitriding alloy layer, a reduced alloy layer and a second nitrided alloy layer. The present invention further proposes a method for forming a film of a transistor. Forming a gate thereon, wherein the 'gate includes at least one layer of nitride reduction=° and then the insulating layer is formed on the substrate to cover the gate. Thereafter, the semiconductor layer is disposed on the layer on the substrate. The source/drain is disposed on the semiconductor layer. The present invention further provides a method of forming a transistor, which is 1247433 15379 twf.doc/g $ forms a gate on the substrate. Next, a gate insulating layer is formed on the substrate to cover the gate. Thereafter, a semiconductor layer is formed on the gate insulating layer on the substrate. Next, a source/drain is formed on the semiconductor layer. Wherein, the source/drain includes at least one layer of aluminum nitride. In the present invention-embodiment, the above-described gate and/or source/drain are formed in the following steps. First, an aluminum-bismuth alloy layer is formed on the substrate. And • the aluminum-niobium alloy layer is subjected to a nitriding step to form an aluminum nitride tantalum alloy layer. A layer of aluminum nitride bismuth alloy is patterned to form a gate and/or a source/drain. / In the embodiment of the invention, the above-mentioned gate and/or source/no-pole are formed in the following steps. First, a first alloy layer is formed on the substrate, and then a second alloy layer is formed on the first-minus alloy layer. Further, a nitriding step is performed on the first, first alloy layer, and a nitrided alloy layer is formed on the (10) first-minus alloy layer. The nitrided alloy layer is then patterned with the first Saoki alloy layer to form a gate and/or source/drain. In the embodiment, the above-mentioned gate and/or source/drainage # are formed in the following steps. First, the first axis on the substrate is reduced to the alloy. Further, the first-nitriding layer is subjected to a first nitridation step to form a '^ nitrided alloy layer. Next, an iU diminishing alloy layer is formed on the first-nitrided alloy layer. Thereafter, a third reduction alloy layer is formed on the second nitride-reduced alloy layer. And, a second nitridation step is performed on the third alloy layer to form a second nitride-reduced alloy layer on the second alloy layer. Next, the second nitrided alloy layer, the second alloy layer and the first nitrided alloy layer are patterned to form _ and (4) hetero/deuterium. The electrode of the thin film transistor of the present invention (gate and/or source/no-pole) package 1247433 15379twf.doc/g is a better resistance to a two-layer aluminum nitride tantalum alloy, which is used in aluminum-bismuth alloy. There is an I:, protective film on the surface, so it is more stable with the metal alloy used in the prior art, so that the electrode has more of the above and other purposes, features and advantages of the county invention for oxidation and erosion. Obviously red' The following is a better example, and with Lai (4), the details are as follows. [Embodiment] FIG. 2 is not a schematic view of a two-sided film transistor according to a preferred embodiment of the present invention. Referring to FIG. 1, the thin film transistor includes a gate 102, a gate insulating layer 104, a semiconductor layer 105, and a source/drain 110. The gate 102 is disposed on the substrate 1B, and the gate insulating layer 1〇4 is disposed above the substrate 1 (9) to cover the dream pole 102. The interlayer insulating layer 1〇4 is composed of, for example, a combination of a oxidized stone layer, a ruthenium nitride layer, or a ruthenium oxide layer and a tantalum nitride layer. The semiconductor layer W5 is disposed on the gate insulating layer ι 4 above the gate electrode 1〇2.汲 U0 is disposed on the semiconductor layer 1〇5. In the present embodiment, the semiconductor layer 105 includes, for example, a channel layer 106 formed on the gate insulating layer 104 and an ohmic contact layer 8 formed between the channel layer 106 and the source/drain 11b. In particular, in accordance with a preferred embodiment of the present invention, gate 1 〇 2 includes a layer of aluminum nitride bismuth alloy to J. In other words, the gate 1〇2 may be a single layer = an aluminum nitride tantalum alloy or a composite layer comprising at least one layer of aluminum nitride tantalum alloy. The right gate 102 is a single layer, and the gate 1〇2 is composed of an aluminum nitride-bismuth alloy layer. In this embodiment, the method of forming the gate 1〇2 of a single layer is as follows: ^ Firstly, in the money processing room, the evaporation process chamber or other conventional deposition 1247433 15379twf.doc/g to A layer of an aluminum-bismuth alloy is formed on the substrate 100. Further, a step of nitriding the aluminum-niobium alloy layer is performed to form an aluminum nitride-ruthenium alloy layer. Here, the nitriding step may be, for example, after the aluminum alloy layer is formed, and nitrogen gas may be introduced into the deposition chamber. Alternatively, nitrogen gas may be introduced into the aluminum-bismuth alloy layer to form a nitrided alloy layer. After that, the nitriding alloy layer is patterned by the lithography and the engraving process to form the gate 102. The right interpole 102 is a two-layer structure, and the interpole 1 〇2 is composed of the Mingji alloy layer 102a and The aluminum nitride tantalum alloy layer i〇2b is composed. Referring to Fig. 2A, the method of forming the double-layer gate 102 in this example is as follows. First, a first alloy layer l〇2a is formed on the substrate 100. Then, a second aluminum-bismuth alloy layer (not shown) is formed on the first layer of the alloy layer 102a. Further, a second nitriding alloy layer is subjected to a nitridation reaction step to form an aluminum nitride bismuth alloy layer 102b. Thereafter, the aluminum nitride tantalum alloy layer 1〇2b is patterned with the first aluminum-niobium alloy layer 102a to form the gate electrode 1〇2. The first aluminum alloy layer i〇2a and the first Shaoji alloy layer are formed in the manner previously described, and the nitridation reaction step is also carried out in the same manner as previously described. If the gate 102 has a three-layer structure, the gate 102 is composed of a first aluminum nitride yttrium alloy layer 102c, an aluminum alloy layer 〇2d, and a second aluminum nitride alloy layer 102e. Please refer to FIG. 3A. In the present embodiment, the method of forming the gate 102 of the three layers is as follows. First, a first aluminum-bismuth alloy layer (not shown) is formed on the substrate 1A. Further, the first aluminum-niobium alloy layer is subjected to a nitridation step as described above to form a first aluminum nitride alloy layer 10c. Then, a second aluminum-bismuth alloy layer 1247433 15379 twf.doc/g 102d is formed on the first aluminum nitride-bismuth alloy layer 10c. Next, a third aluminum-niobium alloy layer (not shown) is formed on the second aluminum-niobium alloy layer 102d. Further, the third aluminum-niobium alloy layer is subjected to a nitridation step as described above to form a second aluminum nitride-bismuth alloy layer 1〇2e. Then, the second nitriding alloy layer l〇2e, the second aluminum bismuth alloy layer i〇2d, and the first nitriding alloy layer l〇2c are patterned to form the gate 1〇2. In another example, the 'source/> and the pole 110 include at least one layer of nitriding alloy B. Referring to Figure 1. In other words, the source /j; and the pole 1 may be a single layer of nitrided alloy or a composite layer comprising at least one layer of nitrided alloy. If the source/drain 110 is a single layer, the source/drain 11 () is composed of an aluminum-niobium alloy layer. Similarly, the method of forming the single-layer source/drain 11 () is as follows. First, an aluminum-bismuth alloy layer is formed on the gate insulating layer 104 to cover the semiconductor layer 105 in a sputtering process chamber, an evaporation process chamber, or other well-known deposition chamber. Further, the aluminum-bismuth alloy layer is subjected to a nitriding step to form an aluminum nitride-bismuth alloy layer, wherein the nitriding step is carried out, for example, after the aluminum-bismuth alloy layer is formed, and nitrogen gas is introduced into the deposition chamber. Alternatively, nitrogen gas is introduced into the deposition chamber while forming a layer of the Shaoji alloy to form a nitrogen-alloyed aluminum alloy layer. Thereafter, the aluminum nitride bismuth alloy layer is patterned to form a source/drain 110. If the source/drain 110 is of a two-layer structure, the source/drain 11 is composed of an alloy layer 110a and an aluminum nitride alloy layer 110b. Please refer to Fig. 2B. Similarly, the method of forming the double-layer source/drain 11 () is as follows. First, a first aluminum-bismuth alloy layer n〇a is formed on the gate insulating layer 104 to cover the semiconductor layer 105. Then, a second aluminum-bismuth alloy layer (not shown) is formed on the first aluminum alloy layer n〇a. Further, the second aluminum-bismuth alloy layer is subjected to a nitridation step of 1247433 15379 twf.doc/g to form an aluminum nitride-bismuth alloy layer 110b. Thereafter, the aluminum bismuth alloy layer 11b and the first aluminum-bismuth alloy layer ii〇a are patterned to form the source/drain 110. The first Shaoji alloy layer 11a and the second Shaoji alloy layer are formed by the method previously described, and the nitriding step is also carried out in the same manner as previously described. When the source/drain 110 is a three-layer structure, the source/drain U0 is composed of an eight first aluminum nitride alloy layer 110c, an aluminum-niobium alloy layer ii〇d, and a second nitrogen-aluminized aluminum alloy layer 110e. Please refer to FIG. 3B for the composition. Similarly, the method of forming the three-layer source/drain 110 is as follows. First, a first aluminum-bismuth alloy layer (not shown) is formed on the gate insulating layer 104 to cover the semiconductor layer 105. Further, the first aluminum-niobium alloy layer is subjected to a nitridation step as described above to form a first aluminum nitride-bismuth alloy layer 11c. Then, a second aluminum-niobium alloy layer 11〇d is formed on the first aluminum nitride tantalum alloy layer 110c. Next, a third aluminum-bismuth alloy layer (not shown) is formed on the second aluminum layer and the gold layer 110d. Further, the third etched alloy layer is subjected to a nitriding step as described above to form a second nitriding alloy layer 11〇e. Then, the second aluminum nitride ruthenium alloy layer u〇e, the second bismuth alloy layer UGd, and the first-nitride reduction alloy layer llGc are patterned to form the source/drain 110. In the example, the gate 102 and the source/drain 110 include a layer of nitrided Wei alloy to J. In other words, the gate 1()2 and the source/drainage = can be a single layer of nitriding age gold or a layer comprising at least a layer of nitrided gold. The above composite layer comprising at least one layer of aluminum nitride bismuth alloy may be a two-layer structure or a three-layer structure. Please refer to FIGS. 2A, 2B, 3A and 2B. 11
1247433 15379twf.doc/g 值得注意的是，因為在銘纪合金的表面上係有— 化物保瘦細’所以纪合金層與習知技術中的金^ 合金比較妓更為穩定，以致於氮化尬合金層對於氧化 與侵兹具妹佳的抵抗性。換姑說，包括至少— 銘紀合金層的薄膜電晶體的電極對於氧化與錢具^較户 2抵抗性。特财，若軸三層的或三層的源極/沒^ 蚪’铭紀合金層會.夾在二層氮化銘紀合金層中間，以避 症呂紀合金層被氧化與侵姓。 α 另外銘紀5孟層的沈積製程以及氮化反應步驟，可 以在相_反魅(原位）巾進行。若形成雙層結構或三層 結構時，也可以在相同的反應室(原位）中進行。因此，^ 發明的.與㈤祕/汲極的製程並不獅，因 製程生產力。 开 一值得注意的是，若本發明之薄膜t晶體是作為液晶顯 示器的開關元件時，对使用雙層或三層的源極/沒極時， 在後續各晝素結構的接觸窗開口的蝕刻製程中，上層氮化 銘紀合金層表面的氮化物薄膜還可以當作姓刻終止^。 雖然本發明已以較佳實施例揭露如上，然其並^用以 限定本發明，任何熟習此技藝者，在不麟本發明之精神 t範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1繪示為依照本發明一較佳實施例之薄膜電晶體的 剖面示意圖。 _ 12 1247433 15379twf.doc/g 體的=:=::明另-較佳實施例之薄膜&脚之薄膜電 晶 曰曰1247433 15379twf.doc/g It is worth noting that, because the surface of the alloy is bonded to the surface of the alloy, the alloy layer is more stable than the gold alloy in the prior art, so that it is nitrided. The bismuth alloy layer is resistant to oxidation and intrusion. According to the exchange, the electrode of the thin film transistor including at least the alloy layer is resistant to oxidation and money. Special wealth, if the axis of the three-layer or three-layer source / no ^ 蚪 ' Ming Ji alloy layer will be sandwiched in the middle of the two layers of nitrite alloy layer, in order to avoid the oxidation of the alloy layer is oxidized and invaded. α In addition, the deposition process of the 5th layer and the nitridation reaction step can be carried out in the phase _ anti-magic (in situ) towel. If a two-layer structure or a three-layer structure is formed, it can also be carried out in the same reaction chamber (in situ). Therefore, the process of inventing and (5) secret/bungee is not a lion, because of process productivity. It is worth noting that if the thin film t crystal of the present invention is used as a switching element of a liquid crystal display, when a double/three-layer source/no-pole is used, etching of a contact window opening of each subsequent monocyte structure is performed. In the process, the nitride film on the surface of the upper nitriding alloy layer can also be terminated as a surname. Although the present invention has been disclosed in the above preferred embodiments, it is intended to limit the present invention, and those skilled in the art can make some modifications and refinements within the scope of the spirit of the present invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing a thin film transistor in accordance with a preferred embodiment of the present invention. _ 12 1247433 15379twf.doc / g body =: =:: Ming - the thin film of the preferred embodiment & film of the foot of the film 曰曰
圖3B繪示為依照本發明又—較佳實施例之薄膜電 體的三層源極/汲極的剖面示意圖。 【主要元件符號說明】 100 :基底 102 :閘極 102a、l〇2d、ll〇a、110d ··鋁記合金層 102b、l〇2c、l〇2e、110b、110c、ll〇e ··氮化鋁釔合 金層 104 :閘絕緣層 105 :半導體層 106 :通道層 108 ··歐姆接觸層 110 ·源極/沒極 13 d：3B is a cross-sectional view showing a three-layer source/drain of a thin film battery in accordance with still another preferred embodiment of the present invention. [Description of main component symbols] 100: Substrate 102: gate 102a, l〇2d, ll〇a, 110d · aluminum alloy layer 102b, l〇2c, l〇2e, 110b, 110c, ll〇e · nitrogen Aluminum bismuth alloy layer 104: gate insulating layer 105: semiconductor layer 106: channel layer 108 · ohmic contact layer 110 · source/dice 13 d: