TWI241772B - Phase-locked loops having a spread spectrum clock generator - Google Patents

Abstract

The phase-looked loop having spread spectrum clock generator of this invention comprises a phase-locked loop and a spread spectrum clock generator. The input signal of the phase-locked loop conies from a reference clock source. The output of the phase-locked loop is used as the standard clock signal and is also supplied to the spread spectrum clock generator, as its input. The spread spectrum clock generator comprises a clock frequency divider, a multiplexer and a counter. The clock frequency divider generates, based on the output of the phase-locked loop, at least tow of a divided-by-M frequency, a divided-by-M+1 frequency and a divided-by-M-1 frequency, which are supplied to the multiplexer. The selection code of the multiplexer is supplied by the counter, which input is supplied by the output of the multiplexer. The output signal of the multiplexer is supplied to the phase-locked loop, as its feedback clock frequency. Down spreading, up spreading and even spreading of the spectrum of the output standard clock are thus achieved.

Description

1241772 Case No. 92131735 Amendment of the fifth month, description of the invention (1) 1. [Technical field to which the invention belongs] The present invention relates to a phase-locked loop with a spread-spectrum clock signal generator ', and particularly to a method using a fixed phase step modulation (Fi X ed phase step modulation) to generate a phase-locked loop of a spread-spectrum clock signal. 2. [Previous Technology] In various digital electronic devices, such as personal computers, network communication devices, computer peripherals, and consumer electronics, quartz clock-out clock signal generating devices are required to provide correct clock signals. As a basis for system synchronization required for electronic equipment. However, due to the intensive movement of digital circuits, a large amount of electromagnetic interference (EMI) has been caused, so that these electronic devices must use additional waves and / or protective devices to reduce electromagnetic interference before they can be put into commercial use ^ In most countries, The specification for electromagnetic interference is mainly in the frequency / peak of the signal ", not its total energy. In various technologies for modulating electromagnetic interference, a 'spread spectrum clock signal generator' (S p r e a d s p c c t r u m 1 Qe k i ng, sSC) is widely used. Spread-spectrum clock signal generator Principle: The frequency of the clock signal is modulated periodically (pe r i 0 d i c a 1 1 y) to form a wider frequency domain distribution to reduce peaks. Phase-Locked Loops-PLL is a built-in block clock signal commonly used in electronic beta

Page 6 1241772 Case No. 92131735% Year_ ^ 1_ ^ Revision V. Description of Invention (2) The device is based on a precise clock signal source, such as a crystal oscillator (crysta 1 〇sci 1 1 at 〇r), provides Clock signal of the desired frequency. The spread-spectrum clock signal generator is built into the phase-locked loop, which can be used to provide a cost-effective clock signal source that meets electromagnetic interference specifications.

U.S. Patent No. 5,488,62 7 to Hardin et al. Provides a "Spread Spectrum Clock Generator and Associated Method". The invention provides a basic architecture for building a spread spectrum clock signal generator in a phase locked loop.

The phase-locked loop of the invention can change the voltage controlled oscillator (VC0) so that its output signal matches the input of the phase detector. The spread-spectrum clock generator, based on a clock pulse, widens and flattens the clock signal generated by the phase-locked loop.

Following the invention of Hard in et al., Other industry professionals have proposed other methods for using the phase-locked loop of the spread-spectrum clock signal generator. among them,

Sha U.S. Patent No. 6, 3 7 7, 64 6 proposes a "Spread Spectrum at Phase Lock Loop"

Feedback Path). According to the invention, the output of the phase-locked loop is fed back to a phase detector at the front end of the phase-locked loop as a component of its input via a feedback signal divider (f e d b a c k d i v i d e r). The output of the feedback " Lu No. divider is sent to a spread-spectrum clock signal generator. The spread-spectrum clock signal generator includes a counter, a 4-bit phase-locked spread-spectrum clock signal generator, a read-only memory, and an adder. The output of the divider (feedback divider) is to provide a modulated waveform to the output of the voltage-controlled oscillator, to expand it in a predetermined frequency band, and reduce its peak value. And the show

T241772 92131735 on page 7 Amendment V. Description of the invention (3) Frequency clock generator, which is used to determine its expanded frequency bandwidth (3, adjustment value of the taxi feedback divider to determine | a and V 夂 waveform) . In the U.S. patent of Sha, the machi program counter uses a counter output to calculate a fixed value according to the clock signal generator. A suitable code in the body (code magic " spread-spectrum clock signal generator read-only memory Γ, provided to the section ri 咚 1, to add to the base number (base number), and branch to the edge feedback division sketch method, then Is the minimum mean square, ^ r ^ is the adjustment value, and its ROM code produces LMS). In this type of frequency-spreading clock (= af — mean squared ', a read-only memory, —only ^ circuit, a counting divider must be used. Among them, the decoding "m: device,: adder, and-frequency clock signal generating circuit Making + U is more complicated. The cost is relatively low. Therefore, it is necessary to provide a phase-locked loop with a low-cost clock generator. Therefore, it is necessary to provide a circuit (or software) design. 】 It is also necessary to provide a phase-locked loop with a spread-spectrum clock signal generator in a different plant, which is less complicated. [Abstract] The purpose of this test is to provide a one-time clock signal generator. Phase-locked loop. Low-frequency has a spread spectrum. The purpose of the present invention is also to provide a simplified and complicated structure: a phase-locked loop with a spread-spectrum clock signal generator. The purpose of the M 3 + ^ is also to provide a utilization. Fixed phase; ^ β ^ + modulation method of phase-locked loop with spread-spectrum clock signal generator

Page 8 1241772 Case No. 92131735% year, month, month, and day of the month Amendment 5. Description of the invention (4) The phase-locked loop with a spread-spectrum clock signal generator according to the present invention includes a phase-locked loop and a spread-spectrum clock signal Generator. The input of the phase-locked loop is a reference clock signal, and its output is provided as an output clock signal to the spread-spectrum clock signal generator as an input. The frequency-spreading clock signal generator includes a clock frequency divider, a multiplexer, and a counter. The clock frequency divider generates an M-removed frequency signal, at least two of the M + 1 frequency signal and the M-1 frequency signal according to an output signal of the phase-locked loop, and supplies the signal to the multiplexer. The selection signal of the multiplexer comes from the counter, and the input signal of the counter comes from the output of the multiplexer. The signal output by the multiplexer is supplied to the phase locked loop as its feedback clock frequency. Fourth, [implementation method] The above and other objects and advantages of the present invention can be made clearer by the following detailed description and referring to the drawings. The following describes the phase-locked loop with a spread-spectrum clock signal generator according to the present invention based on the drawings. FIG. 1 is a circuit block diagram showing an embodiment of a phase-locked loop having a spread-spectrum clock signal generator according to the present invention.

As shown in the figure, the present invention has a phase-locked loop with a spread-spectrum clock signal generator. It basically includes a phase-locked loop (10) and a spread-spectrum clock signal generator (20). The phase-locked loop (1 0) includes a phase / frequency primary tester (1 1), a charge pump (12), a low-pass filter (1 3), and a voltage-controlled oscillator (1 4). ). The input of the phase / frequency detector (1 1) includes a reference clock signal refclk, which is a frequency signal mainly generated by a quartz oscillator and is formed after necessary processing. The output of the phase / frequency detector (1 1) includes a PUMP up signal and a PUMP

Page 9 1241772 Case No. 92131735 y Yueyue Amendment V. Description of the invention (5) The down signal is provided to the two switches (up) and (down) of the charge pump to control the action of the charge pump. After the voltage generated by the charge pump (12) is filtered by the low-pass filter (13), it is provided to the voltage-controlled oscillator (14) as the control voltage vctr1, so that the voltage-controlled oscillator (14) generates a clock Signal cl kout. The voltage controlled oscillator (14) may use any circuit that generates a clock frequency signal in response to an input control voltage. Generally speaking, a ring oscillator is an example. Since the structure of the phase-locked loop (10) is a known technique, anyone who is familiar with Siyi can easily complete it, and it is not the focus of the present invention, so I will not repeat it here.

The spread spectrum clock signal generator (20) of the present invention includes a clock frequency divider (21), a multiplexer (22), and a counter (23). The clock frequency divider (2 1) is a divider. Its input is the output clock signal clkout of the phase locked loop (10).

In the present invention, the clock frequency divider (21) uses a "Fi X edphasestep modulation" (fi X edphasestep modulation) to divide the output clock signal clkout of the phase-locked loop (10) by M and divide ( M + 1) processing. In another example of the present invention, the clock signal c 1 k 0 u t is subjected to an M removal process and a (M-1) process, respectively. In yet another example, the M removal process, the (M + 1) removal process, and the (M-1) removal process are performed separately. That is, the output frequency signal is at least two of M times, M + 1 times, and M-1 times the frequency of the reference clock signal re f c 1 k. The output frequency signal is sent to the input of the multiplexer (2 2). The multiplexer (2 2) can be a 2 to 1 or 3 to 1 multiplexer, and its selection signal comes from the counter (2 3). The counter (23) is a programmable counter, and its input is

Page 10 1241772 Case No. 92131735 9 April / Year Amendment 5. Description of the invention (6) Frequency signal generated by multiplexer (22). The counter (23) reads the frequency signal and sends a control signal to the multiplexer (22) when a certain value is reached to select the frequency of the output signal of the multiplexer (22). There are various possible ways of generating the multiplexer control signal. In the example of the present invention, the following two types can be used: one is to read the frequency signal output by the multiplexer with a counter, and when a certain value is reached, send a control signal to the multiplexer to select the output signal of the multiplexer. frequency. The other is to map the frequency signal output by the multiplexer to a comparison table. To decide whether the divisor of the divider should be increased, maintained, or decreased.

The counter can be composed of two parts. One is a periodic counter, which repeats the operation from 0 to 2 N. The other is a decoder type, which is used to decode the output of the counter to generate a multiplexer control signal. Among them, the value of 2 N can be determined by the ratio of the modulation frequency fm to the frequency of the input clock signal (f p f d of the PFD). And the decoder can be achieved by a hardware circuit or in a programmable manner to perform the signal conversion relationship represented by the lookup table.

According to the embodiment of the present invention, the counter (2 3) can correspond to the frequency signal output by the multiplexer (2 2) to a look-up table to determine whether the divisor of the divider (21) should be increased, maintained or decreased. . The comparison table is a phase-time comparison table. The time value can be calculated in advance and stored for future use. When deciding whether to use the comparison table in the present invention, a comparison table of phase / delay and η can be generated first, and then It is rounded to the nearest integer multiple of the modulation time step T. Fig. 4 is a graph showing the relationship between the cumulative phase and the modulation time step which can be generated by the above method and is applicable to the present invention.

Page 111241772, ---- tj V. Description of the invention (7) The table shows the delay time, the cross pull is also true, and 1 is the number of PFD cycles, and the curve represents the cumulative phase. The result obtained in Figure 4 can be the horizontal axis < PFD periodic table. Shi Min Da Shi-Ma, Peri〇ds), that is, the output of the counter.数据 处理。 Frequency processing. 92131735 — Correction of the output of the division (M-1) divider on the day of the month A, and control the set frequency of the vibrating plate (nominai r ^ q uei ^ yA f _, the signal of the oscillator is # '目 _ using spread-spectrum processing: It is generated by the frequency of the reference clock signal and dk, that is, lg-f refClk X Μ, and f refc is the frequency of ref clk. The oscillating signal is displayed. The frequency processing includes average spreading (average spreading) 'down spreading processing (d0wri Sprea (jing) and up spreading processing (up spreading). Taking down spreading processing as an example, the clock signal is frequency modulated. Up to the set frequency (fn (j, for spreading the clock signal, different modes can be used. Among them, "triangular modulation" is one example. Figure 2 shows the "triangle for reducing the frequency of the clock signal." Modulation (triangle-shape moduation) diagram ° As shown in the figure, the triangular waveform generated by down-spreading the clock signal can be expressed by two linear equations ...

"(Bu 5) fn〇m + 2fm · 5 · fnom · t when 0 &lt; t <ι; t (U) Ufm · (5 · fnom · t when 1 &lt; t &lt; 1 ~ &quot; irn

Among them, f no is the set operating frequency of the voltage-controlled oscillator without spreading processing, (5 is the spectrum spreading ratio, and f is the modulation

Page 12 1241772 Case No. 92131735% Month / Day ^ Labor V. Description of Invention (8)-Control frequency. Phase modulation can be used for frequency modulation of a phase-locked loop. This is because its phase or delay error / (廿 以 "error) is the integral value of its frequency error (frequency err) with time. The phase error of a triangular waveform down-spreading clock signal can be expressed as two divided by time The integration of a segment quaternion polynomial to a linear equation. For example, assuming the initial phase shift is 0, increasing or decreasing its divisor can produce a single-phase step with T = 1 / fn◦. Figure 3 shows The phase-to-time relationship obtained when the frequency is reduced. The figure shows that if the modulation frequency f is selected as the integer value of the divisor of the feedback clock signal f bcik (that is, the input of the phase / frequency detection circuit), The time axis in the figure can be represented by the "count count" of the counter (23) in the figure 丨, as shown at the bottom of the figure 3. The phase-time relationship will become a predetermined "step-count relationship". Therefore, in the circuit design, you can choose to increase or maintain the divider output phase in units of τ. The increase or maintenance can be determined by the characteristics of the phase modulation curve. In the case of the graph in Figure 3, when the phase versus time curve is steeper, the step distance increases, and the divisor should increase. The multiplexer (22) of the present invention is used to select the output (m + 1'M or M-1) of the division β (21) according to the state of the counter (23). The frequency signal generated by the multiplexer (2 2) is sent to the input node (15) of the phase-locked loop (10) on the other hand as the feedback clock signal f be 1 k and the reference clock signal refc After 1 k addition, it is used as the reference clock signal of the phase locked loop. The output clock signal clkout of the phase locked loop (10) passes the clock frequency.

1241772 &amp; Year and month &gt; ° Amendment No. 92131735 V. Description of the invention (9) Rate divider (21) After modulation (10), the phase-locked back can be reduced to reduce its peak value. 0 (0 0 0 ppm To the extent: The present invention uses the above-mentioned fixed phase divisor to be reduced to 2 to: 3 grades with low production cost. 0 In addition, because the step-by-step smoothing of the phase-locked loop is reduced. This technology is still the way to the invention In the description, the spirit of Si Yiming and the different spirits should be included in its [component symbol table] 10 phase-locked loop 11 phase / frequency 4 1 detector 12 charge pump 13 low-pass filter 14 voltage control The oscillator 15 20 21 22 23 provides a modulation waveform to the clock signal of the phase-locked loop circuit to expand to a predetermined bandwidth. In terms of expanding the target frequency by 0.5%, the peak energy greater than 10 d B can be reduced. . The bit modulation method reduces the divider (21) so that the circuit components can be greatly reduced, and the staircase effect produced by the down-modulation can be further added to the loop bandwidth within the scope of the invention patent. It is not difficult for a person with a phase-locked return of a spread-spectrum clock signal generator to understand the extension and changes of the present invention from the above description, as long as it does not exceed the scope of the patent application of the present invention. Input Node Spread Spectrum Clock Signal Generator Clock Frequency Divider Multiplexer Counter

1241772 Schematic description of the case No. 92131735______________________ Good year—4-1—2 ^ Amendment Figure 1 shows a circuit block diagram of an embodiment of a phase-locked circuit with a spread-spectrum clock signal generator according to the present invention. Fig. 2 is a schematic diagram of "triangle-shape modulation" for down-spreading the clock signal frequency. Figure 3 shows the phase-to-time relationship obtained when the frequency is reduced. Fig. 4 is a diagram showing a relationship between a counter signal and a modulation step applicable to the present invention.

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Claims (1)

1241772 _ Case No. 92131735 VI. Scope of patent application 1. A phase-locked loop with a spread-spectrum clock signal generator, comprising a phase-locked loop and a spread-spectrum clock signal generator; the input of the phase-locked loop is a reference clock signal, and the output is used as an output clock signal, And providing input to the spread spectrum clock signal generator; the spread spectrum clock signal generator includes a clock frequency divider, a multiplexer and a counter; the clock frequency divider generates the output signal of the phase locked loop More than one frequency-modulated frequency signal is supplied to the multiplexer; the selection signal of the multiplexer comes from the counter; the input signal of the counter comes from the output of the multiplexer; and the signal output by the multiplexer is provided for To this phase-locked loop as its feedback clock frequency. 2. For example, a phase-locked loop with a spread-spectrum clock signal generator in item 1 of the scope of the patent application, wherein the clock frequency divider performs a division M process, a division (M + 1) process on the output clock signal of the phase-locked loop, and Divide (M-1) at least two kinds of processing, and output the results separately. 3. As shown in item 2 of the scope of patent application, a phase-locked loop with a spread-spectrum clock signal generator, wherein a counter can read the frequency signal output by the multiplexer, and sends a control signal to a certain value when it reaches a certain value. The multiplexer is used to select the frequency of the multiplexer output signal. 4. As shown in item 2 or 3 of the scope of patent application, a phase-locked loop with a spread-spectrum clock signal generator, wherein the counter can correspond to the frequency signal output by the multiplexer to a comparison table to determine whether to increase , Maintain or reduce the divisor of the divider. 5. As shown in item 4 of the scope of patent application, a phase-locked loop with a spread-spectrum clock signal generator, wherein the comparison table is a phase-time comparison table, Page 16 1241772 Case No. 92131735 April / Day Amendment 6. Scope of patent application and including most pre-calculated time values Page 17