TWI241658B - Method of fabricating under bump metallurgy structure and semiconductor wafer with solder bumps - Google Patents

Abstract

A method for fabricating under bump metallurgy (UBM) and a semiconductor wafer with a plurality of solder bumps are proposed. The method includes preparing a wafer having a plurality of electrically connecting pads formed thereon; depositing an adhesive metal layer, such as aluminum layer, on each electrically connecting pad to provide metal layers coating; and stacking at least one barrier layer (e.g. nickel layer) and at least one solder wettable layer (e.g. copper layer) onto the adhesive metal layer, cooperating with the adhesive metal layer to form an under bump metallurgy structure for solder bumps bonding. The barrier layer and the solder wettable layer are stacked alternatively so as to increase the buffer capacity of the barrier layer to avoid bad bump soldering due to the consumption of barrier layer and to reduce stress of the UBM structure to prevent warpage of wafer.

Description

1241658

17504 硅 品 .ptd Page 8 1241658 V. Description of the invention (2) A layer of insulation protection layer 1 1 (Passivation Layer) exposing each solder pad 100 '; on the aluminum (or copper) solder pad 1 〇 An adhesive layer 2 ′ (such as an aluminum layer or a copper layer) is formed on 〇 ′ to protect the aluminum (or copper) pad 10 0 ′; a wet solder layer 9 is formed on the adhesive layer 2 ′ for tin Lead solder (not shown) is fixed; and a plurality of solder bumps 5 'are formed on the wet solder layer 9'. However, when the tin-lead solder 7 'forms a solder bump 5', a high-temperature reflow process must be performed. The high temperature caused by the reflow will cause cross-diffusion between the copper layer and zinc-tin (I nterdiffusi ο η) and An intermetallic compound I (Intermetallic Compound, IMC) such as Cu6Sn5 is formed to form a bonding force. However, as shown in Fig. 2, the formation of the interfacial metal complex I will cause a sharp decrease in the copper layer 9 '. If the copper layer is consumed and contacts the I luminous adhesive layer, no interfacial metal complex bond will be generated due to tin | Lu Will cause the bumps to be unable to be firmly soldered to the electrical connection pads, resulting in increased resistance and damage to the solder bump 5 'soldering reliability and corrosion resistance (Corrosion Resistance) 〇 To avoid solder and copper layers due to re-soldering The formation of the interface metal compound is too fast, which causes the copper layer to be depleted and the solder directly contacts the adhesive metal layer. Therefore, a slower barrier layer (Barrier Layer) is added between the adhesive metal layer and the tin layer as a barrier. To avoid exhaustion of the copper layer. Wherein, the material of the barrier layer may be selected from the group consisting of Nickel, Cobalt, Vanadium, Titanium, Iron, Hunger, Tin-Ni, Ni-Cr, Cu-Sn Alloys, iron-nickel alloys, and other metal deposits.

] 7504 石 夕 品 .ptd Page 9 1241658 V. Description of the invention (3) As shown in Figure 3, the metallization of the bottom of the solder bump (UBM) formed by taking the Ni (V / V) alloy layer as an example The structural layer 4 'includes an adhesive metal layer 2' (such as an aluminum layer) formed on an aluminum bonding pad 100 ', and a barrier layer (such as a nickel layer) attached to the adhesive metal layer 2'. Alloy layer) 3 ', and a wet solder layer 9' (S ο 1 der W e 11 ab 1 e Layer) (such as a copper layer) attached to the nickel-metal alloy layer 3 '. Since the interdiffusion rate between the nickel layer and the tin layer is only one-fifth of the copper-tin interdiffusion rate, even if the tin in the tin solder passes through the copper layer during the reflow process (R ef 1 〇w), but It can still be blocked by the barrier layer, and the intermetallic compound formation thickness is controlled within an acceptable range. However, although the interdiffusion rate between tin and nickel layer (Ni) or nickel vanadium layer (Ni V) is not as good as that of tin-copper layer, the thickness of a single recording layer can only be made up to the limit of the current sputtering process (Sputtering). 0.5 to 0.8 microns, at this thickness, interdiffusion between tin and the recording layer (or nickel starvation layer) will still occur to generate, for example, a Ni 3 S η tin-recording interface metal comonide, so that the solder continues to pass through The copper and nickel layers are converted into interfacial metal co-compounds (IMC) and consume more copper. With the increasing complexity of flip-chip semiconductor packaging structures, the number of reflows is also increasing, and internationally based on environmental considerations, spare no effort in the introduction of lead-free bumps. Decreasing the amount of misalignment will increase the proportion of tin and cause the formation of I MC between tin-copper or tin-nickel layers. After the copper and nickel in the UBM structure layer are completely converted into the interfacial metal co-compound, the tin in the solder will directly contact the aluminum adhesion metal layer. However, tin and aluminum do not produce intermetallic compounds

17504 Shi Xipin · ptd Page 10 1241658

Page 11 1241658 V. Description of the invention (5) The metal structure layer at the bottom of the solder bump with the reliability of the solder joint between the solder bump and the pad. A manufacturing method and a semiconductor wafer structure having a large number of solder bumps by the manufacturing method. Yet another object of the present invention is to provide a process reliability of solder bumps (So 1 der Bumps) in a semiconductor wafer process, and to solve the problem of stress caused by a single barrier layer being too thick in the UBM structure layer. A method for manufacturing a metal structure layer at the bottom of a solder bump that causes warpage or cracking of a wafer, and a semiconductor wafer structure having a large number of solder bumps by using the manufacturing method. In order to achieve the disclosure and other objectives, the present invention provides a method developed for the complex flip-chip semiconductor package structure and lead-free bumps, and is applied to the semiconductor wafer process (Wafer Process) A method for manufacturing a metal layer of an under bump (Unbump Meta 1 1 urgy, UBM) structure. The manufacturing method of the UBM structure layer includes the following steps: preparing a wafer with a plurality of electrical connections formed on a surface thereof and an insulation protection covering the surface of the wafer and exposing only at least a portion of the electrical connections. Depositing an adhesive metal layer (A dhesi n Layer) on the electrical connection pad and the insulation protection layer for subsequent metal layer attachment;

A plurality of barrier layers and Solder Wettable Layers are overlapped and overlapped on the adhesive metal layer, wherein the barrier layer and the wet solder layer are stacked at intervals to be in contact with the adhesive metal. Layers together to form the underlying metal of the solder bump (Under Bump Metallurgy, UBM

] 7504 硅 品 .ptd Page 12 1241658 V. Description of the invention (6)) Structure layer; and forming a plurality of flip-chip bumps on the U B M structure layer. With respect to the above process, the semiconductor wafer structure manufactured by the present invention with a plurality of flip-chip bumps includes: a wafer having a plurality of electrical connection pads formed on its surface and a surface covering the wafer to expose at least a portion Part of the insulation protection layer of the electrical connection pad; an adhesive metal layer is deposited on the electrical connection pad and the insulation protection layer for subsequent metal layer attachment; a plurality of barrier layers and wet solder layers are stacked alternately 'Wherein' the wet solder layer and the barrier layer are stacked on the adhesive metal layer to form a UBM structure layer together with the adhesive metal layer; and a plurality of UBM structures are formed on the adhesive metal layer Flip-chip bumps on the layer. The U BM manufacturing method of the present invention uses a barrier layer (Barrier Layer) and a wet solder layer (Solder Wet table Layer) to alternately stack the traditional single barrier layer / wetting layer to reduce the repeated bonding layer technology. The thickness of each barrier layer reduces the thermal stress generated during reflow and avoids wafer warpage or cracking, so that the solder bump has better process yield and soldering reliability (Bond i ng Re 1 i ab i 1 i ty). In another aspect, the barrier layer and the wet solder layer of the UBM structure layer of the present invention are stacked and spaced apart, and a wet solder layer (such as a copper layer) can be sandwiched between adjacent barrier layers as a stress buffer layer to disperse the barrier layer The generated stress provides sufficient barrier performance of the UBM structure layer through the multilayer barrier layer, and slows down the formation rate of the intermetallic commundum (IC) between the solder and the copper layer or the nickel layer, so that The wet solder layer and the barrier layer do not cause the solder to contact the adhesive metal layer due to the exhaustion of I MC formation, thereby improving the

1241658 V. Description of the invention (7) Process yield and soldering reliability between high solder bumps and electrical connection pads. [Embodiment]: The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention may also be implemented or applied by other different specific embodiments, and various details in this specification may also be based on different viewpoints and applications, and various modifications and changes may be made without departing from the spirit of the present invention. The following examples further illustrate the viewpoints of the present invention in detail, but do not limit the scope of the present invention in any way. FIG. 4 is a schematic cross-sectional view of a semiconductor wafer having a metal structure layer at the bottom of a solder bump of the present invention. The semiconductor wafer structure includes: a wafer 1, a plurality of electrical connection pads 100 are formed on a circuit surface 10a, and the circuit surface 10a is covered, and each of the electrical connection pads 100a is exposed. Insulation protective layer 11 (Passivation Layer);-Adhesive metal layer 2 is deposited on the pad 100 and the insulation protective layer 11 to protect the electrical connection pad 100 and provide subsequent metal layer adhesion; multiple layers The barrier layer 30 and the wet solder layer 31 are stacked on the adhesive metal layer 2 in an interphase, wherein the barrier layer 30 and the wet solder layer 31 are stacked at intervals to be in contact with the adhesive metal layer. 2 collectively form a solder bump bottom metal (UBM) structural layer 4; and a plurality of solder bumps 5 formed on the UBM structural layer 4. The semiconductor wafer 1 is, for example, a silicon (Si) wafer, a gallium arsenide (AsGa) wafer, and the like, and has a circuit surface 10a and an opposite non-circuit surface 10b. The circuit surface 10 a is formed with a large number of, for example, aluminum welds.

] 7504 石 夕 品 .ptd Page 14 1241658 V. Description of the invention (8) The electrical connection pad 1 of the pad or copper pad 1 0, the circuit surface 1 0 3 is covered with an electrical connection pad 1 〇〇 At least part of the exposed insulating protective layer 1 1. However, the material of the insulating protective layer 11 is similar to or can prevent the wafer surface circuit from being isolated from air and dust except that it is selected from polyimide, silicon dioxide, and silicon nitride (Silicon Nitride). Materials, polymers, and the like are suitable for use in the embodiments of the present invention. The pad metal layer 2 formed on the electrical connection pad 100 may be, for example, a copper layer, a chromium layer, or an aluminum layer. The material of the pad metal layer 2 is selectively connected with the electrical layer. Sexual connection pads 1 0 0 are of the same material. Taking this embodiment as an example, the electrical connection pad 100 formed on the wafer 1 is an aluminum pad. Therefore, it is better to select an aluminum layer as the pad metal layer 2 of this embodiment. Taking the UBM structure of this embodiment as an example, as shown in the enlarged view of FIG. 4, the barrier layer 30 and the wet solder layer 3 1 (S ο 1 der W e 11 ab 1 e L ayer) are alternately stacked. Let a wet solder layer 30 be sandwiched between any two adjacent barrier layers 31 for buffering, so as to reduce the stress of the UBM structure layer. Among them, the barrier layer 30 and the wet The welding layers 31 are all sputtering and evaporation, such as Arc Vapor Deposition, Ion Beam Sputtering, and Laser Ablation Depo siti οn) or other methods such as physical vapor deposition (PVD) and chemical vapor deposition (CVD); among them, the material of the general wet solder layer 31 is selected from copper or chromium, and the resistance Choose 30 barriers

17504 石 夕 品 .ptd Page 15 1241658 V. Description of the invention (9) ~ from (Nlckel), drill (Cobalt), M (Vanadlum), Qin ^ hnlun〇, iron (ΐΓ〇Ι〇, nickel vanadium Alloys, tin-nickel alloys, nickel-chromium alloys, steel-tin alloys, and iron-nickel alloys. # 罗 f 下 在 图 5A 至 5Η 图 will explain in detail how the present invention is formed day after day ^ Schematic diagram of the overall fabrication process of a semiconductor wafer structure. ㊉ = Figure 5A, preparation—semiconductor wafer 丨, the wafer 1 has a sense surface 10 level, a non-circuit surface 1 Ob, in the circuit A plurality of circuit patterns (not shown) and electrical connections (1) are formed on the surface, and an insulation and protection layer U (for each electrical connection pad 100) is coated on the surface of the road surface 10a. Passivation Layer). Then, as shown in Figure 5B, electroless plating (Electroless 2 1 a 11 ng), sputtering or vapor deposition on the electrical connection pad 100 and the insulation shy layer 1 stomach 1 An adhesive metal layer 2 is deposited on top for subsequent stacking of a plurality of barrier layers and a wet ^ layer parent, and is bonded with the adhesive gold The layers together form an under bump metallurgy (UBM) structure layer. ^ Then, as shown in FIG. 5C, a method such as sputtering, evaporation, or electrolytic plating is formed on the adhesive metal layer 2 A barrier layer 30, such as Nickel, Cobalt, Vanadium, Titanium, Iron, Ni-V alloy, Sn-Ni alloy, Ni-Cr to Cu-Sn alloy and iron Any of nickel alloys; however, in this embodiment, a nickel layer is used as the material of the barrier layer 30, and a plating layer with a thickness of about 0.5 to 0.5 micrometers is formed by sputtering. As shown in FIG. 5D, a wet solder layer 31 is formed on the barrier layer 30 by the same sputtering method as that of the barrier layer 30, and a barrier layer is used.

1241658 V. Description of the invention (10) 3 〇 On:!: A layer of wet solder layer 31 is placed, and a layer of barrier layer 30 is superimposed on the layer of wet solder layer 31, as shown in FIG. 5E. Knot ^. In this example, a multilayer structure in which two barrier layers 30 and two layers = / gate I on layer 31 are stacked on the adhesive metal layer 2 at intervals, the UBM junction layer 4 of the present invention is simply shown. Then, as shown in FIG. 5F and FIG. 5G, a dry film (Dry FUm) ^ liquid photoresist and other photoresist layer 6 (phοtoresist Laye〇) is used to cover the uppermost wet solder layer 31, so that the corresponding The wet zinc layer 31 on the electrical connection pad 丨 〇〇 is exposed to the photoresist layer opening β 〇; reuse the method such as screen printing (Pri / t Screening) or electrolytic plating to open the photoresist layer 60 A bump 7 is applied to form a solder 7; wherein, the bump 7 may be a tin-lead solder of SnW / Pb: H or Sn9 5 / Pb5, or to replace lead with silver, three tin, copper and its alloy based on environmental considerations To form lead-free solder, etc. 'However, the type of the bump-forming solder 7 is not limited to the above, and any solder material suitable for electrically connecting a semiconductor wafer to a wafer carrier is included in this section. The invention can be implemented. Furthermore, as shown in FIG. 5, the resist layer is removed and the UB structure layer 4 other than the electrical connection pad 100 is removed by etching to expose the insulation again. The protective layer 11 completes the semiconductor wafer structure with most fresh tin bumps 5 as shown in FIG. 4 The UB MM manufacturing method of the present invention uses the alternate stacking method of barrier layer and wet solder layer to replace the traditional single, barrier layer / wet layer, in order to reduce the thickness of each barrier layer through repeated plating technology to reduce stress generation, Avoid wafer warpage or cracking, and make solder bumps have better process yield and soldering reliability

] 7504 石 夕 品 .ptd Page 17 1241658 V. Description of the Invention (11) (Bonding Reliability). In addition, in the UBM structure layer of the present invention, the barrier layer and the wet solder layer are stacked at intervals, so that a wet solder layer (such as a copper layer) can be sandwiched between adjacent barrier layers as a stress buffer layer to disperse the barrier layer. The generated stress provides sufficient barrier performance of the UBM structure layer through multiple barrier layers, slows down the formation rate of the intermetallic compound (IMC) between the solder and the copper layer or the recording layer, and makes the barrier layer and the wet The solder layer does not cause the I MC to be consumed and the solder can contact the adhesive metal layer, thereby improving the process yield and soldering reliability between the solder bump and the electrical connection pad. The above-mentioned embodiments are merely illustrative for explaining the principle of the present invention and its effects, and are not intended to limit the present invention. Anyone skilled in the art can modify and change the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application mentioned later.

17504 石 夕 品 .ptd Page 18 1241658 Brief description of the drawings [Simplified illustration of the drawings] · Figures 1A to 1D show conventional semiconductor wafers with a solder bump bottom metal (UBM) structure layer Schematic diagram of the manufacturing process; Figure 2 is a schematic cross-sectional view of a semiconductor wafer structure with a UBM structure layer with a barrier layer; Figure 3 is a schematic cross-sectional view of a solder bump formed on a wafer surface by a conventional method; Figure 4 is a schematic cross-sectional view of a semiconductor wafer structure with most solder bumps and a partially enlarged schematic view of a UBM structure; and Figures 5 A to 5 Η show a semiconductor wafer structure with most solder bumps of the present invention Schematic diagram of the overall production process. 1,1 'wafer 1 0 a, 1 0 a' circuit surface 10b non-circuit surface 100 electrical connection pad 100 'aluminum pad 11 insulation protection layer 2 pad metal layer 2, aluminum layer 3, nickel vanadium alloy layer 30 Barrier layer 31, 9 'Wet solder layer (copper layer) 4, 4' UBM structure layer 5, 5 'solder bump 6 Photoresist layer 60 Photoresist layer opening 7, 7' bump forms solder I interface metal Concomitant

17504 Bite.ptd Page 19

Claims (1)

1241658 6. Scope of patent application 1. A method for manufacturing an under bump metallurgy (UBM) structure layer includes the following steps: A wafer is prepared, and most electrical connection pads and a cover are formed on the surface. An insulating protective layer is exposed on the wafer surface and each of the electrical connection pads is deposited; an adhesive metal layer is deposited on the electrical connection pad and the insulating protection layer for subsequent metal layer attachment; and the adhesive metal layers overlap each other Barrier layer and Solder Wettable Layer are connected, wherein the barrier layer and the Wettable layer are stacked at intervals to form a bump bottom with the adhesive metal layer. Metallized (Unbump Metallurgy, UBM) structural layer. 2. For the method for manufacturing a UBM structure layer according to item 1 of the patent application scope, wherein the wafer is a silicon wafer. 3. The manufacturing method of the UBM structure layer according to item 1 of the patent application scope, wherein the wafer is a gallium arsenide wafer. 4. The manufacturing method of the UBM structure layer according to the first patent application scope, wherein the electrical connection pad is an aluminum solder pad. -5. For example, the manufacturing method of the UBM structure layer in the scope of patent application item 1, wherein the electrical connection pad is a copper solder pad. 6. The method for manufacturing a UBM structure layer according to item 1 of the scope of patent application, wherein the material of the insulating protective layer is one selected from the group consisting of polyimide (P ο 1 yimide), silicon dioxide, and nitrogen silicide. By. 7. For the manufacturing method of UBM structure layer in the scope of patent application item 1, which ] 7504 石 夕 品 .pt: d page 20 1241658 6. In the scope of patent application, the adhesive metal layer is a layer of inscription. 8. The method for manufacturing a UBM structure layer according to the first patent application scope, wherein the adhesive metal layer is a chromium layer. 9. The method for manufacturing a UBM structure layer according to item 1 of the patent application, wherein the wet solder layer is a copper layer. 10. The method for manufacturing a UBM structure layer according to item 1 of the scope of patent application, wherein the material of the barrier layer is selected from the group consisting of Nickel, Cobalt, Vanadium, Titanium, and Iron. (Iron), nickel-vanadium alloy, tin-nickel alloy, nickel-chromium alloy, copper-tin alloy and iron-nickel alloy and other groups. 1 1. The method for manufacturing a UBM structure layer according to item 1 of the scope of patent application, wherein the wet solder layer and the barrier layer are formed by a money deposit method (S p u 11 e r i n g). 12. The method for manufacturing a UBM structure layer according to item 1 of the scope of patent application, wherein the barrier layer is formed by an electroless ore method (Electroless P 1 a t i ng). 1 3. The method for manufacturing a UBM structure layer according to item 1 of the scope of the patent application, wherein the barrier layer is formed by an electric ore method (E 1 e c t r ο p 1 a t i n g). 14. The method for manufacturing a UBM structure layer according to item 1 of the scope of patent application, wherein the solder bump is a tin-lead bump. 15. The method for manufacturing a UBM structure layer according to item 1 of the scope of patent application, wherein the solder bump is a non-slanted bump (L e a d-f r e e B u in p s 17504 石 夕 品 .ptd Page 21 1241658 6. Scope of patent application 1 6. —A semiconductor wafer structure with most solder bumps formed includes: a wafer with most electrical connection pads formed on the surface and An insulating protective layer covering at least a part of each electrical connection pad covering the surface of the wafer; an adhesive metal layer deposited on the electrical connection pad and the insulating protection layer for subsequent metal layer attachment; a plurality of Barrier layer and Solder Wettable Layer are overlapped on the adhesive metal layer, wherein the barrier layer and the wet solder layer are spaced apart from each other to make contact with the adhesion. The metal layers together form an under bump metallurgy (UBM) structure layer; and a plurality of solder bumps formed on the UBM structure layer. 17. The semiconductor wafer structure according to item 16 of the scope of patent application, wherein the wafer is a smashed wafer. 18. The semiconductor wafer structure according to item 16 of the patent application scope, wherein the wafer is a gallium arsenide wafer. 19. The semiconductor wafer structure according to item 16 of the patent application scope, wherein the electrical connection pad is an aluminum bonding pad. 20. The semiconductor wafer structure according to item 16 of the patent application scope, wherein the electrical connection pad is a copper bonding pad. 2 1. The semiconductor wafer structure according to item 16 of the scope of patent application, wherein the material of the insulating protection layer is selected from one of polyimide (silicon dioxide), silicon dioxide, and nitrogen silicide. By. ] 7504 石 夕 品 .ptd Page 22 1241658 6. Scope of patent application 2 2. For the semiconductor wafer structure with the scope of patent application No. 16 in which the adhesive metal layer is an inscription layer. 2 3. The semiconductor wafer structure according to item 16 of the patent application scope, wherein the adhesive metal layer is a chromium layer. 24. The semiconductor wafer structure according to item 16 of the patent application scope, wherein the wet fresh layer is a copper layer. 25. The semiconductor wafer structure according to item 16 of the patent application, wherein the material of the barrier layer is selected from the group consisting of Nickel, Cobalt, Vanadium, Titanium, and Iron ( Iron), nickel alloys, tin alloys, alloys, copper-tin alloys and iron-nickel alloys. 26. The semiconductor wafer structure according to item 16 of the patent application scope, wherein the wet solder layer and the barrier layer are formed by a sputtering method (S pu 11 e r i n g). 27. The semiconductor wafer structure according to item 16 of the patent application scope, wherein the barrier layer is formed by an electroless electroplating method. 28. The semiconductor wafer structure according to item 16 of the patent application scope, wherein the barrier layer is formed by electroplating. 29. The semiconductor wafer structure according to item 16 of the patent application scope, wherein the solder bump is a tin-lead bump. 30. The semiconductor wafer structure according to item 16 of the patent application scope, wherein the zinc-tin bump is a lead-free bumps. ] 7504 Silicone.ptd Page 23