TWD231747S

TWD231747S - Bumps of chip package

Info

Publication number: TWD231747S
Application number: TW112305775F
Authority: TW
Inventors: 謝忠孝; 劉宥圻
Original assignee: 天鈺科技股份有限公司新竹市新竹科學工業園區篤行路6-8號3樓 (中華民國); 天鈺科技股份有限公司
Priority date: 2023-11-08
Filing date: 2023-11-08
Publication date: 2024-06-11

Abstract

【物品用途】;本設計物品用於半導體元件。;【設計說明】;本設計之要點在於產品之晶片封裝的焊點的形狀及空間分佈。;後視圖不具設計特點且為本案不主張設計之部分，故省略後視圖。;圖式所揭露之虛線部分，為本案不主張設計之部分。圖式所揭露之一點鏈線所圍繞者，係界定本案所欲主張之範圍，該一點鏈線本身為本案不主張設計之部分。[Use of Article];This design article is used for semiconductor components. ;[Design Description];The key point of this design lies in the shape and spatial distribution of the solder joints of the chip package of the product. ;The rear view does not have design features and is not a part of the design advocated by this case, so the rear view is omitted. ;The dotted line part disclosed in the figure is a part not advocated by this case. The area surrounded by the dot chain line disclosed in the figure defines the scope advocated by this case, and the dot chain line itself is a part not advocated by this case.

Description

Chip package solder joints

本設計物品用於半導體元件。This design article is used for semiconductor components.

本設計之要點在於產品之晶片封裝的焊點的形狀及空間分佈。The key point of this design lies in the shape and spatial distribution of the solder joints of the product's chip package.

後視圖不具設計特點且為本案不主張設計之部分，故省略後視圖。The rear view has no design features and is not a design feature of this case, so the rear view is omitted.

圖式所揭露之虛線部分，為本案不主張設計之部分。圖式所揭露之一點鏈線所圍繞者，係界定本案所欲主張之範圍，該一點鏈線本身為本案不主張設計之部分。The dotted line part of the diagram is the part that the case does not claim to design. The part surrounded by the dotted line of the diagram is to define the scope that the case wants to claim, and the dotted line itself is the part that the case does not claim to design.