TW528816B - Method for heat treating silicon wafer - Google Patents

Abstract

The present invention is related to a process where a polycrystalline silicon layer with a thickness of 0.1-1.6 μm is formed on the rear surface of the silicon wafer by chemical vapor deposition (CVD) method and oxygen concentration of a silicon wafer, with which crystal oriented particles (COPs) and interstitial-type large dislocations (L/Ds) are not produced on a wafer surface is not larger than 1.2x10<SP>18</SP> atoms/cm<SP>3</SP> (old ASTM). The above silicon wafer is subjected to a thermal treatment at 1,000 DEG C ± 30 DEG C for 2-5 hours in an oxygen atmosphere, and successively, is subjected to a thermal treatment at 1,130 DEG C ± 30 DEGC for 1-16 hours. More specifically, oxidation induced stacking faults (OSFs) are made obvious in the central part of the silicon wafer. Therefore, when a conventional thermal treatment for making OSF obvious is carried out, the polycrystalline silicon wafer produced through above mentioned method is free of OSF and COP. It makes oxide deposited uniformly over the whole surface of the wafer and obtains uniform gettering effects, without variation between the circumferential edge and central part of the wafer.

Description

528816 A7 B7 V. Description of the invention (1) <Technical Field to which the Invention belongs> The present invention relates to a silicon for semiconductor circuit manufacturing manufactured by the C20Chr a 1 ski me hod (CZ method for short). A method for ripening a wafer, a wafer used in the method, and a wafer processed by the method. 〈Knowledgeable Technology〉 In recent years, the factors that have been regarded as affecting productivity in the manufacture of semiconductor circuits are as follows: Oxygen precipitation that constitutes Oxidation Induced Stacking F a ii 11, K hereinafter referred to as 0 SF The existence of small defects in the material, or the origin of crystalline particles (M) (hereinafter referred to as COP), or invasive transposition (Interstitial-type Large Dislocation (M, referred to as L / D)). OSF is caused by small defects that form its core during the crystal growth, which are introduced into the silicon ingot, and appear during the oxidation process of manufacturing semiconductor devices. In addition, when a mirror-polished silicon wafer is cleaned with a mixed solution of ammonia and hydrogen peroxide, a hole (Pit) will be formed on the wafer surface. When the wafer is detected by a particle detector, the hole will be the same as the original Inherent particles are detected together. The hole system of the upper part is due to crystallization. In order to distinguish it from the inherent particles, it is called COP. The COP of the holes on the surface of such wafers constitutes electrical characteristics, such as time-dependent (time-dependent) dielectric breakdown characteristics (TDDB) of oxide films, and time zero dielectric breakdown characteristics (oxidized films) TZDB). In addition, when a COP exists on the wafer surface, a step difference may occur during the wiring of the device, which may cause a disconnection. At the same time, it may cause a leakage current in the component separation part, which reduces the product yield. -4 A paper size is applicable to China National Standard (CNS) A4 specification (210X 297 mm) JI ---- Ί ---- (Please read the precautions on the back before filling this page)-, 1Τ # ·. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 528816 A7 B7 V. Description of the invention (2) L / D is sometimes called a dislocation cluster, or because a silicon wafer with this defect is immersed in the main hydrogen Etching holes are generated in the selective etching solution of hydrofluoric acid, so it is also called dislocation Pit. L / D also deteriorates electrical characteristics such as leakage characteristics and isolation characteristics. From the above, the silicon wafers used in the fabrication of semiconductor integrated circuits must be reduced to 0 S F, C 0 P, and L / D as much as possible. The manufacturing methods of non-defective silicon single crystals, such as 0SF and transposed clusters (L / D), have not been disclosed in Japanese Patent Laid-Open Nos. 8-3 30316 and 11-iS 93. The method of Japanese Patent Application Laid-Open No. 8-3 3 0 3 1 6 is a method of growing silicon single crystals at a low speed to thermally oxidize the state of the M silicon wafer. The ring-shaped 0SF will disappear at the center of the wafer and may be removed. A method to remove L / D from the wafer. However, when a defect-free silicon single crystal is manufactured by this method, the range of the pulling speed of the silicon single crystal and the range of the temperature gradation within the crystal in the axial direction are narrower. The increase of the diameter increases the difficulty of manufacturing a defect-free silicon single crystal, and sometimes the 0 SF is not ring-shaped and the M-block shape occurs at the center of the wafer due to changes in the pulling speed. As described above, this 0SF may cause deterioration of the leakage characteristics, and therefore, an improved method for manufacturing a silicon single crystal is generally desired. The method disclosed in Japanese Patent Laid-Open Publication No. 1 1-1 3 9 3 is the completeness of the existence of a kind of K-hole type point defect aggregates and inter-lattice silicon-type point defect aggregates, which is the perfect domain. ) As [ρ], a method of pulling a silicon single crystal composed of a complete and unbroken field [P] from a silicon melt. The silicon wafer cut out from this ingot is from the complete field [p] -5-This paper is also applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) (Please read the note on the back first) Please fill in this item to buy) Order printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives A7 B7

528816 V. Description of invention (3) Composition. The complete and non-defective field [P] lies between the field [I] where inter-lattice silicon-type point defects account for the potential and the reading region [V] where void-type point defects are dominant in silicon single crystal blocks. The complete silicon wafer [P] is completed by setting the V / G value (fflffl2 / minutes) so that the pulling speed of the crystal block is VUm / minute, the interface of the silicon melt and the crystal block. When the temperature gradient in the vertical direction of the nearby crystal block is G (υ / mm), 〇SF generated in a circle when the thermal oxidation treatment is performed will be prepared under the condition that the center portion of the wafer disappears. In addition, some semiconductor manufacturers require silicon wafers that do not have OSF, COP, and L / d, and have the performance of de-aeration (Gotte ring) of metal contaminants generated by device engineering (d e v i c e ρ γ o c e s s). When wafers without sufficient oxygen removal performance are contaminated by metal during device engineering, junction leakage or poor operation of the device due to trap levels of metal impurities can reduce the product's performance. Yield. Therefore, in order to solve this problem, a silicon wafer that can exert an intrinsic gettering (referred to as I G) effect during the heat treatment of the Cg is generally required. However, the 0 wafers cut out from the ingots formed by the complete field [P] of the upper part, although they do not have OSF, COP, and L / D, will not necessarily be on the wafer during the device manufacturing process &gt; heat treatment. Oxygen evolution occurs in the electrode, and as a result, there is a disadvantage that a sufficient IG effect cannot be obtained. Traditionally, the heat treatment method in device engineering for the wafer to exert the IG effect is a method of forming defects or intentionally adding impurities in the wafer. Sand wafers processed in this way can absorb contamination from subsequent processes around the pre-formed defects on the wafer. Therefore, it is possible to prevent the installation of 6-this paper size is applicable to the Chinese National Standard (CNS) A4 specification (210x 297 mm) (Please read the precautions on the back before filling this page) -------- -tr ---------- line ·. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 528816 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 Β7 V. Description of the invention (4) Wafer surface Defects or contamination in nearby areas. In addition, in recent years, due to the high concentration of the device (increasing the packaging density), the heat treatment temperature of the device project has a tendency to be lower than 10 Q 0 ° C. Therefore, in conjunction with this low temperature, the IG treatment of the previous project is also required to be low temperature. Into. For this reason, Japanese Patent Application Laid-Open No. 8-4 5 9 4 5 discloses a method including: cutting a silicon single crystal block and polishing and polishing the silicon wafer at a temperature of 500-800 ° C. 0.5-2G hours to introduce a precipitation nucli of oxygen into the wafer; this silicon wafer containing oxygen precipitation nuclei is rapidly heated from room temperature to 8 G (3-1 0 0 0 ° C and The process of maintaining 0.5-2 G minutes; the process of cooling the rapidly heated silicon wafer to room temperature for 0.5-20 minutes; and the process of cooling the cooled silicon wafer from 50 0 ϋ -7 fl Q ° CK 2-1 Q / min. Heating to 80 0 1 1 0 0 υ and keeping at this temperature for 2-4 8 hours of IG processing method. According to this processing method, when Κ When the heating temperature is rapidly heated, not only the surface of the wafer, but also the interior of the wafer will temporarily change to a thermal equilibrium concentration M, which will cause the silicon atoms in the lattice to become deficient, thereby providing an environment where the oxygen precipitation nuclei can grow easily and stably. In order to make up for the lack of silicon atoms between the grids and become stable, the generation of silicon atoms between the grids occurs on the surface of the wafer, and makes the The inter-lattice silicon atoms diffuse into the wafer. Therefore, near the surface of the wafer in which the inter-lattice silicon atoms are deficient, the generation of inter-lattice silicon atoms becomes saturated, and the oxygen nucleation begins to disappear. As silicon atoms generated between the lattices on the wafer surface diffuse into the interior, it takes a while, so the farther away from the interior of the wafer surface, the longer the environment where the oxygen can grow out of the nucleus and grow longer. Therefore, the closer to the wafer surface, the more oxygen Density of precipitation core-7-This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) 11 ^ ----- ^ --- · ^ -------- ^ ·- ------- I 、 (Please read the notes on the back before filling this page) Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 528816 A7 __________ B7 V. The invention description (5) the lower the heat treatment time ( 0.5-20 minutes), the longer the oxygen precipitation nucleus, that is, the thickness of the denuded zone (DZ for short), the greater the thickness. In addition, the temperature is in the range of 800-1000, The larger the diffusion coefficient of the sand atoms between the lattices, the DZ thickness changes in a short time. When heating rapidly and cooling the wafer to 800-11001 after cooling at room temperature, the oxygen precipitation nucleus inside the rapidly heated wafer will grow into oxygen precipitates and become a stable IG source. Oxygen precipitates are called BMD (Bulk Micro Defect). However, the IG treatment method of the upper part requires grinding and polishing of the post-processed sand wafer. It is maintained for 5-20 hours at 50 G-8 0 0 υ. The step of introducing the oxygen precipitation nuclei into the wafer is processed before generating the IG source, and further, after rapid heating, heat treatment is required to grow the oxygen precipitation nuclei inside the wafer into BMD. Therefore, there is a lack of performing multiple heat treatments in the state of the wafer. &lt; Summary of the invention &gt; The first object of the present invention is to provide a wafer which can be concentratedly developed in the center portion even when the conventional 0SF flaring heat treatment (OSF_fflanifesting heat treatment) is performed. Heat treatment method for SFK and C 0 P-free silicon wafers. A second object of the present invention is to provide a polycrystalline silicon layer having a uniform degassing effect (gettering effect) between the wafer peripheral edge portion and the wafer center portion in the full implementation of uniform oxygen precipitation. Silicon wafer manufacturing method. The third object of the present invention is to provide a concentration of 0. 8 X 1 0 1 8 to 1. 4 X 1 0 1 8 -8- even if it is composed of a mixed field of a field [P v] and a field [P 1]. Paper size applies to Chinese National Standard (CNS) A4 (210 X 297 g) (Please read the precautions on the back before filling out this page) Installation ------ Order ------...! 528816 A7 B7 Ministry of Economic Affairs Printed by the Intellectual Property Bureau's Consumer Cooperatives. 5. Silicon wafers cut out from the crystal block of the invention description (6 atoms / cm 3 (old AS T M)). They do not have point defect aggregates and can fully generate oxygen precipitation nuclei. A heat treatment method for a silicon wafer that can exert the IG effect through the heat treatment of a device manufacturing process. A fourth object of the present invention is to provide a heat treatment method for a silicon wafer that does not require an oxygen donor killer treatment process. A fifth object of the present invention is to provide a heat treatment method for a silicon wafer that can reduce the number of heat treatments in the state of a silicon wafer and can exhibit a high IG effect by heat treatment at 950 ° C Μ. 6 The purpose is to provide a method, which can be obtained by the processing method can play a high IG Fruity silicon wafer. The seventh object of the present invention is to provide a single crystal ingot that can produce such a silicon wafer that exhibits a high IG effect. <Means for achieving the object of the invention> The first aspect of the present invention is Provided is a chemical vapor deposition (hereinafter referred to as CVD) method, which does not cause oxygen concentration i.2xl in the silicon wafer surface due to crystalline particles (COP) and intrusive indexing (L / D). a step of forming a polycrystalline silicon layer with a thickness of 0.1-1.6 // ιη at a temperature of 67 ° ± 3 ° at the back of a silicon wafer below iaat〇ffis / cm3 (old ASTM); and A silicon wafer with a polycrystalline silicon layer is placed in an oxygen atmosphere, and then heat-treated at a temperature of 0 ° C to 3 ° C for 2-5 hours, and then implemented at a temperature of U3 (rc ± 3 (rc) for 16 hours. The heat treatment method of the silicon wafer in the processing step is characterized in that the silicon wafer before forming the polycrystalline silicon layer undergoes a heat treatment at the center of the wafer and causes an accumulation of oxidation defects (0 s F) at the center of the wafer. -9- The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love) — · --- l · --------- ------ (please first Read the notes on the back and fill in this page again) 528816 Α7 Β7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. The description of the invention (7). The second aspect of the present invention is to provide a cause that does not occur in the silicon wafer surface. A silicon wafer having a thickness of 0 · 1-1.6u is formed on the back surface of the silicon wafer at a crystal concentration of COP and invasive translocation (L / D) at an oxygen concentration of 1.2 X 10 1 8 atoms / cm3 M (former ASTM). Silicon wafers with a polycrystalline silicon layer with a thickness of m are characterized in that the silicon wafer before the formation of the upper polycrystalline silicon layer is placed in an oxygen atmosphere at a temperature of 10 QG ° C to 3 Q ° C After the heat treatment is performed for 2 to 5 hours, and then the heat treatment is performed at a temperature of 113 ο υ for 1 to 16 hours, oxidation will occur at the center of the wafer to cause the accumulation of defects (0SF). The silicon wafers according to the first and second aspects of the present invention are wafers prepared by the Chuklaski (CZ) method under the condition that 0SF appears at the center of the silicon wafer. Part of the tritium does not have an oxygen precipitation nucleus. At the same time, the part outside the central part K does not contain C 0 P. When a polycrystalline silicon layer is formed on the back surface of such a silicon wafer, a BMD will be formed on the wafer in its entirety during the CVD process. As a result, uniform oxygen precipitation can be performed throughout the wafer, and the uniform I G effect without any deviation between the center portion of the wafer and other parts can be exerted. According to a third aspect of the present invention, the area where the inter-lattice silicon-type point defects are dominant in the silicon single crystal crystal is "I", the area where the void-type point defects are dominant is [V], and the inter-lattice silicon is The non-defective areas where the aggregates of type point defects and the aggregates of void type point defects do not exist at all are regarded as "P". The area with the lowest inter-lattice silicon concentration is taken as [P Π, and the area under the pore density M that can form COP or FPD adjacent to the upper area "V" and belongs to the above-mentioned non-defective area [P] is taken as [P v] At the time, there is no defect from the top -10- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) ---- Order --- ------ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 528816 A7 ___________ B7 V. Description of the invention (8) Silicon wafers with point-free defect aggregates cut out of the crystals formed in the field [P] The heat treatment method. The characteristic point of this heat treatment method is to pull up a silicon single crystal block composed of a mixed field of the above-mentioned fields [P v] and [P i] and having an acid concentration of 0.8X 1018 ~ 1.4X c π3 (former AST Μ), The silicon wafer cut out from the upper crystal block is placed in an atmosphere of nitrogen, argon, hydrogen, oxygen, or a mixed gas thereof, and is held for 30-90 minutes at 6000-8501¾. The fourth aspect of the present invention is to form a silicon single crystal having a denier oxygen concentration of 0.8X HP8 ~ 1.3X l0i8at〇IRS / c πι3 (formerly AST M) from the mixed field of the above-mentioned fields [Pv] and [Pl]. The silicon wafer cut out from the upper crystal block is placed in an atmosphere of nitrogen, argon, hydrogen, oxygen, or a mixed gas thereof, and maintained at 60 2 0-8 5 0 υ 1 2 0-2 5 0 minute. A fifth aspect of the present invention is a silicon single crystal having an oxygen concentration of 0.8X 1018 to 1.4X l (] i8atc) nis / cm3 (former ASTM) composed of a mixed field of the upper field [Pν] and the field [Pl]. The wafer is pulled up, and the Shi Xi wafer cut out of the upper crystal block is placed in an atmosphere of nitrogen, argon, hydrogen, oxygen or a mixed gas thereof, and the temperature rising rate of M 1 15 0 t / s is from 1 1 5 0 υ is heated to 1 2 0 0 ° C, and maintained at Q-3 Q seconds at 1 150-12 G. According to the method of the third to fifth aspects of the present invention, even if the oxygen inclination of the crystal block is 0.8 × 1018 ~ 1.4xi018atoms / cin3 (former ASTM), the wafer of Shi Xiqin is composed of the field [Pv] and the field [P]. When the mixed field is constituted, the silicon wafer cut out from the crystal block is subjected to heat treatment under the conditions of $ uploading, that is, during the growth of the crust, the field [Pi] where no oxygen precipitation nucleus is introduced can show the oxygen precipitation nucleus, and at the same time crystallize In the field of growth, there are areas where oxygen nucleation is introduced. [P v] Obvious oxygen leaching _ 1 1 _ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) r L ------- ---------- ^: ί ------ Aw (Please read the notes on the back before filling this page) 528816 A7 B7 V. Description of the invention (9) Increase in the core density. Therefore, in the semiconductor device manufacturer's device manufacturing process, when the wafer subjected to the above-mentioned heat treatment is heat-treated, the above-mentioned oxygen precipitation nuclei will grow into BMD, so even if it is composed of a mixed field of the field [Pv] and the field [PJ The wafer can also make the wafer fully have the IG effect. A sixth aspect of the present invention is to provide a method including: a step of pulling a silicon wafer from a silicon melt, a step of manufacturing a silicon wafer from the silicon wafer, and a heating rate of the silicon wafer from room temperature to K. Heat treatment method for silicon wafers with rapid heating to 650-950 ° C and maintaining at that temperature for 5-30 minutes, which is characterized in that the silicon wafers will OSC occurs at 25¾ K and contains BMD IX 10s ~ 3x 107 pcs / cib30 without transposition. The method of the sixth aspect of the present invention is to use a crystal containing BMD in the OS F field and the density mentioned above. When round, you can omit the heat treatment step before introducing oxygen precipitation nuclei into the wafer and the growth steps to grow the oxygen precipitation nuclei into BMD. The wafers that have been cut and polished from the crystal block can be rapidly heated according to the above conditions. Can exert high IG effect. This invention will be described in detail according to the following embodiments: A. First embodiment The silicon wafers according to the first to fourth embodiments of the present invention are based on the CZ method, from the silicon melt in the hot zone furnace, according to Voronkov theory. A predetermined pulling speed profile (pu 11 ing-upspeedpr 0fi 1 e) is obtained by pulling a crystal block (ing 〇t) and then cutting from the crystal block. Generally, when the silicon single crystal ingot is pulled from the silicon melt in the hot zone furnace according to the CZ method, point defects and aggregates of point defects (-12- $ paper size are applicable to Chinese national standards ( CNS) A4 size (210 X 297 mm) (Please read the notes on the back before filling out this page) Φ Order ------ «'Line · Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives Print Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau ’s Consumer Cooperative π 528816 A7 B7 V. Description of the invention (10) Agglomerates: defects in sand single crystals. There are two general forms of point defects, namely, vacancy point defects and interstitial point defects. Void-type defects are those in which a silicon atom is detached from the normal position of a silicon crystal lattice. Such voids cause a void-type defect. In addition, when silicon atoms are present at an interstitial site outside the crystal lattice point K, silicon-type point defects between the lattices are caused. Point defects are usually formed at the contact surfaces of molten silicon (fused silicon) and crystal blocks (solid silicon). However, when the crystal block is continuously pulled up, the contact surface portion of the crystal block will start to cool while being pulled up. During cooling, void-type point defects or inter-lattice silicon-type point defects will merge with each other due to diffusion to form aggregates of void-type point defects or inter-lattice silicon-type point defects. In other words, the three-dimensional structure formed by the aggregation of point defects in the aggregation system. In addition to the above-mentioned COP, the aggregates of hole-type point defects also contain defects such as LSTD (Laser S ca 11 ering T graph graphs) or FPD (Flow Pattern Defects). The agglomerates contain the previous L / D defects. FPD is a Secco etching of silicon wafers prepared from ingots and dicing (using K2 Cr2 07: 5 (UHF: pure water = 4 4 g: 2 0 0 0 cc: 1 0 The etching source of 0 0 cc mixed solution is called S eccoetching}, which is a trace source of a unique streamline spectrum (f 1 owpa 11 er η). LSTD is a kind of refraction that is different from silicon when infrared rays are irradiated into a silicon single crystal. The source of the scattered light rate.

Voronkov's theory is based on controlling the V / G ratio (C ° / lain) to grow high-purity crystal blocks with few defects, where VUni / min is the pulling speed of the crystal blocks, and G is the hot zone structure (hot zone structure)-13- This paper size is in accordance with China National Standard (CNS) A4 (21ϋ X 297mm)-IJ ^ ---- ^ --------- ^ · I.- ------ 1 ^ • (Please read the notes on the back before filling this page)

Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperative, and the temperature gradient of the boundary (contact) surface with the silicon melt. According to this theory, as shown in Figure 1, KV / G is used as the horizontal axis, and the void type point defect concentration and the inter-lattice silicon point defect concentration are used as the vertical axis to graphically represent the V / G and point defect concentration. Unit K indicates that the boundary between the void area and the inter-lattice silicon area is determined by V / G. More specifically, when the V / G ratio is at the critical point M, a crystal block with a hole-type point defect concentration is dominant, and when the V / G ratio is at the critical point K, an inter-lattice silicon-type point defect concentration is dominant. crystal. The pull-up speed profile set in the first embodiment of the present invention is determined in such a way that when pulling a crystal block from a silicon melt in a hot zone furnace, the pulling speed and The temperature gradient ratio (V / G) is the first critical ratio ((V / Gh) to prevent the occurrence of inter-lattice silicon-type point defects aggregates and maintains the void-type point defect aggregates at the second critical ratio ( (V / G) 2) K, and is limited to the central area of the silly crystal block with hole-type point defects. This pulling speed profile is based on the Voronkov theory by reference simulation. The cutting of the axial direction experiment or the cutting of the reference crystal block experiment into a wafer, or a combination of these technologies. That is, the decision is made by simulating the axial cutting and cutting of the wafer after the simulation. Then, the simulation is performed repeatedly. For the simulation, a variety of pulling speeds are determined within a predetermined range, and a plurality of reference crystal blocks are grown. As shown in FIG. 2, the pulling speed profile used for the simulation is changed from, for example, 1 · 2βπι / minute high lifting speed (a) adjusted to As mentioned low pull rate per (c), and then adjusted to a higher pulling rate U). The lower pull speed of the upper part can also be 0.4βιπι / min or M, and the change of the pull speed (b) and (d) -1 4-This paper size applies the Chinese National Standard (CNS) A4 specification ( 210 X 297 public love) iru ----------------- ^ Order ί ------ ^ 线 φ * (Please read the precautions on the back before filling in this page) 528816 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 5. The description of the invention (I2) should be linear. A plurality of reference crystal blocks pulled at different speeds are cut along the axial direction, respectively. The optimal V / G ratio is determined by the correlation between the cutting in the axial direction, the confirmation of the wafer and the results of the simulation, and then the optimal pulling speed profile is determined, and a crystal block is manufactured according to this profile. The actual pulling speed profile depends on the diameter of the ingot, the quality of the specific hot zone furnace and the silicon melt used, and K includes a variety of variables that are not limited to these. The fact that the graph shown in Fig. 3 is drawn can be obtained by drawing the sectional view of the crystal block when the K-speed is gradually lowered and the K-speed is reduced by V / G. In Figure 3, [V] represents the area where the hollow hole-type point defect is dominant and the aggregate with the hole-type point defect is present, and [I] indicates that the inter-lattice point defect is dominant and the inter-lattice silicon type is present. In the area where the aggregates of point defects exist, [P] represents the perfect (ideal) area where neither the aggregates K of void point defects nor the aggregation of inter-lattice point defects exist. In addition, there is a causal detection method for point defects such as COP and L / D. The detection sensitivity and the lower detection limit may show different values. For this reason, in this specification, the term "the absence of agglomerates of point defects J" refers to the application of K without stirring to Secco etching of silicon single crystals after mirror processing, using an optical microscope to observe the area and etching allowance. When the product is used as the test volume plus K, the aggregates with flow patterns (void defects) and translocation clusters (silicon point defects between cells) are detected in the inspection volume of lxi0-3Cffl3. When one occasion is used as the lower detection limit (1X103 pcs / cm3), the number of aggregates called point defects is below the upper detection lower limit K. -15- This paper size applies Chinese National Standard (CNS) A4 Specifications (210 X 297 mm) —r IW ------------------ Order -------- &quot; • Wire * (Please read the note on the back first Please fill in this page again for details) 528816 A7 B7 V. Description of the invention (13) As shown in Figure 3, the axial position Pi of the crystal block includes the area where the center-hole type point defect is dominant. The position P2 is greater than the position h. Areas with small hole-type point defects dominate. Position P4 contains the ring-shaped area and center where silicon-type point defects between lattices dominate. Perfect area. Position p3 is the perfect area where there are neither void point defects in the center, nor inter-lattice silicon point defects at the edge. It is adjacent to the perfect area in which the void point defects are dominant. The next smallest area is the area where no COP or L / D occurs within the wafer surface. However, this silicon wafer is subjected to the traditional 0SF explicit heat treatment method, and the temperature is 30οοου in an oxygen atmosphere for 30 to 5 hours at a temperature of 2-5 hours. After the heat treatment, followed by a heat treatment for 16 hours at 1 1 3 0 υ ± 30 0 υ, 0SF can occur. That is, as shown in Figure 4, it occurs near 1/2 of the radius of the wafer ^. 0SP ring. Therefore, the hole type point defect surrounded by the 0SF ring has a tendency of C0P to occur. In this regard, in the wafer ^, 0SF is not ring-shaped and occurs only in the center of the wafer. Use The silicon wafer in the first embodiment is such a wafer W2. As shown in FIG. 5, the silicon wafer W2 is not ring-shaped, but occurs only at the center of the wafer. Such a wafer W 2 series cut from the crystal block that grows at a pulling speed profile that can only occur in one of the center sections Figure 6 is a plan view. Because this wafer does not form a ring shape, 0SF does not contain any C0P, and no interstitial dislocation occurs. For the silicon wafer of the first real Ife form, The oxygen concentration in the wafer is further controlled. According to the CZ method, by changing the flow rate of hydrogen supplied to the furnace in the hot zone, the rotation speed of the quartz crucible storing the melt, and the pressure in the furnace in the hot zone, etc. In this paper, the paper size applies the Chinese National Standard (CNS) A4 specification (210 x 297 mm) (Please read the precautions on the back before filling in this page) \ -------- Order P-^ --- --- Line 1 ^ ----- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 528816 A7 B7 V. Description of the invention (14) (Please read the precautions on the back before filling this page) Control the oxygen in the wafer concentration. The oxygen concentration inside the wafer needs to be controlled at 1 · 2 X 1018atoms / cia3M (old ASTM). To achieve this oxygen concentration, for example, the flow rate of hydrogen needs to be controlled at 18-150 liters / minute, the rotation speed of the quartz crucible storing the silicon melt is 4-9 rpm, and the pressure in the hot zone furnace is 15-60 atmospheric pressure. The oxygen concentration of the silicon crystal ring of the first embodiment is controlled at 1.2 × 10 ^ β a toms / cm3 κ (former AS TM) to prevent excessive precipitation of oxygen precipitation nuclei. The surface of the silicon wafer cut from the crystal block pulled according to the above conditions is CVD, for example, using SiH4 to form a polysilicon layer with a thickness of 0.1-1.6 mi at a temperature of 670¾ to 30¾. When the thickness of the polycrystalline silicon layer is under O.luinM, the effect is not good. When it exceeds, the productivity is reduced. Therefore, the preferred thickness is in the range of 1.0-1.6 / iia. Before the polycrystalline silicon layer is formed, even if the oxygen concentration in the wafer surface is uniform, oxygen precipitation is likely to occur at the center of the wafer, and the other parts are not prone to oxygen precipitation. The formation of the polycrystalline silicon layer allows the oxygen in the wafer surface to be precipitated. Homogenize. Therefore, when the above-mentioned silicon wafer having a polycrystalline silicon layer is heat-treated in a semiconductor device project, even if there is an oxygen precipitation core in the wafer, since the core does not grow, a conventional OSF-manifesting heat treatment (OSF-manifesting) heat treat ent) does not occur at 0 SF. [B] The second embodiment of the present invention Prints clothes for the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The second embodiment of the present invention is the same as the first embodiment, and the sand crystal block is pulled from the sand melt according to Voronkov theory. The pulling speed profile of the embodiment in this case is as shown in Figure 7, which is determined so that when pulling the silicon ingot from the silicon melt in the hot zone furnace, the ratio of the pulling speed to the temperature gradient (V / G) Maintained at the 3rd threshold of aggregates that can prevent the occurrence of inter-lattice silicon-type point defects. -17- This paper size applies the Chinese National Standard (CNS) A '丨 size (210 χ 297 male cage) 528816 A7 ___B7 _ 5. Description of the invention (15) (Please read the precautions on the back before filling out this page) tb ((V / G) 3) and limit the agglomerates of void-type point defects to the void-type points in the center of the crystal block Below the 4th critical ratio ((V / G) 4) in the area where defects are dominant. In Figure 7, [I] represents the advantages of inter-lattice silicon-type point defects and the inter-lattice silicon-type point defects exist ((V / G) 3), and [P] represents the aggregates and inter-lattice-type point defects. The perfect field where the aggregate of silicon-type defects does not exist ((V / G) 3) ~ ((V / GW). The field [V] adjacent to the field [P] has a field [OSF] that forms an OSF core [(OSF] (( V / G) 4) ~ ((V / G) 5) exist. This perfect domain [P] is further classified into domain [Pd and domain [Pv] ♦ [Pi] is the V / G ratio from the above (▽). To The critical point area, and [Pv] is the V / G ratio from the critical point to the upper (V / G) 2 area. That is, [Pd] is the lowest adjacent to the area [I] and has an invasive transposition. The area of inter-lattice silicon-type point defect concentration below the inter-lattice silicon-type point defect concentration, and [Pv] is a void type at the lowest void-type point defect concentration M adjacent to [v] and having the lowest SF that can be formed. The area of the concentration of point defects. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the pulling speed is slowly reduced, and the cross section of the crystal block is reduced when V and G are reduced. The fact shown in Figure 8 can be known. .In the crystal block shown in Figure 8 Areas where void-type point defects are dominant [V], areas where inter-lattice silicon-type point defects are dominant, and areas where aggregates of void-type point defects and inter-lattice silicon-type point defects do not exist [P] As mentioned above, the perfect field [Pt] is further classified into a field [Pd and a field [Pν], where the field [Pν] is a field that does not form aggregates and has void point defects, and the field [Pi] is not Areas where aggregates are formed and inter-lattice silicon-type point defects are present. As shown in Figure 8, the axial position Pi of the crystal block contains -1 8-^ in the center of the paper. The Chinese standard (CNS) A4 specification applies. (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 528816 A7 B7 V. Description of the invention (I6) The area with hole type dot defects is dominant. Position P4 is the area with silicon grid type point defects. The superior circle area and the center perfect area. In addition, the position P3 is neither agglomerates containing void-type point defects in the center in the second embodiment, nor agglomerates containing silicon-type point defects between cells. Body, so it is a perfect realm. As can be seen from Fig. 8, the wafer Wi corresponding to the position Pi is an area in which a hole type dot defect is dominant in the center. The wafer W4 corresponding to the position P4 is a circle containing silicon point defects between the lattices. And the perfect area in the center. In addition, the wafer Wi corresponding to the position p3 is the wafer of the second embodiment, which is a condensate with no void-type point defects in its center and no inter-lattice silicon-type defects in its edges. The aggregate is completely perfect, that is, the field [Pv] and the field [PU mixed field. The very small field that touches the complete field where the void point defect is dominant (Figure 7 (V / G ) 4- (V / G) 5) is an area where COP and LD do not occur in the wafer surface. However, for this kind of silicon round ^, conventionally known as 0SF explicit heat treatment, heat treatment in an oxygen atmosphere at a temperature of ΚΙΟΟΟυ ± 30 C for 2 to 5 hours, followed by a heat treatment of κ 11 3 0 other soil 3 0 1C. 16 At hours, 0SF is generated. As shown in Fig. 4 of the first embodiment, 0SF occurs near 1/2 of the wafer radius of the wafer h, and thus the area where the hole-type point defects surrounded by the OSF ring dominates tends to be COP. The silicon crystal of the second embodiment is a wafer W3 with a top surface, and its plan view is shown in FIG. Wafer W3 is intended to undergo the heat treatment according to the second embodiment to form an oxygen precipitation nucleus at a desired density K on wafer W3. Therefore, its oxygen concentration must be maintained at 0 · 8 X 1018 to 1.4X 1018 atoms / cia3 (formerly ASTM ). -19- The size of this paper applies to China National Standard (CNS) A4 (2) (jx 297 mm) II Γ -------- ^ · L. I I ----- (Please read the back first Please note this page and fill in this page again) 528816 A7 B7 V. Description of the invention (1 * 7) The heat treatment of the wafer W3 on silicon is as follows: This heat treatment is to place the wafer W3 under nitrogen, argon, hydrogen or oxygen Or in the atmosphere of such mixed gas, it is implemented by maintaining 3G-9Q points at 600-850-5, or 120-250 points at 600-850¾. The heating is preferably 50-100¾ / min. The wafer is introduced into a heat-treating furnace maintained at 600-8501 at a high speed. When the temperature is maintained at δϋουκ or at a holding time of 30 minutes, the increase (growth) of oxygen precipitation nuclei is insufficient, and it is used by the semiconductor device manufacturer's device. During the manufacturing process, the BMD density required for the IG effect cannot be obtained. When the holding temperature exceeds 850 ° F, the density of the oxygen nucleus in the field [Pi] is low, so it cannot be obtained during the heat treatment of the device manufacturing process. BMD density required for IG effect. In addition, keep the temperature at 600-850¾ and keep the temperature over 90 minutes and 120 At K, there are too many inter-lattice-type point defects accompanying the formation of oxygen precipitation nuclei, which inhibits the precipitation of oxygen precipitation nuclei. When the retention time is above 250 minutes K, the productivity decreases. The above heat treatment conditions are included in Heat treatment conditions for forming a polysilicon layer on the back of a wafer by CVD method (ie, holding temperature 6 5 Q υ soil 3 G ° C, holding time 5-300 minutes). Therefore, CVD method When a polycrystalline silicon layer is formed on the back surface, the above-mentioned heat treatment conditions can be used to achieve the purpose of the second embodiment of the present invention by forming the polycrystalline silicon layer. The thickness of the polycrystalline silicon layer at this time is 0.1-2.0 / iiu. The polycrystalline silicon layer is formed on the back surface of the wafer. In this case, a larger amount of oxygen precipitation nuclei are formed near the back surface of the wafer that is in contact with the polycrystalline silicon layer. In this form, the polycrystalline silicon layer can be left as it is, or it can be immersed in mixed acid K water or fluoric acid and nitric acid or Polycrystalline silicon layer is removed from acid etching solution diluted with acetic acid or alkaline etching solution diluted with K0Η or NaOH water.-20-This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) --- ----- * — l · (Please read the precautions on the back before filling this page) Order L -----! Line | Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs's Consumer Cooperatives 528816 A7 B7 V. Description of the invention (18) When the heat treatment of the upper part is performed, The oxygen donor killer treatment step in the wafer process can be omitted. C. Third Embodiment of the Present Invention The third embodiment of the present invention is the same as the first embodiment, and is melted from silicon based on Voronkov theory. Lift the silicon block. The predetermined pulling speed profile of the third embodiment of the present invention is the same as that of the second embodiment. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) The silicon wafer of the third embodiment is the wafer W3 shown in Figures 8 and 9. When the wafer W3 is heat-treated in accordance with the third embodiment to cause oxygen nucleation above the desired density to occur thereon, the wafer W3 must have an oxygen saturation of 0.8xl (P8 to 1.4 × lOUatoms / cmM old "TM). The heat treatment of this silicon wafer W3 is to place the wafer W3 in an atmosphere of nitrogen, argon, hydrogen, oxygen, or a mixed gas thereof, and heat it from room temperature to a temperature of 1150-1200 t at a temperature increase rate of 10-15 Dt! / S: after In this temperature range, the temperature is maintained for 0-30 seconds. That is, the heat treatment of the third embodiment is rapid heating. The retention time "0 seconds" here means that the temperature is only increased without being maintained. The heating means The wafer is introduced into a heat treatment furnace that maintains room temperature. In the case of continuous lotus rotation, the inside of the heat treatment furnace that maintains hundreds of degrees by the remaining heat, and K 10-150 t! / S, preferably K 5 0-1 0 0 * 0 The rate of heating per second is 1150-12ϋ0 !. At a heating rate of 10t! / Sec, although the oxygen precipitation nuclei increase, but the processing capacity is low, it is not practical. Also, the oxygen precipitation nuclei at 115Q ° CK The increase is insufficient, and the IG effect cannot be obtained when heat treatment is performed in the device manufacturing process of a semiconductor device manufacturer. The necessary BMD density. In addition, when the holding temperature exceeds 1200¾ or the holding time exceeds 30 seconds, problems such as slippage or reduction in heat treatment productivity may occur. In addition, the heating rate exceeds 15 G ° c / second, Because of its own weight-21- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 528816 A7 B7 Five printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives, the invention statement (I9) stress or in-plane The problem of sliding occurs due to the deviation of the temperature distribution. The oxygen donor removal processing step in the wafer manufacturing process can be eliminated (reduced) during the thermal processing as described above. D. Fourth embodiment of the present invention. Fourth embodiment of the present invention. It is the same as the first embodiment, and the silicon ingot is pulled from the silicon melt based on Voronkov theory. The predetermined pulling speed profile of the fourth embodiment of the present invention is the same as that of the first embodiment. This is illustrated in Fig. 10. Each symbol in Fig. 10 corresponds to that in Fig. 3. The characteristic point of this fourth embodiment is that wafer W2 corresponding to position P2 contains wafers in the center compared to wafer Wi. 1 of the total area / 2 area (50%) area where the hole type point defect has the advantage. The perfect area where the hole type point has the advantage is the small area adjacent to the surface where no C0P and L / The field of D. But for this silicon wafer, according to the traditional 0SF manifestation heat treatment (〇SF manifesting heat treatment), Klf100t under an oxygen atmosphere: heat treatment at a temperature of 30 ° C for 2-5 hours, followed by 11 3 When QC soil 3 D υ is heat-treated for 1 to 16 hours, 0 SF occurs. That is, as shown in FIG. 11, a 0SF ring occurs near the periphery of the wafer W2. C0P tends to appear in the hole-type point defects surrounded by this 0SF ring. In response, 0SF does not form a ring shape on the wafer 2 but a disk shape occurs at the center of the wafer. The silicon wafer used in the fourth embodiment is such a wafer W2, and 0SF occurs at 25¾ K of the total area of the wafer. When 0SF is less than 25% of the total area, the occurrence area of BMD is narrow and the ig effect cannot be fully exerted. Therefore, it is preferably 50-80%. -22-, this paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) -βι ίφ ---- I --- I --- — 111 —-- ^ · 1 I I-- ----- (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 528816 A7 B7 V. Description of the invention (20) Silicon wafer W2 of the fourth embodiment, as described in Section As shown in FIG. 12, the OSP is not in the shape of a ring and is selected by the ingot growing in the center according to the predetermined pulling speed profile. The plan view is shown in FIG. 13. Since the silicon wafer W2 $ SF is not ring-shaped, it does not contain COP, and LD (invasive transposition) does not occur at the same time. The ingot used to make the silicon wafer of the present invention contains BMD that does not undergo indexing at a ratio of IX to 3 × 107 pieces / cm3. Therefore, it is not necessary to use it according to JP-A No. 8-4 5 9 4 5. Before the rapid heating, the state of the K wafer should be heated at a low temperature of 500-8001 and maintained for 0.5-20 hours. The introduced oxygen precipitates the nucleus. When the BMD density is IX 105 / cid3M, it is difficult to obtain a sufficient IG effect when the K wafer is heated rapidly. Another 3X 107 / cbi3 is the maximum density that allows BMD to occur in the 0SF field. In the heating method according to the fourth embodiment, it is preferable that a silicon wafer 含有 2 containing BMD which does not undergo indexing with a lift ratio is rapidly introduced into a furnace heated at 650-950 ° C at room temperature. In addition, the upper silicon wafer W2 can be placed at room temperature in a high-speed heating furnace equipped with a lamp that can generate high heat, and the method can be used to rapidly heat the lamp to 650-950¾. That is, the heat treatment of the fourth embodiment is also rapid heating. The so-called rapid heating refers to heat treatment at a heating rate of υ / min, preferably 30 oxi / min. When rapid heating is performed by light irradiation, the wafer can be heated uniformly. Therefore, it has the advantage that the wafer is less likely to warp than a wafer placed in a preheated furnace. If the final temperature reached by the rapid heating is 650 t: K, the BMD near the wafer surface cannot be completely eliminated, so DZ (layers without defects) cannot be fully ensured. If it exceeds 950 ° C, indexing will occur before the BMD near the surface of the wafer disappears, so -23- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------ ------ i Install --- (Please read the precautions on the back before filling this page) 1T. 528816 A7 B7 V. Invention Description (2 works) (Please read the precautions on the back before filling this page) Nor can DZ be fully ensured. For this reason, it is best to be 80G-9001. In addition, when the holding time is at 0.5 minute K, the time for shrinking the B M D on the wafer surface is too short, and the BMD on the wafer surface cannot be sufficiently eliminated, so it is difficult to fully ensure the DZ. If it exceeds 30 minutes, the thickness of DZ will exceed requirements and productivity will be affected. For this reason, the holding time needs to be set in the range of 0.5-30 minutes, preferably in the range of 10-30 minutes. The rapid heating is carried out in a nitrogen atmosphere or an oxygen atmosphere or the atmosphere, preferably in a nitrogen atmosphere. After rapid heating, cool the silicon wafer to room temperature to form a DZ from the wafer surface to a depth of l-100iuffl, so that the part deeper than this DZ has a BMD density of lx 105 ~ 3x 107 pieces / cm3. Wafer. <Examples> Examples and comparative examples of the present invention are described below: Example 1 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, pulling the crystal block to grow over the full length of the crystal block, corresponding to the position shown in FIG. 3 The field of P2. At this time, in order to control the oxygen concentration in the crystal block, the flow rate of argon was maintained at about 110 liters / minute, the rotation speed of the quartz crucible storing the silicon melt was 5-10 rpm, and the inside of the hot zone furnace was about 60 torr. After grinding, chamfering and polishing the silicon wafer obtained by cutting the pulled crystal block, the chemical etching process is used to remove the damage on the surface of the wafer and CVD method is used to form a thickness of 1.5 on the back of the wafer using SifU at 680¾ ^ In polycrystalline silicon layer. Then, mirror polishing was performed to obtain a silicon wafer having a diameter of 8 inches and a thickness of 725 / iiB. Comparative Example 1 Except that a polycrystalline silicon layer was not formed, other methods were implemented according to the method described in Example 1, and a silicon wafer was prepared as Comparative Example 1. -24- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 528816 A7 B7 V. Description of the invention (22) <Comparative Evaluation 1 &gt; For implementation The silicon wafers of Example 1 and Comparative Example 1 were subjected to the second heat treatment of the heat treatment of the silicon-like semiconductor device engineering. That is, in an oxygen atmosphere, the wafers were processed at a temperature of W 7 Ο υ for 8 hours, and then thermally processed at a temperature of 10 Q Q Ό for 12 hours. Then, the FT-IR was used to measure the oxygen concentration on the wafer surface from the central portion to the peripheral portion of the wafers of Example 1 and Comparative Example 1. The oxygen concentration difference Δ [0i] before and after the heat treatment is shown in FIG. As shown in Figs. 14 and 15, the oxygen concentration difference Δ [0 i] before and after the heat treatment of Comparative Example 1 varies greatly from the center portion of the wafer to about 40 ffia. However, compared to this, the oxygen concentration difference Δ [Oi] before and after the heat treatment in Example 1 decreases only approximately 90 niia from the center of the wafer, so that the K wafer is substantially uniform. In addition, another silicon wafer of Example 1 and another silicon wafer of Comparative Example 1 were also subjected to a heat treatment at a temperature of 1 ο ο ο υ for 4 hours, and then heat-treated at a temperature of 1130 ¾ for 3 hours (ignition). Oxidation treatment (pyrogenic oxidation treatment), and then visually inspected for the presence of 0SF. As a result, a white clouded 0SF was found in the center of the wafer of Comparative Example 1, but the wafer of Example 1 was free of 0SF. appear. Example 2 A silicon single crystal pulling device was used to pull up a P-type silicon crystal block doped with boron (B) having a diameter of 8 inches. The crystal block has a length of 1200 mm, a crystal orientation (100), a resistivity of about 1 GQ cm, and an oxygen concentration of 1.0 × 1018atoas / cm3 (formerly ASTM). V / G during pulling is continuously reduced from 0 · 24®πι2 / min to 0 · 181 ^ 2 / min t, and two crystal ingots are cultivated under the same conditions, among which -25- this paper size is applicable 0 National Standard (CNS) A4 specification (210 X 297 mm) ------- i --- rAW ^ ------- Γ -------- (Please read the Please fill out this page again) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 528816 Α7 _______ Β7 V. One of the crystal blocks of the invention description (23), as shown in Figure 8, cut off from its center along the pull direction, And check the position of each field, the other one cut out the silicon wafer W3 corresponding to the position P3 in Figure 8 as a sample. That is, the sample of this embodiment is a wafer W3 as shown in FIG. 9 with a domain [Pv] in the center and a domain [Pd] around it, and a domain [Pv] further around this domain. The wafer W3 cut out from the crystal block and mirror-polished is placed in a nitrogen atmosphere, and heat-treated at 650 ° F for 30 minutes. Example 3 Except that the same wafer in Example 2 was cut out and the mirror-polished wafer W3 was heat-treated at a temperature of 650 ° and a holding time of 90 minutes, the rest was implemented in accordance with Example 2. Spring Example 4 Except that the wafer after mirror polishing is subjected to a heat treatment at a temperature of 65 Dt! And a holding time of 210 minutes, the rest is implemented according to Example 2. Embodiment 5 Except that the wafer W3 after mirror polishing is heat-treated at a temperature of 750 ° F and a holding time of 60 minutes, the rest is implemented according to Embodiment 2. Example 6 The wafer W3 after mirror polishing was heat-treated at a temperature of 750 ° F. and a holding time of 90 °. Embodiment 7 Except that the wafer W3 after mirror polishing is heat-treated at a temperature of 85 ° F. and a holding time of 30 minutes, the rest is implemented in accordance with Embodiment 2. Example 8-2 6-This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) „----------- 1TL ------- line (please first Read the notes on the back and fill in this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 528816 Λ7 B7 V. Description of the invention (24) Except for the wafer w3 with a temperature of 85 ° and a holding time of 120 minutes Except for the heat treatment, the rest is implemented according to Example 2. Comparative Example 2 The wafer W3 after mirror polishing of the same crystal block cut out in Example 2 is not subjected to heat treatment. Comparative Example 3 except for wafer W3 after mirror polishing Except for the heat treatment at a temperature of 6 5 0 υ and a holding time of 100 minutes, the rest is implemented in accordance with Example 2. Comparative Example 4 Except for performing a heat treatment at a temperature of 750 υ and a holding time of 20 minutes on the wafer W3 after mirror polishing, the rest It is implemented according to Example 2. Comparative Example 5 Except that the wafer W3 after mirror polishing is heat-treated at a temperature of 80 Gt and a holding time of 100 minutes, it is implemented according to Example 2. <Comparative Evaluation 2 &gt; Preparation Example 4 each of wafers W3 of 2-8 and Comparative Example 2-5, and the surface of these wafers W3 It contains Fe, Cr, Ni, Cu and other metal elements to dissolve the wafers and forcefully pollute Fe, Cr, Ni, and Cu. Then, the entire wafer W3 is sequentially heat-treated at 900 for 2 hours. Heat treatment at 1000 ° C for 5 hours and heat treatment at 800 ° C for 1 · 5 hours to diffuse the gold element into the entire bulk of the wafer. The heat treatment after such contamination is equivalent to semiconductor manufacturing In order to confirm the IG effect of metal contamination, the wafer is etched with a secco etching solution to a thickness of about 2 / z in thickness and placed in a spotlight -27- This paper size applies Chinese national standards ( CNS) A4 specification (210 X 297 mm) l · ---- M .------- r ^ ^ ------ (Please read the precautions on the back before filling this page) 528816 A7 B7 V. Description of the invention (25) The presence or absence of haze is observed. The presence or absence of haze in Examples 2-8 and Comparative Examples 2-5 is shown in Table 1. In addition, an optical microscope photograph of Example 2 is shown in Figs. 16A-16D, and an optical microscope photograph of Comparative Example 2 is shown in Figs. 17A-17D. Figs. 16A and 17A respectively show contamination with Fe. A quarter of the wafers of Example 2 and Comparative Example 2. Similarly, Figures 16B and 17B show contamination with Cr, Figures 16C and 17C are contaminated with Ni, and Figures 16D and 17B Figure 17D shows a quarter of the wafers of Example 2 and Comparative Example 2 contaminated with Cu, respectively. --Install --- (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Table 1 Heat treatment conditions turbidity temperature (υ) time (minutes) field [Ρν] field [ Pi] Example 2 650 30 No No Example 3 650 90 No No Example 4 650 210 No No Example 5 750 60 No Inr Μ Example 6 750 90 No No Example 7 850 30 No M Example 8 850 120 None -ίππ Μ Comparative Example 2--InC Thermal Yes Comparative Example 3 650 100 inf Yes fcb Comparative Example 4 750 20 No Yes Comparative Example 5 800 100 No Yes Table 1, 16A-16D and 17A-17D Only in the area [Pi] of the wafer of Comparative Example 2-5, turbidity occurs. This is because Comparative Example-2 8-This paper size applies the Chinese National Standard (CNS) A4 specification (210 x 297 mm). Order- · 528816 A7 ______ B7 V. Description of the invention (26) Under the heat treatment conditions of 2-5, the oxygen density of the wafer is low, and the heat treatment after pollution cannot exert the IG effect. Since the wafer of Example 2-8 did not appear turbid, the areas [Pv] and [Pi] had high-density oxygen precipitation nuclei in their entirety, which caused the IG effect. Example 9 'A boron (B) -doped P-type sand crystal block with a diameter of 8 was pulled using a silicon single crystal pulling device. The crystal block has a length of 1200 fflffl, a crystal orientation (100), a resistivity of about 10 Ω cm, and an oxygen concentration of 1.0 × 1018 at 0ffls / cni3 (former ASTM). The crystal block was grown under the condition that the V / G during pulling was continuously reduced from 0 · 24βιβι2 / min t to 0.18 mm2 / min, and two crystal blocks were grown under the same condition, one of which is shown in Figure 8 , Cut the center of the crystal block in the pulling direction to check the position of each field; the other crystal block is cut out as a sample as shown in FIG. 8 to the wafer W3 corresponding to the P 2 position. As shown in FIG. 9, this sample wafer W3 has a region [Pν] in the center, a region [PΗ] around it, and a region [Pν] further around the region [Pi]. The wafer W3 cut out from the crystal block and mirror-polished is placed in a nitrogen atmosphere, heated from a room temperature to a temperature of about 50 ° C / s to a temperature of 1150 ° C, and then not maintained at this temperature, and immediately heat-treated. Embodiment 10 Except that the heat treatment is performed on the wafer W3 at a temperature of 1150 ° for 5 seconds, the rest is implemented according to Embodiment 9. Embodiment 11 Except that the wafer W3 is heat-treated, it is maintained at a temperature of 1150 ° F. for 30 seconds, and the rest is implemented according to Embodiment 9. -29- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) (please read the precautions on the back before filling this page); install t.— ijm 1: mouth, f ϋ · 1 an ni ··· · 1. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 528816 Α7 _ _____ Β7 V. Description of the invention (27) m 12 Except for the temperature at which the heat treatment of wafer W3 is changed to 1 2 0 0 ¾ The rest is implemented according to Embodiment 9. m 13 is implemented in accordance with Embodiment 9 except that the temperature for heat-treating wafer W3 is changed to ΐ200υ and maintained at this temperature for 5 seconds. Example 1 4 Except that the temperature for heat-treating the wafer W3 was changed to 12 () t! And maintained at this temperature for 3Q seconds, the rest was implemented in accordance with Example 9. Comparative Example 6 Wafer W3 after mirror polishing of the same crystal block cut out of Example 2 was not subjected to heat treatment. Comparative Example 7 Except that the wafer W3 was heat-treated, it was kept at the temperature of uoot! For 5 seconds, and the rest was implemented according to Example 9. Comparative Example 8 Except that the wafer W3 was heat-treated, it was maintained at a temperature of 1100 ° for 30 seconds, and the rest was implemented according to Example 9. Comparative Example 9 Except that the wafer W3 was heat-treated, it was maintained at a temperature of 110 ° C. for 60 seconds, and the rest was implemented according to Example 9. Comparative Example 10 Except that the wafer W3 was heat-treated, it was maintained at a temperature of 11501C for 60 seconds, and the rest was implemented according to Example 9. * -30- This paper size is in accordance with China National Standard (CNS) A4 (210 χ 297 mm) (Please read the precautions on the back before filling out this page) Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 528816 A7 ___ ______ B7 V. Description of Invention (28)

Jbt Example 11 Except that the wafer W3 is heat-treated, it is maintained at a temperature of 12 00 ¾ for 60 seconds, and the rest is implemented according to Example 9. Example 12 Except that the heat treatment was performed on the wafer W3, the temperature was maintained at 125 ° C for 5 seconds, and the rest was implemented according to Example 9. Comparative Example 1 Except that the wafer W3 was heat-treated, it was maintained at a temperature of ΐ25〇υ for 30 seconds, and the rest was implemented according to Example 9. &lt; Comparative evaluation 3 &gt; The wafers of Examples 9-14 and Comparative Examples 6-13 were respectively subjected to a heat treatment in a device process of a semiconductor device maker under a nitrogen atmosphere and maintained at 800 ° F. for 4 hours, and then Heat treatment in an oxygen atmosphere at 1000 t for 16 hours. After the heat treatment, the wafers were cleaved, and the wafer surface was selectively etched with a Wright etching solution, and then observed with an optical microscope to measure the wafer surface to a depth of 3 50 / im [Pi] and The BMD area density corresponding to the area [Pi] and the presence or absence of slip. The results are shown in Table 2. (Please read the notes on the back before filling this page)-· 装 tri ----- 1 、. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-31- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 528816 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (29) Table 2 Heat treatment conditions BMD area density (cm2) With or without slip temperature (0 Time (minutes) Field [Pv ] Field [Pi] Example 9 1150 0 3.6X 104 3 · 5 × ΙΟ4 Without Example 10 1150 5 2.4X 10 * 2.3 × ΙΟ4 Without Example 11 1150 30 1.2X 104 1.0 × ΙΟ4 Without Example 12 1200 0 532.0X lfl4 411.0 × ΙΟ4 No Example 13 1200 5 412.OX 104 356.ΟΧ ΙΟ4 No Example 14 1200 30 37.7 × 104 77.3 × IO4 No Comparative Example 6 No treatment 40.〇Χ ΙΟ4 0 · 1 × ΙΟ4 No Comparative Example 7 1100 5 1.0 × ΙΟ4 0 · 1Χ ΙΟ4 No comparative example 8 1100 30 2 · 2Χ ΙΟ4 0 · 1Χ ΙΟ4 No comparative example 9 1100 60 2 · 2Χ ΙΟ4 0 · 1Χ IO04 No comparative example 10 1150 60 0 · 5 × ΙΟ4 0.1 × ΙΟ4 Yes Comparative Example 11 1200 60 125.〇Χ ΙΟ4 0.5χ ΙΟ4 Comparative example 12 1250 5 73 · 5 × IO4 68.5 × ΙΟ4 Comparative example 13 1250 30 65.4 × ΙΟ4 58.8 × ΙΟ4 It can be known from Table 2 that the BMD area corresponding to the area [Pi] of the wafer of Comparative Example 6-11 The density does not reach the BMD area density that can express the effect of IG (ie IX 104 / cm2, preferably 2X 104 / cm2). Although the areas [Pv] of Comparative Examples 12 and 13 and equivalent areas [Pi] Part of the BMD area density exceeds 2X 104 pcs / cb2, but slippage occurs. The wafers of Comparative Examples 10 and 11 also have slippage. In response, the wafers of Examples 9, 10, 12-14 The area [Pv] and the area equivalent to the area [Pi] have a BMD area density of more than 2 × 1G4 pieces / cm2, and no slippage occurs. In particular, the wafers of Examples 12-14 have a higher BMD area density. In addition, the embodiments Although the wafer of 11-32- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 x 297 mm) ί. * &Quot; &quot; · Broadcasting book ----- — .S., (Please read the precautions on the back before filling this page) 528816 A7

V. Description of the invention (30) The BMD area density is lower than 2X 104 pcs / cm2, but the precipitation distribution in the wafer is uniform. Example 15 When pulling a silicon single crystal ingot from a silicon melt, as shown in FIG. 1, the ratio of the pulling speed to the temperature gradient (V / G) is maintained at (V / G) 2 or more above the critical point. At the same time, a wafer with an oxygen atmosphere and a looot temperature of 2 hours and then processed at 11QQ ° C for 12 hours will produce 0SF at 252 of its total area. The full length of this crystal block corresponds to the position p2 shown in FIG. 10. After pulling out the wafer from the pulled crystal block and grinding it with K to remove corners, the surface of the wafer was removed by chemical etching to obtain a mirror silicon wafer. This mirror wafer was heated from room temperature to 850 ° C at a temperature rising rate of κ30 / min, and kept at this temperature for 5 minutes, and then cooled to room temperature. Example 1 6 Except that the ingot was pulled to make 0SF in 50¾ of the total area of the wafer, the processed wafer was subjected to 850¾ and 5/5 heat treatment in the same manner as in Example 15. Example 17 In addition to the 0SF occurring in 8Π of the total area of the wafer, the processed wafer was heat-treated at K85G ° C and 0.5 minutes in the same manner as in Example 15. Example 18 Except that the ingot was pulled so that 0 SF occurred in 80% of the total area of the wafer, the processed wafer was subjected to K850P and a heat treatment of 5/5 in the same manner as in Example 15. Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling out this page). ------- 11-Order ·· ------- Economy Printed by the Employees 'Cooperatives of the Ministry of Intellectual Property Bureau 528816 A7 ----- B7 Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (31) Example 1 9 Except for lifting the crystal block to make the total area on the wafer Except for the occurrence of OSF at 80S !, the processed wafer was subjected to K85Qt: and 10-minute heat treatment in the same manner as in Example 15. Example 20 0 Except that the ingot was pulled to cause OSF to occur in 80¾ of the total area of the wafer, the processed wafer was subjected to a heat treatment of K85 and 20 minutes in the same manner as in Example 15. Example 2 1 Except that the ingot was pulled to cause 0SF to occur in 80% of the total area of the wafer, the processed wafer was treated with K850Κ and heat-treated for 30 minutes in the same manner as in Example 15. Example 22 Except that the ingot was pulled so that OSF occurred in 80% of the total area of the wafer, the processed wafer was subjected to K700t :, 5 minutes heat treatment in the same manner as in Example 15. Example 2 3 Except that the ingot was pulled to cause 0SF to occur in 80% of the total area of the wafer, the processed wafer was heat-treated at 8001C and 5 minutes in the same manner as in Example 15. Example 2 4 Except that the ingot was pulled so that 0SF occurred in 80% of the total area of the wafer, the processed wafer was treated with K950t! For 5 minutes in the same manner as in Example 15. -34-(Please read 4 notes on the back before filling and writing this page)-! * Order -------- Γ f This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 528816 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _ B7 _-__ V. Description of the Invention (32) Comparative Example 1 4 Except for pulling the crystal block to cause OSF to occur in 15% of the total area of the wafer In the same manner as in Example 15, the processed wafer was heat-treated at 850 ° F and 5 minutes. Comparative Example 15 Except that the ingot was pulled to cause OSF to occur at 80X of the total area of the wafer, the processed wafer was treated with M64G1C for 5 minutes in the same manner as in Example 15. Comparative Example 16 Except that the ingot was pulled to cause OSF to occur in 80% of the total area of the wafer, the processed wafer was heat-treated in the same manner as in Example 15 for 5 minutes. Comparative Example 17 Except that the ingot was pulled to cause 0SF to occur in 80% of the fiber area of the wafer, the processed wafer was subjected to heat treatment at 850 ° F and 40 minutes in the same manner as in Example 15. <Comparative Evaluation 4> Each of the wafers of Examples 15-24 and 14-17 was cleaved, and then the wafer surface was selectively etched by Ryder etchant, and then the width and DZ of the DZ were measured with an optical microscope observation. BMD density of wafer surface depth of 25 〇αΐΒ. The measurement results are shown in Table 3. A 50,000-times magnification microscope photo of the BMD in the wafer after rapid heating in Example 18 is shown in FIG. 18. -35-This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) I -----— It ----- (Please read the precautions on the back before filling this page) 528816 A7 B7 V. Description of the invention (33) Table 3 Total area ratio in the 0SF field U) IG heat treatment conditions BMD density (X 106 / cm3) DZ width (u ffl) Temperature (υ) Time (minutes) Example 15 25 850 5 2.6 40 Example 16 50 850 5 3.4 40 Example Π 80 850 0.5 10.0 15 Example 18 80 850 5 10.0 35 Example 19 80 850 10 11.0 45 Example 20 80 850 20 10.0 65 Example 21 80 850 30 12.0 85 Implementation Example 22 80 700 5 23.0 20 Example 23 80 800 5 22.0 35 Example 24 80 950 5 24.0 55 Comparative Example 14 15 850 5 100K at 1.0 M Comparative Example 15 80 640 5 20.0 0 Comparative Example 16 80 1000 5 5.0 100K The above comparative example Π 80 850 40 12.0 100K (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs It can be seen from Table 3 that after the IG heat treatment, due to the OSF of Comparative Example 14, The field is too small, accounting for only 15¾ of the total wafer surface, so the BMD density is not up to IG effect volatilization of 10s / cm3 of the spectrum. As for Comparative Example 15, the DZ was not formed on the wafer surface because the heat treatment temperature was too low, that is, 640 °. The heat treatment of Comparative Example 16 was too high, i.e., 100P, and thus formed 02 with a necessary width. In addition, Comparative Example 17 had a long heat treatment time, i.e., 40 minutes, and thus a DZ having a necessary width over K was formed. In this regard, the silicon wafers of Examples 15-24 have a BMD density of lDs to 107 / cm3, which can exert the IG effect. In particular, Examples 17-22 in which the 0SF field is 80% have a BMD density of l〇7 / cai3 of -36- ~ 1 ~~ ---- order ---------. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Ministry of Economic Affairs Printed by the Intellectual Property Bureau's Consumer Cooperatives 528816 A7 ___B7 _ 5. The invention description (34) spectrum, in which Example 19-21 of heat treatment time 10-30 minutes and Example 24 of heat treatment temperature 9 5 0 ¾, shows 4 5 -8 5 / im DZ with large width. It can also be seen from the micrograph of Fig. 18 that the BMD existing in the crystal circle after the rapid heating treatment has been dislocated. Brief description of the drawings. Figure 1 is a diagram showing the relationship between the V / G ratio and the concentration of void-type point defects or inter-lattice silicon-type defects according to Voronkov theory in the first embodiment of the present invention. The characteristic diagram of the variation of the pulling speed in the pulling speed profile. Figure 3 shows the areas where the void type point defects are dominant in the reference crystal block of the first embodiment of the present invention, and the silicon type point defects between the lattices are dominant. X-ray tomography image of the realm and the perfect realm; Fig. 4 is a diagram showing a state where 0SF appears on the silicon wafer Wi at the position Pi corresponding to Fig. 3; Fig. 5 is a Pit through the position corresponding to the third picture Sectional view of the axial center of the crystal block cut along the axial direction; FIG. 6 is a diagram showing a state where 0SF appears in the center portion of the silicon wafer # 2 corresponding to the position 卩 2 in FIG. 3; FIG. 7 is Voronkov theory shows the relationship between the V / G ratio and the concentration of void-type point defects or inter-lattice silicon-type defects in the second and third embodiments of the present invention; FIG. 8 shows the reference crystals of the second and third embodiments of the present invention. Block No. -37- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) &quot; 1 * 111111 ^ 1-11 I · 11111FI (Please read the notes on the back before filling out this page) 528816 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Description (35) X-ray tomographic images of the area where the hole type point defect is dominant, the area where the silicon type point defect is dominant, and the perfect field; Figure 9 is a plan view showing the silicon wafer W3 corresponding to the position p3 of Figure 8; Fig. 10 is an X-ray tomographic image of a field in which a hole type point defect is dominant in a reference crystal block in the fourth embodiment of the present invention, a field in which inter-lattice silicon type point defects are dominant, and a complete field. Fig. 11 is a display The silicon wafer at position h corresponding to FIG. 3 has a state where OSF appears; FIG. 12 is a cross-section cut along the axial direction through the axis center of the crystal block corresponding to position 卩 2 in FIG. 10 FIG. 13 is a diagram showing a state where OSF appears at the center of the silicon wafer ^ corresponding to position 10 in FIG. 10; FIG. 14 is a diagram showing each silicon wafer in Example 1 and Comparative Example 1 In the wafer surface before and after the first heat treatment imitating the heat treatment of semiconductor device engineering △ [〇i] status diagram; Figure 15 shows the silicon wafers of Example 1 and Comparative Example 1 in the wafer surface before and after the second heat treatment imitating the semiconductor device engineering heat treatment △ [〇i] Fig. 16A is an optical microscope photograph of whether the wafer of Example 2 was contaminated with Fe, and Fe was diffused into the entire wafer with or without turbidity; Fig. 16B is a diagram of Example 2 Wafer W2 is contaminated with Cr, and whether there is an optical neck micromirror photo of turbidity after Cr diffuses into the entire wafer; FIG. 16C is a view showing that the wafer of Example 2 is contaminated with Ni, and Ni expands to -38. -This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) ^ -------- tT --------- (Please read the precautions on the back before filling in this (Page) 528816 A7 B7_ V. Description of the invention (36) Optical micrograph of turbidity after scattering to the whole wafer; Figure 16D shows the wafer ¥ 2 of Example 2 contaminated by (: 11, Cu Optical micrograph of turbidity after diffusion into the entire wafer; Figure 17A shows the wafer ¥ 2 of Comparative Example 2 contaminated with 卩 6 Let the Fe diffuse into the entire wafer and see if there is any optical turbidity; Figure 17B is the contamination of the wafer of Example 2 and the contamination caused by the diffusion of Cr into the entire wafer. Photograph of an optical microscope; FIG. 17C is an optical microscope photograph of whether the wafer W2 of Example 2 is contaminated with Ni, and Ni has diffused into the entire wafer with or without turbidity; FIG. 17D is a crystal of Example 2 Circle ¥ 2 is contaminated by (: 11, whether there is an optical microscope photo of turbidity after Cu has diffused into the entire wafer; circle δ is the status of oxygen precipitates (BMD) in wafers subjected to rapid heat treatment. Micrograph. -* — · "1-1 #-装 ------- 卜 定 -------- 卜 —up. (Please read the notes on the back before filling out this page) Intellectual Property Bureau, Ministry of Economic Affairs The paper size of the printed clothing paper of the employee consumer cooperative is applicable to the Chinese National Standard (CNS) A4 (210 x 297 mm)

Claims (1)

528816 Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, A9 B9 C9 D9 Patent Application No. 89122008, Republic of China &quot; Monthly Revision, Revised Application Scope of Patent &lt; Please read the precautions on the back before drawing) 1. The heat treatment method for silicon wafers includes the following: No crystal particles and intrusive indexing gas concentrations occur within the wafer surface 1.2 &gt; &lt; 101831: 〇11 ^ / (! 1113 下 (旧 &amp; 5 了The step of forming a polycrystalline silicon layer with a thickness of 0.1-1.6 m in accordance with the chemical vapor deposition method on the back of the silicon wafer; placing the above-mentioned silicon wafer with a polycrystalline silicon layer under an oxygen atmosphere, After performing heat treatment at a temperature of 100OCtSOC for 2-5 hours, the process of heat treatment at a temperature of 11301 to 3010 is continued for 1-16 hours; its characteristics are as follows: before forming the polycrystalline sand layer described above, When the above-mentioned heat treatment is performed on the wafer, those who cause accumulation defects due to oxidation will appear at the center of the wafer. 2. A method for manufacturing a silicon wafer with a polycrystalline silicon layer, which uses a chemical vapor deposition method to crystallize No occurrence in a circular plane The method of forming a polycrystalline silicon layer with a thickness of 0.1-1 · 6 μin on the back of a silicon wafer with crystalline particles and an oxygen-converting oxygen concentration of 1.2 × 1018atoros / cin3 (older ASTM) is particularly advantageous. ： The silicon wafer is subjected to a heat treatment at a temperature of 1000 ¾ ± 30 ¾ for 2-5 hours under the oxygen atmosphere before the formation of the above polycrystalline silicon layer, and then a heat treatment of 1130 ¾ to 30 t: is continued for 1 to 16 hours. At the time, the defects caused by oxidation and accumulation at the center of the wafer will appear. -1- This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 528816 B9 C9 D9 3. — A heat treatment method for silicon wafers, This wafer is cut out from a crystal block formed by the perfect field [P]. The method includes: X Please read the precautions on the back before drawing.) Pull from the silicon melt. [Pv] and field [Single silicon ingot composed of a mixed field of PJ and having an oxygen concentration of 0.8X1018 ~ 1.4 × 1018 (former ASTM); and after a silicon wafer is cut out from the ingot, the silicon wafer is placed in nitrogen, argon, and hydrogen In the atmosphere of oxygen, oxygen or mixture thereof, at 600-850 t: The temperature is maintained between 30 and 90 minutes; the domain [P] is a perfect domain where neither the interstitial silicon-type point defect aggregates nor the void-type point defect aggregates exist; the domain [Pd] is adjacent to the domain [I] And the area which belongs to the above-mentioned perfect area [P] and has the lowest inter-lattice silicon concentration that can form an intrusive translocation; the above-mentioned area [I] is in the silicon single crystal block, the inter-lattice silicon The field where the point defect is dominant; the field [V] is the field where the hole type point defect is dominant; and the field [Pv] is adjacent to the above field [V] and belongs to the above perfect field [P] and has a formability The area of pore density below the pore density of COP or FPD. The Intellectual Property Bureau of the Ministry of Economic Affairs ’s consumer co-operative society printed silicon to accumulate in the stack, and learned how to use the tactics to deal with the heat. The third layer of the Fan Si Lijing, please apply for it. Such as the face back 4, the circle. Crystal method 5 Finished by—1 kind 1 from pseudo-round crystal The method 311 heat-treated round crystal silicon be kind This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) 528816 A9 B9 C9 D9 US field [P] The formed crystal block is cut out, and the method includes: pulling up from a silicon melt solution composed of a mixed field of a field [Pv] and a field [Pi] and having an oxygen concentration of 0 · δ × ΐ18 ~ 1 · 4 × 1018 ( Old ASTM); and after cutting out the silicon wafer from the crystal block, the silicon wafer is placed in an atmosphere of nitrogen, bell hydrogen, oxygen or a mixture thereof, and maintained at a temperature of 600-850 " 1 20-250 points; the field [P] is a perfect field in which the aggregates of silicon-type point defects between the lattices and the aggregates of void-type point defects do not exist; the field [Pl] is adjacent to the field Π] and belongs to the above The perfect area [P] and the area with the lowest inter-lattice silicon concentration that can form intrusive translocations. The above-mentioned area [I] is that in the silicon single crystal block, the inter-lattice silicon point defects account for Area of advantage; Area [V] is the area where void point defects are dominant; and Area [Ρν] Adjacent to the above-mentioned field [V] and the perfect field [P] described above and have a void concentration below the void concentration that can form C0P or FPD, please read the precautions on the back before drawing), τ line economy Printed by the Ministry of Intellectual Property Bureau's Consumer Cooperatives 6. If the heat treatment method of item 5 of the patent scope is applied, the chemical vapor deposition method is used for the heat treatment when a polycrystalline silicon layer is formed on the back of the silicon wafer. 7. — Silicon wafer Heat treatment method, the wafer is pseudo cut out from a crystal block formed by the perfect field [P], the method includes: 3 one person one paper size applies Chinese National Standard (CNS) Α4 specification (210X29 * 7 mm) 528816 A9 B9 C9 D9 is a silicon single crystal ingot composed of a mixed domain of the domain [Pv] and the domain [Pi] and having an oxygen concentration of 0.8X1018 to 1.4X1018 (formerly ASTM) from silicon melting; and from the crystal After the silicon wafer is cut out, the silicon wafer is placed in an atmosphere of nitrogen, argon, hydrogen, gas, or a compound thereof, and is heated from room temperature to 1150-1200 at a temperature of 10-150 T: / s. * 0, and stay in this temperature range for 0_30 seconds; where The domain [P] is a perfect domain where neither agglomerates of silicon-type point defects between the lattices nor agglomerates of void-type point defects exist; the domain [Pd] is adjacent to the domain [I] and belongs to the above-mentioned perfect domain [P] and The area with the lowest inter-lattice silicon concentration that can form intrusive indexing; the above-mentioned area [I] is the area where inter-lattice silicon-type point defects are dominant in silicon single crystal blocks; V] is the area where the hole-type point defect is dominant; and the area [Pv] is the space adjacent to the above-mentioned area [V] and the perfect area [P] described above, and has a space below the concentration of pores that can form COP or FPD. Area of pore concentration. 8. A method for heat treatment of a silicon wafer, including: a step of pulling a silicon single crystal block from a silicon melt; a step of cutting a silicon wafer from the crystal block; a temperature rising rate of 101 / min or more from room temperature The silicon wafer is rapidly heated to 650_950t: and maintained at the temperature range of 0,5-30 minutes; characterized in that when the wafer is subjected to thermal oxidation treatment, oxidation occurs in more than 25% of the total area of the wafer Causes stacking defects without indexing— ^ — This paper size applies to China National Standard (CNS) A4 (210X297 mm) --------- # 1. 0 Please read the back Note for re-drawing) Order _ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ---- 528816 A9 B9 C9 D9 produces lx 1015 ~ 3X 107 oxygen precipitates / cra3. 9. The heat treatment method according to item 8 of the scope of patent application, wherein the sand single crystal block is pseudo-pulled from the silicon melt, so that when the silicon wafer prepared by the silicon wafer is subjected to thermal oxidation treatment, the total area of the silicon wafer will be In more than 25% of the regions, gasification-induced accumulation defects and IX 1015 ~ 3 × 107 / Cffl3 gas deposits without translocation occurred. J ---? --- 1 .-- (Please read the precautions on the back before drawing) -Line _ Printed by the Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5- This paper size applies to Chinese National Standards (CNS) A4 specifications (210X297 mm)