TW301020B - - Google Patents
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- TW301020B TW301020B TW085105771A TW85105771A TW301020B TW 301020 B TW301020 B TW 301020B TW 085105771 A TW085105771 A TW 085105771A TW 85105771 A TW85105771 A TW 85105771A TW 301020 B TW301020 B TW 301020B
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- diffusion barrier
- barrier metal
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- H10D64/011—
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- H10W20/048—
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- H10P14/418—
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- H10W20/033—
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- H10W20/047—
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
Description
301020 麵涛部中夬棣率局貝工消費合作衽印製 五、發明説明(1 ) 發明之背景 本發明係關於於半導體裝置中製造擴散障壁金屬層之方 法,其可防止在半導體裝置之金屬線路形成之時該半導體 裝置之金屬線路物質擴散進'入其下層,且更特別係關於, 製造擴散障壁金屬層之方法,其可被使用於深而狹窄之接 觸。 、一般而言’一氧化釕層(Ru02)於超過256M DRAM以上 之高度積链半導體裝置中被使用作爲擴散障壁金屬層,且 被使用作爲鋁、鎢或銅製成之金屬線路層之膠合層。於先 前技藝中,氧化釕層係藉物理氣相沉積(PVD)或化學氣相 沉積(CVD)方法所製成。在PVD方法中,釕與氧被化合以 製成氧化釕層《於CVD方法中’釕來源氣體與氧經由金屬 有機化學氣相沉積方法被化合以製成氧化釕層。 然而’在氧化釕層係由CVD方法所形成之;^合中,不純 物被加入氧化釕層中。此增加了層之阻抗値。在使用PVD 之場合中,氧化釕物層之有效範圍不佳,且氧化釕層與碎 之反應可能形成一 <5夕化物層。另外,於氧化釕層沉積時, 氧化速率係太低以致於無法形成穩定之氧化釘層。 發明之板单 本發明之目的係提供於半導體裝置中製造擴散障壁金屬 層心方法’其可防止在釕與矽層間之界面形成一矽化物層 ’且在高溫下形成一穩定之氧化釕層。 爲達成本發明之目的,此處提供於半導體裝置中製造擴 散障壁金屬層之方法以防止在該半導體裝置中之金屬線路 請 先 閲 讀 背. 之 注- 旁 裝 訂 線 L尺(加χ297公楚 五、發明説明(2 ) A7 B7 經濟部中央梂準局負工消費合作社印裝 材料擴散進入在該金屬線路下之矽層,該方法包含以下步 驟:將該矽層之表面曝露於氧電漿中,以防止在該矽層與 擴散障壁金屬層間<界面形成一矽化物;在該矽層上形成 第一擴散障壁金屬層;將氧·離子佈植入該第一擴散障壁金 屬層内;及在該第一擴散障壁金屬層上形成第二擴散障壁 金屬層。 -附圖之簡短敘述 本發明之其他目的與樣態自.以下具體實例之敘述及參考 隨附之圖示將變得更易明白,其中: 第1 A圖至圖1 F圖係舉例說明.根據本發明之具體實例以 製造擴散障壁層製法之剖面囷。 發明之詳細敘述 本發明之較佳具趙實例將參考隨附之諸圖示於以下描述 。第1入圖至1F圖係形成氧化釕層作爲擴散障壁金屬層之 説明製程之剖面圖。 如第1 A圖所示,一絕緣層3被形成於矽基質i與場氧化 層2之上,而一導電層4被形成於場氧化層2之上。然後, 一絕緣層5被形成於基質1整體表面之上,且絕緣層3及5 視需要被移除以形成一接觸孔,因此暴露出梦基質1與導 電層4之預定部份。 如第1B圖所示’基質1之整體表面被暴露於%電漿6之 中。此處’ 〇2電漿6粘附於在其上已形成導電層4與絕緣 層5之基質1之整體表面,〇2電漿係由低於5〇w以下之低 電犯’及在5 seem至50 seem之氣流下於電衆增強化學氣 請 先 聞 讀. 背 冬.
I 裝 訂 線 5- 經濟部中央梂準局負工消費合作社印袋 A7 ________B7 五、發明説明(3 ) 相沉積(PEC VD)室被製得》如以上所述,藉實施〇2電漿處 理’其係有可能防止於後續之熱處理時在釕與梦間之界面 形成矽化物,及在高溫下形成穩定之氧化釕層。 如第1C圖所示,第一釕雇7於PVD濺射室中在其上形成 導電層4與絕緣層5之基質1之整體表面上被形成,厚度達 100 A至5000 A。然後,〇2被佈植入第一釕層7之整體表 、面。此處,02佈植之實施,係考慮根據第一釕層7之厚度 所對應之範圍Rp。例如,若第一釕層之厚度係200 A,02 被佈植之配方量係1〇ΐ5·1〇19離子/平方公分與在5〇 keV能 量程度。 如第1D圖所示,第二釕層9在形成第一釕層7之相同條 件下被形成。然後,在其上已形成第一與第二釕層7及9之 基質1在其中氬氣與氣氣,或氮氣與氧氣被混合經一至五 小時之管中被熱處理。在如此做之後,如第1E囷所示,最 後氧化穷層10被形成。此處,導入管中之氬氣/氧氣或氮 乳/氧氣之氣流約爲1〇〇 sccm/10 seem至2000 sccm/300 seem,且管中之溫度約爲400。匚至700*c ^如以上所述, 〇2被佈植入第一與第二釕層之間且在管中實施熱處理,如 此以致可製成穩定之氧化釕層。第圖係説明使用氧化釕 層1〇作爲擴散障壁而形成金屬線路Η之装置之剖面圖示 。金屬線路1 1係由鋁,鎢或銅製得。 根據本發明如以上所述者,其係有可能防止在介於釕層 與碎層間之界面形成矽化物。因此,可獲得穩定之氧化釕 層。藉利用穩定之氧化釕層作爲擴散障壁,其可防止金屬 本紙張从適用中國國2ΐ〇χ;ϋ--- ---^--L-----丨裝------訂-----一線 (請先閱讀免面之:vi意事項再填寫本頁) 線路之材料擴散,且形成具有低阻抗之金屬接頭。 301020 A7 ----— B7 五、發明説明(4 ) 雖然本發明之較佳具體實例已 熟練此方面技藝者將認知各種修 能’且不致遠離本發明在所-附之 樣態與精神。 被揭示以説明用途,彼等 正’添加與替代均係有可 申請專利範圍中所揭示之
Claims (1)
- ABCD 經濟部中央標準局負工消費合作社印裝 六、申請專利範圍 L 一種於半導體裝置中製造擴散障壁金屬層之方法,係以 防止半導體裝置中之金屬線路材料、擴散進入金屬線路 下之矽層,該方法包含以下步驟: 將該矽層之表面曝露於氧電漿中,以防止矽層與擴散 障壁金屬層間之界面形成矽化物; 在該矽層上形成一層第一擴散障壁金屬層; -氧離子佈植入第一擴散障壁金屬層内;及 在第一擴散障壁金屬層上形成一層第二擴散障壁金屬 層。 2.根據申請專利範園第i項之方法,其中該第—與第二擴 散障壁金屬層係釕層。 3-根據申請專利範圍第i項之方法,其中該%電漿係在低 於50 W以下之低電能下、及在5 8<?(:111至5〇 sccm之氣流 下、於電漿增強化學氣相沉積(PEC VD)室中製得。 4. 根據申請專利範圍第2項之方法,其中氧離子之密度係 ι〇15-ιο19離子/平方公分。 5. 根據申請專利範圍第2項之方法,其中該第—擴散障壁 金屬層之厚度係100 A至500 A。 6. 根據申請專利範圍第i項之方法’該形成第二擴散障壁 金屬層之步驟,進一步包含氧化第一與第二擴散障壁2 屬層之步驟。 7. 根據申請專利範圍第6項之方法,其中該氧化步银係在 一試管中進行熱處理,其中氬氣與氧氣,與氮氣與氧氣 係經混合1至5小時。 _____-8- 本紙張XJLit財家鮮(c:NS ) A4胁(21Qx297公着) ---„-----裝------訂-----7線 . 1' 《 (請先閱讀^面之足意事項再填寫本頁) 3G1020 ABCD 六、申請專利範圍 8. 根據申請專利範圍第7項之方法,其中在該管中之該氬 氣/氧氣流或氮氣/氧氣流約爲100 sccm/io seem至2000 sccm/300 seem 。9. 根據申請專利範圍第8項之方法,其中試管中之溫度約 爲 400°C 至 700°C。 請 先 閏 讀 背 ιέ 之 注- 意 事 項 再— 填 % 本 頁 裝 訂 線 經濟部中央標準局員工消費合作社印裳 9- 本紙張尺度逋用中國國家橾準(CNS ) Α4规格(210 X 297公釐)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950012306A KR0172772B1 (ko) | 1995-05-17 | 1995-05-17 | 반도체 장치의 확산장벽용 산화루테늄막 형성 방법 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW301020B true TW301020B (zh) | 1997-03-21 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW085105771A TW301020B (zh) | 1995-05-17 | 1996-05-16 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US5637533A (zh) |
| JP (1) | JPH08316321A (zh) |
| KR (1) | KR0172772B1 (zh) |
| CN (1) | CN1048819C (zh) |
| DE (1) | DE19620022C2 (zh) |
| GB (1) | GB2300970B (zh) |
| TW (1) | TW301020B (zh) |
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| DE102020110480B4 (de) | 2019-09-30 | 2024-06-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Middle-of-Line-Interconnect-Struktur und Herstellungsverfahren |
| US11462471B2 (en) * | 2019-09-30 | 2022-10-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Middle-of-line interconnect structure and manufacturing method |
| TW202200828A (zh) | 2020-06-24 | 2022-01-01 | 荷蘭商Asm Ip私人控股有限公司 | 含鉬薄膜的氣相沉積 |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61163264A (ja) * | 1985-01-11 | 1986-07-23 | Hitachi Ltd | 白金族金属の酸化膜形成法 |
| US4851895A (en) * | 1985-05-06 | 1989-07-25 | American Telephone And Telegraph Company, At&T Bell Laboratories | Metallization for integrated devices |
| JPH0779136B2 (ja) * | 1986-06-06 | 1995-08-23 | 株式会社日立製作所 | 半導体装置 |
| US5183775A (en) * | 1990-01-23 | 1993-02-02 | Applied Materials, Inc. | Method for forming capacitor in trench of semiconductor wafer by implantation of trench surfaces with oxygen |
| JPH04364759A (ja) * | 1991-06-12 | 1992-12-17 | Kawasaki Steel Corp | 半導体装置及びその製造方法 |
| US5200360A (en) * | 1991-11-12 | 1993-04-06 | Hewlett-Packard Company | Method for reducing selectivity loss in selective tungsten deposition |
| US5407855A (en) * | 1993-06-07 | 1995-04-18 | Motorola, Inc. | Process for forming a semiconductor device having a reducing/oxidizing conductive material |
| GB2291264B (en) * | 1994-07-07 | 1998-07-29 | Hyundai Electronics Ind | Method for forming a metallic barrier layer in semiconductor device and device made by the method |
| US5555486A (en) * | 1994-12-29 | 1996-09-10 | North Carolina State University | Hybrid metal/metal oxide electrodes for ferroelectric capacitors |
| US5521121A (en) * | 1995-04-03 | 1996-05-28 | Taiwan Semiconductor Manufacturing Company | Oxygen plasma etch process post contact layer etch back |
-
1995
- 1995-05-17 KR KR1019950012306A patent/KR0172772B1/ko not_active Expired - Fee Related
-
1996
- 1996-05-15 US US08/648,285 patent/US5637533A/en not_active Expired - Lifetime
- 1996-05-16 TW TW085105771A patent/TW301020B/zh not_active IP Right Cessation
- 1996-05-17 CN CN96108935A patent/CN1048819C/zh not_active Expired - Fee Related
- 1996-05-17 JP JP8123722A patent/JPH08316321A/ja active Pending
- 1996-05-17 GB GB9610393A patent/GB2300970B/en not_active Expired - Fee Related
- 1996-05-17 DE DE19620022A patent/DE19620022C2/de not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1048819C (zh) | 2000-01-26 |
| GB2300970A (en) | 1996-11-20 |
| US5637533A (en) | 1997-06-10 |
| KR0172772B1 (ko) | 1999-03-30 |
| CN1147145A (zh) | 1997-04-09 |
| DE19620022C2 (de) | 2002-09-19 |
| GB2300970B (en) | 1999-10-13 |
| JPH08316321A (ja) | 1996-11-29 |
| DE19620022A1 (de) | 1996-11-21 |
| GB9610393D0 (en) | 1996-07-24 |
| KR960042954A (ko) | 1996-12-21 |
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| MM4A | Annulment or lapse of patent due to non-payment of fees |