TW202534408A - Display panel - Google Patents

Abstract

A display panel including a first substrate, a second substrate, a liquid crystal layer, a plurality of data lines, a plurality of scan lines, a plurality of pixel structures, a first common electrode layer, a plurality of bridge patterns, a plurality of first spacers and a second common electrode layer is provided. The liquid crystal layer is disposed between the first substrate and the second substrate. The data lines and the scan lines are disposed on the first substrate, and intersect each other. Each of the pixel structures has an active device and a pixel electrode electrically connected to each other. The first common electrode layer and the bridge patterns are disposed on the first substrate, and are electrically connected to each other. The first common electrode layer overlaps the pixel structures. The first spacers are disposed on the second substrate, and respectively abut the bridge patterns. The second common electrode layer disposed on the second substrate covers the first spacers to electrically connect the bridge patterns.

Description

Display Panel

The present invention relates to a display technology, and in particular to a display panel.

In one type of current display panel, the common electrode layers of multiple pixel structures are interconnected, forming storage capacitors with each pixel electrode. As display panel size and resolution continue to increase, capacitive coupling between the common electrode layer and other conductive layers causes delays in signal transmission on the common electrode layer, causing the voltage level of the common electrode layer to deviate as it moves away from the signal source. This voltage level deviation can lead to insufficient storage capacitance in the display pixels, compromising display quality.

The present invention provides a display panel with better operating electrical performance.

The display panel of the present invention includes a first substrate, a second substrate, a liquid crystal layer, multiple data lines, multiple scan lines, multiple pixel structures, a first common electrode layer, multiple bridge patterns, multiple first spacers, and a second common electrode layer. The first substrate and the second substrate are arranged along a stacking direction. The liquid crystal layer is arranged between the first substrate and the second substrate. Multiple data lines and multiple scan lines are arranged on the first substrate and intersect with each other. Multiple pixel structures are arranged on the first substrate and each has an active element and a pixel electrode. The active element is electrically connected to the pixel electrode, one of the multiple data lines, and one of the multiple scan lines. The first common electrode layer and the multiple bridge patterns are arranged on the first substrate and are electrically connected to each other. The first common electrode layer overlaps the multiple pixel structures. A plurality of first spacers are disposed on the second substrate and respectively abut the bridge patterns along the stacking direction. A second common electrode layer is disposed on the second substrate and covers the plurality of first spacers to electrically connect the bridge patterns.

In one embodiment of the present invention, the first common electrode layer of the display panel has a plurality of openings, and these openings overlap with a plurality of pixel electrodes of a plurality of pixel structures along the stacking direction.

In one embodiment of the present invention, the multiple bridge patterns of the display panel and the multiple pixel electrodes of the multiple pixel structures are formed in the same film layer.

In one embodiment of the present invention, the first common electrode layer of the display panel overlaps with a plurality of pixel electrodes of a plurality of pixel structures.

In one embodiment of the present invention, each pixel structure of the display panel further comprises a first transfer pattern disposed between the pixel electrode and the active device, with the pixel electrode electrically connected to the active device via the first transfer pattern. A second transfer pattern is disposed between each bridge pattern and the first common electrode layer. Each bridge pattern is electrically connected to the first common electrode layer via the second transfer pattern, and the first and second transfer patterns are formed from the same film layer.

In one embodiment of the present invention, each pixel structure of the display panel further comprises a capacitor electrode electrically connected to the active element and the first transfer pattern. The capacitor electrode is capacitively coupled to the first common electrode layer to form a storage capacitor.

In one embodiment of the present invention, each pixel structure of the display panel further comprises a reflective layer. The reflective layer has an opening that overlaps the pixel electrode and defines a reflective region for each pixel structure. The opening in the reflective layer defines a light-transmitting region for each pixel structure, and the orthographic projection of the opening on the substrate surface of the first substrate lies within the orthographic projection of the pixel electrode on the substrate surface.

In one embodiment of the present invention, the multiple bridge patterns of the display panel and the reflective layer of each pixel structure are formed from the same film layer.

In one embodiment of the present invention, a transfer pattern is disposed between each bridge pattern and the first common electrode layer of the display panel. Each bridge pattern is electrically connected to the first common electrode layer via the transfer pattern, and the transfer pattern and the pixel electrode are formed in the same film layer.

In one embodiment of the present invention, the first common electrode layer of the display panel is capacitively coupled to the pixel electrode to form a storage capacitor.

In one embodiment of the present invention, the display panel further includes a plurality of second spacers disposed on the second substrate and overlapping the plurality of pixel structures. The plurality of first spacers and the plurality of second spacers are formed from the same film layer.

In one embodiment of the present invention, the display panel further includes a plurality of second spacers disposed on the second substrate and located on a side of the second common electrode layer facing away from the second substrate.

Based on the above, in a display panel according to one embodiment of the present invention, a first substrate is provided with a plurality of bridge patterns electrically connected to a first common electrode layer, while a second substrate is provided with a second common electrode layer and a plurality of first spacers adapted to abut the plurality of bridge patterns. The second common electrode layer covers the first spacers, electrically contacting the bridge patterns and establishing electrical connection between the first and second common electrode layers. This effectively reduces voltage level variations between different regions of the first common electrode layer, which overlaps with multiple pixel structures, thereby improving the voltage level distribution uniformity of the first common electrode layer.

The aforementioned technical contents, features, and functions of the present invention are clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. Directional terms such as up, down, left, right, front, and back, etc., mentioned in the following embodiments are merely references to the directions in the accompanying drawings. Therefore, the directional terms used are for illustrative purposes only and are not intended to limit the present invention.

Figure 1 is a schematic front view of a display panel according to a first embodiment of the present invention. Figures 2 and 3 are schematic cross-sectional views of the display panel of Figure 1. Figure 4 is a schematic cross-sectional view of another modified embodiment of the display panel of Figure 3. Figures 2 and 3 correspond to sections A-A' and B-B' in Figure 1, respectively. For clarity, Figure 1 only illustrates portions of the film layers of Figures 2 and 3.

Referring to Figures 1 to 3 , the display panel 10 includes a first substrate 101, a second substrate 102, and a liquid crystal layer (LCL). The first and second substrates 101, 102 are stacked along a stacking direction (e.g., direction D3). The liquid crystal layer (LCL) is disposed between the first and second substrates 101, 102. Unless otherwise specified, the stacking relationship between the two components is defined by the aforementioned stacking direction, and the stacking direction will not be further discussed.

It should be understood that although the display panel 10 in FIG1 only illustrates one pixel structure PX, one data line DL, and one scan line SL, the display panel 10 actually includes multiple pixel structures PX, multiple data lines DL, and multiple scan lines SL. For example, multiple data lines DL may be arranged on the first substrate 101 along direction D1 and extend in direction D2. Multiple scan lines SL may be arranged on the first substrate 101 along direction D2 and extend in direction D1. More specifically, these data lines DL intersect at these scan lines SL and define multiple pixel regions of the display panel 10. Multiple pixel structures PX are disposed on the first substrate 101, corresponding to these pixel regions, and are each electrically connected to a scan line SL and a data line DL. For example, the plurality of pixel structures PX may be arranged in a plurality of rows and columns along the direction D1 and the direction D2, respectively. That is, the pixel structures PX are arranged in an array on the first substrate 101.

Specifically, each of these pixel structures PX includes an active element T and a pixel electrode PE that are electrically connected to each other. In this embodiment, the method for forming the active element T may include the following steps: sequentially forming a gate electrode GE, a gate insulation layer 110, a semiconductor pattern SC, a source electrode SE, and a drain electrode DE on a first substrate 101. The semiconductor pattern SC is disposed overlapping the gate electrode GE. The source electrode SE and the drain electrode DE overlap the semiconductor pattern SC and are electrically connected to two different regions of the semiconductor pattern SC. In this embodiment, the gate electrode GE of the active element T may be optionally disposed below the semiconductor pattern SC to form a bottom-gate thin-film transistor (TFT), but this is not limiting. In other embodiments, the gate of the active device can optionally be disposed above the semiconductor pattern to form a top-gate thin-film transistor (TFT). Furthermore, the active device T can be covered with an insulating layer 120. In this embodiment, the insulating layer 120 is, for example, a passivation layer.

It should be noted that the gate GE, source SE, drain DE, semiconductor pattern SC, gate insulating layer 110, and passivation layer (i.e., insulating layer 120) can be respectively implemented by any gate, any source, any drain, any semiconductor pattern, any gate insulating layer, and any passivation layer known to those skilled in the art for use in a display panel. Furthermore, the gate GE, source SE, drain DE, semiconductor pattern SC, gate insulating layer 110, and passivation layer can be respectively formed by any method known to those skilled in the art, and therefore will not be described in detail here.

In this embodiment, the pixel electrode PE is disposed on the insulating layer 120 and is electrically connected to the drain electrode DE of the active device T via the contact hole TH2 in the insulating layer 120. In this embodiment, the pixel electrode PE is, for example, a light-transmitting electrode, and the material of the light-transmitting electrode includes a metal oxide, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, or other suitable oxides, or a stack of at least two of the foregoing. More specifically, the display panel 10 of this embodiment can be a light-transmitting liquid crystal display panel, but is not limited thereto.

Furthermore, the display panel 10 may also include a first common electrode layer CEL1 and a plurality of bridge patterns BP, which are electrically connected to each other. The first common electrode layer CEL1 is disposed between the first substrate 101 and the gate insulation layer 110 and overlaps the plurality of pixel structures PX. Specifically, the first common electrode layer CEL1 has a plurality of openings CEL1op, and these openings CEL1op overlap the plurality of pixel electrodes PE of the plurality of pixel structures PX. Of particular note is that the pixel electrode PE not only overlaps the opening CEL1op of the first common electrode layer CEL1, but also overlaps the portion surrounding the opening CEL1op in the first common electrode layer CEL1 to form the storage capacitor of the pixel structure PX. In this embodiment, the first common electrode layer CEL1 and the gate electrode GE can be the same film layer, but this is not limited to this.

The orthographic projection of the bridge pattern BP on the substrate surface 101s of the first substrate 101 is located within the orthographic projection of the first common electrode layer CEL1 on the substrate surface 101s. In other words, the bridge pattern BP completely overlaps the first common electrode layer CEL1. In this embodiment, the bridge pattern BP is disposed on the insulating layer 120 and electrically connected to the first common electrode layer CEL1 via contact holes TH1 in the gate insulating layer 110 and the insulating layer 120. For example, the bridge pattern BP and the pixel electrode PE can be formed from the same film layer to avoid adding additional process steps.

On the other hand, a second common electrode layer CEL2 is disposed on the second substrate 102. This second common electrode layer CEL2 is, for example, a light-transmitting electrode. For example, when the display panel 10 is operating, the electric field generated between the second common electrode layer CEL2 and the pixel electrodes PE of each pixel structure PX is suitable for driving the multiple liquid crystal molecules (not shown) in the liquid crystal layer LCL to rotate, forming an arrangement corresponding to the direction and intensity of the electric field. By changing the arrangement of these liquid crystal molecules, the polarization state of light passing through the liquid crystal layer LCL is altered, resulting in a light output brightness corresponding to the arrangement. In this embodiment, the liquid crystal layer (LCL) is driven in a twisted nematic (TN) mode or an electrically controlled birefringence (ECB) mode, for example.

To create a chamber between the first substrate 101 and the second substrate 102 to accommodate the liquid crystal layer (LCL), the second substrate 102 is further provided with a plurality of first spacers SP1 and a plurality of second spacers SP2. The plurality of first spacers SP1 are arranged to overlap the plurality of bridging patterns BP on the first substrate 101 and are adapted to abut against these bridging patterns BP (as shown in FIG2 ). The plurality of second spacers SP2 can be arranged to overlap the plurality of active elements T on the first substrate 101 and are adapted to abut against these active elements T (as shown in FIG3 ). However, the present invention is not limited to this. In other embodiments (not shown), the second spacers SP2 can also overlap the pixel electrodes PE, and some of the second spacers SP2 may not abut the pixel electrodes PE. In other words, the second spacers SP2 can have different heights.

Of particular note is that the second common electrode layer CEL2 can achieve electrical connection with multiple bridge patterns BP by covering these bridge patterns BP. From another perspective, the first common electrode layer CEL1 on the first substrate 101 can be electrically connected to the second common electrode layer CEL2 on the second substrate 102 through the abutment between the bridge patterns BP and the first spacers SP1. This effectively reduces the voltage level variation between different regions of the first common electrode layer CEL1, which overlaps multiple pixel structures PX, thereby improving the voltage level distribution uniformity of the first common electrode layer CEL1.

On the other hand, in this embodiment, multiple second spacers SP2 can be disposed on the side of the second common electrode layer CEL2 facing away from the second substrate 102 (as shown in Figure 3). In other words, the second spacers SP2 and the first spacers SP1 can be different film layers. For example, the first spacers SP1 and the second spacers SP2 can be fabricated separately using two photomasks. This design prevents the second spacers SP2 from being excessively squeezed by external forces, thereby increasing the risk of electrical short circuits between the second common electrode layer CEL2 and electronic components on the first substrate 101. In other words, this increases the design flexibility of the second spacers SP2.

However, the present invention is not limited to this. In another variant embodiment, the second spacers SP2-A of the display panel 10A and the first spacers SP1 in FIG. 2 can be formed from the same film layer and both are located between the second common electrode layer CEL2 and the second substrate 102 (as shown in FIG. 4 ). For example, the first spacers SP1 and the second spacers SP2 can be manufactured using the same mask, such as a half-tone mask.

In this embodiment, the second substrate 102 may optionally be provided with a plurality of color filter patterns CF, a light-shielding pattern layer BM, and a cover layer 130. These color filter patterns CF overlap with the plurality of pixel electrodes PE and are adapted to allow multiple colors of light (e.g., red, green, and blue, but not limited thereto) to pass through. However, the present invention is not limited thereto. In other embodiments, the second substrate 102 may not be provided with the color filter patterns CF. In this embodiment, the cover layer 130 covers the plurality of color filter patterns CF and the light-shielding pattern layer BM, and the plurality of second spacers SP2 and the second common electrode layer CEL2 are provided on the cover layer 130.

Other embodiments will be listed below to illustrate the present disclosure in detail, wherein the same components will be marked with the same symbols, and the description of the same technical content will be omitted. For the omitted parts, please refer to the above embodiments and will not be repeated below.

Figure 5 is a schematic front view of a display panel according to a second embodiment of the present invention. Figures 6 and 7 are schematic cross-sectional views of the display panel in Figure 5 . Figure 6 corresponds to section line C-C' in Figure 5 . Figure 7 corresponds to section lines D-D' and E-E' in Figure 5 . For clarity, Figure 5 only shows a portion of the film layers in Figures 6 and 7 .

Referring to Figures 5 to 7 , the display panel 20 of this embodiment differs primarily from the display panel 10 of Figures 1 to 3 in the design of the pixel structure and the structure of the bridge film between the first and second common electrode layers. Specifically, in this embodiment, the pixel structure PX-A of the display panel 20 may further include a capacitor electrode CPE and a first transfer pattern TP1.

Specifically, the capacitor electrode CPE is disposed between the gate insulation layer 110 and the insulation layer 120 and extends from the drain electrode DE of the active device T. That is, the capacitor electrode CPE is electrically connected to the drain electrode DE of the active device T. The first transfer pattern TP1 is disposed on the insulation layer 120 and electrically connected to the capacitor electrode CPE via a contact hole TH2 in the insulation layer 120. In this embodiment, a planarization layer 140 may also be disposed on the insulation layer 120. The pixel electrode PE-A of the pixel structure PX-A may be disposed on the planarization layer 140 and electrically connected to the first transfer pattern TP1 via an opening 140op2 in the planarization layer 140.

In other words, the pixel electrode PE-A of this embodiment is electrically connected to the active device T via the first transfer pattern TP1 and the capacitor electrode CPE. In this embodiment, the planar layer can be implemented using any planar layer used in display panels known to those skilled in the art, and the planar layer can be formed using any method known to those skilled in the art, so detailed description is omitted here.

Of particular note is that the orthographic projection of capacitor electrode CPE on first substrate 101 is within the orthographic projection of first common electrode layer CEL1-A on first substrate 101, with gate insulation layer 110 disposed between the two. More specifically, capacitor electrode CPE and first common electrode layer CEL1-A are capacitively coupled to form the storage capacitor of pixel structure PX-A.

In this embodiment, the pixel electrode PE-A is, for example, a reflective electrode, and the material of the reflective electrode includes a metal, an alloy, a metal nitride, a metal oxide, a metal oxynitride, or other suitable materials, or a stack of metal and other conductive materials. In other words, the display panel 20 of this embodiment can be a reflective liquid crystal display panel, but is not limited thereto. Therefore, although the first common electrode layer CEL1-A of this embodiment also overlaps the pixel electrode PE-A, it does not have an opening (such as the opening CEL1op shown in FIG. 1 ) that overlaps the pixel electrode PE-A.

On the other hand, in this embodiment, a second transfer pattern TP2 is provided between the bridge pattern BP-A and the first common electrode layer CEL1-A. The bridge pattern BP-A is electrically connected to the first common electrode layer CEL1-A via the second transfer pattern TP2. Specifically, the second transfer pattern TP2 may be provided between the insulating layer 120 and the planar layer 140 and electrically connected to the first common electrode layer CEL1-A via the contact hole TH1 formed between the gate insulating layer 110 and the insulating layer 120. The bridge pattern BP-A is provided on the planar layer 140 and electrically connected to the second transfer pattern TP2 via the opening 140op1 in the planar layer 140.

In this embodiment, the bridge pattern BP-A and the pixel electrode PE-A can be formed in the same film layer, and the second transfer pattern TP2 and the first transfer pattern TP1 can be formed in the same film layer. This avoids adding additional process steps.

Because the first common electrode layer CEL1-A of this embodiment is also electrically connected to the second common electrode layer CEL2 on the second substrate 102 via the abutment between the first spacer SP1 and the bridge pattern BP-A, the voltage level differences between different regions of the first common electrode layer CEL1-A, which overlaps with multiple pixel structures PX-A, can be effectively reduced, thereby improving the uniformity of the voltage level distribution of the first common electrode layer CEL1-A. This improves the operating electrical performance of the display panel 20.

Figure 8 is a schematic front view of a display panel according to a third embodiment of the present invention. Figures 9 and 10 are schematic cross-sectional views of the display panel in Figure 8 . Figures 9 and 10 correspond to section lines F-F' and G-G' in Figure 8 , respectively. For clarity, Figure 8 only shows a portion of the film layers in Figures 9 and 10 .

Referring to Figures 8 to 10 , the display panel 30 of this embodiment differs primarily from the display panel 20 of Figures 5 to 7 in the design of the pixel structure and the structure of the bridge film between the first and second common electrode layers. Specifically, in this embodiment, while the pixel structure PX-B of the display panel 30 lacks the first transfer pattern TP1 shown in Figure 7 , it further includes a reflective layer RFL.

In this embodiment, the pixel electrode PE-B is, for example, a light-transmitting electrode. The reflective layer RFL is disposed on the pixel electrode PE-B and is in direct electrical contact therewith. The reflective layer RFL has an opening RFLop that overlaps the pixel electrode PE-B. The reflective layer RFL can define the reflective area RA of the pixel structure PX-B, and its opening RFLop can define the light-transmitting area TA of the pixel structure PX-B. It is particularly noteworthy that the orthographic projection of the opening RFLop of the reflective layer RFL on the substrate surface 101s of the first substrate 101 is located within the orthographic projection of the pixel electrode PE-B on the substrate surface 101s. More specifically, the display panel 30 of this embodiment can be a semi-transflective liquid crystal display panel or a micro-transflective liquid crystal display panel.

On the other hand, in this embodiment, the first common electrode layer CEL1-B is disposed on the active device T. Specifically, the active device T may be covered with a planar layer 140A. The first common electrode layer CEL1-B is disposed on the planar layer 140A and covered by the insulating layer 120A. Of particular note, in this embodiment, the contact hole TH2 of the insulating layer 120A overlaps the opening 140op2 of the planar layer 140A. The pixel electrode PE-B and the reflective layer RFL may extend into the opening 140op2 of the planar layer 140A and be electrically connected to the capacitor electrode CPE via the contact hole TH2 of the insulating layer 120A.

Of particular note is that the orthographic projection of the capacitor electrode CPE on the first substrate 101 is within the orthographic projection of the first common electrode layer CEL1-B on the first substrate 101, with a planar layer 140A disposed between the two. The orthographic projection of the capacitor electrode CPE on the first substrate 101 is also within the orthographic projection of the pixel electrode PE-B on the first substrate 101, with an insulating layer 120A disposed between the two.

On the other hand, in this embodiment, the display panel 30 may further include a third common electrode layer CEL3 disposed between the gate insulation layer 110 and the first substrate 101 (i.e., the third common electrode layer CEL3 and the gate electrode GE may be the same film layer). The orthographic projection of the capacitor electrode CPE on the first substrate 101 is located within the orthographic projection of the third common electrode layer CEL3 on the first substrate 101, with the gate insulation layer 110 disposed therebetween.

More specifically, capacitor electrode CPE is capacitively coupled to first common electrode layer CEL1-B to form the first storage capacitor of pixel structure PX-B. First common electrode layer CEL1-B is capacitively coupled to pixel electrode PE-B to form the second storage capacitor of pixel structure PX-B. Capacitive electrode CPE is capacitively coupled to third common electrode layer CEL3-B to form the third storage capacitor of pixel structure PX-B. In other words, compared to pixel structure PX-A in FIG5 , which has only one storage capacitor, pixel structure PX-B of this embodiment has three storage capacitors connected in parallel. Consequently, the storage capacity of pixel structure PX-B can be significantly increased.

In this embodiment, the bridge pattern BP-B is disposed on the insulating layer 120A and electrically connected to the first common electrode layer CEL1-B via the transfer pattern TP and the contact hole TH1 in the insulating layer 120A. For example, to avoid adding additional process steps, the bridge pattern BP-B and the reflective layer RFL of the pixel structure PX-B can be formed from the same film layer, while the transfer pattern TP and the pixel electrode PE-B can be formed from the same film layer. Therefore, similar to the connection between the reflective layer RFL and the pixel electrode PE-B, the bridge pattern BP-B can directly electrically contact the transfer pattern TP.

Because the first common electrode layer CEL1-B of this embodiment is also electrically connected to the second common electrode layer CEL2 on the second substrate 102 via the abutment between the first spacer SP1 and the bridge pattern BP-B, the voltage level differences between different regions of the first common electrode layer CEL1-B, which overlaps with multiple pixel structures PX-B, can be effectively reduced, thereby improving the uniformity of the voltage level distribution of the first common electrode layer CEL1-B. This improves the operating electrical performance of the display panel 30.

On the other hand, since the pixel structure PX-B of this embodiment has a light-transmitting area TA, the first common electrode layer CEL1-B, the capacitor electrode CPE, and the third common electrode layer CEL3 respectively have openings CEL1op, CPEop, and CEL3op that overlap the light-transmitting area TA (i.e., the opening RFLop of the reflective layer RFL).

In summary, in a display panel according to one embodiment of the present invention, a first substrate is provided with a plurality of bridge patterns electrically connected to a first common electrode layer, while a second substrate is provided with a second common electrode layer and a plurality of first spacers adapted to abut the plurality of bridge patterns. The second common electrode layer covers the first spacers, electrically contacting the bridge patterns and establishing electrical connection between the first and second common electrode layers. This effectively reduces voltage level variations across different regions of the first common electrode layer, which overlaps with multiple pixel structures, thereby improving the voltage level uniformity of the first common electrode layer.

10, 10A, 20, 30: Display panel 101: First substrate 101s: Substrate surface 102: Second substrate 110: Gate insulation layer 120, 120A: Insulation layer 130: Covering layer 140, 140A: Planarization layer 140op1, 140op2, CEL1op, CEL3op, RFLop, CPEop: Openings BM: Shading pattern layer BP, BP-A, BP-B: Bridging pattern layer CEL1, CEL1-A, CEL1-B: First common electrode layer CEL2: Second common electrode layer CEL3: Third common electrode layer CF: Color filter pattern CPE: Capacitor electrode D1, D2, D3: Direction DE: Drain DL: Data Line GE: Gate LCL: Liquid Crystal Layer PE, PE-A, PE-B: Pixel Electrodes PX, PX-A, PX-B: Pixel Structure RA: Reflective Area RFL: Reflective Layer SC: Semiconductor Pattern SE: Source SL: Scan Line SP1: First Spacer SP2, SP2-A: Second Spacer T: Active Device TA: Transparent Area TH1, TH2: Contact Holes TP: Transfer Pattern TP1: First Transfer Pattern TP2: Second Transfer Pattern A-A’, B-B’, C-C’, D-D’, E-E’, F-F’, G-G’: Section Lines

Figure 1 is a schematic front view of a display panel according to a first embodiment of the present invention. Figures 2 and 3 are schematic cross-sectional views of the display panel of Figure 1. Figure 4 is a schematic cross-sectional view of another modified embodiment of the display panel of Figure 3. Figure 5 is a schematic front view of a display panel according to a second embodiment of the present invention. Figures 6 and 7 are schematic cross-sectional views of the display panel of Figure 5. Figure 8 is a schematic front view of a display panel according to a third embodiment of the present invention. Figures 9 and 10 are schematic cross-sectional views of the display panel of Figure 8.

10: Display Panel

101: First substrate

101s: Substrate Surface

102: Second substrate

110: Gate insulation layer

120: Insulating layer

130: Covering layer

BM: Light-blocking pattern layer

BP: Bridge pattern

CEL1: First common electrode layer

CEL2: Second common electrode layer

D3: direction

LCL: Liquid Crystal Layer

SP1: First gap

TH1: Contact hole

A-A’: section line

Claims (12)

A display panel comprises: A first substrate and a second substrate, stacked in a stacking direction; A liquid crystal layer disposed between the first and second substrates; A plurality of data lines disposed on the first substrate; A plurality of scan lines disposed on the first substrate and intersecting the data lines; A plurality of pixel structures disposed on the first substrate, each having an active element and a pixel electrode, the active element electrically connected to the pixel electrode, one of the data lines, and one of the scan lines; A first common electrode layer disposed on the first substrate and overlapping the pixel structures; A plurality of bridge patterns disposed on the first substrate and electrically connected to the first common electrode layer; A plurality of first spacers are disposed on the second substrate and abut the bridge patterns along the stacking direction; and a second common electrode layer is disposed on the second substrate and covers the first spacers to electrically connect the bridge patterns. The display panel as described in claim 1, wherein the first common electrode layer has a plurality of openings, and the openings overlap the plurality of pixel electrodes of the pixel structures along the stacking direction. The display panel as described in claim 1, wherein the bridge patterns and the pixel electrodes of the pixel structures are formed in the same film layer. The display panel as described in claim 1, wherein the first common electrode layer overlaps a plurality of the pixel electrodes of the pixel structures. The display panel as described in claim 4, wherein each of the pixel structures further comprises a first transfer pattern disposed between the pixel electrode and the active element, and the pixel electrode is electrically connected to the active element via the first transfer pattern; a second transfer pattern is disposed between each of the bridge patterns and the first common electrode layer, and each of the bridge patterns is electrically connected to the first common electrode layer via the second transfer pattern; and the first transfer pattern and the second transfer pattern are formed from the same film layer. In the display panel of claim 5, each of the pixel structures further comprises a capacitor electrode electrically connecting the active element and the first transfer pattern, and the capacitor electrode is capacitively coupled with the first common electrode layer to form a storage capacitor. The display panel as described in claim 1, wherein each of the pixel structures further has a reflective layer, the reflective layer having an opening overlapping the pixel electrode, and the reflective layer defines a reflective region of each of the pixel structures. The opening of the reflective layer defines a light-transmitting region of each of the pixel structures, and the orthographic projection of the opening on the substrate surface of the first substrate is located within the orthographic projection of the pixel electrode on the substrate surface. The display panel as described in claim 7, wherein the bridge patterns and the reflective layer of each of the pixel structures are the same film layer. In the display panel of claim 7, a transfer pattern is provided between each of the bridge patterns and the first common electrode layer, each of the bridge patterns is electrically connected to the first common electrode layer via the transfer pattern, and the transfer pattern and the pixel electrode are formed in the same film layer. The display panel as described in claim 7, wherein the first common electrode layer is capacitively coupled with the pixel electrode to form a storage capacitor. The display panel of claim 1 further comprises: A plurality of second spacers disposed on the second substrate and overlapping the pixel structures, wherein the first spacers and the second spacers are formed from the same film layer. The display panel of claim 1 further comprises: A plurality of second spacers disposed on the second substrate and located on a side of the second common electrode layer facing away from the second substrate.