TW202135289A - Memory device, data processing device, and data processing method - Google Patents

Abstract

An efficient FeFET-based CAM is disclosed which is capable of performing normal read, write but has the ability to match input data with don't-care. More specifically, a Ferroelectric FET Based Ternary Content Addressable Memory is disclosed. The design in some examples utilizes two FeFETs and four MOSFETs per cell. The CAM can be written in columns through multi-phase writes. It can be used a normal memory with indexing read. It also has the ability for ternary content-based search. The don't-care values can be either the input or the stored data.

Description

Content addressable memory based on ferroelectric field school transistor

The content of this disclosure is generally about content-addressable memory ("content-addressable memory; CAM") devices. The content of ternary CAM ("ternary CAM; TCAM") devices can be addressed. Memory devices are used in a wide range of electronic devices, especially those used in high-speed search applications (such as routing in network-connected devices) Electronic devices, this is due to content matching implemented by hardware.

CAM devices have certain advantages over certain other types of memory devices, such as high-speed search capabilities. However, the conventional CAM device also has certain disadvantages. For example, TCAM devices implemented by certain semiconductor devices, such as complementary metal-oxide-semiconductor ("complementary metal-oxide-semiconductor; CMOS") devices, require at least fourteen transistors per bit for storage. Compared with many other types of memory devices, such implementations tend to cause lower data density (bits per cell area) and higher power consumption. Efforts are being made to develop CAM devices with improved characteristics.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these components and configurations are only examples and are not intended to be limiting. For example, in the following description, forming the first feature over or on the second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also be included in the first feature and the second feature. An embodiment in which additional features may be formed between the second features so that the first feature and the second feature may not directly contact. In addition, the present disclosure may repeat icon numbers and/or letters in various examples. This repetition is for simplicity and clarity, and does not in itself indicate the relationship between the various embodiments and/or configurations discussed.

This disclosure is generally about content addressable memory ("CAM") and specifically about ternary CAM ("TCAM"). Generally speaking, CAM makes it possible to access data from the content stored in the memory instead of the address (ie index) of the memory where the data is stored. The CAM compares the input search data with the data stored in the matrix of memory locations, and returns the address of the memory storage data that matches the searched data. CAM can identify matches in a single clock and is therefore a faster search system than many other search systems. CAM can be used in a wide range of applications that require higher search speeds. CAM is fully used to classify and forward Internet protocol (IP) packets in network routers. In networks such as the Internet, messages such as emails or web pages are sent by first breaking the message into small data packets and then sending each data packet separately via the network. These packets are routed from the source, pass through the intermediate nodes of the network (called routers) and are reassembled at the destination to reproduce the original message. The router compares the destination address of the packet with all possible routes in order to select an appropriate route. CAM is particularly suitable for implementing such query operations due to its fast search capabilities. CAM has also found applications in other fields, including parametric curve extraction, data compression, image processing, and other string matching or pattern matching applications, such as genome sequencing.

In some applications, such as network routing, packets with different addresses can be routed to the same port. For example, it can be a case where all packets with addresses in a certain range are routed to the same port. For example, packets with addresses in the range of 110100 to 110111 can all be routed to the same port. In such cases, the last two bits of the address have no effect on the routing purpose. Therefore, in some instances, the ternary CAM or TCAM is used to store the address to be matched with the address in the incoming packet. TCAM stores one of three possible values: "0", "1" or "X", where "X" is a don't care value, which means both "0" and "1", meaning It is said that the stored "X" produces a match regardless of whether the incoming bit is "0" or "1". Therefore, for example, the stored "1101XX" will be a match with "110100", "110101", "110110" and "110111".

The high speed of the CAM including the TCAM is often achieved at the cost of the complexity of the memory cell and the corresponding high silicon area and the high power consumption of the conventional memory structure. For example, a TCAM cell implemented by a complementary metal oxide semiconductor ("CMOS") may include fourteen or more transistors. Certain embodiments disclosed in this disclosure utilize ferroelectric field-effect transistors (FeFET)-based memory components to implement TCAM, resulting in superior performance in one or more aspects (including speed, device complexity, device density, and power consumption). Improved performance in conventional devices.

According to some embodiments, the memory device includes one or more TCAM memory cells, each adapted to store at least three values one at a time, one of the values indicates "0", and one of the values indicates " 1" and one of the stated values indicate "X" (don't care). In some embodiments, each memory cell includes two data storage units, each adapted to store one binary bit ("0" or "1"). Each data storage unit includes a match line ("matchline; ML") switching transistor; the ML switching transistors of the two data storage units form a serial combination with each other. As used in this disclosure, the "tandem combination" of a transistor and another component means the main current path (for example, the source to the drain of a field-effect transistor or the emitter to the collector of a bipolar junction transistor) . Each memory cell further includes a series combination of FeFET and input switching transistor. One end of the series combination in one of the data storage units (such as the drain or source of FeFET) is connected to one end of the series combination of the ML switching transistor; the series in the other of the data storage units One end of the column combination (such as the drain or source of a FeFET) is connected to the junction between the ML switching transistors.

The control terminal (base or gate) of the ML switching transistor can be connected to a common ML enable line ("ML Enable line; EN _ML ") to receive the ML enable signal. The gate of each of the FeFETs can be connected to a common word line ("wordline;WL") to receive the WL signal to enable data to be written to and read from the FeFET. The junction between the FeFET and the serial combination of the input switching transistor can be connected to a select line ("selectline;SL") to receive a signal to enable data to be written to and read from the FeFET. The drain or source of the FeFET connected to the respective ML switching transistor can be connected to a bit line ("bitline;BL") to receive the BL signal so that data can be written to and read from the FeFET. The control terminal (the gate of the base) of each input switching transistor can be connected to the input line ("inputline;IN") to receive the input value to be matched with the value stored in the FeFET.

In some embodiments, the TCAM array includes TCAM cells described above and configured in columns and rows. The ML switching transistors in each column of the TCAM cell are connected in series and share a common ML enable line and a common WL. The TCAM cells in each row share a common BL, a common SL, and a common IN. In some embodiments, TCAM cells can be used for data storage and retrieval by conventional methods, and for content-based searches. In some such embodiments, each TCAM cell is adapted to store two bits of data. In some embodiments, the data storage cells in the TCAM array are configured for column-by-column writing and row-by-row reading.

In some embodiments, the method of data processing includes storing a set of values in a memory array, each of which indicates a binary "0", "1" or "X" (don't care), the stored value This represents the first binary pattern. The method further includes providing a second set of values, each corresponding to a respective one of the first set of values and indicating a binary "0", "1" or "X". The second set of values represents the second Binary bit pattern. At least one of the first set and the second set of values includes a value indicating a binary "X". The method further includes comparing each of the first set of values with the corresponding one in the second set of values, and if each value in the first set and the corresponding value in the second set are consistent with each other, or At least one of the two values indicates "X", and a signal indicating a match between the first binary pattern and the second binary pattern is generated. In some embodiments, at least one of the first set of values indicates "X"; in some embodiments, at least one of the second set of values indicates "X."

In some more detailed embodiments, as shown in FIG. 1A, a data processing device 100 , such as a TCAM, includes columns 112 (the i-th column is labeled 112 _i ) and a row 114 (the j-th row is labeled 114 _j ) An array 110 of TCAM cells 120 (each cell is labeled 120 _i,j ). The configuration of the TCAM cells 120 in the columns and rows is a logical configuration but can also be a physical configuration. Each TCAM cell 120 is adapted to store a value indicating "0", "1" or "X", such as a pair of binary bits. The value stored in the TCAM cell 120 in each column 112 represents the pattern to be compared with the input pattern, as explained in more detail below. In some embodiments, the TCAM cell is described in further detail below in conjunction with FIG. 1B to FIG. 1H and FIG. 2. The TCAM cell 120 in each row 114 is connected to the common pair of input lines IN and IN# (connected to the IN and IN# lines of the TCAM cells marked IN _j and IN# _j respectively in the jth row). The input line is connected to the search data input interface 130. In some embodiments, the search data input interface 130 is a register or a driver for supplying the pattern to be searched. The pattern includes, for example, a value, and each value indicates "0", "1" or "X". The TCAM cells 120 in each column 112 are connected in series to form a matching line ML (the i-th column is labeled ML with ML _i ). Each ML is adapted to receive the ML input signal at one end and output the ML output signal to the amplifier 140 (the amplifier labeled 140 _i in the i-th column) at the other end. As explained in more detail below, the ML output of each row 112 (e.g. to the respective amplifier 140 ) indicates a signal ( For example, binary "1"). If each value in the pattern to be matched and the corresponding value in the stored pattern are consistent with each other, or at least one of the two values indicates “X”, then “match” in such embodiments is indicated on the ML . In some embodiments, connecting the amplifier 140 to match the output interface 150, the map matching apparatus comprising such an encoder, in some embodiments, the output interface 150, the encoder indicates "match" each such output ports ML The number of destination specifiers.

In some embodiments, as described in more detail below in conjunction with FIG. 3, the TCAM cells 120 in each column 112 are connected to a common word line WL (not shown in FIG. 1; shown in FIG. 3; the i-th column is labeled as WL _i 's WL). The TCAM cell 120 in each row 114 is connected to the common bit line BL and BL# (connected to the BL and BL# lines of the TCAM cells labeled BL _j and BL# _j in the j-th row). The TCAM cell 120 in each row 114 is connected to a common pair of selection lines SL and SL# (connected to the SL and SL# lines of the TCAM cells _{marked as SL j} and SL# _j , respectively, in the j-th row). In some embodiments, as described in more detail below, the combination of the signals at WL, BL, BL#, SL, SL#, IN, and IN# for each TCAM cell 120 enables writing values to the TCAM cell 120 and The stored value is read from the TCAM cell 120.

With further reference to FIGS. 1B and 1C, in some embodiments, FeFET 160 is used in the TCAM cell. Each block contains FeFET 160 (Bulk) 162 and the substrate 162 are separated from the bulk of the heavily doped source 170 and drain 168, 168 between the source region 162 of the block 170 and the source drain doping in , Thereby forming a channel region 172 therebetween. FeFET 164 further comprises a ferroelectric layer, the ferroelectric layer 164 covers the source region 172 and drain electrode 170 separated from the channel region 168. The FeFET further includes a gate electrode 166 covering the ferroelectric layer 164 .

As shown in FIGS. 1D to 1F, when the gate 166 (at a voltage V _G ) is biased with respect to the source 170 and the drain 168 , so that the ferroelectric layer is in a given direction (in this example, from the gate toward the bulk) of the polarization, it becomes a channel region corresponding to a memory state (e.g. "1") of low resistance, and the quasi Xuzi Yuan extreme drain of drain current (drain current; I _D) in the source Flow under a pole-to-drain bias (1 volt in this example); on the contrary, when the gate 166 is biased with respect to the source 170 and the drain 168 , so that the ferroelectric layer is in the opposite direction (in this example, from toward the gate block) when the polarization becomes the channel region corresponds to a different memory state (e.g. "0") of a high resistance, and is allowed to drain Xuzi Yuan extreme drain current (I _D) in the source Flow (or only a small current flows) with a pole-to-drain bias (1 volt in this example). As indicated in FIG. 1F, V _G - I _D curve exhibits hysteresis, wherein V _G must reverse the polarization of the ferroelectric layer 164 exceeds the threshold voltage (V _T) in a direction opposite to the polarization direction. Therefore, the magnitude of the difference in V _T between the two states constitutes a memory window ("memory window; MV") and the magnitude of the gate-to-source voltage V _GS must exceed MV to switch between memory states.

Various ferroelectric materials used for the ferroelectric layer can be used to manufacture FeFETs. Examples of suitable ferroelectric materials include hafnium oxide and hafnium zirconium oxide. For example, hafnium oxide with silicon cations (Si:HfO _{2) can be used.} Fig. 1G shows the polarization versus electric field curve _{of Si:HfO 2} for varying Si cation molar fraction (cat%). Since polarization is related to conductivity, and electric field is related to voltage, the hysteresis loop in the curve of polarization and electric field indicates ferroelectric properties. As shown in Figure 1G, there is hysteresis for a series of compositions, but it is most pronounced at about 4.4 cat%. Therefore, hafnium oxide having substantially this composition can be used. Other ferroelectric materials can also be used.

According to some embodiments, the array of TCAM cells, in addition to being able to be configured to perform content-based search operations, can also be configured to act as a conventional FeFET memory array. In some embodiments, such as those shown in FIG. 1H (for simplicity and clarity of illustration, BL#, SL#, and IN# are omitted), when IN and ML (not shown for simplicity and clarity) ) all shutdown, the TCAM array becomes FeFET memory array 161, wherein WL, BL and SL are biased to FeFET cells for writing cells 160 and 160 read from the FeFET. Specifically, in order to write data to the FeFET, WL (gate) is biased with respect to BL/SL (drain/source). For example, in order to write "0", a positive pulse can be applied to WL and a negative pulse can be applied to BL/SL; to write "1", a negative pulse can be applied to WL and a positive pulse can be applied To BL/SL. In some embodiments, data is written line by line by, for example, writing all "0"s synchronously and writing all "1s" synchronously (or reverse the order), as described in more detail below. To read from the FeFET, BL may be pre-charged to the voltage V _R, while SL is connected to ground. The voltage V _R indicates the WL pulse applied to the column, while the remaining column is set to the ground WL, BL and column value stored in the column. In some embodiments, the TCAM device 300 also includes a stored data input/output ("input/output;I/O") interface (not shown). The stored data input/output interface, in some examples, includes a A driver for writing data to the WL signal of the FeFET, and a sense amplifier connected to the BL for reading the data stored in the FeFET.

More specifically, according to some embodiments, as shown in FIG. 2, the TCAM device 300 includes TCAM cells arranged in a column 312 (the i-th column is labeled 312 _i ) and a row 314 (the j-th row is labeled 314 _j ). A two-dimensional array 310 of 320 (each cell is labeled 320 _i,j ). Each TCAM cell 320 includes two data storage units 342 and 348 , each of which is adapted to store one binary bit ("0" or "1"). Each data storage unit includes a match line ("ML") switching transistor 326 and a match line switching transistor 332 (FET in this example); the ML switching transistors of the two data storage units form a series combination with each other. Each memory cell 342 and memory cell 348 further includes a series combination of FeFET 322 , FeFET 328, and input switching transistor 324 and input switching transistor 330. In some embodiments, the drain or source of the FeFET of the series combination in one of the data storage units is connected to one end of the series combination of the ML switching transistor; The drain or source of the FeFET in the series combination is connected to the junction between the ML switching transistors. In the example embodiment shown in FIG. 2, the sources of FeFET 322 and FeFET 328 are connected to the input switching transistor (FET in this example) 324 , the drain of the input switching transistor 330 , and FeFET 322 , The drain of FeFET 328 is connected to ML switching transistor 326 and ML switching transistor 332 . In some embodiments, the sources of the input switching transistor (FET) 324 and the input switching transistor 330 are connected to a voltage reference point, such as ground in this example.

In this embodiment, the control terminals (base or gate) of the ML switching transistor 326 and the ML switching transistor 332 are connected to a common ML enable line ("EN _ML ") to receive the ML enable signal. The gate of each of FeFET 322 and FeFET 328 is connected to a common word line ("WL") to receive the WL signal so that data can be written to FeFET 322 and FeFET 328 and read from FeFET 322 and FeFET 328 Get information. The junction between FeFET 322 and FeFET 328 and the serial combination of input switching transistor 324 and input switching transistor 330 is connected to the selection line ("SL" or "SL#") to receive the SL signal, so that Able to write data to FeFET and read data from FeFET. The drain or source of FeFET 322 and FeFET 328 connected to the respective ML switching transistor 326 and ML switching transistor 332 is connected to the bit line ("BL" or "BL#") to enable data writing To FeFET 322 and FeFET 328 and read data from FeFET 322 and FeFET 328. The control terminal (the gate of the base) of each input switching transistor 324 and input switching transistor 330 is connected to the input line ("IN" or "IN#") to receive the information to be stored in FeFET 322 and FeFET 328 The value matches the input value.

In some embodiments, the TCAM array 310 includes the TCAM cells 320 described above and configured in rows 314 and columns 312 . The ML switching transistor 326 and the ML switching transistor 332 of each column in the TCAM cell 320 are connected in series and share the common ML enable line and the common WL of the column. The TCAM cells in each row share a common BL, a common BL#, a common SL, a common SL#, a common IN, and a common IN#. In some embodiments, TCAM cells can be used for data storage and retrieval by conventional methods, and for content-based searches. For example, when ENML is all off and IN and IN# are all off, the device 300 becomes the same as the example circuit 170 depicted in FIG. 1H and functions as a FeFET memory array.

In the example shown in FIG. 2, each TCAM cell 320 is adapted to store a pair of data bits, one bit is stored in FeFET 322 and the other bit is stored in FeFET 328 . The bit pair stored in each TCAM cell 320 indicates "0", "1" or "X". In some examples below, each pair is represented as "( b ₁ , b ₂ )", where each of b ₁ and b ₂ can be "0" or "1". For example, in some embodiments , the (0, 1) stored in the TCAM cell 320 indicates the binary "0"; (1, 0) indicates the binary "0" and (0, 0) indicates the "X" .

In some embodiments, the digital pattern representing the binary string is stored in the TCAM cell 320 , and each pattern is stored in the row 312 . The input digital pattern is compared with the stored digital pattern, and the row storing the matching pattern (not counted as a match) is sent by, for example, "1" on the respective ML. In some embodiments, the TCAM cell 320 writes row by row. In some embodiments, the rows of the data storage unit 342 and the data storage unit 348 are written one row at a time. In some embodiments, such as the example shown in FIG. 3, each row of the FeFET can be written in two stages, where all "0"s are written in one stage and all "1"s are written in another stage. Writing "0" involves applying a positive pulse (for example, 1.0 volt) to the WL in all the columns to be written with "0", and applying a negative pulse (for example, -1.0 volt) to the BL and SL of the row to be written , Or BL# and SL#. Writing "1" involves applying a negative pulse (for example -1.0 volt) to the WL in all the columns to be written "1", and applying a positive pulse (for example 1.0 volt) to the BL and the row of the row to be written SL, or BL# and SL#. In the example shown in FIG. 3, "0" is written first, but the reverse order can also be used.

As a specific example, as shown in FIGS. 4-7, in order to write the row 314 TCAM cell, all "0"s are written to the appropriate FeFET 322 (associated with BL, SL, and IN) in the row. Next, all "0"s are written to the appropriate FeFET 328 in the row (associated with BL#, SL#, and IN#). Then, all "1"s are written to the remaining FeFET 322 in the row. Then, all "1"s are written to the remaining FeFET 328 in the row. More specifically, in a write operation, 0 volts are applied to all IN lines and IN# lines, all input switching transistors 324 and 330 are turned off, and 0 volts are applied to all EN _ML lines, Turn off all ML switching transistors. Therefore, the TCAM device is configured as a FeFET memory array similar to the memory array shown in FIG. 1H.

As shown in FIG. 4, in order to write "0" to FeFET 322 , a positive pulse is applied to the WL of the column to be written with "0", and the BL and SL of the row to be written are biased to negative Voltage. The BL and SL of the remaining rows, and all BL# and SL# are biased at 0 volts. As shown in FIG. 5, in order to write "0" to FeFET 328 , a positive pulse is applied to the WL of the column to be written with "0", and the BL# and SL# of the row to be written are biased as Negative voltage. The BL# and SL# of the remaining rows, and all BL and SL are biased at 0 volts.

As shown in FIG. 6, in order to write "1" to FeFET 322 , a negative pulse is applied to the WL of the column to be written with "1", and the BL and SL of the row to be written are biased to positive Voltage. The BL and SL of the remaining rows, and all BL# and SL# are biased at 0 volts. As shown in FIG. 7, in order to write "1" to FeFET 328 , a negative pulse is applied to the WL of the column to be written with "1", and the BL# and SL# of the row to be written are biased It is a positive voltage. The BL# and SL# of the remaining rows, and all BL and SL are biased at 0 volts.

In some embodiments, the data stored in the TCAM cell is read row by row. When reading data, apply 0 volts to all IN lines and IN# lines, turn off all input switching transistors 324 and 330 , and apply 0 volts to all EN _ML lines, turn off all ML switches Transistor. Therefore, the TCAM device is configured as a FeFET memory array similar to the memory array shown in FIG. 1H. In order to read the data row, as shown in Figure 8, precharge all BL and BL# to a positive read voltage V _R ( | V _R | ＜ |V _T | ), and set all SL and SL# to 0 volts. Then the read voltage pulse V _R is applied to WL column to be read. For FeFET 322 and FeFET 328 that store "1", the drain-to-source (BL to SL or BL# to SL#) resistance is higher, and therefore the discharge rate from BL or BL# will be extremely small. In some instances are close to zero, and the read voltage pulse V _R is applied to the WL during the time period, the voltage drop on the BL or BL # to a minimum, close to zero in some instances. On the contrary, for FeFET 322 and FeFET 328 storing "0", the drain-to-source (BL to SL or BL# to SL#) resistance is lower, and therefore the discharge rate from BL or BL# will be faster. and the read voltage pulse V _R is applied to the WL during the time period, the voltage on BL and BL # is significant will drop. Thus, at the end of the read pulse voltage V _R, BL, or BL # on the voltage instruction value stored in the respective FeFET, and can be used, for example, analog to digital converter ( "analog-to-digital converter; DAC") (Not shown) Converted to a binary value indicating the stored value.

In some embodiments, as shown in FIG. 9, in order to determine whether the input pattern matches any pattern stored in the TCAM array 310 , the input pattern is applied to the IN line and the IN# line; for example, the precharge switch is turned on Transistor 910 and all EM _ML lines are turned on to turn on all ML switching transistors 226 and ML switching transistors 232 to precharge the matching line ML to the matching voltage V _M ; ground all SL and SL#; and use the read All pulse voltage V _R WL. As discussed above, “0” stored in FeFET 322 and FeFET 328 implies lower BL to SL or BL# to SL# resistance, and “1” implies higher BL to SL or BL# to SL# resistance. For the input switching transistor 324 and the input switching transistor 330 , a "1" at the corresponding IN or IN# turns the transistor on, and a "0" turns off the transistor. Since each FeFET 322 and FeFET 328 are connected in series with respective input switching transistors 324 and input switching transistors 330 , they can only be connected to both FeFET 322 and FeFET 328 of BL or BL# and respective input switching transistors. 32 4. When the input switching transistor 330 is on or has a low resistance, there will be significant discharge through the series combination. Therefore, only when the value at the respective IN or IN# is "1" and the respective FeFET 322 and FeFET 328 store "0", there will be significant discharge through the series combination; all other combinations do not produce discharge. Or produce very low discharge. Since each column 312 FeFET 322, FeFET 328 severally input switching transistor 324, the input switching transistor 330 from all combinations of tandem columns ML branch, only when it is in a row of IN or IN # Only when the value at which is "1" and the respective FeFET 322 and FeFET 328 store "0", there will be a significant discharge from the ML.

Therefore, for the binary pair (IN, IN#) at the input and the binary pair (data, data#) in the respective FeFET 322 and FeFET 328 stored in the TCAM cell 320 , if IN = 1 and DATA = 0, or IN# = 1 and DATA# = 0, or both, there will be a significant discharge from the corresponding ML. That is, only when the input (0, 1) is applied to the TCAM cell storing (1, 0), or the input (1, 0) is applied to the TCAM cell storing (0, 1), there will be a significant discharge. If (0, 1) is defined as indicating the binary digit "0" and (1, 0) is defined as the indicating binary digit "1", then only when the binary digit is input and the binary digit stored separately When there is a mismatch, there will be a significant discharge from the ML. If the input binary digits match the stored binary digits (that is, the stored (0, 1) input (0, 1), or the stored (1, 0) input (1, 0)) match , There will be no significant discharge.

In addition, if (0, 0) of (IN, IN#) and (1, 1) of (data, data#) are defined as "X" (don’t care), then if the binary digit or the stored binary is input If the carry bit is "X", there will be no significant discharge from the ML of the TCAM cell 320. The matching situation is summarized in Table 1 below ("X" in Table 1 represents a bit that can be "0" or "1"): Table 1. Input-data matching enter enter# material material# match 0 1 0 1 No discharge (matching) 0 1 1 0 Discharge (mismatch) 1 0 0 1 Discharge (mismatch) 1 0 1 0 No discharge (matching) 0 0 X X No discharge (matching) X X 1 1 No discharge (matching)

Therefore, in some embodiments, if each binary digit in the input binary digit pattern and the corresponding binary digit in the stored binary digit pattern are consistent with each other, or at least one of the two binary digits is "X", the voltage on ML will be substantially maintained at V _M , thereby indicating a match between the input binary bit pattern and the stored binary bit pattern. If there is at least one mismatched binary bit between the input binary bit pattern and the stored binary bit pattern, the voltage on the ML will be significantly reduced due to the discharge.

As a specific example, in FIG. 9, TCAM array 310 illustrated as storing the following set of values: indicate column ₀ binary digit bit pattern "1010" (1, 0), (0, 1), (1, 0), (0, 1); indicated in column ₁ binary digit bit pattern "1010" (1, 0), (0, 1), (1, 0), (0, 1), and indicates the column _n (0, 1), (1, 0), (0, 1), (1, 0) of the binary digit pattern "0101" in _-1. Apply the set of input values (1, 0), (0, 1), (1, 0), (0, 1) indicating the binary bit pattern "1010" at the IN line and IN# line in the four rows 314 . Since the input binary bit pattern is consistent with those stored in row ₀ and row ₁ , the ML of both _{row 0} and row ₁ is substantially maintained at V _M , or higher than a certain threshold voltage. Since the input binary bit pattern is inconsistent with the binary bit pattern stored in row _{n -1} , and there are no extraneous bits in any binary bit pattern, the ML of _{row n -1} will drop significantly from V _M, Or fall below the threshold voltage.

As another specific example, in FIG. 10, the TCAM array 310 is shown as a collection of the same values as shown in FIG. 9. Apply the set of input values (1, 0), (0, 0), (1, 0), (0, 1) indicating the binary bit pattern "1X10" at the IN line and IN# line in the four rows 314 . _{Because the input binary bit pattern is consistent with those stored in row 0} and row ₁ , except for the second most significant bit ("most significant bit; MSB"), and because the second MSB of the input binary bit pattern is irrelevant Therefore, the ML of both _{column 0} and column ₁ remains substantially at V _M , or higher than a certain threshold voltage, thereby indicating a match. Because the input binary bit pattern is not consistent with the binary bit pattern stored in row _{n -1} and at least a pair of corresponding digits (such as MSB) in the input binary bit pattern and the stored binary bit pattern are neither consistent with each other nor Without "X", the ML of _{column n -1} will drop significantly from V _M , or drop below the threshold voltage, thereby indicating a mismatch.

As another specific example, in FIG. 11, the TCAM array 310 is shown to store a set of the same values as shown in FIG. 9, except _{that the second value stored in row 0} indicates the binary number "X" ( 1, 1) other than. That is, instead of the binary bit pattern "1010", "1X10" is stored in row ₀ . As shown in Figure 9, the input values (1, 0), (0, 1), (1, 0), (0 , 1) collection. Because the input binary bit pattern is consistent with the binary bit pattern _{stored in row 0} except for the second most significant bit ("MSB"), and because the second MSB of the binary bit pattern _{stored in row 0 is irrelevant} Therefore, the ML of _{column 0} remains substantially at V _M , or higher than a certain threshold voltage, thereby indicating a match. Since the input binary bit pattern is consistent with the binary bit pattern stored in column ₁ , the ML of _{column 1} remains substantially at V _M or higher than the threshold voltage, thereby indicating a match. Since the input binary bit pattern is inconsistent with the binary bit pattern stored in row _{n -1} , and there are no extraneous bits in any binary bit pattern, the ML of _{row n -1} will drop significantly from V _M, Or fall below the threshold voltage.

In more general terms, in some embodiments, as outlined in Figure 12, a data processing method 1200 includes ( 1210 ) storing a set of values in a memory array, each of which can alternately represent two Carry "0", "1" and "X"(don't care), and the stored value represents the first binary pattern. The method further includes ( 1220 ) providing a second set of values, each corresponding to a respective one of the first set of values and indicating a binary bit "0", "1" or "X", the first set of values The second set thus represents the second binary bit pattern. The method further includes ( 1230 ) comparing each of the first set of values with a corresponding one of the second set of values, and ( 1240 ) if each value in the first set is compared with the second set Corresponding values in are consistent with each other, or at least one of the two values indicates "X", then a signal indicating a match between the first binary pattern and the second binary pattern is generated.

The example embodiments described above provide a FeFET-based CAM that has an efficient structure and can be used as both a conventional memory with index reading and a ternary content addressable memory . In addition, the embodiment allows irrelevant values to be included in the stored data or input, thereby allowing increased application flexibility.

The foregoing summarizes the features of several embodiments, so that those with ordinary knowledge in the relevant technical field can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose and/or achieving the same advantages of the embodiments introduced herein. Those with ordinary knowledge in the technical field should also realize that such equivalent structures do not deviate from the spirit and scope of the content of the disclosure, and those with ordinary knowledge in the technical field can do so without departing from the spirit and scope of the disclosure. Various changes, substitutions and changes are made in this article.

100: data processing device 110, 310: array 112, 312 _{: row 112 i , 312 i} : i-th column 114, 314: row 112 _j , 312 _j : j-th row 120, 320 _{: TCAM cell 120 i, j, 320 i,j} : each cell 130: search data input interface 140, 140 i: amplifier 150: matching output interface 160, 322, 328: FeFET 161: FeFET memory array 162: bulk substrate 164: ferroelectric layer 166: gate 168 : Drain 170: Source 172: Channel area 300: TCAM devices 324, 330: Input switching transistors 326, 332: ML switching transistors 342, 348: Data storage unit 910: Precharge switching transistors 1200: Method 1210, 1220, 1230, 1240: Step BL, BL#: bit line IN _j-1 ~IN _j+1 , IN# _j-1 ~IN# _j+1 : input line ML _i-2 ~ML _i+1 : matching line SL, SL #: select line V _G, V _R: voltage V _GS: gate-to-source voltage V _M: match the voltage V _T: threshold voltage WL: wordline

When read in conjunction with the accompanying drawings, the following detailed description will best understand the aspect of the present disclosure. It should be noted that according to standard practices in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the size of various features can be increased or decreased arbitrarily. Figure 1A is a schematic diagram illustrating an example ternary content addressable memory (TCAM) device according to some embodiments. FIG. 1B and FIG. 1C are respectively a schematic structure and symbolic representation of a ferroelectric field-effect transistor (FeFET) of the type used in the TCAM device shown in FIG. 1A according to some embodiments. 1D, 1E, and 1F are respectively a schematic diagram of a FeFET in a low resistance state, a schematic diagram of a FeFET in a high resistance state, and a drain current and a gate voltage showing the hysteresis characteristics of FeFET according to some embodiments. Curve. Fig. 1G shows the polarization versus electric field curve _{of Si:HfO 2} for varying Si cation molar fraction (cat%). According to some embodiments, the ferroelectric properties are evident at about 4.4 cat%. Figure 1H schematically illustrates a two-dimensional array of FeFET memory cells according to some embodiments. Figure 2 schematically illustrates a Ternary Content Addressable Memory (TCAM) device according to some embodiments. FIG. 3 shows a staged writing of memory components in a TCAM device of the type depicted in FIG. 2 according to some embodiments. Figure 4 illustrates writing 0 to data bits of certain TCAM cells in a column of the TCAM array according to some embodiments. Figure 5 illustrates writing 0 to the data complement (data#) bits of certain TCAM cells in the rows of the TCAM array according to some embodiments. Figure 6 illustrates writing 1 to data bits of certain TCAM cells in a row of the TCAM array according to some embodiments. FIG. 7 shows the data complementary (data#) bits of some TCAM cells in the rows of the TCAM array that are written to according to some embodiments. Figure 8 illustrates row reading from a memory cell according to some embodiments. FIG. 9 illustrates a search operation according to some embodiments, in which a specific bit pattern is searched for a specific bit pattern. FIG. 10 illustrates a search operation according to some embodiments, in which a bit pattern containing don't care bits is searched for a specific bit pattern. Figure 11 illustrates a search operation according to some embodiments, in which a specific bit pattern is searched for a bit pattern, some of which contain extraneous bits. FIG. 12 outlines the process of data processing using content addressable memory according to some embodiments.

100: data processing device

110: Array

112 _i : i-th column

114 _j : row j

120: TCAM cell

120 _i,j : each cell

130: Search data input interface

140 _i : amplifier

150: matching output interface

IN _{j - 1} ~IN _{j + 1} 、IN# _{j - 1} ~IN# _{j + 1} : input line

ML _{i - 2} ~ML _{i + 1} : match line

Claims (20)

A memory device includes: The first data storage unit and the second data storage unit are each adapted to store a binary bit, and each of the data storage units includes: Match line ("ML") switching transistors; and Tandem combination of ferroelectric field effect transistor ("FeFET") and input switching transistor, The ML switching transistors of the first data storage unit and the second data storage unit are connected to each other at the junction to form a serial combination with a first end and a second end, One end of the series combination of the FeFET and the input switching transistor in the first data storage unit is connected to the first end of the series combination of the ML switching transistor at a junction. One end, and one end of the series combination of the FeFET and the input switching transistor in the second data storage unit is connected to the junction between the ML switching transistor. The memory device according to claim 1, wherein the FeFET in each of the first data storage unit and the second data storage unit has a gate, a source, and a drain, and the first The drain of the FeFET in a data storage unit is connected to the first end of the series combination of the ML switching transistor, and all of the FeFET in the second data storage unit The drain is connected to the junction between the ML switching transistors. The memory device according to claim 2, wherein each of the ML switching transistor and the input switching transistor is a field effect transistor ("FET") having a gate, a source, and a drain, The gates of the ML switching transistors in the first data storage unit and the second data storage unit are connected to each other and are adapted to receive a match line ("ML") enable signal, The gates of the FeFETs in the first data storage unit and the second data storage unit are connected to each other and are adapted to receive word line ("WL") signals, and The gate electrode of the input switching transistor is adapted to receive respective input signals. The memory device according to claim 1, further comprising: a third data storage unit and a fourth data storage unit, each adapted to store a binary bit, each of the data storage units includes: ML switching transistor; and The series combination of FeFET and input switching transistor, The ML switching transistors of the third data storage unit and the fourth data storage unit are connected to each other at the junction to form a serial combination having a first end and a second end, and the first end is connected to the The second end of the serial combination of the ML switching transistors of the first data storage unit and the second data storage unit, the first data storage unit, the second data storage unit, the The ML switching transistors of the third data storage unit and the fourth data storage unit form a matching line having an input terminal and an output terminal, One end of the series combination of the FeFET and the input switching transistor in the third data storage unit is connected to the first end of the series combination of the ML switching transistor at a junction. One end of the series combination of the FeFET and the input switching transistor in the fourth data storage unit is connected to the third data storage unit and the fourth data storage unit The ML switches the junction between the transistors. The memory device according to claim 4, wherein each of the FeFET, ML switching transistor, and input switching transistor has a gate, a source, and a drain, and the memory device further includes: WL, connected to the gate of the FeFET in the memory device; The ML enable line is connected to the gate of the ML switching transistor; A plurality of pairs of a first bit line and a second bit line ("BL"), wherein the first bit line is connected to the ML switching circuit of the first data storage unit and the second data storage unit The first end of the serial combination of crystals, the second bit line is connected to the ML switching transistor between the first data storage unit and the second data storage unit Interface, the third bit line is connected to the first end of the serial combination of the ML switching transistors of the third data storage unit and the fourth data storage unit, and the fourth bit Wire connected to the interface between the ML switching transistors of the third data storage unit and the fourth data storage unit; A plurality of select lines ("SL"), each connected to the junction between the FeFET and the input switching transistor in each of the data storage units; and A plurality of pairs of first input lines and second input lines ("IN") are each connected to the gate of the input switching transistor in each of the data storage units. The memory device according to claim 4, wherein the drain of each of the FeFETs in each of the data storage units is connected to the ML switching transistor of the data storage unit. The memory device according to claim 6, wherein, for each of the data storage units, the drain of the input switching transistor is connected to the source of the respective FeFET, and The source of the input switching transistor is adapted to be connected to a common voltage reference point. The memory device according to claim 4, further comprising a switching device adapted to connect the input terminal of the match line to a reference voltage. A data processing device includes: Multiple character lines ("WL"); Multiple match line activation ("ML activation") lines; Multiple bit lines ("BL"); Multiple selection lines ("SL"); Multiple input lines ("IN"); A plurality of data storage units are logically arranged into a plurality of rows and rows, each of the rows of the data storage unit and each of the WL and each of the ML enable lines One is related, and each of the rows of the data storage unit is related to a respective one of the BL, a respective one of the SL, and a respective one of the IN Each of the data storage units includes: Match line ("ML") switching transistor; Ferroelectric Field Effect Transistor ("FeFET"); and The input switching transistor is connected to the FeFET at the junction and forms a series combination with the FeFET. The gate of the FeFET is connected to the associated WL; the first end of the series combination is connected To the associated BL; the junction between the input switching transistor and the FeFET is connected to the associated SL; the gate of the input switching transistor is connected to the associated IN; The ML switching transistors in each row of the data storage device are serially connected to each other at a plurality of BLs to form a matching line having an input terminal and an output terminal, and the ML switching transistors in each row of the data storage device The gate of the transistor is connected to the associated ML enable line. The data processing device according to claim 9, wherein the first end of the series combination of the input switching transistor and FeFET in each of the plurality of data storage devices is the FeFET Of the source or the drain. The data processing device described in claim 9 further includes: A plurality of switching devices, each associated with a respective one of the matching lines, the plurality of switching devices being adapted to connect the input terminal of the matching line to a reference voltage; and The matching output interface is adapted to receive the signal from the output terminal of the plurality of match lines and generate an output signal indicative of the signal from the output terminal of the match line. The data processing device described in claim 11 further includes: A search data input interface, adapted to supply binary signals to the plurality of INs; and The stored data input/output ("I/O") interface is adapted to supply the character line WL with a signal indicating the data to be stored in the data storage unit, and is adapted to receive instructions from the BL to store in The signal of the data in the data storage unit. The data processing device according to claim 12, wherein: The storage data I/O interface is adapted to store three different combinations of binary bits in each pair of data storage units in each pair of rows, one combination indicates a binary bit "0", and a combination indicates two Carry "1", and a combination indicates binary irrelevant ("X"), thereby storing a set of values indicating the stored binary bit pattern in each row of the data storage unit, where each digit is "0" , "1" or "X"; and The search data input interface is adapted to supply three different combinations of binary digits for each pair of the IN associated with the respective pair of rows, one combination indicating a binary "0" and one combination indicating Binary "1", and a combination indicates binary "X", thereby supplying a set of values indicating the input binary bit pattern to all rows of the data storage unit, where each digit is "0", "1" or "X"; and Each of the ML is adapted to supply at the output a first signal indicating a match between the stored binary bit pattern and the input binary bit pattern, in the input binary bit pattern Each digit of and the individual digits in the stored binary digit pattern are consistent with each other, or at least one of the two digits is "X". The data processing device according to claim 13, wherein each of the set of stored values includes a pair of binary numbers ( b ₁ , b ₂ ) = (0, 1), (1, 0) Or (1, 1), where (0, 1) indicates the binary "0", (1, 0) indicates the binary "1" and (1, 1) indicates the binary "X". The data processing device according to claim 14, wherein each of the set of input values includes a pair of binary numbers ( a ₁ , a ₂ ) = (0, 1), (1, 0) or ( 0, 0), where (0, 0) indicates the binary "X". A data processing method, including: Store a first set of values in the memory array. Each of the first set of values can alternately represent the binary bits "0", "1" and "X" (don’t care), and the stored value is thereby Represents the first binary bit pattern; Provide a second set of values, each corresponding to one of the first set of values and indicating a binary "0", "1" or "X", the second set of values thereby represents the first set of values Binary bit pattern; Comparing each of the first set of values with a corresponding one of the second set of values; and If each value in the first set and the corresponding value in the second set are consistent with each other, or at least one of the two values indicates "X", then generate the first binary pattern indicating A signal that matches the second binary pattern. The data processing method according to claim 16, wherein storing the first set of values includes storing a set of binary value pairs, wherein storing each of the binary value pairs includes combining the binary value pairs Each pair of the first data storage unit and the second data storage unit written into the memory device, each of the data storage units includes: Match line ("ML") switching transistors; and A series combination of a ferroelectric field effect transistor ("FeFET") and an input switching transistor. Each of the ML switching transistor, the FeFET, and the input switching transistor has a gate, a source, and a drain. And the FeFET has a threshold voltage for changing its memory state, The ML switching transistors of the first data storage unit and the second data storage unit are connected to each other at the junction to form a serial combination with a first end and a second end, One end of the series combination of the FeFET and the input switching transistor in the first data storage unit is connected to the first end of the series combination of the ML switching transistor at a junction. One end, and one end of the series combination of the FeFET and the input switching transistor in the second data storage unit is connected to the junction between the ML switching transistor, wherein The writing of each bit of the binary value pair to each of the data storage units includes: Turning off both the ML switching transistor and the input switching transistor; and A voltage with an amplitude greater than the threshold voltage is applied between the gate and the source and drain of the FeFET. The data processing method according to claim 17, wherein: The comparing step includes applying an input voltage indicating the value of the bit to the gate of each input switching transistor; and The generating step includes summing the currents in the series combination of the FeFET and the input switching transistor in the set of data storage cell pairs. The data processing method according to claim 17, wherein the storing step includes storing a plurality of sets of values, and each set of the respective rows of the data storage units in the memory array includes data logically arranged in rows and rows The storage unit, wherein the set of storing a plurality of values includes: During the first time period, synchronously write all "0"s in the binary value to a row of the data storage unit; and During a second time period different from the first time period, all "1"s in the binary value are synchronously written to the row of the data storage unit. The data processing method according to claim 17, further comprising reading the first set of values from the data storage unit.

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