TWI851006B - In-dynamic memory search device and operation method thereof - Google Patents

Abstract

An in-dynamic memory search device and an operation method thereof are provided. The in-dynamic memory search device includes at least one word line, at least two bit lines, at least one match line, at least one unit cell, at least two search lines, at least one pre-charge unit and at least one sense unit. The unit cell includes two storage elements and two search transistors. Each of the storage elements includes a write transistor and a read transistor. The write transistor is connected to the word line and one of the bit lines. The read transistor is connected to the write transistor and the match line. The search transistors are respectively connected to the read transistors. The search lines are respectively connected to the search transistors. The pre-charge unit is connected to the match line. The sense unit is connected to the match line.

Description

Dynamic memory in-body search device and its operation method

The present disclosure relates to a memory device and an operating method thereof, and in particular to a dynamic memory search device and an operating method thereof.

Traditionally, TCAM based on static random access memory (SRAM) can be used in commercial applications such as network routers. However, a single TCAM requires 16 transistors, which will require a considerable area and power consumption, limiting its potential in certain energy-constrained applications.

TCAM can be used in routers, database searches, in-memory data processing, and neuromorphic computing.

With the rise of IoT applications, the demand for low static power CAM is also increasing. TCAM based on emerging memories (RRAM, PCM, FeFET) has been shown to overcome the challenges of area density/static power without sacrificing performance. However, the on/off ratio in ReRAM and PCM is not enough for many practical applications that require parallel search of massive data sets. Because in the TCAM array, the leakage current of TCAM cells on the same match line will be added together, and the limited R ratio makes it difficult to distinguish between the full match state and the 1-bit mismatch state when the number of groups is large. In addition, the limited endurance of TCAM of these emerging memories also limits the frequency of data update.

The present disclosure is about a dynamic in-memory search device and its operation method. The dynamic in-memory search device disclosed in the present disclosure is a TCAM similar to DRAM (it adopts a pair of 2T0C structures and 2 search transistors) to perform the function of in-memory search. The dynamic in-memory search device 100 can provide unlimited update frequency, fast search and on/off ratio suitable for long search strings. The unit memory cell UC is a 6T0C structure. Compared with the TCAM of SRAM, the 6T0C structure has a smaller area. The technology disclosed in the present disclosure is very suitable for routers, database search, memory data processing and neural morphological computing.

According to one aspect of the present disclosure, an in-dynamic memory search device is provided. The in-dynamic memory search device includes at least one word line, at least two bit lines, at least one matching line, at least one unit memory cell, at least two search lines, at least one precharge unit and at least one sensing unit. The unit memory cell includes two storage elements and two search transistors. Each storage element includes a write transistor and a read transistor. The write transistor is connected to the word line and one of the bit lines. The read transistor is connected to the write transistor and the matching line. The search transistors are respectively connected to the read transistors. At least two search lines are respectively connected to the search transistors. The precharge unit is connected to the matching line. The sensing unit is connected to the matching line.

According to another aspect of the present disclosure, a method for operating a search device in a dynamic memory is provided. The search device in a dynamic memory includes at least one word line, at least two bit lines, at least one matching line, at least one unit memory cell and two search transistors. The unit memory cell includes two storage elements and two search transistors. Each storage element includes a write transistor and a read transistor. The write transistor is connected to the word line and one of the bit lines. The read transistor is connected to the write transistor and the matching line. The operation method includes the following steps. Write a storage data to the unit memory cell. Precharge the matching line. Input a search data to the search lines. Sense a voltage of the matching line to determine whether the search data matches the storage data.

In order to better understand the above and other aspects of this disclosure, the following is a specific example, and the attached drawings are used to explain in detail as follows:

100,200: Dynamic memory in-body search device

CG, CGj: pre-charged unit

CV1,CV2,CV3: curves

DT, DTj: store data

EC:decoder

GD: Ground terminal

Irk,Iwk: leakage current

Irp: conduction current

ML,MLj:matching line

RS:Search results

RT0,RT1,RT_0,RT_1,RT_2,RT_3: read transistors

SA,SAj: Sensing unit

SE0, SE1, SE_0, SE_1, SE_2, SE_3: storage components

SL1,SL1’,SLi,SLi’:Search line

SR: Search data

SRi: bit

ST0, ST1: Search transistor

SN,SN’: storage node

UC,UCij:unit memory cell

Voff: Off voltage

Von: Starting voltage

WBL0,WBL1,WBLi,WBLi’: bit line

WT0,WT1,WT_0,WT_1,WT_2,WT_3: write transistors

WWL,WWLj: character line

FIG. 1 is a schematic diagram of an in-dynamic memory search device according to an embodiment.

Figures 2A to 2D illustrate the operation of Table 1.

Figures 3A to 3D illustrate the operation of Table 2.

Figure 4 shows a flow chart of an operation method of a dynamic memory in-body search device according to an embodiment.

Figure 5A shows the I-V characteristic curve of the write transistor.

Figure 5B shows the current-voltage characteristic curve of the transistor.

Figures 6A to 6D show four types of 2T0C structures.

FIG. 7 illustrates a dynamic memory in-body search device according to an embodiment.

Figure 8 shows an example of a matching line curve.

Please refer to FIG. 1, which shows a schematic diagram of an in-dynamic memory search device 100 according to an embodiment. The in-dynamic memory search device 100 is a TCAM similar to DRAM to perform an in-memory search function. For example, the in-dynamic memory search device 100 can be a two-dimensional flash memory device or a three-dimensional flash memory device. As shown in FIG. 1, a unit memory cell UC of the in-dynamic memory search device 100 is used to store a bit of storage data DT. After a search data SR is input into the in-dynamic memory search device 100, a search result RS is output to know whether the storage data DT matches the search data SR.

In the present disclosure, the dynamic memory search device 100 can provide unlimited update frequency, fast search and on/off ratio suitable for long search strings. The detailed structure of the dynamic memory search device 100 and its operation method will be described as follows.

As shown in Figure 1, the unit memory cell UC is a 6T0C structure. Compared with the TCAM of SRAM, the 6T0C structure has a smaller area. "6T0C" refers to 6 transistors and 0 capacitors. In this embodiment, the 6T0C structure includes a pair of storage elements SE0, SE1 and two search transistors ST0, ST1. Each storage element SE0, SE1 is a 2T0C structure. The "2T0C" structure refers to 2 transistors and 0 capacitors. In detail, the storage element SE0 includes a write transistor WT0 and a read transistor RT0; the storage element SE1 includes a write transistor WT1 and a read transistor RT1.

The dynamic memory in-memory search device 100 includes at least one word line WWL, at least two bit lines WBL0, WBL1, at least one match line ML, at least one unit memory cell UC, at least two search lines SL1, SL1', at least one precharge unit CG and at least one sensing unit SA. A gate of the write transistor WT0 is connected to the word line WWL, a source/drain of the write transistor WT0 is connected to the bit line WBL0, and another source/drain of the write transistor WT0 is connected to a gate of the read transistor RT0. The gate of the read transistor RT0 is connected to the source/drain of the write transistor WT0, one source/drain of the read transistor RT0 is connected to the match line ML, and the other source/drain of the read transistor RT0 is connected to a source/drain of the search transistor ST0. A gate of the search transistor ST0 is connected to the search line SL1, one source/drain of the search transistor ST0 is connected to the source/drain of the read transistor RT0, and the other source/drain of the search transistor ST0 is connected to a ground terminal GD. The read transistor RT0 and the search transistor ST0 are connected in series between the match line ML and the ground terminal GD.

A gate of the write transistor WT1 is connected to the word line WWL, a source/drain of the write transistor WT1 is connected to the bit line WBL1, and the other source/drain of the write transistor WT1 is connected to a gate of the read transistor RT1. A gate of the read transistor RT1 is connected to the source/drain of the write transistor WT1, a source/drain of the read transistor RT1 is connected to the match line ML, and the other source/drain of the read transistor RT1 is connected to a source/drain of the search transistor ST1. One gate of the search transistor ST1 is connected to the search line SL1', one source/drain of the search transistor ST1 is connected to the source/drain of the read transistor RT1, and the other source/drain of the search transistor ST1 is connected to the ground terminal GD. The read transistor RT1 and the search transistor ST1 are connected in series between the match line ML and the ground terminal GD.

The pre-charge unit CG is connected to the matching line ML to pre-charge the matching line ML to a predetermined voltage level. The sensing unit SA is connected to the matching line ML to sense the voltage of the matching line ML.

Please refer to Table 1 and Figures 2A to 2D. Table 1 records the voltage applied to the search device 100 in the dynamic memory when writing the storage data DT. Figures 2A to 2D illustrate the operation of Table 1. In the first column of Table 1, the storage data DT to be stored in the unit memory cell UC is "0". In the second column of Table 1, the storage data DT to be stored in the unit memory cell UC is "1". In the third column of Table 1, the storage data DT to be stored in the unit memory cell UC is "Don't care". "Don't care" can match any search data SR. In the fourth column of Table 1, the storage data DT to be stored in the unit memory cell UC is "Invalid". "Invalid" cannot match any search data SR.

As shown in FIG. 2A and the first column of Table 1, "0" is to be stored in the unit memory cell UC. A start voltage (e.g., 3V) is applied to the word line WWL to turn on the write transistors WT0 and WT1. A turn-off voltage (e.g., 0V) is applied to the search lines SL1 and SL1' to turn off the search transistors ST0 and ST1. A predetermined low voltage (e.g., 0V) is applied to the bit line WBL0, and a predetermined high voltage (e.g., 1V) is applied to the bit line WBL1. "Predetermined low voltage, predetermined high voltage" ("0V, 1V") represents the storage data DT "0". Since the write transistor WT0 is turned on, the 0V applied to the bit line WBL0 will be stored in the storage node SN between the write transistor WT0 and the read transistor RT0. Since the write transistor WT1 is turned on, the 1V applied to the bit line WBL1 will be stored in the storage node SN’ between the write transistor WT1 and the read transistor RT1.

As shown in FIG. 2B and the second column of Table 1, "1" is to be stored in the unit memory cell UC. A start voltage (e.g., 3V) is applied to the word line WWL to turn on the write transistors WT0 and WT1. A turn-off voltage (e.g., 0V) is applied to the search lines SL1 and SL1' to turn off the search transistors ST0 and ST1. A predetermined high voltage (e.g., 1V) is applied to the bit line WBL0, and a predetermined low voltage (e.g., 0V) is applied to the bit line WBL1. "Predetermined high voltage, predetermined low voltage" ("1V, 0V") represents the "1" of the storage data DT. Since the write transistor WT0 is turned on, 1V applied to the bit line WBL0 will be stored in the storage node SN between the write transistor WT0 and the read transistor RT0. Since the write transistor WT1 is turned on, 0V applied to the bit line WBL1 will be stored in the storage node SN’ between the write transistor WT1 and the read transistor RT1.

As shown in FIG. 2C and the third column of Table 1, “Don’t care” is to be stored in the unit memory cell UC. An enable voltage (e.g., 3V) is applied to the word line WWL to turn on the write transistors WT0 and WT1. A turn-off voltage (e.g., 0V) is applied to the search lines SL1 and SL1’ to turn off the search transistors ST0 and ST1. A predetermined low voltage (e.g., 0V) is applied to the bit line WBL0, and a predetermined low voltage (e.g., 0V) is applied to the bit line WBL1. “Predetermined low voltage, predetermined low voltage” (“0V, 0V”) indicates “Don’t care” of the stored data DT. Since the write transistor WT0 is turned on, 0V applied to the bit line WBL0 will be stored in the storage node SN between the write transistor WT0 and the read transistor RT0. Since the write transistor WT1 is turned on, 0V applied to the bit line WBL1 will be stored in the storage node SN’ between the write transistor WT1 and the read transistor RT1.

As shown in FIG. 2D and the fourth column of Table 1, "Invalid" is to be stored in the unit memory cell UC. An enable voltage (e.g., 3V) is applied to the word line WWL to turn on the write transistors WT0 and WT1. A turn-off voltage (e.g., 0V) is applied to the search lines SL1 and SL1' to turn off the search transistors ST0 and ST1. A predetermined high voltage (e.g., 1V) is applied to the bit line WBL0, and a predetermined high voltage (e.g., 1V) is applied to the bit line WBL1. "Predetermined high voltage, predetermined high voltage" ("1V, 1V") indicates "Invalid" of the stored data DT. Since the write transistor WT0 is turned on, the 1V applied to the bit line WBL0 will be stored in the storage node SN between the write transistor WT0 and the read transistor RT0. Since the write transistor WT1 is turned on, the 1V applied to the bit line WBL1 will be stored in the storage node SN’ between the write transistor WT1 and the read transistor RT1.

Please refer to Table 2 and Figures 3A to 3D. Table 2 shows the voltage applied to the search device 100 in the dynamic memory when searching for the stored data DT. Figures 3A to 3D illustrate the operation of Table 2. In the first row of Table 2, the search data SR is "0". In the second row of Table 2, the search data SR is "1". In the third row of Table 2, the search data SR is "Wildcard". "Wildcard" can match any stored data DT. In the fourth row of Table 2, the search data SR is "Invalid". "Invalid" cannot match any stored data DT.

As shown in Figure 3A, the search data SR is "0" and the storage data DT is "0". 1V and 0V are applied to the search lines SL1 and SL1' respectively, and 0V and 1V are stored in the storage nodes SN and SN' respectively. The storage node SN is 0V, so the read transistor RT0 is turned off, and 0V is applied to the search line SL1', so the search transistor ST1 is turned off. Therefore, the voltage of the matching line ML will remain unchanged.

As shown in Figure 3B, the search data SR is "1" and the storage data DT is "0". 0V and 1V are applied to the search lines SL1 and SL1' respectively, and 0V and 1V are stored in the storage nodes SN and SN' respectively. The storage node SN' is 1V, so the read transistor RT1 is turned on, and 1V is applied to the search line SL1, so the search transistor ST1 is turned on. Therefore, the voltage of the matching line ML will be pulled down.

As shown in Figure 3C, the search data SR is "Wildcard" and the storage data DT is "0". 0V and 0V are applied to the search lines SL1 and SL1' respectively, and 0V and 1V are stored in the storage nodes SN and SN' respectively. The storage node SN is 0V, so the read transistor RT0 is turned off, and 0V is applied to the search line SL1, so the search transistor ST1 is turned off. Therefore, the voltage of the matching line ML will remain unchanged.

As shown in Figure 3D, the search data SR is "0" and the storage data DT is "Don't care". 1V and 0V are applied to the search lines SL1 and SL1' respectively, and 0V and 0V are stored in the storage nodes SN and SN' respectively. The storage node SN is 0V, so the read transistor RT0 is turned off, and 0V is applied to the search line SL1, so the search transistor ST1 is turned off. Therefore, the voltage of the matching line ML will remain unchanged.

Some examples have been described above, but the operation of the dynamic memory search device 100 is not limited to the above examples. The operation of the dynamic memory search device 100 can be performed through the following flowchart.

Please refer to FIG. 4, which is a flow chart showing an operation method of a dynamic memory search device 100 according to an embodiment. The operation method includes steps S110 to S140. In step S110, as shown in the example of FIGS. 2A to 2D, the storage data ST is written into the unit memory cell UC. Please refer to FIG. 5A, which shows the current-voltage characteristic curve (I-V characteristic curve) of the write transistor WT0 (or the write transistor WT1). In this step, the word line WWL is applied with an activation voltage Von (for example, 3V) to activate the write transistors WT0 and WT1. When the write transistors WT0 and WT1 are activated, the voltage applied to the bit lines WBL0 and WBL1 will be stored in the storage nodes SN and SN’.

After the voltage is stored in the storage nodes SN and SN', the word line WWL is applied with an off voltage Voff (for example, 0V or -2V) to turn off the write transistors WT0 and WT1 so that the voltage stored in the storage nodes SN and SN' can be maintained. In one embodiment, the material of the channel layer of the write transistors WT0 and WT1 can be indium gallium zinc oxide (IGZO), polycrystalline silicon (poly-silicon), amorphous silicon (a-Si), or polycrystalline germanium (poly-Ge), so that the leakage current Iwk of the write transistors WT0 and WT1 can be reduced as much as possible. When the leakage current Iwk of the write transistors WT0 and WT1 can be quite low, the voltage stored in the storage nodes SN and SN’ can be well maintained.

Then, in step S120, as shown in the examples of Figures 3A to 3D, the pre-charge unit CG pre-charges the match line ML. For example, the match line ML can be pre-charged to a set voltage (e.g., 5V).

Next, in step S130, as shown in the examples of Figures 3A to 3D, the search data SR is input to the search lines SL1 and SL1'. In this step, when the voltage stored in the storage node SN is 1V, the read transistor RT0 is turned on; when the voltage stored in the storage node SN' is 1V, the read transistor RT1 is turned on; when the voltage applied to the search line SL1 is 1V, the search transistor ST0 is turned on; when the voltage applied to the search line SL1' is 1V, the search transistor ST1 is turned on.

Please refer to FIG. 5B, which shows the current-voltage characteristic curve of the read transistor RT0 (or the read transistor RT1). In one embodiment, the material of the channel layer of the read transistors RT0 and RT1 is, for example, single crystal silicon, single crystal Ge, III-V material, indium gallium zinc oxide (IGZO), so that the pass current Irp of the read transistors RT0 and RT1 can be increased as much as possible. When the pass current Irp of the read transistors RT0 and RT1 can be quite high, the voltage pull-down of the matching line ML can become quite obvious and the search speed can also be improved.

As shown in FIG. 5B , the conduction current Irp is about 1*10 ^-6 A, and the leakage current Irk is about 1*10 ^-12 A. The on/off ratio of the read transistors RT0 and RT1 is quite large (about 10 ^-6 ), and can be applied to long string searches.

Next, in step S140, the sensing unit SA senses the voltage of the matching line ML to determine whether the search data SR matches the storage data DT.

The storage elements SE0 and SE1 are a 2T0C structure. In some embodiments, the 2T0C structure can be implemented by the following four structures. Please refer to Figures 6A to 6D, which illustrate four 2T0C structures. As shown in Figure 6A, the storage element SE_0 includes a write transistor WT_0 and a read transistor RT_0. In the storage element SE_0, the write transistor WT_0 and the read transistor RT_0 are both a threshold voltage tunable transistor. For example, the write transistor WT_0 has a charge storage layer or a ferroelectric layer in its gate stack, and the read transistor RT_0 has a charge storage layer or a ferroelectric layer in its gate stack. The charge storage layer or the ferroelectric layer is represented by a slash. For example, the charge storage layer is a SONOS structure or a floating gate, and the ferroelectric layer is a FeFET structure.

As shown in FIG. 6B , the storage element SE_1 includes a write transistor WT_1 and a read transistor RT_1. In the storage element SE_1, only the read transistor RT_1 is a critical voltage adjustable transistor. For example, the write transistor WT_1 does not have any charge storage layer or any ferroelectric layer, and the read transistor RT_1 has a charge storage layer or a ferroelectric layer in its gate stack. The charge storage layer or the ferroelectric layer is represented by a slash. For example, the charge storage layer is, for example, a SONOS structure or a floating gate, and the ferroelectric layer is, for example, a FeFET structure.

As shown in FIG. 6C , the storage element SE_2 includes a write transistor WT_2 and a read transistor RT_2. In the storage element SE_2, only the write transistor WT_2 is a critical voltage adjustable transistor. For example, the write transistor WT_2 has a charge storage layer or a ferroelectric layer in its gate stack, and the read transistor RT_2 does not have any charge storage layer or any ferroelectric layer. The charge storage layer or the ferroelectric layer is represented by a slash. For example, the charge storage layer is, for example, a SONOS structure or a floating gate, and the ferroelectric layer is, for example, a FeFET structure.

As shown in FIG. 6D , the storage element SE_3 includes a write transistor WT_3 and a read transistor RT_3. In the storage element SE_3, the write transistor WT_3 and the read transistor RT_3 are not critical voltage adjustable transistors. For example, the write transistor WT_3 does not have any charge storage layer or any ferroelectric layer, and the read transistor RT_3 does not have any charge storage layer or any ferroelectric layer.

In the 2T0C structure implemented by the critical voltage adjustable transistor, the leakage current and the conduction current can be adjusted, and many advantages can be obtained. For example, as shown in Figure 5A, when the leakage current Iwk of the write transistors WT0 and WT1 is adjusted lower, the voltage stored in the storage nodes SN and SN' can be maintained well. In addition, as shown in Figure 5B, when the conduction current of the read transistors RT0 and RT1 is adjusted higher, the voltage pull-down of the match line ML becomes more obvious and the search speed can be increased. When the start/stop ratio of the read transistors RT0 and RT1 is adjusted larger, it can be applied to the search of long strings.

Furthermore, in the storage elements SE0 and SE1, the storage data DT is stored in the storage nodes SN and SN' through voltage, so the search device in the dynamic memory can provide an unlimited update frequency.

In addition, the above-mentioned dynamic memory internal search device 10 can be implemented using an array structure to search for long strings. Please refer to Figure 7, which shows a dynamic memory internal search device 200 according to an embodiment. The dynamic memory internal search device 200 includes a plurality of word lines WWLj, a plurality of bit lines WBLi, WBLi’, a plurality of matching lines MLj, a plurality of unit memory cells UCij, a plurality of search lines SLi, SLi’, a plurality of pre-charge units CGj, a plurality of sensing units SAj and a decoder (priority encoder) EC. The search data SR includes a plurality of bits SRi. After the search data SR is input to the dynamic memory search device 200, the sensing unit SAj senses the voltage of the matching line MLj to determine whether the storage data DTj matches the search data SR. Please refer to Figure 8, which shows the curves CV1, CV2, and CV3 of the example of the matching line MLj. When all bits of the storage data DTj match all bits of the search data SR, the voltage of the curve CV1 is maintained without being pulled down.

When one bit of the storage data DTj does not match a corresponding bit of the search data SR, the voltage of the curve CV2 is slightly pulled down.

When two bits of the stored data DTj do not match the corresponding two bits of the search data SR, the curve CV3 is pulled down significantly.

The decoder EC can output the search result RS according to the voltage pull-down amount. In the search result RS, the stored data DTj can be sorted according to the matching degree.

According to the above embodiment, the dynamic in-memory search device is a TCAM similar to DRAM (which uses a pair of 2T0C structures and 2 search transistors) to perform the in-memory search function. The dynamic in-memory search device 100 can provide unlimited update frequency, fast search and on/off ratio suitable for long search strings. The unit memory cell UC is a 6T0C structure. Compared with the TCAM of SRAM, the 6T0C structure has a smaller area. The technology disclosed in this disclosure is very suitable for routers, database searches, memory data processing and neural morphological computing.

In summary, although the present disclosure has been disclosed as above by the embodiments, it is not intended to limit the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the scope defined by the attached patent application.

100: Dynamic memory in-body search device

CG: Pre-charged unit

DT: Save data

GD: Ground terminal

ML: Matching line

RS:Search results

RT0,RT1: read transistors

SA: Sensing unit

SE0, SE1: storage element

SL1,SL1’:Search line

SR: Search data

ST0, ST1: Search transistor

SN,SN’: storage node

UC:Unit memory cell

WBL0,WBL1:bit line

WT0, WT1: write transistor

WWL: Character Line

Claims (10)

An in-dynamic memory search device includes: at least one word line; at least two bit lines; at least one match line; at least one unit memory cell, including: two storage elements, each of which includes: a write transistor connected to the word line and one of the bit lines; and a read transistor connected to the write transistor and the match line; and two search transistors connected to the read transistors respectively; at least two search lines connected to the search transistors respectively; at least one precharge unit connected to the match line; and at least one sensing unit connected to one end of each read transistor through the match line. The dynamic memory search device as described in claim 1, wherein each storage element includes a storage node, each storage node is located between each write transistor and each read transistor, and the unit memory cell stores a bit of storage data in the storage nodes. A dynamic memory search device as described in claim 2, wherein the storage data is written into the storage nodes by turning on the write transistors. The dynamic memory search device as described in claim 1, wherein in each of the storage elements, the write transistor and the read transistor are both threshold voltage tunable transistors. A dynamic memory search device as described in claim 1, wherein in each of the storage elements, one of the write transistor and the read transistor is a threshold voltage tunable transistor. A dynamic memory in-body search device as described in claim 1, wherein one of the read transistors and one of the search transistors are connected in series between the matching line and a ground terminal. An operation method of a dynamic memory search device, wherein the dynamic memory search device includes at least one word line, at least two bit lines, at least one matching line, at least one unit memory cell and two search transistors, the unit memory cell includes two storage elements and two search transistors, each of the storage elements includes a write transistor and a read transistor, the write transistor is connected to the word line and the bit lines. One of the bit lines, the read transistor is connected to the write transistor, one end of each read transistor is connected to the sensing unit through the matching line, and the operation method includes: writing a storage data to the unit memory cell; precharging the matching line; inputting a search data to the search lines; and sensing a voltage of the matching line to determine whether the search data matches the storage data. The method for operating a dynamic memory search device as described in claim 7, wherein each storage element includes a storage node, each storage node is located between each write transistor and each read transistor, and in the step of writing the storage data into the unit memory cell, one bit of the storage data is stored in the storage nodes. The method for operating a dynamic memory search device as described in claim 7, wherein in the step of writing the storage data into the unit memory cell, the storage data is written into the storage nodes by turning on the write transistors. The method for operating a dynamic memory in-body search device as described in claim 7, wherein in the step of sensing the voltage of the match line, when the voltage of the match line is maintained, it is determined that the search data matches the stored data.

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