JP2009038099A - Semiconductor device - Google Patents

Abstract

A main object of the present invention is to provide a semiconductor device provided with a highly reliable resistance element in which an insulating film underlying a resistance layer is protected from electrostatic breakdown.
An N type epitaxial layer is formed on a surface of a semiconductor substrate. A semiconductor substrate 1 is formed with a P + isolation layer 3 for isolating the epitaxial layer 2 into a plurality of element regions. A polysilicon resistance layer 5 is formed on the epitaxial layer 2 surrounded by the P + isolation layer 3 via an insulating film 4. An insulating film 6 is formed on the insulating film 4 so as to cover the polysilicon resistance layer 5. Contact holes 7 a and 7 b reaching the polysilicon resistance layer 5 are formed in the insulating film 6. Wiring layers 8a and 8b are formed in the contact holes 7a and 7b. A P + impurity layer 9 is formed on the surface of the epitaxial layer 2 in a part below the polysilicon resistance layer 5.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device provided with a resistance element.

  In a semiconductor integrated circuit, in order to prevent electrostatic breakdown (ESD) due to surge voltage such as static electricity, overvoltage and electromagnetic noise radiated from peripheral devices, a protection circuit (hereinafter referred to as static electricity) is placed near the input / output terminals. An electric breakdown protection circuit).

  A general electrostatic breakdown protection circuit will be described with reference to FIG. An internal circuit 100 is provided on a semiconductor substrate made of silicon or the like. The internal circuit 100 is an analog circuit or a digital circuit, and includes an input circuit, an output circuit, an input / output circuit, and the like. The wiring 102 connecting the internal circuit 100 and the input / output terminal 101 has a source connected to the ground wiring, a drain connected to the wiring 102, and a gate and source connected to a so-called diode-connected N-channel MOS transistor 103. And a MOS transistor type protection circuit 105 comprising a P channel type MOS transistor 104 having a source connected to the power supply wiring, a drain connected to the wiring 102, and a gate and a source diode connected. A ground voltage GND is supplied to the ground wiring, and a power supply voltage VDD is supplied to the power supply wiring. A protective resistor R is connected between the input / output terminal 101 and the internal circuit 100.

  As the protective resistance R, an element made of a polysilicon layer having a relatively high resistance value (hereinafter referred to as a polysilicon resistance layer) is used. A device structure of a conventional protective resistor R will be described with reference to a cross-sectional view of FIG.

  An N− type epitaxial layer 111 is formed on the surface of the P type semiconductor substrate 110. A P + isolation layer 112 for isolating the epitaxial layer 111 into a plurality of element regions is formed. The P + isolation layer 112 has a configuration in which an upper isolation layer 112a and a lower isolation layer 112b made of a P-type impurity are overlapped and integrated in the epitaxial layer 111.

  A polysilicon resistance layer 114 is formed on the epitaxial layer 111 surrounded by the P + isolation layer 112 via an insulating film 113 such as a silicon oxide film.

  An insulating film 115 such as a silicon nitride film is formed on the epitaxial layer 111 so as to cover the polysilicon resistance layer 114. Contact holes 116a and 116b reaching the polysilicon resistance layer 114 are formed in the insulating film 115, and wiring layers 117a and 117b made of aluminum or the like are formed in each contact hole. The wiring layer 117 a is connected to the input / output terminal 101, and the wiring layer 117 b is connected to the internal circuit 100.

  The operation of the electrostatic breakdown protection circuit shown in FIG. 3 will be briefly described. When an excessive surge voltage is applied through the input / output terminal 101, the N-channel MOS transistor 103 or the P-channel MOS transistor 104 breaks down and a current flows from the input / output terminal 101 to the power supply voltage VDD side or the ground voltage GND side. Flows. Moreover, the surge voltage to the internal circuit 100 side is suppressed by the protective resistance R.

In this way, the internal circuit 100 is protected from electrostatic breakdown. In addition, the technique relevant to this invention is described in the following patent documents, for example.
JP 59-104171 A

  With recent miniaturization and high integration of semiconductor devices, the occurrence of electrostatic breakdown tends to increase. In particular, an ESD application pulse in a CDM (Charged Device Model) is a very fast pulse with a rise time of about 1 ns, so that the protective resistance R before the protection circuit (the MOS transistor type protection circuit 105 in the above description) operates. There is a problem in that a pulse is directly applied to the insulating film 113 under the polysilicon resistance layer 114 and the internal circuit 100 is destroyed. CDM is a destruction model caused by charge transfer when a metal terminal of a semiconductor device comes into contact with a charged external metal (such as a package or a lead frame).

  SUMMARY OF THE INVENTION Accordingly, it is a main object of the present invention to provide a semiconductor device including a highly reliable resistance element that protects an insulating film underlying a resistance layer from electrostatic breakdown.

  The main features of the present invention are as follows. That is, the semiconductor device of the present invention is formed on the first conductive layer, the first insulating film formed on the first semiconductor layer, and the first insulating film. It is characterized by comprising a resistance layer and a second semiconductor layer of the second conductivity type formed on a part of the surface of the first semiconductor layer and below the resistance layer.

  The semiconductor device of the present invention has a configuration in which a reverse conductivity type semiconductor layer is formed on the surface of the semiconductor layer below the resistance layer, and more parasitic capacitances are connected in series than in the past. According to such a configuration, when an overvoltage is applied to the resistance layer, the overvoltage is shared by each parasitic capacitance, that is, the voltage applied to the insulating film below the resistance layer is relaxed. Therefore, the insulating film is hardly broken, and the ESD tolerance can be improved as compared with the conventional case.

  Next, a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1A is a plan view showing the semiconductor device according to the present embodiment, and FIG. 1B is a cross-sectional view along the line XX.

  An N type epitaxial layer 2 is formed on the surface of a P type semiconductor substrate 1. The epitaxial layer 2 is formed by a known epitaxial crystal growth method.

  In addition, a P + isolation layer 3 for separating the epitaxial layer 2 into a plurality of element regions is formed on the semiconductor substrate 1. The P + isolation layer 3 has a configuration in which an upper isolation layer 3a and a lower isolation layer 3b made of P-type impurities are overlapped and integrated in the epitaxial layer 2, and an annular shape surrounding the polysilicon resistance layer 5 Is formed. Upper isolation layer 3 a is formed by downwardly diffusing P-type impurities such as boron (B) from the upper surface of epitaxial layer 2. On the other hand, the lower separation layer 3 b is formed by upwardly diffusing P-type impurities such as boron (B) from the bottom side of the semiconductor substrate 1. Since adjacent elements are electrically isolated by the P + isolation layer 3, there are various elements (for example, a MOS transistor type protection circuit 105 as shown in FIG. An input / output terminal 101) may be formed. The P + separation layer 3 is connected to a ground wiring (not shown).

  An insulating film 4 (for example, a silicon oxide film by a thermal oxidation method or a CVD method) is formed on the epitaxial layer 2 surrounded by the P + isolation layer 3, and a polysilicon resistance layer 5 is formed through the insulating film 4. ing. The polysilicon resistance layer 5 is formed, for example, by depositing a polysilicon layer on the insulating film 4 by the CVD method and then etching the polysilicon layer into a predetermined pattern.

  An insulating film 6 (for example, a BPSG film or a silicon nitride film formed by a CVD method) is formed on the insulating film 4 so as to cover the polysilicon resistance layer 5. In the insulating film 6, a plurality (two in this embodiment) of contact holes 7a and 7b reaching the polysilicon resistance layer 5 are formed. In each contact hole 7a, 7b, wiring layers 8a, 8b made of a conductive layer such as aluminum or copper are formed.

  A P + impurity layer 9 is formed on the surface of the epitaxial layer 2 in a part below the polysilicon resistance layer 5. The P + impurity layer 9 is not connected to the wiring layer 8a or the wiring layer 8b and is in an electrically floating state. The P + impurity layer 9 is formed by partially injecting a P-type impurity such as boron (B) into the epitaxial layer 2 and thermally diffusing it. When an element such as a MOS transistor or a bipolar transistor is formed in another region, the P + impurity layer 9 may be formed simultaneously with ion implantation necessary for forming the element. P + impurity layer 9 is formed on the surface of epitaxial layer 2 and below contact hole 7a, and has a boundary between contact hole 7a and contact hole 7b. Thus, the P + impurity layer 9 of the present embodiment is formed below the region of the insulating film 4 where a surge voltage is likely to be strongly applied.

  In the configuration described above, as shown in FIG. 1B, a parasitic capacitance C1 having the insulating film 4 as a dielectric is generated between the polysilicon resistance layer 5 and the P + impurity layer 9, and the P + impurity layer 9, the epitaxial layer 2, and the like. A parasitic capacitance C2 is generated at the PN junction portion, and a parasitic capacitance C3 is generated at the PN junction portion between the epitaxial layer 2 and the bottom of the semiconductor substrate 1. Each parasitic capacitance (C 1, C 2, C 3) is connected in series between one terminal (wiring layer 8 a) of the polysilicon resistance layer 5 and the bottom of the semiconductor substrate 1.

  The capacitance value of the parasitic capacitance C1 is proportional to the dielectric constant and surface area of the insulating film 4 and inversely proportional to the thickness thereof. The capacitance value of the parasitic capacitance C2 is proportional to the surface area of the PN junction and the dielectric constant of the epitaxial layer 2, and inversely proportional to the thickness of the depletion layer. The capacitance value of the parasitic capacitance C3 is proportional to the surface area of the PN junction and the dielectric constant of the semiconductor substrate 1, and inversely proportional to the thickness of the depletion layer.

  Next, the operation when the semiconductor device configured as described above is used as the protective resistor R ′ will be described with reference to FIGS. 1A, 1B, and 3. The wiring layer 8a is connected to the input / output terminal 101 as shown in FIG. 3, and the wiring layer 8b is connected to the input stage of the internal circuit 100 (for example, the gate of each MOS transistor constituting the CMOS inverter).

  When an excessive surge voltage is applied to the input / output terminal 101 and is transmitted to the polysilicon resistance layer 5 via the wiring layer 8a, the voltage is concentrated particularly on the insulating film 4 below the contact hole 7a. become.

  Here, in the conventional semiconductor device (see FIG. 4), the parasitic capacitance Ca between the polysilicon resistance layer 114 and the epitaxial layer 111 and the parasitic capacitance Cb between the epitaxial layer 111 and the bottom of the semiconductor substrate 110 are connected in series. Have a connection. Therefore, when a surge voltage is applied from the input / output terminal 101 to the wiring layer 117a, the surge voltage is applied between the polysilicon resistance layer 114 and the bottom of the semiconductor substrate 110, but the parasitic capacitance Ca, Since Cb is connected in series, the surge voltage is shared by two capacitors (parasitic capacitances Ca and Cb).

  On the other hand, in this embodiment, the P + impurity layer 9 is formed. Therefore, the surge voltage applied from the input / output terminal 101 to the wiring layer 8a is shared by the three parasitic capacitances (C1, C2, C3). In other words, the voltage applied to the insulating film 4 is suppressed by the action of the parasitic capacitance C2 generated by the formation of the P + impurity layer 9 as compared with the conventional case. In addition, since the P + impurity layer 9 according to this embodiment is formed so as to cover a region of the insulating film 4 where a surge voltage is likely to be strongly applied, the effect of preventing the breakdown of the insulating film 4 is high.

  As described above, the semiconductor device of the present invention has a configuration in which several impurity layers of opposite conductivity types are stacked below the resistance layer, and the parasitic capacitance is connected in series between the resistance layer and the bottom of the semiconductor substrate. ing. According to such a configuration, since the voltage applied to the insulating film below the resistance layer is relaxed, the ESD tolerance can be improved as compared with the conventional case.

  Therefore, by connecting the above-described semiconductor device as the protective resistor R ′ between the input / output terminal 101 and the internal circuit 100 as shown in FIG. 3, particularly against a surge voltage having a fast rising speed as in the CDM mode. Therefore, it is possible to constitute an electrostatic breakdown protection circuit having a high ESD resistance and to protect the internal circuit. Although the MOS transistor type protection circuit 105 is formed in FIG. 3, a protection circuit may be formed using a diode.

  The present invention is not limited to the above-described embodiment, and can be modified without departing from the gist thereof. For example, as shown in FIG. 2, a configuration in which an N + impurity layer 10 is formed on the surface of the P + impurity layer 9 and a parasitic capacitance C4 connected in series can be further added can be adopted. According to such a configuration, the voltage applied to the insulating film 4 can be further reduced as compared with the above embodiment. Note that C1 ′ shown in FIG. 2 is a parasitic capacitance using the insulating film 4 between the polysilicon resistance layer 5 and the N + impurity layer 10 as a dielectric. In the case where an N-type semiconductor substrate is used, the configuration of the above embodiment may be configured with a reverse conductivity type. The present invention can be widely applied as a technique for preventing electrostatic breakdown of an insulating film formed below a resistance element.

1A and 1B are a plan view and a cross-sectional view illustrating a semiconductor device according to an embodiment of the invention. It is sectional drawing which shows the example of a change of the semiconductor device which concerns on embodiment of this invention. It is a circuit diagram which shows the electrostatic breakdown protection circuit which concerns on embodiment of this invention, and the conventional electrostatic breakdown protection circuit. It is sectional drawing explaining the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Epitaxial layer 3 P + isolation layer 3a Upper isolation layer 3b Lower isolation layer 4 Insulating film 5 Polysilicon resistance layer 6 Insulating film 7a, 7b Contact hole 8a, 8b Wiring layer 9 P + impurity layer 10 N + impurity layer 100 Internal circuit 101 I / O terminal 102 Wiring
103 N-channel MOS transistor
104 P-channel MOS transistor 105 MOS transistor-type protection circuit 110 Semiconductor substrate 111 Epitaxial layer 112 P + isolation layer 112a Upper isolation layer 112b Lower isolation layer 113 Insulating film 114 Polysilicon resistance layer 115 Insulating films 116a and 116b Contact holes
117a, 117b Wiring layer R, R 'Protection resistance C1, C1', C2, C3, C4, Ca, Cb Parasitic capacitance

Claims (4)

A first semiconductor layer of a first conductivity type;
A first insulating film formed on the first semiconductor layer;
A resistance layer formed on the first insulating film;
A semiconductor device comprising: a second semiconductor layer of a second conductivity type formed on a part of the surface of the first semiconductor layer and below the resistance layer. A second insulating film covering the resistance layer and having at least first and second contact holes reaching the resistance layer;
A first wiring layer formed in the first contact hole and connected to the resistance layer; and a second wiring layer formed in the second contact hole and connected to the resistance layer. ,
The second semiconductor layer is formed below the first contact hole,
The semiconductor device according to claim 1, wherein a boundary of the second semiconductor layer is located between the first contact hole and the second contact hole. 3. The semiconductor device according to claim 2, further comprising a third semiconductor layer of a first conductivity type on a surface of the second semiconductor layer below the first contact hole. An input / output terminal and an internal circuit connected to the input / output terminal;
4. The resistance layer is connected to the input / output terminal through the first wiring layer, and is connected to the internal circuit through the second wiring layer. A semiconductor device according to 1.

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