TW201943197A - Switching regulator and control circuit and control method thereof - Google Patents

Abstract

The present invention provides a switching regulator and a control circuit and a control method thereof. The switching regulator includes: a power stage circuit, which operates an upper switch and a lower switch therein according to an upper signal and a lower signal respectively, to convert an input voltage to an output voltage, and to generate an inductor current flowing through an inductor therein; and a control circuit, which includes an operation signal generation circuit and an adjustment signal generation circuit, wherein the adjustment signal generation circuit is configured to operably generate an adjustment level according to the upper signal, the lower signal, and/or the inductor current, wherein the adjustment level is switched between a reverse recovery level and an anti-latchup level, and is electrically connected to a lower switch isolation region of the lower switch. The reverse recovery level is lower than the input voltage. The anti-latchup level is higher than the reverse recovery level to prevent an latchup effect.

Description

Switching power supply circuit, control circuit and control method thereof

The invention relates to a switching power supply circuit, a control circuit and a control method thereof, and particularly to a switching power supply circuit, a control circuit and a control method thereof, which can prevent the interlocking effect of parasitic transistors and shorten the reverse recovery time. .

FIG. 1A shows a schematic circuit diagram of a typical switching power supply circuit 10. The switching power supply circuit 10 includes a control circuit 11 and a power stage circuit 12. Among them, the upper bridge switch 121 and the lower bridge switch 122 of the power stage circuit 12 are operated according to the upper bridge signal UG and the lower bridge signal LG, respectively, to convert the input voltage Vin into the output voltage Vout, and The inductor 123 of the stage circuit 12 generates an inductor current IL.

FIG. 1B shows a signal waveform diagram of the switching power supply circuit 10 when the load circuit 14 is lightly loaded. Among them, the so-called light load refers to a situation in which the power consumption is very small relative to the full load, that is, compared to the full load. Generally speaking, light load refers to a load ratio of 30% or less within the load range of the step-down switching power supply circuit 10. The so-called light load here refers to the situation where the inductor current IL oscillates up and down at the zero current level (0A).

As shown in Figure 1B, in order to ensure that the upper bridge switch 121 and the lower bridge switch 122 do not conduct at the same time, after the upper bridge signal UG is switched from the upper bridge high potential UGH to the upper bridge low potential UGL, the hysteresis before the lower bridge switch is turned on. During DT1, the low-side signal LG is switched from the low-side low potential LGL to the low-side high potential LGH. After the low-side signal LG is switched from the low-side high potential LGH to the low-side low potential LGL, the dead time period before the high-side switch is turned on is passed. DT2, the upper bridge signal UG is switched from the upper bridge low potential UGL to the upper bridge high potential UGH. It should be noted that the high-side switch 121 is coupled between the input voltage Vin and the phase node PH, and the low-side switch 122 is coupled between the phase node PH and the ground potential GND. Therefore, the high-side high potential UGH and the low-side high The potential of the potential LGH with respect to the ground potential GND is not the same; the potential of the upper bridge low potential UGL and the lower bridge low potential LGL with respect to the ground potential GND are also different.

Please continue to refer to FIG. 1B. Due to the continuity of the current flowing through the inductor, during the dead time period DT1 before the low-side switch is turned on, the low-side switch 122 is not turned on, but the parasitic diode LD is turned on, so the phase node PH The phase node voltage LX is lower than the forward voltage of the ground potential GND-parasitic diode LD; during the dead time DT2 before the upper-bridge switch is turned on, the upper-bridge switch 121 is not turned on, but the parasitic diode UD therein It is turned on, so the phase node voltage LX is higher than the forward voltage of the input voltage Vin-parasitic diode UD.

As shown in Figure 1B, when the high-side switch is in the dead time period DT2 before the inductor current IL is a negative current lower than zero current, it will cause a parasitic PNP transistor in the high-side circuit 121 and the low-side circuit 122 The parasitic NPN transistor is turned on. Because the PNP transistor and the NPN transistor are electrically connected to each other, an interlocking effect is caused, and the switching power supply circuit 10 is damaged.

In view of this, the present invention proposes a switching power supply circuit, a control circuit and a control method thereof that can prevent the parasitic transistor from interlocking and shorten the reverse recovery time.

In one aspect, the present invention provides a switching power supply circuit for converting an input voltage into an output voltage. The switching power supply circuit includes: a power stage circuit, which is based on an upper bridge signal and the following A bridge signal corresponding to operating one of the upper bridge switch and the lower bridge switch respectively to convert the input voltage to the output voltage and generate an inductive current in one of the inductors; and a control circuit coupled to the power stage circuit Including: a switching signal generating circuit coupled with the power stage circuit for generating the upper bridge signal and the lower bridge signal according to a command signal; and an adjustment signal generating circuit with the power stage circuit and the The switch signal generating circuit is coupled to provide an adjustment potential according to the upper bridge signal, the lower bridge signal or / and the inductor current, and the adjustment potential is electrically connected to a lower bridge switch isolation area of one of the lower bridge switches; The adjustment potential is switched between a reverse recovery potential and an anti-interlock potential; wherein the reverse recovery potential is lower than the input voltage; The lock potential is used to avoid an interlocking effect and is higher than the reverse recovery potential.

According to another aspect, the present invention provides a control circuit for a switching power supply circuit, wherein the switching power supply circuit is used to convert an input voltage to an output voltage, and includes: a power stage circuit. The bridge signal and the lower bridge signal respectively operate one of the upper bridge switch and the lower bridge switch to respectively convert the input voltage into the output voltage and generate an inductive current in one of the inductors; and the control circuit and the control circuit Including: a switch signal generating circuit coupled with the power stage circuit for generating the upper bridge signal and the lower bridge signal according to a command signal; and an adjustment signal generating circuit with the power stage circuit and the switch The signal generating circuit is coupled to provide an adjustment potential according to the upper bridge signal, the lower bridge signal or / and the inductor current, and the adjustment potential is electrically connected to a lower bridge switch isolation area of one of the lower bridge switches; wherein the The adjustment potential is switched between a reverse recovery potential and an anti-interlock potential; wherein the reverse recovery potential is lower than the input voltage; The interlocking potential is used to avoid an interlocking effect and is higher than the reverse recovery potential.

According to another aspect, the present invention provides a control method for a switching power supply circuit, including: generating an upper bridge signal and a lower bridge signal according to a command signal; and using the upper bridge signal and the lower bridge signal, respectively Operating one of the upper bridge switch and the lower bridge switch in a power stage circuit to convert an input voltage to an output voltage and generate an inductive current in one of the inductors; and according to the upper bridge signal, the lower bridge signal or / And the inductor current provides an adjustment potential, and the adjustment potential is electrically connected to a lower-bridge switch isolation area of the lower-bridge switch; wherein the adjustment potential is switched between a reverse recovery potential and an anti-interlock potential; The reverse recovery potential is lower than the input voltage; the anti-interlock potential is used to avoid an interlocking effect, and is higher than the reverse recovery potential.

In a preferred embodiment, the adjustment voltage is within a reverse recovery time after the lower bridge signal is switched from the lower voltage of the lower bridge to the high voltage of the lower bridge. The hysteresis period before the switch is turned on is the anti-interlock potential.

In a preferred embodiment, the adjustment signal generating circuit includes a logic circuit, and the logic circuit causes the adjustment potential to be inverted from the lower bridge signal according to the lower bridge signal.

In a preferred implementation form, the adjustment signal generating circuit includes a logic circuit, and the logic circuit is based on the upper bridge signal and the lower bridge signal, so that the adjustment circuit is located between the upper bridge signal and the upper dead period before the lower bridge switch is turned on. During the hysteresis period before the bridge switch is turned on, it is switched to the anti-interlock potential; and during other periods, it is switched to the reverse recovery potential.

In a preferred embodiment, the adjustment signal generating circuit includes a negative current clock generating circuit for generating a negative current clock signal according to the inductor current, wherein the negative current clock signal is in the inductor. When the current is negative, switch to a cognitive level; a judgment circuit is coupled to the negative current clock generating circuit to generate a judgment signal based on the negative current clock signal and a reference signal; and a switch A circuit is coupled to the judgment circuit, and is configured to switch the adjustment potential between the reverse recovery potential and the anti-interlock potential according to the judgment signal.

In the foregoing embodiment, the determination circuit includes: a low-pass filter coupled to the negative current clock generating circuit for generating a comparison signal according to the working ratio of the cognitive level; and a comparison circuit Is coupled to the low-pass filter to compare the comparison signal with the reference signal to generate the judgment signal.

In a preferred embodiment, the reverse recovery potential is a ground potential, and the anti-interlock potential is the input voltage or a phase voltage.

Detailed descriptions will be provided below through specific embodiments to make it easier to understand the purpose, technical content, features and effects of the present invention.

The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of the preferred embodiments with reference to the drawings. The drawings in the present invention are schematic, and are mainly intended to show the coupling relationship between the circuits, and the relationship between the circuits or the element layers. As for the shape, thickness, and width of the circuits and the element layers, they are not according to Drawn proportionally.

Please refer to FIGS. 2A-2C, which show a first embodiment of the present invention. FIG. 2A is a schematic circuit diagram of the switching power supply circuit 20. As shown in FIG. 2A, the switching power supply circuit 20 includes a control circuit 21 and a power stage circuit 22. Among them, the power stage circuit 22 operates the upper bridge switch 221 and the lower bridge switch 222 respectively according to the upper bridge signal UG and the lower bridge signal LG to convert the input voltage Vin into the output voltage Vout and generate the inductance 223 therein. The inductor current IL supplies power to the load circuit 14. The power stage circuit 22 includes, for example, but is not limited to, a step-down type power stage circuit as shown in FIG. 2A. In addition, the power stage circuit 22 may also include a synchronous or non-synchronous step-down type as shown in FIGS. 3A-3G, Step-up, back-pressure, buck-boost and step-up and back-pressure power stage circuits.

Please continue to refer to FIG. 2A, the control circuit 21 is coupled to the power stage circuit 22, and includes a switching signal generating circuit 211 and an adjusting signal generating circuit 213. The switching signal generating circuit 211 is coupled to the power stage circuit 22, and is configured to generate an upper bridge signal UG and a lower bridge signal LG according to a command signal COMM to operate the upper bridge switch 221 and the lower bridge switch 222, and then convert the input voltage Vin Is the output voltage Vout. The command signal COMM may be, for example, as shown in FIG. 2A, related to the output voltage Vout, or may be a preset target potential related to the output voltage Vout, or may be related to flowing through the upper bridge switch 221 or the lower bridge switch 222. Current, or the result of integrating the above parameters, etc., so that the switching signal generating circuit 211 can operate the upper bridge switch 221 and the lower bridge switch 222 to adjust the output voltage Vin or the output current Iout to a preset target level. .

The adjustment signal generation circuit 213 is coupled to the power stage circuit 22 and the switching signal generation circuit 211 to provide an adjustment potential ADJ according to the upper bridge signal UG, the lower bridge signal LG or / and the inductor current IL (such as the inductor current related signal ILX). , And the adjustment potential ADJ is electrically connected to the lower-bridge switch isolation region of the lower-bridge switch 222 (such as the N-type isolation well region NWI2 shown in FIG. 2C). The adjustment potential ADJ is switched between the reverse recovery potential and the anti-interlock potential. The reverse recovery potential is lower than the input voltage Vin. The anti-interlock potential is higher than the reverse recovery potential to prevent the parasitic transistor in the upper-bridge switch 221 and the lower-bridge switch 222 from generating an interlocking effect.

As shown in FIG. 2A and referring to the cross-sectional schematic diagram of the power stage circuit 22 shown in FIG. 2C, the upper bridge switch 221 includes a parasitic diode UD and a parasitic transistor UT in addition to the main switch UPT of the upper bridge. As shown in FIG. 2A and referring to the cross-sectional schematic diagram of the power stage circuit 22 shown in FIG. 2C, the lower-side switch 222 includes a parasitic diode LD and a parasitic transistor LT in addition to the lower-side main switch LPT. The parasitic transistor UT is a PNP transistor, and the parasitic transistor LT is an NPN transistor. The structure of the parasitic transistor is shown in FIG. 2C, and the circuit is shown in FIG. 2A.

Please continue to refer to FIG. 2A and also refer to FIG. 2B, where FIG. 2B shows the switching power supply when the load circuit 14 is lightly loaded or the inductor current IL oscillates up and down at the zero current level (0A). A schematic diagram of the signal waveform of the supply circuit 20.

As shown in Figure 2B, in order to ensure that the upper bridge switch 221 and the lower bridge switch 222 are not conducting at the same time, after the upper bridge signal UG is switched from the upper bridge high potential UGH to the upper bridge low potential UGL, the hysteresis before the lower bridge switch is turned on. During DT1, the low-side signal LG is switched from the low-side low potential LGL to the low-side high potential LGH. After the low-side signal LG is switched from the low-side high potential LGH to the low-side low potential LGL, the dead time period before the high-side switch is turned on is passed. DT2, the upper bridge signal UG is switched from the upper bridge low potential UGL to the upper bridge high potential UGH. It should be noted that the high-side switch 221 is coupled between the input voltage Vin and the phase node PH, and the low-side switch 222 is coupled between the phase node PH and the ground potential GND. Therefore, the high-side high potential UGH and the low-side high The potential of the potential LGH with respect to the ground potential GND is not the same; the potential of the upper bridge low potential UGL and the lower bridge low potential LGL with respect to the ground potential GND are also different.

Please continue to refer to FIG. 2B. Due to the continuity of the current flowing through the inductor, during the dead time period DT1 before the low-side switch is turned on, the low-side switch 122 is not turned on, but the parasitic diode LD is turned on, so the phase node PH The phase node voltage LX is lower than the forward voltage of the ground potential GND-parasitic diode LD; during the dead time DT2 before the upper-bridge switch is turned on, the upper-bridge switch 121 is not turned on, but the parasitic diode UD therein It is turned on, so the phase node voltage LX is higher than the forward voltage of the input voltage Vin-parasitic diode UD.

FIG. 2C shows a schematic cross-sectional view of the upper bridge switch 221 and the lower bridge switch 222. As shown in the figure, the upper bridge switch 221 and the lower bridge switch 222 are fully isolated lateral diffused devices, which belong to a high-voltage component. The upper bridge switch 221 and the lower bridge switch 222 are both N-type high-voltage components. The upper bridge switch 221 includes: P-type substrate PSUB, P-type substrate well area PWS1, N-type deep well area DNW1, N-type isolation well area NWI1, P-type deep well area DPW1, P-type isolation well area PWI1, and N-type high-pressure well area HVNW1 , P-type body region PBODY1, multiple insulation structures INS, drift oxidation region DOX, gate UGT, source USO, drain UDR, multiple P-type contacts PC, and multiple N-type contacts NC. The lower bridge switch 222 includes: P-type substrate PSUB, P-type substrate well area PWS2, N-type deep well area DNW2, N-type isolated well area NWI2, P-type deep well area DPW2, P-type isolated well area PWI2, and N-type high-pressure well area HVNW2 , P-type body region PBODY2, multiple insulation structures INS, drift oxidation region DOX, gate LGT, source LSO, drain LDR, multiple P-type contacts PC, and multiple N-type contacts NC. The upper bridge switch 221 and the lower bridge switch 222 are separated by an N-type isolation well area NWIS.

The so-called high-voltage component refers to that during normal operation, the voltage applied to the drain is higher than a specific voltage, such as 5V, and the P-type body region PBODY1 (PBODY2) and the drain UDR (LDR) are in an N-type high-pressure well. The lateral distance (drift region length) of the drift region in the region HVNW1 (HVNW2) is adjusted according to the operating voltage to which it is subjected during normal operation, so it can be operated at a higher specific voltage. This is well known to those with ordinary knowledge in the art and will not be described in detail here.

The P-type substrate PSUB includes a semiconductor substrate, such as but not limited to a P-type silicon substrate, or other P-type semiconductor substrates. The multiple insulation structures INS are used to electrically isolate different areas. The insulating structure INS is not limited to a shallow trench isolation (STI) structure as shown in FIG. 2C, and may also be a local oxidation of silicon (LOCOS) structure. The drift oxidation region DOX is formed on the drift region and is connected to the drift region. The drift oxidation region DOX is, for example but not limited to, a chemical vapor deposition (CVD) oxidation region as shown in FIG. 2C, and may also be a shallow trench isolation (STI) structure or a local oxidation (local oxidation). oxidation of silicon (LOCOS) structure.

The P-type substrate well region PWS1 (PWS2) has a P-type conductivity type and is formed on a semiconductor layer Sml on the P-type substrate PSUB. A method for forming the P-type substrate well region PWS1 (PWS2), for example, but not limited to, implanting P-type conductive impurities into the semiconductor layer Sml on the P-type substrate PSUB in the form of accelerated ions in an ion implantation process step ( It may be the same semiconductor substrate as the P-type substrate PSUB, or it may be an epitaxial layer formed on the P-type substrate PSUB, which is well known to those with ordinary knowledge in the art and will not be repeated here) to form a P-type Substrate well area PWS1 (PWS2). The P-type substrate well region PWS1 (PWS2) is electrically connected to the P-type substrate PSUB.

The N-type deep well area DNW1 (DNW2) is formed in the P-type substrate PSUB and is located directly below the N-type isolated well area NWI1 (NWI2), the P-type deep well area DPW1 (DPW2), and the P-type isolated well area PWI1 (PWI2). . A method for forming DNW1 (DNW2) in an N-type deep well region, such as, but not limited to, an N-type impurity implanted into a P-type substrate PSUB in the form of accelerated ions in an ion implantation process step to form an N-type deep well region DNW1 ( DNW2).

The N-type isolation well area NWI1 (NWI2) is formed in the semiconductor layer Sml on the P-type substrate PSUB. A method for forming the N-type isolation well area NWI1 (NWI2), for example, but not limited to, implanting N-type conductive impurities into the semiconductor layer Sml on the P-type substrate PSUB in the form of accelerated ions in an ion implantation process step, In the vertical direction, the N-type isolated well area NWI1 (NWI2) is located on the N-type deep well area DNW1 (DNW2), and is connected and electrically connected to the N-type deep well area DNW1 (DNW2), forming a closed one in the semiconductor layer Sml. Area, so that the P-type deep well area DPW1 (DPW2), the P-type isolated well area PWI1 (PWI2), the N-type high-pressure well area HVNW1 (HVNW2), and the P-type body area PBODY1 (PBODY2) are all in the closed area.

The P-type deep well region DPW1 (DPW2) is formed in the semiconductor layer Sml on the N-type deep well region DNW1 (DNW2), and is located directly below the N-type high-pressure well region HVNW1 and the P-type body region PBODY1. A method for forming DNW1 (DNW2) in a P-type deep well region, such as, but not limited to, an ion implantation process step in which P-type impurities are implanted into the semiconductor layer Sml in the form of accelerated ions to form a P-type deep well region DPW1 (DPW2 ).

The P-type isolated well region PWI1 (PWI2) is formed in the semiconductor layer Sml on the N-type deep well region DNW1 (DNW2). A method for forming a P-type isolated well region PWI1 (PWI2), such as, but not limited to, implanting a P-type conductive impurity in the form of accelerated ions into a semiconductor on an N-type deep well region DNW1 (DNW2) in an ion implantation process step. In the layer Sml, and vertically, the P-type isolated well area PWI1 (PWI2) is located on the N-type deep well area DNW1 (DNW2) and is connected to the N-type deep well area DNW1 (DNW2); in the horizontal direction, the P-type isolated well area PWI1 (PWI2) is connected and electrically connected to the P-type deep well area DPW1 (DPW2). In the semiconductor layer Sml, the P-type isolated well area PWI1 (PWI2) and the P-type deep well area DPW1 (DPW2) surround another closed area, so that the N-type high-pressure well area HVNW1 (HVNW2) and the P-type body area PBODY1 (PBODY2 ) Are all in the other enclosed area.

The body region PBODY1 (PBODY2) has a P-type conductivity type and is formed in the semiconductor layer Sml on the P-type deep well region DPW1 (DPW2). A method of forming the body region PBODY1 (PBODY2), for example, but not limited to, implanting P-type impurities into the semiconductor layer Sml in the form of accelerated ions in an ion implantation process step to form the body region PBODY1 (PBODY2). In the vertical direction, the body region PBODY1 (PBODY2) is located below the upper surface of the semiconductor layer Sml and is connected to the upper surface.

The N-type high-pressure well region HVNW1 (HVNW2) is formed in the semiconductor layer Sml on the P-type deep well region DPW1 (DPW2). A method for forming the HVNW1 (HVNW2) in the N-type high-pressure well region, for example, but not limited to, in an ion implantation process step, N-type impurities are implanted into the semiconductor layer Sml in the form of accelerated ions to form an N-type high-pressure well in the bulk region Zone HVNW1 (HVNW2). In the vertical direction, the N-type high-pressure well region HVNW1 (HVNW2) is located below the upper surface of the semiconductor layer Sml and is connected to the upper surface. The body region PBODY1 (PBODY2) is adjacent to the N-type high pressure well region HVNW1 (HVNW2) in the lateral direction.

The gate UGT (LGT) is formed on the upper surface of the semiconductor layer Sml. In the vertical direction, part of the body region PBODY1 (PBODY2) and at least part of the drift oxidation region DOX are located below the gate UGT (LGT) and connected to the gate. UGT (LGT). The gate UGT (LGT) includes at least a dielectric layer, a conductive layer, and a spacer layer. A dielectric layer is formed on the upper surface and connected to the upper surface, and the dielectric layer is connected to the body region PBODY1 (PBODY2) in a vertical direction. The conductive layer is used as an electrical contact of the gate UGT (LGT), and is formed on all dielectric layers and connected to the dielectric layers. The spacer layer is formed on both sides of the conductive layer to serve as electrical insulating layers on both sides of the gate UGT (LGT).

Please continue to refer to FIG. 2C. The source USO (LSO) and the drain UDR (LDR) have an N-type conductivity type. In the vertical direction, the source USO (LSO) and the drain UDR (LDR) are formed on the semiconductor layer Sml. Under the surface and connected to the upper surface, the source USO (LSO) and drain UDR (LDR) are respectively located in the body region PBODY1 (PBODY2) of the gate UGT (LGT) below the channel direction and away from the body region PBODY1 ( PBODY2) in the high-pressure well area HVNW1 (HVNW2). Among them, in the channel direction, the reversal area is located at the source USO (LSO) and the high-pressure well area HVNW1 (HVNW2), and is connected to the upper body area PBODY1 (PBODY2) for the upper bridge switch 221 (lower bridge switch 222) ) Reverse current channel in conducting operation. Among them, in the channel direction, the drift region is located between the drain UDR (LDR) and the body region PBODY1 (PBODY2), and is connected to the upper surface of the high-voltage well region HVNW1 (HVNW2), which is used as the upper bridge switch 221 (lower bridge switch) 222) A drift current channel in a conducting operation.

Please continue to refer to FIG. 2C. A plurality of P-type contact PCs are respectively formed in the P-type substrate well area PWS1 (PWS2), the P-type isolated well area PWI1 (PWI2), and the P-type body area PBODY1 (PBODY2) as each of the above. Electrical contacts in the P-type area. A plurality of N-type contacts NC are formed in the N-type isolated well area NWI1 (NWI2), the N-type high-pressure well area HVNW1 (HVNW2), and the N-type isolated annular well area NWIS to serve as the electrical contacts of the aforementioned N-type areas. . The N-type isolation well area NWIS is formed between the upper bridge switch 221 and the lower bridge switch 222 to separate the upper bridge switch 221 and the lower bridge switch 222.

It should be noted that the so-called reverse current channel means that the upper bridge switch 221 (lower bridge switch 222) has a reverse voltage under the gate UGT (LGT) due to the voltage applied to the gate UGT (LGT) during the conducting operation. The area where the inversion layer is passed to allow the on current to pass between the source USO (LSO) and the drift current channel. This is well known in the art and is not described in detail here. Other embodiments of the present invention And so on.

It should be noted that the so-called drift current channel refers to an area where the upper bridge switch 221 (lower bridge switch 222) passes the conduction current in a drift manner during the conduction operation. This area is well known to those with ordinary knowledge in the field and is not allowed here. To repeat.

One of the technical features of the present invention that is superior to the prior art is that according to the present invention, the parasitic diode LD in the lower bridge switch 222 is changed from the ON state to the non-conducting state within the reverse recovery time RT after the OFF state, such as the following Within the reverse recovery time RT after the bridge switch on-state hysteresis period DT1, the adjustment potential ADJ is switched to the reverse recovery potential ARR to shorten the reverse recovery time RT of the parasitic diode LD compared to the prior art; and The parasitic transistor UT in the high-side switch 221 and the parasitic transistor LT in the low-side switch 222 are turned on simultaneously, so that in the prior art, during a latchup effect, for example, hysteresis before the high-side switch is turned on During DT2, the adjustment potential ADJ is switched to the anti-interlock potential ALU to avoid the occurrence of an interlock effect.

During the dead time period DT1 before the low-side switch is turned on, the parasitic diode LD in the low-side switch 222 is turned on, and then the low-side signal LG is switched from the low-side low potential LGL to the low-side high potential LGH because the parasitic diode LD requires After a period of reverse recovery time (trr), RT will be completely non-conducting. In the reverse recovery time RT after the low-level signal LG is switched from the low-level low potential LGL to the low-level high potential LGH, the lower-bridge switch 222 lower-bridge switch isolation area (such as the N-type isolation well area shown in FIG. 2C) is reduced. NWI2) to the reverse recovery potential ARR, such as but not limited to the ground potential GND or the low-side low potential LGL, can shorten the reverse recovery time RT of the parasitic diode LD in the low-side switch 222 compared to the prior art.

Therefore, within the reverse recovery time RT after the low-side signal LG is switched from the low-side low potential LGL to the low-side high potential LGH, the adjustment signal generation circuit 213 switches the adjustment potential ADJ to a reverse recovery potential ARR that is lower than the input voltage Vin And electrically connect the adjustment potential ADJ (reverse recovery potential ARR) to the lower-bridge switch 222 lower-bridge switch isolation area (N-type isolation well area NWI2 shown in Figure 2C), which can shorten the reaction time compared to the prior art. Reverse recovery time (trr) RT. Generally speaking, as long as the reverse recovery potential ARR is lower than the input voltage Vin, it will help shorten the reverse recovery time RT. For example, the reverse recovery potential can be ground potential GND, low-side low potential LGL, or other preset low The potential of the input voltage Vin.

The reverse recovery time RT refers to the time it takes for a diode (for example, a parasitic diode LD) to go from the conducting state to being completely non-conducting. Generally speaking, the diode cannot be completely turned off immediately after the diode is turned on, and a certain amount of reverse current will still flow. The larger the reverse current is, the larger the power loss will be and increase the reaction time, which will affect the switching efficiency of the lower-bridge switch 222. Therefore, in order to shorten the reverse recovery time RT of the lower-side switch 222 compared to the prior art, the present invention is, for example, within the reverse recovery time RT after the lower-side signal LG is switched from the lower-side low potential LGL to the lower-side high potential LGH. , Make the adjustment potential ADJ be the reverse recovery potential ARR lower than the input voltage Vin, and electrically connect the adjustment potential ADJ to the lower-bridge switch 222 lower-bridge switch isolation area (as shown in Figure 2C, N-type isolation well area NWI2 ) To shorten the reverse recovery time RT compared to the prior art. In a preferred embodiment, the reverse recovery potential ARR is, for example, but not limited to, a ground potential GND or a low-side low potential LGL.

On the other hand, when the inductor current IL is lower than zero current and the parasitic diode UD in the high-side switch 121 is turned on, for example, during the dead time period DT2 before the high-side switch is turned on, as shown in FIG. 2B, the low-side If the emitter potential of the parasitic transistor LT in the switch 222 is electrically connected to the ground potential GND or the low-side low potential LGL, the parasitic transistor UT in the high-side switch 221 and the The parasitic transistor LT is turned on at the same time, and a latchup effect occurs, which damages the power electrode circuit 22. In order to avoid the above-mentioned interlocking effect, the adjustment signal generation circuit 213 makes the adjustment potential ADJ an anti-interlock potential ALU during the dead time period before the upper-bridge switch is turned on, and electrically connects the adjustment potential ADJ to the lower-bridge switch 222 and isolates the lower-bridge switch. Area (such as the N-type isolated well area NWI2 shown in FIG. 2C), in which the anti-interlock potential ALU is higher than the aforementioned reverse recovery potential ARR. In a preferred embodiment, the anti-interlock potential ALU is, for example, but not limited to, a low-side high potential LGH, a high-side high potential UGH, an input voltage Vin, or a phase voltage LX. The anti-interlock potential ALU is used to prevent the parasitic transistor LT in the lower-side switch 222 from being turned on, thereby avoiding an interlock effect.

In a word, the adjustment signal generating circuit 213 switches the adjustment potential ADJ to the reverse recovery potential ARR and the anti-interlock potential ALU at an appropriate time. The reverse recovery potential ARR is lower than the input voltage Vin and the reverse interlock potential is higher than the reverse recovery potential. The reverse interlock potential is used to prevent the parasitic transistor in the upper bridge switch 221 and the lower bridge switch 222 from generating an interlock effect. That is, as long as the interlocking effect can be avoided and is higher than the reverse recovery potential, it can be used as the anti-interlock potential.

Figures 4A-4C show a second embodiment of the present invention. This embodiment shows a more specific implementation of the adjustment signal generating circuit 213. As shown in FIG. 4A, the adjustment signal generating circuit 213 includes, for example, but is not limited to, a logic circuit that makes the adjustment potential ADJ inverse to the lower bridge signal LG according to the lower bridge signal LG. As shown in FIG. 4A, the logic circuit includes, for example, an inverse logic gate NOT1, which receives the lower-side signal LG and generates an adjustment potential ADJ which is inverse to the lower-side signal LG. As shown in FIG. 4B, the adjustment potential ADJ is the reverse phase of the lower bridge signal LG, and the reverse recovery time RT after the dead time period DT1 before the lower bridge switch is turned on can be obtained. The embodiment is to adjust the low potential ADL) to shorten the reverse recovery time RT of the parasitic diode LD compared to the prior art; and during the dead time period DT2 before the on-bridge switch is turned on, the adjustment potential ADJ is an anti-interlock potential ( In this embodiment, the high potential ADH is adjusted to avoid interlocking effects. The adjusted low potential ADL is lower than the input voltage Vin, and the adjusted high potential ADH is higher than the adjusted low potential ADL.

It should be noted that the so-called reverse phase means that the current signal LG is at the high potential LGH of the lower bridge, and the adjustment potential ADJ is the adjusted low potential ADL, which is a relatively low potential, and its potential level is not necessarily lower than that of the lower bridge. The potential LGL is the same, and it only needs to be low enough to shorten the reverse recovery time RT compared to the prior art. For example, the potential LGL may be the ground potential GND or the low-side low potential LGL. When the low-level signal LG is at the low-level low potential LGL, the adjustment potential ADJ is to adjust the high-level ADH, and it is a relatively high potential. The potential level does not have to be the same as the high-level potential LGH of the low-level, it only needs to be high enough to avoid interlocking effects. That is, it may be, for example, the lower-side high potential LGH, the upper-side high potential UGH, the input voltage Vin, or the phase voltage LX.

FIG. 4C shows a schematic cross-sectional view of the upper bridge switch 221 and the lower bridge switch 222. As shown in the figure, the adjustment potential ADJ is the reverse signal of the lower-side signal LG, and the adjustment potential ADJ is electrically connected to the lower-bridge switch isolation area of the lower-bridge switch 222 (such as the N-type isolation well area NWI2 shown in FIG. 4C) .

Figures 5A-5B show a third embodiment of the present invention. This embodiment shows another specific implementation of the adjustment signal generating circuit 213. As shown in FIG. 5A, the adjustment signal generating circuit 213 includes, for example, but is not limited to, a logic circuit that adjusts the potential ADJ during the dead time period DT1 and DT1 before the lower switch is turned on according to the upper bridge signal UG and the lower bridge signal LG. During the hysteresis period DT2 before the upper-bridge switch is turned on, it switches to the anti-interlock potential ALU; and during other periods, it switches to the reverse recovery potential ARR.

As shown in FIG. 5A, the adjustment signal generating circuit 213 includes, for example, NOT logic gate NOT2, NOT logic gate NOT4, NAND logic gate NAND2, and NOT logic gate NOT6. As shown in the figure, the NOT logic gates NOT2 and NOT4 respectively receive the upper bridge signal UG and the lower bridge signal LG, and perform logical NOT operations on the upper bridge signal UG and the lower bridge signal LG, respectively, and input the result to the NAND logic gate NAND2. The NAND logic gate NAND2 performs a logical NAND operation on the above two NOT logical operation results, and generates a logical operation result NNA. The NOT logic gate NOT6 performs a logic NOT operation on the logic operation result NNA, and generates an adjustment potential ADJ, as shown in the signal waveform diagram in FIG. 5B.

It should be noted that this embodiment is one of the implementations of the adjustment signal generating circuit 213, so that the adjustment potential ADJ is switched to the anti-interlock during the dead time period DT1 before the lower-bridge switch is turned on and the dead time period DT2 before the upper-bridge switch is turned on. The potential ALU is switched to the reverse recovery potential ARR during periods other than the period DT1 before the lower-bridge switch is turned on and the period DT2 before the high-bridge switch is turned on. Among them, the anti-interlock potential ALU is relatively higher than the reverse recovery potential ARR, and the upper bridge signal UG, the lower bridge signal LG, the anti-interlock potential ALU and the reverse recovery potential ARR are all relative potentials. For example, a displacement circuit ( level shifter circuit) After adjusting the upper bridge signal UG or the lower bridge signal LG, perform logical operations. As long as the reverse recovery potential ARR is lower than the input voltage, for example, it can be the ground potential GND or the low-side low potential LGL, it has the effect of shortening the reverse recovery time; the anti-interlock potential ALU, such as but not limited to the low-side high potential LGH, High-side UGH, input voltage Vin, or phase voltage LX. The anti-interlocking potential ALU is used to prevent the parasitic transistor LT in the lower-bridge switch 222 from being turned on, thereby preventing the parasitic transistor LT and UT from generating an interlocking effect.

Figures 6A-6B show a fourth embodiment of the present invention. This embodiment shows another specific implementation of the adjustment signal generating circuit 213. As shown in FIG. 6A, the adjustment signal generating circuit 213 includes, for example, but is not limited to, a logic circuit, which is similar to the logic circuit shown in FIG. 5A. Compared with the embodiment shown in FIG. 5A, this embodiment The logic circuit further includes a flip-flop circuit FF. The flip-flop circuit FF in this embodiment inputs the adjustment potential in the third embodiment (referred to as the front adjustment potential ADJ 'in this embodiment) to the flip-flop circuit FF. According to the adjustment potential ADJ ′, the hysteresis period DT2 before the upper-bridge switch is turned on is switched to the anti-interlock potential ALU; and in other periods, the hysteresis period DT1 before the lower-bridge switch is turned on is switched to the reverse recovery potential ARR. Adjust the potential ADJ as shown in the signal waveform diagram in Figure 6B.

Figures 7A-7C show a fifth embodiment of the present invention. This embodiment shows another specific implementation of the adjustment signal generating circuit 213. As shown in FIG. 7A, the adjustment signal generating circuit 213 includes, but is not limited to, a negative current clock generating circuit 2131, a determining circuit 2133, and a switching circuit 2135. Please also refer to FIGS. 7A-7C. The negative current clock generating circuit 2131 is used to generate a negative current clock signal NCC according to the inductor current IL. The negative current clock signal NCC switches to the cognition when the inductor current IL is a negative current. Level ACK. The judgment circuit 2133 is coupled to the negative current clock generating circuit 2131, and is configured to generate a judgment signal DTM according to the negative current clock signal NCC and the reference signal Vreft. The switching circuit 2135 is coupled to the judgment circuit 2133, and is configured to switch the adjustment potential ADJ to the reverse recovery potential ARR and the anti-interlock potential ALU according to the determination signal DTM.

In this embodiment, the negative current clock generating circuit 2131 switches the negative current clock signal NCC to the cognitive level ACK according to the inductor current IL, for example, when the inductor current IL is a negative current, and the inductor current IL is a positive current. , The negative current clock signal NCC is switched to a relatively low level LCK. When the inductor current IL is switched up and down at zero current, the negative current clock signal NCC accordingly switches between the cognitive level ACK and the relatively low level LCK. The judging circuit 2133 includes, for example but not limited to, a comparison circuit CMP as shown in the figure, which can compare the negative current clock signal NCC and the reference Vref, and generate a judging signal DTM according to the comparison result, and then adjust the adjustment potential ADJ to the inductor current IL as When the current is negative, the adjustment potential ADJ is switched to the anti-interlock potential ALU, and when the inductor current IL is a positive current, the adjustment potential ADJ is switched to the reverse recovery potential ARR.

Figures 8A-8B show a sixth embodiment of the present invention. This embodiment shows another specific implementation of the judgment circuit 2133. As shown in FIG. 8A, the determination circuit 2133 includes a low-pass filter LPF and a comparison circuit CMP. The low-pass filter LPF is coupled to the negative current clock generating circuit 2131 to generate a comparison signal according to the duty ratio of the cognitive level ACK. The comparison circuit CMP is coupled to the low-pass filter LPF, and is used to compare the comparison signal with the reference signal Vref to generate a judgment signal DTM. For example, as shown in FIG. 8B, when the inductor current IL oscillates up and down near a zero current, the negative current clock generating circuit 2131 generates a negative current clock signal NCC according to the inductor current IL, and ACKs and a relatively low level at the cognitive level. Switch between quasi-LCK. The low-pass filter LPF processes the NCC low-pass filtering of the negative current clock signal, and generates a DC comparison signal. For example, when the working ratio of the cognitive level ACK is higher than a preset ratio, the comparison signal of DC will be higher than the reference signal Vref, so that the determination signal DTM is, for example, but not limited to, a high level, and then the adjustment potential ADJ is switched. The anti-interlock potential ALU. That is, in this embodiment, when the ratio of the inductor current IL to the negative current is higher than a preset high ratio, the adjustment potential ADJ is switched to the anti-interlock potential ALU, and the positive current of the inductor current IL is not low. At the preset high ratio, the adjustment potential ADJ is switched to the reverse recovery potential ARR.

This embodiment is intended to illustrate that according to the present invention, it is not only based on the reverse recovery time RT after the parasitic diode LD in the lower bridge switch 222 changes from the ON state to the non-conducting state OFF, for example, before the lower bridge switch is turned on. Within the reverse recovery time RT after the dead time DT1, the adjustment potential ADJ must be immediately switched to the reverse recovery potential ARR; and during the dead time DT2 before the high-side switch is turned on, the adjustment potential ADJ must be immediately switched to the reverse recovery potential ARR. Interlocking potential ALU. Instead, adaptively decide to switch the adjustment potential ADJ between the reverse recovery potential ARR and the anti-interlock potential ALU according to the time proportion of the inductor current IL being a negative current.

The present invention has been described above with reference to the preferred embodiments, but the above is only for making those skilled in the art easily understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. The described embodiments are not limited to separate applications, and can also be combined. For example, two or more embodiments can be used in combination, and part of the composition of one embodiment can also be used instead of the other embodiment. Corresponding components. In addition, in the same spirit of the present invention, those skilled in the art can consider various equivalent changes and various combinations. For example, the logic circuit in the foregoing embodiment is not limited to the inverse logic gate and NAND logic gate shown. It can also be replaced by other logic gates, as long as the same logic operation result can be achieved. The term "processing or calculation or generating an output result according to a signal" in the present invention is not limited to the signal itself, but also includes performing voltage-current conversion, current-voltage conversion, and / or ratio conversion on the signal when necessary. Wait, then process or calculate according to the converted signal to produce an output result. In the same spirit of the invention, those skilled in the art can think of various equivalent changes. For example, without affecting the main characteristics of the device, other process steps or structures can be added, such as a threshold voltage adjustment region. All these can be deduced by analogy according to the teachings of the present invention. Therefore, the scope of the invention should cover the above and all other equivalent variations. In addition, any embodiment of the present invention does not have to achieve all the objectives or advantages. Therefore, any one of the scope of the claimed patent should not be limited to this.

10,20‧‧‧Switching power supply circuit

11,21‧‧‧Control circuit

211‧‧‧Switch signal generating circuit

213‧‧‧Adjust the signal generating circuit

12,22‧‧‧Power stage circuit

121,221‧‧‧High bridge switch

122,222‧‧‧Low-bridge switch

123,223‧‧‧Inductance

14‧‧‧Load circuit

2131‧‧‧ Negative current clock generating circuit

2133‧‧‧Judgment circuit

2135‧‧‧Switch circuit

ACK‧‧‧ Cognitive Level

ADJ, ADJ’‧‧‧‧adjust the potential

ADH‧‧‧Adjust high potential

ADL‧‧‧Adjust low potential

ALU‧‧‧Anti-interlocking potential

ARR‧‧‧Reverse Recovery Potential

COMM‧‧‧Command signal

CMP‧‧‧Comparison circuit

DNW1, DNW2‧‧‧N deep well area

DPW1, DPW2‧‧‧P deep well area

DOX‧‧‧ drift oxidation zone

DT1‧‧‧Hysteresis before the lower-bridge switch is turned on

DT2‧‧‧Hysteresis before the upper-bridge switch is turned on

DTM‧‧‧ Judgment Signal

FF‧‧‧ Flip-Flop Circuit

GND‧‧‧ ground potential

HVNW1, HVNW2‧‧‧N type high pressure well area

IL‧‧‧Inductive current

ILX‧‧‧Inductor current related signals

INS‧‧‧Insulation Structure

Iout‧‧‧Output current

LCK‧‧‧ relatively low level

LD, UD‧‧‧‧parasitic diode

LDR, UDR‧‧‧Drain

LG‧‧‧ Lower Bridge Signal

LGH‧‧‧Underside high potential

LGL‧‧‧Lower potential

LGT, UGT‧‧‧Gate

LPF‧‧‧Low-pass filter

LPT‧‧‧Under the main switch

LSISO‧‧‧Low-side switch isolation area

LSO, USO‧‧‧Source

LT, UT‧‧‧‧parasitic transistor

LX‧‧‧node voltage

NAND2‧‧‧NAND logic gate

NC‧‧‧N type contact

NCC‧‧‧Negative current clock signal

NNA‧‧‧Logic operation result

NOT1,2,4,6‧‧‧‧Inverse logic gate

NWI1, NWI2‧‧‧N type isolated well area

NWIS‧‧‧N-type isolation well area

PBODY1, PBODY2‧‧‧P type body area

PC‧‧‧P type contact

PH‧‧‧phase node

Psub‧‧‧ substrate

PSUB‧‧‧P type substrate

PWI1, PWI2‧‧‧P type isolated well area

PWS1, PWS2‧‧‧P-type substrate well area

RT‧‧‧ Reverse Recovery Time

Sml‧‧‧Semiconductor layer

UG‧‧‧Stop signal

UGH‧‧‧High potential on the bridge

UGL‧‧‧Low potential on the bridge

UPT‧‧‧Main bridge switch

Vin‧‧‧ input voltage

Vout‧‧‧Output voltage

Vref‧‧‧Reference signal

1A and 1B show a schematic circuit diagram and a signal waveform diagram of a switching power supply circuit 10 of the prior art, respectively. Figures 2A-2C show a first embodiment of the present invention. Figures 3A-3G show synchronous or non-synchronous step-down, step-up, step-down, step-up and step-down and step-up and step-down power stage circuits. Figures 4A-4C show a second embodiment of the present invention. Figures 5A-5B show a third embodiment of the present invention. Figures 6A-6B show a fourth embodiment of the present invention. Figures 7A-7C show five embodiments of the present invention. Figures 8A-8B show a sixth embodiment of the present invention.

Claims (21)

A switching power supply circuit is used to convert an input voltage into an output voltage. The switching power supply circuit includes: a power stage circuit, which respectively operates one of the upper bridges according to an upper bridge signal and a lower bridge signal. A switch and a lower bridge switch to convert the input voltage to the output voltage and generate an inductive current in one of the inductors; and a control circuit coupled to the power stage circuit, including: a switching signal generating circuit, and The power stage circuit is coupled to generate the upper bridge signal and the lower bridge signal according to a command signal; and an adjustment signal generating circuit is coupled to the power stage circuit and the switching signal generating circuit for The upper bridge signal, the lower bridge signal or / and the inductor current provide an adjustment potential, and the adjustment potential is electrically connected to a lower bridge switch isolation region of one of the lower bridge switches; wherein the adjustment potential is switched to a reverse recovery potential And an anti-interlock potential; wherein the reverse recovery potential is lower than the input voltage; wherein the anti-interlock potential is used to avoid an Effect, and higher than the reverse recovery potential. The switching power supply circuit according to item 1 of the scope of patent application, wherein the adjusting power is within a period of reverse recovery time after the lower bridge signal is switched from the lower voltage of the lower bridge to the high voltage of the lower bridge, and the reverse recovery is Potential, and is the anti-interlock potential during the hysteresis period before an upper-bridge switch is turned on. The switching power supply circuit according to item 2 of the scope of patent application, wherein the adjustment signal generating circuit includes a logic circuit, and the logic circuit causes the adjustment potential to be inverted from the lower bridge signal according to the lower bridge signal. The switching power supply circuit according to item 2 of the scope of the patent application, wherein the adjustment signal generating circuit includes a logic circuit, and the logic circuit makes the adjustment circuit be turned on according to the upper bridge signal and the lower bridge signal. The front hysteresis period and the front hysteresis period during which the upper-bridge switch is turned on are switched to the anti-interlock potential; and in other periods, they are switched to the reverse recovery potential. The switching power supply circuit according to item 1 of the patent application scope, wherein the adjustment signal generating circuit includes: a negative current clock generating circuit for generating a negative current clock signal according to the inductor current, wherein the negative The current clock signal is switched to a cognitive level when the inductor current is a negative current; a judging circuit is coupled to the negative current clock generating circuit to generate a signal based on the negative current clock signal and a reference signal; A judgment signal; and a switching circuit coupled to the judgment circuit for switching the adjustment potential between the reverse recovery potential and the anti-interlock potential based on the judgment signal. The switching power supply circuit according to item 5 of the scope of patent application, wherein the judgment circuit includes: a low-pass filter coupled to the negative current clock generating circuit for operating ratio according to the cognitive level, Generating a comparison signal; and a comparison circuit coupled to the low-pass filter for comparing the comparison signal with the reference signal to generate the judgment signal. The switching power supply circuit according to item 1 of the scope of patent application, wherein the reverse recovery potential is a ground potential or a lower bridge low potential, and the anti-interlock potential is a lower bridge high potential, an upper bridge high potential, The input voltage or a phase voltage. A control circuit for a switching power supply circuit, wherein the switching power supply circuit is used to convert an input voltage into an output voltage, and includes: a power stage circuit, which operates correspondingly according to an upper bridge signal and a lower bridge signal, respectively. One of the upper bridge switch and the lower bridge switch converts the input voltage to the output voltage and generates an inductive current in one of the inductors; and the control circuit, the control circuit includes: a switching signal generating circuit, and the The power stage circuit is coupled to generate the upper bridge signal and the lower bridge signal according to a command signal; and an adjustment signal generating circuit is coupled to the power stage circuit and the switching signal generating circuit for The upper bridge signal, the lower bridge signal or / and the inductor current provide an adjustment potential, and the adjustment potential is electrically connected to a lower bridge switch isolation region of one of the lower bridge switches; wherein the adjustment potential is switched between a reverse recovery potential and Between an anti-interlock potential; wherein the reverse recovery potential is lower than the input voltage; wherein the anti-interlock potential is used to avoid Locking effect, and higher than the reverse recovery potential. According to the control circuit of the switching power supply circuit described in item 8 of the scope of patent application, wherein the adjusting power is within a period of reverse recovery time after the lower bridge signal is switched from the lower voltage of the lower bridge to the high voltage of the lower bridge, The reverse recovery potential is the anti-interlock potential during the hysteresis period before an upper-bridge switch is turned on. The control circuit of the switching power supply circuit according to item 9 of the scope of the patent application, wherein the adjustment signal generating circuit includes a logic circuit, and the logic circuit makes the adjustment potential inverse to the lower bridge signal according to the lower bridge signal. . According to the control circuit of the switching power supply circuit described in item 9 of the scope of the patent application, wherein the adjustment signal generating circuit includes a logic circuit, the logic circuit makes the adjustment circuit be located according to the upper bridge signal and the lower bridge signal. The hysteresis period before the bridge switch is turned on and the hysteresis period before the on-bridge switch is switched to the anti-interlock potential; and in other periods, it is switched to the reverse recovery potential. According to the control circuit of the switching power supply circuit described in item 8 of the scope of patent application, wherein the adjustment signal generating circuit includes: a negative current clock generating circuit for generating a negative current clock signal according to the inductor current, The negative current clock signal is switched to a cognitive level when the inductor current is a negative current; a judgment circuit is coupled to the negative current clock generating circuit for using the negative current clock signal and a reference A signal to generate a judgment signal; and a switching circuit coupled to the judgment circuit for switching the adjustment potential between the reverse recovery potential and the anti-interlock potential based on the judgment signal. The control circuit of the switching power supply circuit according to item 12 of the patent application scope, wherein the judging circuit includes: a low-pass filter coupled to the negative current clock generating circuit for controlling the The working ratio generates a comparison signal; and a comparison circuit is coupled to the low-pass filter to compare the comparison signal with the reference signal to generate the judgment signal. The control circuit of the switching power supply circuit according to item 8 of the scope of the patent application, wherein the reverse recovery potential is a ground potential or a lower bridge low potential, and the anti-interlock potential is a lower bridge high potential and an upper bridge High potential, the input voltage, or a phase voltage. A control method for a switching power supply circuit includes: generating an upper bridge signal and a lower bridge signal according to a command signal; and using the upper bridge signal and the lower bridge signal to respectively operate an upper bridge in a power stage circuit. A switch and a lower bridge switch to convert an input voltage to an output voltage and generate an inductor current in one of the inductors; and provide an adjustment potential based on the upper bridge signal, the lower bridge signal or / and the inductor current And the adjustment potential is electrically connected to an isolation region of a lower bridge switch of the lower bridge switch; wherein the adjustment potential is switched between a reverse recovery potential and an anti-interlock potential; wherein the reverse recovery potential is lower than the input voltage Where the anti-interlock potential is used to avoid an interlock effect, and is higher than the reverse recovery potential. The control method of the switching power supply circuit according to item 15 of the scope of the patent application, wherein the adjusting power is within a period of reverse recovery time after the lower bridge signal is switched from the lower voltage of the lower bridge to the high voltage of the lower bridge. The reverse recovery potential is the anti-interlock potential during the hysteresis period before an upper-bridge switch is turned on. The control method of the switching power supply circuit according to item 16 of the scope of patent application, wherein the step of generating the adjustment potential includes using a logic circuit to make the adjustment potential inverse to the signal of the lower bridge according to the signal of the lower bridge. . According to the control method of the switching power supply circuit according to item 16 of the scope of patent application, wherein the step of generating the adjustment potential includes using a logic circuit to make the adjustment power at a lower level according to the upper bridge signal and the lower bridge signal. The hysteresis period before the bridge switch is turned on and the hysteresis period before the on-bridge switch is switched to the anti-interlock potential; and in other periods, it is switched to the reverse recovery potential. According to the control method of the switching power supply circuit according to item 15 of the scope of patent application, wherein the step of generating the adjustment potential includes: generating a negative current clock signal according to the inductor current, wherein the negative current clock signal is at When the inductor current is a negative current, switch to a cognitive level; generate a judgment signal based on the negative current clock signal and a reference signal; and switch the adjustment potential to the reverse recovery potential and based on the judgment signal This anti-interlock potential. According to the control method of the switching power supply circuit described in item 19 of the scope of patent application, wherein the step of generating the judgment signal based on the negative current clock signal and the reference signal includes: according to the working ratio of the cognitive level, Generating a comparison signal; and comparing the comparison signal with the reference signal to generate the judgment signal. The control method of the switching power supply circuit according to item 15 of the scope of the patent application, wherein the reverse recovery potential is a ground potential or a lower bridge low potential, and the anti-interlock potential is a lower bridge high potential and an upper bridge High potential, the input voltage, or a phase voltage.