TWI850100B - Semiconductor device - Google Patents

Abstract

A semiconductor device includes an epitaxial layer having a first conductivity type disposed on a substrate having the first conductivity type. A first well region having a second conductivity type is disposed in the epitaxial layer. A gate electrode is disposed on the first well region. A source contact region and a drain contact region both having the first conductivity type are disposed in the first well region and located on two sides of the gate electrode, respectively. A second well region having the first conductivity type is disposed in the epitaxial layer. The second well region laterally abuts the first well region and is in contact with a portion of the substrate. The second well region and the portion of the substrate construct a resistor, and the resistor is electrically coupled to a ground terminal. A heavily doped region having the first conductivity type is disposed in the second well region and electrically connected to the source contact region.

Description

Semiconductor devices

The present disclosure relates to a semiconductor device for a switching circuit, and in particular to a semiconductor device including a transistor and a resistor connected in series in an upper bridge driving circuit.

Metal-oxide semiconductor field effect transistor (MOSFET) is the most commonly used component in integrated circuits. It can be widely used as a power switching component in various power applications and power lines. For example, in a switching circuit (or bridge circuit) structure in which the switching components are connected in series, MOSFET components are respectively arranged on the upper bridge (high side) and the lower bridge (low side) as switching components, and the switching components of the upper bridge and the lower bridge are alternately turned on and off. In order to prevent the switching elements of the upper and lower bridges from being turned on at the same time and causing a short circuit, it is usually necessary to set up another level shifter to detect the potential signal of the upper bridge circuit and transmit this potential signal back to the lower bridge circuit. When the potential signal of the upper bridge circuit is detected to be erroneous, the lower bridge circuit can transmit a signal to turn off the upper bridge circuit. However, in the current switching circuit architecture, another level shifter needs to be set up, so it is not possible to effectively save the manufacturing cost of the integrated circuit and reduce the size of the chip.

In view of this, the present disclosure proposes a semiconductor device, which includes a transistor and a resistor connected in series in the upper bridge driving circuit to accurately detect the upper bridge potential signal between the upper bridge switching element and the lower bridge switching element to avoid the upper bridge and the lower bridge switching elements being turned on at the same time to cause a breakdown short circuit, and the aforementioned transistor and resistor can be manufactured using the existing structure of the upper bridge driving circuit, which will not increase the occupied area of the semiconductor device, which is conducive to reducing the manufacturing cost and reducing the size of the chip.

According to an embodiment of the present disclosure, a semiconductor device is provided, including a substrate, an epitaxial layer, a first well region, a gate, a source contact region, a drain contact region, a second well region, and a heavily doped region. The substrate has a first conductivity type, the epitaxial layer has the first conductivity type and is disposed on the substrate, the first well region has a second conductivity type and is disposed in the epitaxial layer, the gate is disposed on the first well region, the source contact region and the drain contact region both have the first conductivity type and are disposed in the first well region and are respectively located on both sides of the gate, the second well region has the first conductivity type and is disposed in the epitaxial layer, laterally adjacent to the first well region and in contact with a portion of the substrate, wherein the second well region and a portion of the aforementioned substrate constitute a resistor, and the resistor is electrically coupled to the ground terminal, the heavily doped region has the first conductivity type, is disposed in the second well region, and is electrically connected to the source contact region.

In order to make the features of this disclosure clear and easy to understand, the following is a detailed description of the embodiments with the help of the attached drawings.

100: Part of a switching circuit

200: Switching circuit

101: Upper bridge transistor

102: Lower bridge transistor

103: The third transistor

104: The third resistor

201: One-way switch element

202: Capacitor

203:Boost device

204: Control Logic

205: Level shift circuit

206: Bridge drive circuit

207: Lower bridge drive circuit

HS: upper bridge potential signal

VS: Supply voltage

VB: boost voltage

VIN: Input voltage

VF: floating reference voltage

S1: First signal

S2: Second signal

SET: Set signal

RST: Reset signal

SHO: upper bridge output signal

SLD: Lower bridge drive signal

SLO: Lower bridge output signal

300:Semiconductor devices

301: Base

301P: Part of the base

303: Epitaxial layer

303P, 303P-1, 303P-2: Part of the epitaxial layer

305: Fourth Well Area

307: The third well area

309: First Well Area

311: Second well area

313: Source contact area

315: Drain contact area

317: Remixed area

319: substrate contact area

320: Gate dielectric layer

321: Gate

322: Conductive layer

323: First mixed area

325: Second mixed area

330: Interlayer dielectric layer

331: Drain contact

332: Source contact

333, 336: Conductive hole

334: Drain electrode

335: Source electrode

340: Interconnection structure

S101, S103, S105, S107: Steps

In order to make the following easier to understand, the drawings and their detailed text descriptions can be referred to simultaneously when reading this disclosure. Through the specific embodiments in this article and reference to the corresponding drawings, the specific embodiments of this disclosure are explained in detail, and the working principles of the specific embodiments of this disclosure are explained. In addition, for the sake of clarity, the features in the drawings may not be drawn according to the actual scale, so the size of some features in some drawings may be deliberately enlarged or reduced.

FIG. 1 is a block diagram of a portion of a switching circuit according to an embodiment of the present disclosure.

Figure 2 is a block diagram of a switching circuit according to an embodiment of the present disclosure.

Figure 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

Figure 4 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure.

FIG. 5 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure.

FIG6 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure.

Figures 7, 8 and 9 are cross-sectional schematic diagrams of some stages of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

The present disclosure provides several different embodiments that can be used to implement different features of the present disclosure. For the purpose of simplifying the description, the present disclosure also describes examples of specific components and arrangements. The purpose of providing these embodiments is only for illustration and not for limitation. For example, the description below of "a first feature is formed on or above a second feature" may refer to "the first feature is in direct contact with the second feature" or "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact. In addition, various embodiments in the present disclosure may use repeated reference symbols and/or text annotations. These repeated reference symbols and annotations are used to make the description more concise and clear, rather than to indicate the relationship between different embodiments and/or configurations.

In addition, for the spatially related descriptive terms mentioned in this disclosure, such as "under", "low", "down", "above", "above", "up", "top", "bottom" and similar terms, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another (or multiple) elements or features in the drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientations of semiconductor devices during use and operation. With the different orientations of the semiconductor device (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.

Although the present disclosure uses the terms first, second, third, etc. to describe various elements, components, regions, layers, and/or sections, it should be understood that these elements, components, regions, layers, and/or sections should not be limited by these terms. These terms are only used to distinguish a certain element, component, region, layer, and/or section from another element, component, region, layer, and/or section, and they do not imply or represent any previous sequence of the element, nor do they represent the arrangement order of a certain element and another element, or the order of the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present disclosure, the first element, component, region, layer, or section discussed below can also be referred to as the second element, component, region, layer, or section.

The terms "about" or "substantially" mentioned in this disclosure generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of specific description of "about" or "substantially", the meaning of "about" or "substantially" can still be implied.

The terms "coupling", "coupling", and "electrical connection" mentioned in this disclosure include any direct and indirect electrical connection means. For example, if the text describes that a first component is coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

Although the invention disclosed herein is described below by means of specific embodiments, the invention principles disclosed herein can also be applied to other embodiments. In addition, in order not to obscure the spirit of the invention, certain details will be omitted, and these omitted details belong to the knowledge scope of those with ordinary knowledge in the relevant technical field.

The present disclosure relates to a semiconductor device including a transistor and a resistor connected in series in an upper bridge driving circuit of a switching circuit. By connecting the transistor and the resistor in series, the upper bridge potential signal between the upper bridge switching element and the lower bridge switching element can be accurately detected to avoid the upper bridge and the lower bridge switching elements being turned on at the same time and causing a breakdown short circuit. In addition, the existing structure of the upper bridge driving circuit can be used to manufacture the transistor and the resistor connected in series, which will not increase the occupied area of the semiconductor device, and is conducive to reducing the manufacturing cost and reducing the size of the chip.

FIG. 1 is a block diagram of a portion 100 of a switching circuit according to an embodiment of the present disclosure. The portion 100 of the switching circuit includes an upper bridge transistor 101, a lower bridge transistor 102, and an upper bridge driver circuit 206. In one embodiment, the upper bridge transistor 101 and the lower bridge transistor 102 may both be N-type metal oxide semiconductor (NMOS) field effect transistors. The upper bridge transistor 101 is connected in series with the lower bridge transistor 102, and the upper bridge driver circuit 206 is coupled to the upper bridge transistor 101. According to some embodiments of the present disclosure, the upper bridge driving circuit 206 includes a third transistor 103 connected in series with a third resistor 104, the third transistor 103 can be a P-type metal oxide semiconductor (PMOS) field effect transistor, the third resistor 104 can be a P-type resistor, the node between the upper bridge transistor 101 and the lower bridge transistor 102 is coupled to the drain of the third transistor 103, one end of the third resistor 104 is coupled to the source of the third transistor 103, and the other end of the third resistor 104 is coupled to the ground. According to some embodiments of the present disclosure, the third transistor 103 of the P-type transistor and the third resistor 104 of the P-type resistor are configured in the upper bridge driving circuit 206. The third transistor 103 is connected in series with the third resistor 104 to accurately detect the upper bridge potential signal HS between the upper bridge transistor 101 and the lower bridge transistor 102. When the upper bridge potential signal HS is detected to be erroneous, the upper bridge driving circuit 206 can transmit a signal to turn off the upper bridge transistor 101, and there is no need to set up another level shifter to avoid the upper bridge transistor 101 and the lower bridge transistor 102 being turned on at the same time to cause a breakdown short circuit.

FIG. 2 is a block diagram of a switching circuit 200 according to an embodiment of the present disclosure, wherein the switching circuit 200 includes an upper bridge transistor 101, a lower bridge transistor 102, a boost device 203, a level shift circuit 205, an upper bridge driver circuit 206, a control logic 204, and a lower bridge driver circuit 207. In some embodiments, the switching circuit 200 may be a half-bridge driver circuit, a switching buck converter, or other switching circuits, wherein the input voltage VIN of the upper bridge transistor 101 is greater than the supply voltage VS. The control logic 204 receives the supply voltage VS, and generates the first signal S1 and the second signal S2 to the level shift circuit 205 according to the input signal. The level shift circuit 205 operates between the boost voltage VB and the ground voltage of the ground terminal, and converts the first signal S1 and the second signal S2 between the supply voltage VS and the ground voltage to the setting signal SET and the reset signal RST between the boost voltage VB and the floating reference voltage VF. The upper bridge driving circuit 206 receives the boost voltage VB and the floating reference voltage VF, and generates the upper bridge output signal SHO according to the setting signal SET and the reset signal RST to control the upper bridge transistor 101.

The control logic 204 also generates a lower bridge drive signal SLD to the lower bridge drive circuit 207. The lower bridge drive circuit 207 receives the supply voltage VS and generates a lower bridge output signal SLO according to the lower bridge drive signal SLD to control the lower bridge transistor 102. In normal operation, when the lower bridge drive circuit 207 controls the lower bridge transistor 102 to be turned on by the lower bridge output signal SLO, the upper bridge drive circuit 206 controls the upper bridge transistor 101 to be turned off by the upper bridge output signal SHO, and the node of the floating reference voltage VF is coupled to the ground terminal through the lower bridge transistor 102, so that the floating reference voltage VF is 0V. When the lower bridge driver circuit 207 controls the lower bridge transistor 102 to be non-conductive, the upper bridge driver circuit 206 controls the upper bridge transistor 101 to be conductive, and provides the input voltage VIN to the node of the floating reference voltage VF, so that the floating reference voltage VF is equal to the input voltage VIN. Since the upper bridge transistor 101 and the lower bridge transistor 102 are the same components, in order to maintain the same gate-source cross-voltage for the upper bridge transistor 101 and the lower bridge transistor 102, the boost device 203 is used to boost the boost voltage VB to the sum of the supply voltage VS and the input voltage VIN.

The boost device 203 includes a unidirectional switch element 201 and a capacitor 202. The capacitor 202 is coupled between the node of the boost voltage VB and the node of the floating reference voltage VF. The unidirectional switch element 201 is coupled between the supply voltage VS and the node of the boost voltage VB. When the boost voltage VB is less than the supply voltage VS, the unidirectional switch element 201 provides the supply voltage VS to the node of the boost voltage VB. When the boost voltage VB is higher than the supply voltage VS, the unidirectional switch element 201 isolates the supply voltage VS from the node of the boost voltage VB to prevent the excessive boost voltage VB from being fed back to the supply voltage VS and damaging other circuits.

According to some embodiments of the present disclosure, a third transistor 103 is configured in the upper bridge driving circuit 206 and is connected in series with a third resistor 104. The upper bridge driving circuit 206 can generate a signal to control the gate of the third transistor 103. The source of the third transistor 103 is coupled to one end of the third resistor 104, and the other end of the third resistor 104 is coupled to the ground. The drain of the third transistor 103 receives the upper bridge potential signal HS between the upper bridge transistor 101 and the lower bridge transistor 102. The third transistor 103 is connected in series with the third resistor 104 to accurately detect the upper bridge potential signal HS. When the upper bridge potential signal HS is detected to be erroneous, the upper bridge driver circuit 206 can transmit a signal to turn off the upper bridge transistor 101 to avoid the upper bridge transistor 101 and the lower bridge transistor 102 being turned on at the same time and causing a breakdown short circuit, so there is no need to set up another level shifter.

FIG. 3 is a schematic cross-sectional view of a semiconductor device 300 according to an embodiment of the present disclosure. As shown in FIG. 3 , the semiconductor device 300 includes an epitaxial layer 303 stacked and grown on a substrate 301. Both the substrate 301 and the epitaxial layer 303 have a first conductivity type, such as a P-type substrate and a P-type epitaxial layer, respectively. In some embodiments, the substrate 301 and the epitaxial layer 303 may be composed of silicon (Si), silicon carbide (SiC), aluminum nitride (AlN), gallium nitride (GaN) or other suitable semiconductor materials. A first well region 309 of the second conductivity type, for example, an N-type well region (n-type well, NW), is disposed in the epitaxial layer 303, a gate 321 is disposed on the first well region 309, a gate dielectric layer 320 is disposed below the gate 321, a source contact region 313 and a drain contact region 315 are disposed in the first well region 309, and are respectively located on both sides of the gate 321, and the source contact region 313 and the drain contact region 315 both have the first conductivity type, for example, a P-type heavily doped region (P ⁺ ).

As shown in FIG. 3 , the semiconductor device 300 further includes a second well region 311 of the first conductivity type, for example, a P-type well region (p-type well, PW) disposed in the epitaxial layer 303. The second well region 311 is laterally adjacent to the first well region 309, and in one embodiment, the second well region 311 contacts a portion 301P of the substrate. According to some embodiments disclosed herein, the second well region 311 and a portion 301P of the substrate constitute a third resistor 104. The third resistor 104 may be a P-type resistor, and the third resistor 104 may be electrically coupled to the ground terminal via the substrate 301. In addition, a heavily doped region 317 of the first conductivity type, such as a P-type heavily doped region (P ⁺ ), is disposed in the second well region 311 , and the heavily doped region 317 can be electrically connected to the source contact region 313 via the interconnect structure 340 . In one embodiment, the first well region 309, the source contact region 313, the drain contact region 315 and the gate 321 can constitute a P-type enhancement transistor, and this P-type enhancement transistor corresponds to the third transistor 103 in Figures 1 and 2, wherein the drain contact region 315 receives the upper bridge potential signal HS, and the third transistor 103 of the P-type enhancement transistor is connected in series with the third resistor 104 of the P-type resistor to detect the upper bridge potential signal HS.

In addition, the semiconductor device 300 further includes a first doped region 323 and a second doped region 325 disposed in the first well region 309, the first doped region 323 and the second doped region 325 both have a first conductivity type, for example, both are P-type lightly doped regions, wherein the source contact region 313 is located in the first doped region 323, and the drain contact region 315 is located in the second doped region 325. In addition, a second conductivity type bulk contact region 319, for example, an N-type heavily doped region (N ⁺ ), is also disposed in the first well region 309, and the bulk contact region 319 is laterally separated from the source contact region 313 and the first doped region 323.

Still referring to FIG. 3 , the semiconductor device 300 further includes a third well region 307 of the second conductivity type, such as a high voltage n-type well region (HVNW) disposed in the epitaxial layer 303, and the third well region 307 surrounds the first well region 309 and the second well region 311. In one embodiment, a portion 303P of the epitaxial layer may be located between the second well region 311 and the third well region 307, and the portion 303P of the epitaxial layer is located directly above a portion 301P of the substrate. The second well region 311 is laterally adjacent to and contacts a portion 303P of the epitaxial layer, so that the heavily doped region 317 in the second well region 311 can be coupled to a portion 301P of the substrate via the second well region 311 and a portion 303P of the epitaxial layer to adjust the resistance value of the third resistor 104. For example, the resistance value of the third resistor 104 can be controlled and adjusted by the plane layout shape, area and doping concentration of the second well region 311 and a portion 303P of the epitaxial layer to meet the different electrical requirements of various circuits. In addition, the semiconductor device 300 also includes a fourth well region 305 of the second conductivity type, such as a deep high voltage n-type well region (DHVNW) disposed in the substrate 301, wherein the first well region 309, the second well region 311 and the third well region 307 are all located directly above the fourth well region 305, and the fourth well region 305 surrounds a portion 301P of the substrate. In some embodiments, the bottom surfaces of the first well region 309, the second well region 311 and the third well region 307 can all contact the top surface of the fourth well region 305. In other embodiments, the bottom surfaces of the first well region 309 and the second well region 311 are separated from the top surface of the fourth well region 305 by a distance.

FIG. 4 is a cross-sectional schematic diagram of a semiconductor device 300 according to another embodiment of the present disclosure. In the semiconductor device 300 of FIG. 4, the second well region 311 is laterally extended to the third well region 307 adjacent to the second well region 311, so that the contact area between the second well region 311 and a portion 301P of the substrate is increased, so that the third resistor 104 of the semiconductor device 300 of FIG. 4 has a different resistance value from the third resistor 104 of the semiconductor device 300 of FIG. 3. In this embodiment, the resistance value of the third resistor 104 can be controlled by the plane layout shape, area and doping concentration of the second well region 311. For other component features of the semiconductor device 300 of FIG. 4, please refer to the relevant description of the semiconductor device 300 of FIG. 3, which will not be repeated here.

FIG. 5 is a cross-sectional schematic diagram of a semiconductor device 300 according to another embodiment of the present disclosure. In the semiconductor device 300 of FIG. 5, a conductive layer 322 may be disposed directly above a portion 303P of the epitaxial layer, and the conductive layer 322 may be electrically connected to the heavily doped region 317 and the source contact region 313 via an interconnect structure 340, so that the conductive layer 322 has a shielding effect. For other component features of the semiconductor device 300 of FIG. 5, please refer to the relevant description of the semiconductor device 300 of FIG. 3, which will not be repeated here.

FIG. 6 is a cross-sectional schematic diagram of a semiconductor device 300 according to another embodiment of the present disclosure. In the semiconductor device 300 of FIG. 6, a portion 303P-1 of the epitaxial layer 303 is located between the second well region 311 and the third well region 307, and another portion 303P-2 of the epitaxial layer 303 is located between the bottom surface of the first well region 309 and the bottom surface of the second well region 311 and the top of the fourth well region 305. In this embodiment, the first well region 309 and the second well region 311 do not contact the fourth well region 305, and the heavily doped region 317 in the second well region 311 can be coupled to a portion 301P of the substrate via the second well region 311 and a portion 303P-2 of the epitaxial layer. The second well region 311, a portion 303P-2 of the epitaxial layer, and a portion 301P of the substrate constitute a third resistor 104. In addition, the resistance value of the third resistor 104 can be controlled and adjusted by the thickness of a portion 303P-2 of the epitaxial layer. For other component features of the semiconductor device 300 in FIG. 6, please refer to the relevant description of the semiconductor device 300 in FIG. 3, which will not be repeated here.

According to some embodiments of the present disclosure, the third transistor 103 in FIG. 3, FIG. 4, FIG. 5 and FIG. 6 can be formed by the structure of the P-type enhancement transistor in the upper bridge driver circuit 206. In addition, the structure of the upper bridge driver circuit 206 further includes an isolation ring surrounding the P-type enhancement transistor, and the second well region 311 of the third resistor 104 can be formed by a part of the isolation ring. The third transistor 103 and the third resistor 104 in these embodiments of the present disclosure can be arranged in the layout structure of the upper bridge driver circuit 206, and by forming the P-type enhancement transistor and the isolation ring in the upper bridge driver circuit 206, the third transistor 103 and the third resistor 104 connected in series are simultaneously generated, so there is no need to set up another level shifter to detect the upper bridge potential signal HS. The semiconductor device of some embodiments of the present disclosure will not increase the footprint, which can save manufacturing costs and reduce the size of the chip.

FIG. 7, FIG. 8 and FIG. 9 are cross-sectional schematic diagrams of some stages of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Referring to FIG. 7, in step S101, a substrate 301 is first provided, such as a P-type semiconductor substrate, which can be composed of silicon (Si), silicon carbide (SiC) or other suitable semiconductor materials. Using an ion implantation process and a mask, N-type dopants are implanted in the substrate 301 to form a fourth well region 305, such as a high-voltage N-type deep well region (DHVNW), and the fourth well region 305 surrounds a portion 301P of the substrate. In some embodiments, the doping concentration of the fourth well region 305 is, for example, 5E14 to 1E17 cm ^-3 . Then, an epitaxial growth process is used to form an epitaxial layer 303 on the substrate 301, such as a P-type epitaxial layer, which can be composed of silicon (Si), silicon carbide (SiC) or other suitable semiconductor materials. An ion implantation process and another mask are used to implant N-type dopants in the epitaxial layer 303 to form a third well region 307, such as a high voltage N-type well region (HVNW), wherein the third well region 307 is located directly above the fourth well region 305, and the bottom surface of the third well region 307 can contact the top surface of the fourth well region 305. The doping concentration of the fourth well region 305 may be higher than the doping concentration of the third well region 307 . In some embodiments, the doping concentration of the third well region 307 is, for example, 1E14 to 8E16 cm ⁻³ .

Continuing to refer to FIG. 7, in step S103, an ion implantation process and a mask are used to implant N-type dopants in the epitaxial layer 303 to form a first well region 309, such as an N-type well region (NW). In some embodiments, the doping concentration of the first well region 309 is, for example, 5E16 to 5E17 cm ^-3 . The first well region 309 is located directly above the fourth well region 305, and the first well region 309 may be laterally adjacent to the third well region 307 located on the left side. In some embodiments, the bottom surface of the first well region 309 may contact the top surface of the fourth well region 305. In other embodiments, the bottom surface of the first well region 309 may be separated from the top surface of the fourth well region 305 by a distance. Then, another ion implantation process and another mask are used to implant P-type dopants in the epitaxial layer 303 to form a second well region 311, such as a P-type well region (PW). In some embodiments, the doping concentration of the second well region 311 is, for example, 5E16 to 5E17 cm ^-3 . The second well region 311 is located directly above the fourth well region 305. In some embodiments, the bottom surface of the second well region 311 may contact the top surface of the fourth well region 305. In other embodiments, the bottom surface of the second well region 311 may be separated from the top surface of the fourth well region 305 by a distance. In addition, the second well region 311 is laterally adjacent to the first well region 309, and a portion 303P of the epitaxial layer is located between the second well region 311 and the third well region 307. In addition, in some embodiments, the bottom surface of the second well region 311 may contact the top surface of the portion 301P of the substrate. In other embodiments, the bottom surface of the second well region 311 may be separated from the top surface of the portion 301P of the substrate by a distance.

Next, referring to FIG. 8 , in step S105, an ion implantation process and a mask are used to implant P-type dopants in the first well region 309 to form a first doped region 323 and a second doped region 325, both of which are, for example, P-type lightly doped regions. In some embodiments, the first doped region 323 and the second doped region 325 have the same doping concentration, for example, 1E16 to 1E18 cm ^-3 . Then, a gate dielectric layer 320 is formed on the first well region 309 using deposition, photolithography, and etching processes, and the composition thereof is, for example, silicon oxide. Next, a gate 321 and a conductive layer 322 are formed on the first well region 309 and a portion of the epitaxial layer 303P, respectively, using deposition, photolithography and etching processes. The gate 321 and the conductive layer 322 are composed of, for example, doped polysilicon, wherein the gate 321 is located between the first doped region 323 and the second doped region 325, and on the gate dielectric layer 320, the bottom surface of the conductive layer 322 can contact the top surface of a portion of the epitaxial layer 303P.

Then, referring to FIG. 9 , in step S107 , an ion implantation process and a mask are used to implant N-type dopants in the first well region 309 to form a substrate contact region 319, such as an N-type heavily doped region (N ⁺ ). In some embodiments, the doping concentration of the substrate contact region 319 is, for example, 5E18 to 5E19 cm ^-3 . Then, another ion implantation process and another mask are used to implant P-type dopants in the first doped region 323 and the second doped region 325 to form a source contact region 313 and a drain contact region 315, respectively. At the same time, P-type dopants are implanted in the second well region 311 to form a heavily doped region 317. The first doped region 323 , the second doped region 325 , and the heavily doped region 317 are, for example, P-type heavily doped regions (P ⁺ ). In some embodiments, the first doped region 323 , the second doped region 325 , and the heavily doped region 317 have the same doping concentration, for example, 5E18 to 5E19 cm ⁻³ . Thereafter, an interlayer dielectric layer 330 is deposited on the epitaxial layer 303, and a drain contact 331, a source contact 332, and vias 333 and 336 are formed in the interlayer dielectric layer 330 using photolithography, etching, and deposition processes, which are electrically connected to the drain contact region 315, the source contact region 313, the heavily doped region 317, and the conductive layer 322, respectively. Next, a drain electrode 334 and a source electrode 335 are formed on the interlayer dielectric layer 330 using deposition, photolithography and etching processes, wherein the drain electrode 334 is electrically connected to the drain contact region 315 via the drain contact 331, and the source electrode 335 is electrically connected to the source contact region 313, the heavily doped region 317 and the conductive layer 322 via the source contact 332, the vias 333 and 336, respectively, to complete the semiconductor device 300 shown in FIG. 5 . The drain electrode 334 can receive the upper bridge potential signal HS, and the source electrode 335, the source contact 332 and the via 333 can be used to couple the source of the third transistor 103 to one end of the third resistor 104, so as to connect the third transistor 103 and the third resistor 104 in series. According to some embodiments of the present disclosure, the manufacturing of the semiconductor device 300 including the third transistor 103 and the third resistor 104 can be integrated with the manufacturing process of the upper bridge driver circuit 206, without the need to add additional process steps and masks, thereby saving the manufacturing cost of the semiconductor device.

The above is only the preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the patent application of the present invention shall fall within the scope of the present invention.

103: The third transistor

104: The third resistor

300:Semiconductor devices

301: Base

301P: Part of the base

303: Epitaxial layer

303P: Part of the epitaxial layer

305: Fourth Well Area

307: The third well area

309: First Well Area

311: Second well area

313: Source contact area

315: Drain contact area

317: Remixed area

319: substrate contact area

320: Gate dielectric layer

321: Gate

323: First mixed area

325: Second mixed area

340: Interconnection structure

HS: upper bridge potential signal

Claims (15)

A semiconductor device includes: a substrate having a first conductivity type; an epitaxial layer having the first conductivity type and disposed on the substrate; a first well region having a second conductivity type and disposed in the epitaxial layer; a gate disposed on the first well region; a source contact region and a drain contact region both having the first conductivity type and disposed in the first well region, and respectively located on the gate. On both sides of the source; a second well region having the first conductivity type, disposed in the epitaxial layer, laterally adjacent to the first well region, and contacting a portion of the substrate, wherein the second well region and the portion of the substrate constitute a resistor, and the resistor is electrically coupled to a ground terminal; and a heavily doped region having the first conductivity type, disposed in the second well region, and electrically connected to the source contact region. The semiconductor device as described in claim 1 further includes a third well region having the second conductivity type, disposed in the epitaxial layer and surrounding the first well region and the second well region. A semiconductor device as described in claim 2, wherein a portion of the epitaxial layer is located between the second well region and the third well region, and the portion of the epitaxial layer is located directly above the portion of the substrate. A semiconductor device as described in claim 3, wherein the second well region is laterally adjacent to and in contact with the portion of the epitaxial layer. The semiconductor device as described in claim 3 further includes a conductive layer disposed directly above the portion of the epitaxial layer, and the conductive layer is electrically coupled to the heavily doped region and the source contact region. A semiconductor device as described in claim 2, wherein the second well region is laterally adjacent to and in contact with the third well region. The semiconductor device as described in claim 2 further includes a fourth well region having the second conductivity type and disposed in the substrate, wherein the first well region, the second well region and the third well region are all located directly above the fourth well region, and the fourth well region surrounds the portion of the substrate. A semiconductor device as described in claim 7, wherein the bottom surface of the first well region and the bottom surface of the second well region are both in direct contact with the top surface of the fourth well region. A semiconductor device as described in claim 7, wherein the bottom surface of the first well region and the bottom surface of the second well region are both separated from the top surface of the fourth well region by a distance. The semiconductor device as described in claim 1 further includes a first doped region and a second doped region, both of which have the first conductivity type and are disposed in the first well region, wherein the source contact region and the drain contact region are respectively located in the first doped region and the second doped region. The semiconductor device as described in claim 10 further includes a substrate contact region having the second conductivity type, disposed in the first well region, and laterally separated from the source contact region and the first doped region. A semiconductor device as described in claim 1, wherein the first well region, the source contact region, the drain contact region and the gate constitute a P-type enhancement transistor, the resistor is a P-type resistor, and the P-type enhancement transistor is connected in series with the P-type resistor. A semiconductor device as described in claim 12, wherein the P-type enhancement transistor and the P-type resistor are arranged in a top bridge driving circuit of a switching circuit to detect a top bridge potential signal between a top bridge transistor and a bottom bridge transistor. A semiconductor device as described in claim 13, wherein the upper bridge driving circuit controls the closing of the upper bridge transistor according to the detected upper bridge potential signal. A semiconductor device as described in claim 13, wherein the structure of the upper bridge driver circuit includes an isolation ring, and the second well region is a part of the isolation ring.

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