TW201931964A - A structure of a Printing Circuit Board and a carrier and methods of manufacturing semiconductor package - Google Patents

Abstract

The invention discloses a structure composed of a circuit board combined with a carrier board and a method for manufacturing a package, wherein the circuit board has at least a circuit and a solder resist layer, and the carrier board has at least one component, and the solder resist layer may have a correspondence with the circuit. A set of reserved openings (or through-holes), which will be removed during the manufacturing process of the package, so that the circuit can be used for external electrical communication, and one surface of the solder resist layer is bonded to one surface of the circuit , The other surface is bonded to one surface of the carrier board; in the manufacturing process of the package, when the circuit board is combined with plastic, and the carrier board needs to be removed with an etching solution, the solder mask layer is used to completely cover the surface of the circuit. Feature, which can avoid the damage caused by the attack of the etching solution. When the reserved openings of the solder mask layer are converted into through-holes, at least a part of the edge area of the circuit surface can still be covered by the solder mask layer. Therefore, the circuit and the insulator can be more firmly combined, and accordingly, the thickness of the circuit can be implemented thinner, which can reduce the thickness of the circuit board and the package, and the circuit board can further have an insulator and / or a second as required. line.

Description

Circuit board and package manufacturing method

The invention relates to a circuit board and a package manufacturing method, in particular to a circuit board for a semiconductor wafer and / or a package, and a package manufacturing method.

As shown in Figures 14-1 to 14-4, the manufacturing method of the conventional package 1A is described later. The sectional view of the manufacturing method of the conventional package 1A shown in Figure 14-1 is shown below. First, a conventional circuit board is provided. 5A and detachable carrier 8K, wherein the circuit board 5A includes an insulator 4H and a power-supply transmission line 35, and the insulator 4H has an upper surface 41, a lower surface 42 and a via 44 The circuit 35 has an upper surface 31, a lower surface 32, and a side 33. The circuit 35 is provided on the lower surface 42 of the insulator 4H, and the lower surface 32 and the side 33 are joined to the insulator 4H. The lower surface 32 is exposed in the through hole 44. The part is implemented as a terminal 324 for external electrical communication. The upper surface 31 is exposed on the lower surface 42 of the insulator 4H. The thickness T of the insulator 4H is the thickness T4 between the upper surface 41 and the lower surface 32 of the circuit 35. The thickness T3 of the circuit 35 is composed of 15 ~ 30 micrometers (μm); the carrier board 8K is made of copper clad laminate 8A, prepreg 8B and detachable copper The copper foil substrate 8A is composed of two copper foils 8A1 and an adhesive 8A2. The adhesive 8A2 is made of a cured adhesive or His suitable adhesive composition consists of the adhesive 8A2 which joins the two copper foils 8A1 together, and makes the adhesive 8A2 be between the two copper foils 8A1, and the detachable copper foil 8C can be made of two copper foils. And a thin film layer (not shown), the thin film layer joins two copper foils together, and the thin film layer is interposed between the two copper foils, wherein the copper foil joined with the thin film layer is implemented as a bonding layer 8C1, and the other copper foil bonded to the film layer is implemented as a separation layer 8C2, and the separation layer 8C2 is combined with the copper foil substrate 8A by a curing glue 8B, and the bonding layer 8C1 and the separation layer 8C2 It may consist of a copper layer and / or other applicable metal layers. The carrier board 8K is located on the lower surface 42 of the circuit board 5A insulator 4H, and is bonded to the lower surface 42 of the circuit board 5A insulator 4H by the bonding layer 8C1. So that the upper surface 31 of the circuit 35 is not exposed to the atmosphere. Then, a chip 20 and a conductive member 18 implemented as a wire are provided. Among them, the chip 20 is first set on the upper surface 41 of the insulator 4H, and then the conductive member 18 is borrowed. Bonded to the terminal 24 of the chip 20 and the contact 324 of the circuit 35, respectively, so that the chip 20 and the circuit board 5A are electrically connected. Connect, then, provide the plastic 60, which covers the surface of the wafer 20, the conductive member 18, and the circuit board 5A. Based on this, the package 1A has been formed; then, the conventional package 1A manufacturing method shown in FIG. 14-2 The cross-sectional view provides a disassembly process to separate the bonding layer 8C1 and the disassembly layer 8C2 of the carrier board 8K, so that the disassembly layer 8C2, the curing glue 8B, and the copper foil substrate 8A are removed at the same time. The removal process is performed with an etching solution. Next, as shown in FIG. 14-3 is a bottom view, an etching removal process is provided to remove the bonding layer 8C1 of the detachable copper foil, so that the upper surface 31 of the circuit 35 Bare on the lower surface 42 of the insulator 4H; then, as shown in the cross-sectional view of the manufacturing method of the conventional package 1A shown in FIG. 14-4, a solder ball S is provided as required, and the solder ball S is bonded to the upper surface 31 of the circuit 35, so that the chip 20 can be The solder ball S is used for external electrical communication. According to the above description, the circuit board 5A has at least the following disadvantages, which are explained as follows: 1) As shown in Figure 14-4, the thickness T3 of the circuit 35 is usually greater than 15 microns. After the solder ball S is bonded, when the solder ball S is pulled by the external force F, the lower surface 32 of the circuit 35 and the insulator 4H are likely to be caused. Delamination or gap G is generated at the joint, which makes the electrical transmission between the circuit 35 and the conductive member 18 unstable, and even the electrical connection cannot be caused, which damages the package 1A. Although the thickness of the circuit 35 can be increased from T3 to 22 microns Or thicker, by increasing the joint area and strength of the side 33 and the insulator 4H to avoid the gap G of the package 1A, but the thick line 35 can not effectively reduce the thickness T of the insulator 4H, but also increase the production cost. The circuit board 5A cannot meet the demand for thinner electronic products; 2) As shown in Figure 14-2, during the removal of the spin-off layer 8C1 by the etching solution, a part of the circuit 35 is also removed, so that The thickness T3 of the line 35 is converted to a thinner thickness T3K. According to this, the side area 33 of the line 35 is reduced to the bonding area with the insulator 4H, thereby reducing the bonding strength of the line 35 and the insulator 4H, and the line 35 and the solder ball S are joined. It is easier to damage the circuit board 5A because the solder ball S is pulled by the external force F.

The invention is a structure and a method for manufacturing a package composed of a circuit board combined with a carrier board. The circuit board is composed of at least a circuit and a solder mask. The carrier board is composed of at least one component. The reserved opening (or through-hole) corresponding to the circuit is converted into an opening during the manufacturing process of the package, so that the circuit can be used for external electrical communication. The surface is bonded to the upper surface of the circuit, the upper surface is bonded to the surface of the carrier board, and the features of the surface of the circuit are covered by a solder mask. In this way, the etching solution of the carrier board can be prevented from being removed during the manufacturing process of the package. Damage caused by attacks; at the same time, the carrier board can be used to protect the solder mask and improve the warpage of the circuit board. It can also reduce the cost of the carrier board without the copper foil split from the conventional carrier board. This makes the circuit board of the present invention meet the requirements of the electronics industry for "thin" and improve the quality of the circuit board.

31, 3A1, 3B1, 41‧‧‧ upper surface

6S, 71, 81, 91‧‧‧ upper surface

32, 42, 72, 82, 92‧‧‧ lower surface

33, 43, 53, 73, 83‧‧‧ side

18‧‧‧ conductive parts

20‧‧‧Chip

24, 3A‧‧‧ endpoint

30, 35, 70‧‧‧ lines

324, 724‧‧‧ contact

3A4‧‧‧Joint Zone

3B‧‧‧ Extension

40, 4H‧‧‧ insulator

44‧‧‧through hole

50, 51, 5A‧‧‧Circuit board

60‧‧‧plastic

65‧‧‧ film

39, 79, 99‧‧‧ convex

80, 88, 8K‧‧‧ carrier board

85‧‧‧ side wall

86, 96‧‧‧ opening

87‧‧‧ blind hole

801‧‧‧ adjustment layer

8C1‧‧‧Joint layer

8A‧‧‧ Copper foil substrate

8B‧‧‧Cure glue

8C‧‧‧detachable copper foil

8A1‧‧‧copper foil

8A2‧‧‧Adhesive

8C2‧‧‧Split layer

90, 95‧‧‧ solder mask

90F‧‧‧ part of solder mask

9F‧‧‧Reserved opening

10.1A‧‧‧package

D‧‧‧ Depth

F‧‧‧ external force

G‧‧‧ Clearance

KK‧‧‧ Cutting Line

S‧‧‧ solder ball

T, T3, T3k, T4, T5, T30‧‧‧thickness

T40, T8C1, T8C2‧‧‧thickness

L‧‧‧Width

Figure 1-1: A structural cross-sectional view of the circuit board and the carrier board along the cutting line KK shown in Figure 1-2

Figure 1-2: Bottom view of the circuit board

Figures 2 ~ 8: Structural cross-sections of circuit boards and carrier boards

Figure 9-1 ~ Figure 13-3: Three different cross-sectional views of the manufacturing method of the package

Figure 14-1 ~ Figure 14-2: Cross-sectional views of the manufacturing method of conventional packages

Figure 14-3: Bottom view of a conventional package

Figure 14-4: A cross-section of the manufacturing method of a conventional package.

Figures 1-1 to 1-2 show the basic structure of the circuit board and carrier board structure of the present invention. Among them, Figure 1-2 is a bottom view of the circuit board 51, and Figure 1-1 is a carrier board 80. The cross-sectional view and the cross-sectional view of the circuit board 51 along the cutting line KK in FIG. 1-2. The thickness T5 of the circuit board 51 is particularly suitable for the requirement of not more than 30 microns (that is, T5 ≦ 30 microns), such as: 25, 20, 10, 2 microns or For other applicable thicknesses, the circuit board 51 includes: line 30, for power transmission, which can be made of suitable conductors such as copper or nickel, and has an upper surface 31, a lower surface 32, a side 33, and a thickness T30, a thickness T30. It is particularly suitable for requirements not larger than 10 microns, such as: 10, 5, 3, 1 microns or other applicable thicknesses. The line 30 is composed of at least one endpoint 3A, and the line 30 of this embodiment is composed of the endpoint 3A and the adjacent The extension 3B is formed by joining. The upper surface 31 is composed of the upper surface 3A1 of the endpoint 3A and the upper surface 3B1 of the extension 3B. At the same time, the endpoint 3A is used for external electrical communication and the edge area of the upper surface 3A1 is implemented. For the junction area 3A4, the upper and lower surfaces 31, 32 of this line 30 can be implemented as rectangular or circular or irregular patterns, so that the line 30 The solder mask 90 is freely extended on the lower surface 92; the solder mask 90 is composed of an insulating substance, such as a solder mask or epoxy or other applicable insulating substance, and has a The open hole 9F, the upper surface 91 and the lower surface 92 are reserved. Among them, the reserved hole 9F is composed of a part 90F of the solder mask layer 90, and the reserved hole 9F is provided corresponding to the end 3A of the line 30 to prevent soldering. The lower surface 92 of the layer 90 is bonded to the upper surface 31 of the circuit 30, so that the upper surface 31 of the circuit 30 is completely encapsulated without being exposed to the outside of the solder mask layer 90. A part 90F of the solder mask layer 90 will be damaged during the manufacturing process of the package. Removal converts the reserved opening 9F into an opening (96_see FIG. 9-4), so that the terminal 3A of the line 30 can be used for external electrical communication, wherein the circuit board 51 is only stacked by the line 30 and the solder resist layer 90 According to this, the thickness T5 of the circuit board can be less than 30 microns, or even less than 2 microns, so that the circuit board 51 of the present invention can meet the "thin" demand of the electronics industry; the carrier board 80 can be made of copper or other suitable Made of metal, or composed of resin or other suitable non-metal, which has an upper surface 81, lower The surface 82 and the side 83, the carrier plate 80 is joined with the solder resist layer 90. In the embodiment of the carrier plate 80 shown in FIG. 1-1, the lower surface 82 of the carrier plate 80 and the upper surface 91 of the solder resist layer 90 are formed. By bonding, the upper surface 81 of the carrier board 80 is exposed to the atmosphere, and the carrier board 80 can be replaced with the carrier boards 80, 88, 8K as shown in FIG. 2 to FIG. 14-1, so that the carrier board 80 can be composed of a single component or multiple Components, the carrier board of the embodiment of Figure 1-1 is composed of a single group According to the above description, during the manufacturing process of the package 10 (see FIG. 9-2), when the carrier board 80 needs to be removed with an etching solution, the circuit 30 is completely covered by the solder resist 90. The characteristics of the surface 31 make the circuit 30 not damaged by the attack of the etching solution, thereby improving the quality of the circuit board 51 or reducing the thickness and cost of the circuit board 51 and the package body. In addition, since the carrier board 80 is bonded to the solder resist layer 90, It is possible to prevent the solder resist layer 90 from being damaged by an external force.

As shown in FIG. 2, it is a structural cross-sectional view of the circuit board 50 and the carrier board 80. The thickness T5 of the circuit board 50 and the thickness T30 of the circuit 30 are the same as those shown in FIG. 1-1. The characteristics and symbols of the circuit board 50 and the carrier board 80 are as follows. It is the same as the circuit board 51 and the carrier board 80 in FIG. 1-1. Please refer to the description in FIG. 1-1. The difference is that the solder resist layer 90 covers the side 33 of the circuit 30 to increase and prevent the circuit 30. The bonding area of the solder layer 90 can be more firmly combined with the solder resist layer 90 to avoid peel-off damage of the circuit 30 from the solder resist 90.

As shown in FIG. 3, it is a structural cross-sectional view of the circuit board 50 and the carrier board 88. The circuit board 50 is particularly suitable for the requirement that the thickness of the insulator 40 is T40 not more than 30 microns (that is, T40 ≦ 30 microns), such as: 25, 20, 10 , 2 micron or other applicable thickness, the characteristics and symbols of the circuit board 50 and the carrier board 88 are the same as the circuit board 51 and the carrier board 80 of FIG. 1-1, please refer to the description of FIG. 1-1, where the circuit board The difference between 50 and 50 is that it further has an insulator 40, which has an upper surface 41, a lower surface 42, a side edge 43, and a through hole 44, which is composed of an insulating substance, such as epoxy resin or solder resist or other applicable insulating substances. The thickness T40 is composed of the thickness T4 between the lower surface 32 and the upper surface 41 of the circuit 30 and the thickness T30 of the circuit 30. The insulator 40 is bonded to the lower surface 92 of the solder resist layer 90 and covers the lower surface 32 of the circuit 30 and its sides. Edge 33, where the through hole 44 is provided corresponding to the lower surface 32 of the line 30, and the portion of the lower surface 32 of the line 30 that is exposed from the through hole 44 of the insulator 40 is implemented as a contact 324, so that the contact 324 can be connected for power supply. The contact 324 is exposed in the insulator through hole 44; the difference between the carrier board is that the carrier board 88 is composed of multiple component groups In this embodiment, the carrier plate 88 is composed of the adjustment layer 801 and the carrier plate 80 joined together, and the surface of the adjustment layer 801 exposed to the atmosphere is implemented as the upper surface 81 of the carrier plate 88. The material of the adjustment layer 801 is different from that of the carrier plate 80. It can be implemented as an insulating substance or curing glue or solder mask or other suitable materials. The circuit board 50 can improve the rigidity and reduce the cost by adjusting the layer 801, because if the carrier board 80 is implemented as copper, when the thickness of the carrier board 80 is greater than At 36 microns, in addition to high material costs, during the manufacturing process of the circuit board 50, when a working panel is divided into substrates with multiple circuit boards 50 by a milling cutter, the milling cutter will be accelerated. Damage increases the production cost, and due to the high coefficient of thermal expansion (CTE) of copper, during the production or use of a substrate with multiple circuit boards 50, the substrate may be damaged by collision and extrusion due to excessive warpage of the substrate. By combining an adjustment layer 801 with a low material cost and a different thermal expansion coefficient from that of the carrier board 80, the thickness of the carrier board 80 can be reduced to 3 to 18 microns, which can reduce costs, and maintain the rigidity of the circuit board 50 and conform to mass production. Degree of warping 50 has Better usability. At the same time, since the carrier plate 88 can only be composed of the adjustment layer 801 and the carrier plate 80, the carrier plate 88 does not need to have the detachable copper foil 8C and curing of the carrier plate 8K as shown in Figure 14-1. Adhesive 8B, according to this, can reduce material costs and production costs, making the circuit board 50 more practical; and if the circuit board 50 is combined with the carrier board 8K shown in Figure 14-1, it can also avoid the conventional circuit board 5A The disadvantages are explained as follows: 1) In the manufacturing process of the package, when the carrier board 8K bonding layer 8C1 needs to be removed by an etching solution (see FIGS. 9-1 to 9-3 and description), the upper surface 31 of the circuit 30 It is completely encapsulated by the solder resist layer 90, so that the line 30 can be prevented from being thinned or damaged by the attack of the etching solution. According to this, the thickness T30 of the line 30 can be thinner than the thickness T3 of the conventional line 35 in FIG. 14-1, such as: 11 , 7, 4, 1 micron or other suitable thickness, so that the circuit board 50 and the package can use the thin circuit 30 to achieve a thinner product, and use the thin circuit 30 to reduce the material and production cost. ; 2) After the wiring 30 is combined with the solder ball S (see FIG. 9-4), the bonding area 3A4 of the wiring 30 is covered by the solder resist layer 90 (see FIG. 9-4) ), So that the circuit 30 can still be more firmly combined with the insulator 40, so that when the solder ball S is pulled by the external force F, the layered damage between the lower surface 32 of the circuit 30 and the insulator 40 can be avoided; After the shown carrier board 88 is replaced by the carrier board 8K shown in FIG. 14-1, the bonding layer 8C1 of the carrier board 8K can also be regarded as being implemented as the carrier board 80 (see FIG. 1-1), and accordingly So that the structure of the circuit board and the carrier board can achieve useful and practical effects.

As shown in FIG. 4, it is a structural cross-sectional view of the circuit board 51 and the carrier board 88. The characteristics and symbols of the circuit board 51 and the carrier board 88 are the same as those of the circuit board 50 and the carrier board 88 in FIG. 3. Please refer to FIG. 3 for explanation. Among them, the circuit board 51 is different in that it further includes a second circuit 70 for power transmission, and has an upper surface 71, a lower surface 72, a side 73, and a convex portion 79. The convex portion 79 is located on the lower surface. 72, and the lower surface 72 is joined with the upper surface 41 of the insulator 40, so that the convex portion 79 is accommodated in the through hole 44 of the insulator 40, and is connected to the line 70 contact 324 to be in electrical communication; the difference between the carrier plate 88 is: adjustment The layer 801 has a blind via 87 having a width L and a depth D. The blind hole 87 may or may not pass through the adjustment layer 801 by changing the depth D. In this embodiment, the blind hole 87 is a through adjustment layer 801, so that a part of the carrier plate 80 can be exposed in the blind hole 87, and the blind hole 87 does not penetrate the carrier plate 88. The carrier plate 88 can at least change the width L and / or depth of the blind hole 87 by D, used to change the thermal expansion coefficient of the carrier board 88, thereby improving the degree of warpage of the circuit board 51, and avoiding crush damage due to excessive warpage In addition, a solder resist layer may be provided on the upper surface 41 of the insulator 40 to protect the second circuit 70 as required, and a conductive layer (not shown) may be provided on the upper surface 71 of the second circuit 70 as required. ) To facilitate external electrical connection.

As shown in FIG. 5, it is a structural cross-sectional view of the circuit board 51 and the carrier board 80. The characteristics and symbols of the circuit board 51 and the carrier board 80 are the same as those of the circuit board 50 and the carrier board 80 in FIG. 2. The difference is that the circuit board 51 has an insulator 40 having an upper surface 41, a lower surface 42, On the side 43 and the through hole 44, the insulator 40 is bonded to the lower surface 92 of the solder mask 90 and covers the lower surface 32 of the circuit 30. The through hole 44 is provided corresponding to the lower surface 32 of the circuit 30 so that the lower surface 32 of the circuit 30 The part exposed in the through hole 44 of the insulator 40 is implemented as a contact 324, so that the contact 324 can be used for power supply and communication. In addition, the circuit board 51 can be provided with a second line 70 (dotted line) for power transmission according to requirements. The surface 71, the lower surface 72, the side 73, and the convex portion 79. The convex portion 79 is provided on the lower surface 72, and the lower surface 72 is joined to the upper surface 41 of the insulator 40, so that the convex portion 79 is accommodated in the through hole 44 of the insulator 40. The circuit board 51 is connected to the contact 324 of the line 70 and is in electrical communication, so that the circuit board 51 has a higher line density due to the second line 70.

As shown in FIG. 6, it is a structural cross-sectional view of the circuit board 51 and the carrier board 80. The characteristics and symbols of the circuit board 51 and the carrier board 80 are the same as those of the circuit board 50 and the carrier board 80 in FIG. 2. The two differences of the circuit board 51 are: 1). The circuit 30 further has a convex portion 39, and the convex portion 39 is provided on the lower surface 32 of the circuit 30; 2). It also has a second circuit 70 and an insulator 40, of which the second The circuit 70 has a side 73, an upper surface 71, and a lower surface 72. A part of the lower surface 72 is implemented as a contact 724 for power communication. The insulator 40 has an upper surface 41, a lower surface 42, and a through hole 44, and the insulator 40. It is bonded to the lower surface 92 of the solder resist layer 90 and the lower surface 32 of the circuit 30. The second circuit 70 is located on the upper surface 41 of the insulator 40, and the insulator 40 covers the lower surface 72 and the side 73 of the second circuit 70. The upper surface 71 of the second circuit 70 is exposed on the upper surface 41 of the insulator 40. At the same time, the contact 724 of the second circuit 70 is exposed on the through hole 44, and the through hole 44 of the insulator 40 is provided corresponding to the line protrusion 39. The convex portion 39 of the circuit 30 is set in the through hole 44 and is connected to the contact 724 of the second circuit 70 to be in electrical communication.

As shown in FIG. 7, it is a structural cross-sectional view of the carrier board 80 and the circuit board 51. Among them, the characteristics and symbols of the carrier board 80 are the same as those of the carrier board 80 in FIG. 1-1. The difference is that the carrier board 80 has an opening 86, which is implemented as a through-hole, and the opening 86 has a side wall 85. The opening 86 is provided corresponding to the end 3A of the line 30; and the characteristics of the circuit board 51 The symbols are the same as those of the circuit board 50 in FIG. 3. Please refer to the description in FIG. 3. The difference is that the solder mask layer 90 of the circuit board 51 has a convex portion 99 which is provided on the upper surface 91 of the solder mask layer 90. In addition, a part 90F of the solder resist layer 90 is accommodated in the opening 86 of the carrier board 80. Accordingly, the reserved opening 9F of the solder resist 90 is also accommodated in the opening 80 of the carrier board 80, and the opening 86 is The side wall 85 is joined to the convex part 99 of the solder resist layer 90, so that the solder resist layer 90 is joined to the side wall 85 of the lower surface 82 of the carrier board 80 and the opening 86 of the carrier board 80, and thereby the circuit board 51 and the package are bonded. During the bonding process, the carrier board 80 can be removed (see Figure 10-2) or retained (see Figure 12-2). When the carrier board 80 is retained, the heat dissipation of the package can be improved by the carrier board 80 Efficacy, or 8 on the side of the carrier board 80 3 Add nickel or other applicable metal layers or films (see Figure 12-3) to improve the area and efficiency of the package's resistance to electromagnetic interference; in addition, the upper surface 81 of the carrier board 80 can be joined with a first Two solder mask layers (95) are used to protect the carrier plate 80, wherein the second solder mask layer (95) is bonded to the upper surface 81 and the solder mask layer 90 of the carrier plate 80, and the second solder mask layer (95 ) The surface can be joined with another carrier board, such as the carrier board 8K shown in FIG. 14-1, wherein if the second solder resist (95) is joined with the carrier board 8K shown in FIG. 14-1, Then, the other carrier board (ie, the carrier board 8K shown in FIG. 14-1) is bonded to the second solder resist layer (95) through its bonding layer 8C1. In addition, the other carrier board can also be implemented as The carrier board 88 shown in FIG. 3 to FIG. 4 is used to avoid the warpage of the circuit board 51.

As shown in FIG. 8, it is a structural cross-sectional view of the circuit board 50 and the carrier board 80. The characteristics and symbols of the circuit board 50 and the carrier board 80 are the same as those of the circuit board 51 and the carrier board 80 in FIG. 7. The difference is that the solder mask layer 90 of the circuit board 50 has an opening 96 that penetrates the solder mask layer 90, and the opening 96 is provided corresponding to the end 3A of the line 30 and the opening 86 of the carrier board 80 so that The terminal 3A of the line 30 can be used for external electrical communication. At the same time, the convex portion 99 is provided on the upper surface 91 of the solder resist layer 90. The convex portion 99 of the solder resist layer 90 is accommodated in the opening 86 of the carrier board 80, and The convex portion 99 of the solder layer 90 is still joined with the opening 86 of the carrier plate 80 and the side wall 85. According to this, the solder resist layer 90 is joined with the lower surface 82 and the side wall 85 of the carrier plate 80, so that the carrier plate 80 and the The joint area and strength of the solder mask layer 90 can further prevent peeling damage between the carrier plate 80 and the solder mask layer 90, and the convex portion 99 of the solder mask layer 90 can be convex or flush with the upper surface 81 of the carrier plate 80, or At least a part of the convex part 99 of the solder resist layer 90 is not connected with the side wall 85 of the opening 86 of the carrier board 80, so that the carrier board 80 can be in electrical communication with the line 30 through the side wall 85 and tin or other conductors, and the upper surface of the carrier board 80 81 on demand The second solder resist layer (95) is bonded to protect the carrier board 80, wherein the second solder resist layer 95 may have a through-hole opening, and the through-hole opening is connected with the carrier board opening 86 and the solder resist layer. The opening 96 and the end point 3A are set correspondingly; it is known from the circuit boards 50 and 51 shown in FIGS. 1-1 to 8 that the upper surface 31 of the circuit 30 is covered with the solder resist layer 90, and can be changed or replaced. Circuits 30, 70 and / or carrier boards 80, 88, or additional components can make circuit boards 50, 51 more practical.

As shown in FIGS. 9-1 to 9-4, cross-sectional views of the manufacturing method of the package 10 are shown. First, as shown in FIG. 9-1, a circuit board 50 and a carrier board 8K are provided. Among them, the circuit board The structure and features of 50 are the same as the circuit board 50 in FIG. 3, please refer to the description in FIG. 3, and the carrier board 8K is composed of multiple components, and the structure and features of the carrier board 8K are the same as those of the carrier board 8K in FIG. 14-1. Please refer to the description of FIG. 14-1, in which the carrier plate 8K bonding layer 8C1 is bonded to the upper surface 91 of the solder resist layer 90, and the lower surface of the bonding layer 8C1 can be implemented as the lower surface 82 of the carrier plate 8K. The upper surface of the foil substrate 8A is implemented as the upper surface 81 of the carrier board 8K. Then, a wafer 20 is provided, and the wafer 20 is bonded to the circuit board 50. The wafer 20 of FIG. 9-1 is located on the upper surface 41 of the insulator 40. A conductive member 18 implemented as a wire, the two ends of the conductive member 18 are respectively connected to the terminal 24 of the chip 20 and the contact 324 of the circuit board 50 line 30, so that the chip 20 and the circuit board 50 are in electrical communication, and then, a plastic 60, a plastic 60 is provided. The surface of the wafer 20, the conductive member 18, and the circuit board 50 is encapsulated, and the package body 10 has been formed. The wafer 20 may also be It is implemented as the wafer 20 shown in FIG. 11-1, and the conductive member 18 can also be implemented as the conductive member 18 shown in FIG. 11-1. Among them, the bonding layer 8C1 of the carrier board 8K shown in FIG. 9-1 It can also be regarded as being implemented as a carrier board 80 (see Fig. 1-1). Based on this, the structure of the circuit board and the carrier board can be more useful and practical; And the removal process composed of FIG. 9-3, the carrier board 8K is removed. The description of this removal process is as follows. First, as shown in FIG. 9-2, the bonding layer of the copper foil 8C can be detached. The 8C1 and the separation layer 8C2 are separated, so that the separation layer 8C2, the curing adhesive 8B, and the copper foil substrate 8A are removed. According to this, only the bonding layer 8C1 (80) of the carrier board 8K is bonded to the solder resist layer 90. Among them, The bonding layer 8C1 (80) shown in FIG. 9-2 can also be regarded as being implemented as a carrier plate 80, and this removal process can be implemented by using machinery and equipment or manually and / or other applicable removal processes; Next, as shown in FIG. 9-3, the bonding layer 8C1 is removed, and at this point, the carrier board 8K is removed, so that the upper surface 91 of the solder resist layer 90 can be exposed to the atmosphere, and this FIG. 9- The bonding layer 8C1 of the 3 embodiment is transferred by an etching liquid. In addition, because the line 30 is completely encapsulated by the solder resist layer 90, the line 30 is not damaged or thinned by the attack of the etching solution; then, as shown in FIG. 9-4, a hole-opening process is provided. The hole process is implemented by means of laser or chemical solvent. A part of 90F of the solder resist layer 90 is removed, the reserved opening 9F is converted into an opening 96, and the end 3A of the line 30 can be connected for power supply. This embodiment The solder ball S is electrically connected, because the bonding area 3A4 located at the edge of the end point 3A is still bonded to the solder resist layer 90, so that the circuit 30 and the insulator 40 can be more firmly bonded together. According to this, when the solder ball When S is pulled by an external force F, it is difficult or not to cause layering or gap damage as shown in FIG. 14-4 between the lower surface 32 of the line 30 and the insulator 40, and the thickness T30 of the line 30 can be implemented more than that in FIG. 14 -1 The thickness T3 of the conventional circuit 35 is thinner, so that the thickness of the package body 10 can also be implemented to be thinner. Among them, a conductive layer (not shown) can be provided on the surface of the circuit 30 as required to facilitate For external electrical connection; In addition, in the embodiment shown in FIG. 9-1, the bonding layer 8C1 has a thickness T8C1. The thickness T8C1 of the layer 8C1 may be about 18 microns (or other applicable thickness), and the split layer 8C2 has a thickness T8C2, and the thickness T8C2 of the split layer 8C2 is about 3-5 microns (or other applicable thickness), By making the thickness T8C1 of the bonding layer 8C1 greater than the thickness T8C2 of the separation layer 8C2 (ie, T8C1> T8C2), the damage of the circuit board 50 can be avoided because a removal process is provided (see FIG. 9-2 and FIG. 9-3), because the thickness T8C1 of the bonding layer 8C1 is thicker than the thickness T8C2 of the split layer 8C2, the bonding layer 8C1 can be more firmly bonded to the solder resist layer 90. Accordingly, when the detachable copper When the bonding layer 8C1 of the foil 8C is separated from the separation layer 8C2, the bonding layer 8C1 can not be easily torn by the separation layer 8C2, so that the solder resist 90 (or even the circuit board 50) is not easily damaged, and the circuit board can be avoided. 50; among them, when the removal process is provided, if the bonding layer 8C1 is not damaged by the split layer 8C2, the thickness of the bonding layer 8C1 T8C1 may be smaller than the thickness of the split layer 8C2 T8C2 ( That is, T8C1 <T8C2).

As shown in Figs. 10-1 to 10-3, it is a cross-sectional view of the manufacturing method of the package body 10. First, as shown in FIG. 10-1, the structure of a circuit board 51 and a carrier board 88 is provided. The features and symbols of the circuit board 51 are the same as those of the circuit board 51 of FIG. 4, and the features and symbols of the carrier board 88 are the same as those of FIG. The carrier board 88 is the same, please refer to FIG. 3 and FIG. 4. Next, a wafer 20 is provided, and the wafer 20 is positioned on the upper surface 41 of the insulator 40 so that the wafer 20 is bonded to the circuit board 51. The conductive member 18, the two ends of the conductive member 18 are respectively connected to the terminal 24 of the wafer 20 and the circuit board 51 line 70, so that the wafer 20 and the circuit board 51 are in electrical communication, and then, a plastic 60 is provided to encapsulate the wafer 20 and the conductive member 18 And the circuit board 51, according to which the package body 10 has been formed; then, as shown in FIG. 10-2, a removal process is provided to remove the carrier board 88, and the removal process can be performed by mechanical grinding, laser, chemical Etching and / or other applicable removal procedures are implemented, so that the carrier board 88 (ie, the carrier board 80 and the adjustment layer 801) is separated from the circuit board 51, and the upper surface 91 of the solder mask layer 90 of the circuit board 51 is exposed to the atmosphere. Before removing the carrier plate 80, a hole-opening process may be provided first, and a blind hole 87 (dotted line) is opened in the adjustment layer 801. It is used to improve the efficiency of removing the carrier board 80 and / or adjust the curvature of the circuit board 51. Next, as shown in FIG. 10-3, a hole-opening process is provided to remove a portion 90F of the solder resist layer 90 so that The reserved opening 9F is converted into an opening 96, so that the terminal 3A of the line 30 can be used for power communication. Among them, the junction area 3A4 located at the edge of the terminal 3A is still connected to the solder resist 90, so that the line 30 and the insulator 40 are connected. It can be more firmly joined together. According to this, between the lower surface 32 of the line 30 and the insulator 40, it is difficult or not to cause the damage of the layering or gap as shown in Figure 14-4, and the opening process can be laser Or chemical etching and / or other applicable opening processes.

As shown in FIGS. 11-1 to 11-3, it is a cross-sectional view of the manufacturing method of the package body 10. First, as shown in FIG. 11-1, a circuit board 51 and a carrier board 80 structure are provided. The characteristics and symbols of the carrier plate 80 are the same as those in FIG. 6. Please refer to FIG. 6 for explanation. Next, a wafer 20 and a conductive member 18 implemented as a conductive bump are provided. The wafer 20 is implemented as a flip chip. ), The wafer 20 is bonded to the circuit board 51. The wafer 20 of FIG. 11-1 is located on the lower surface 42 of the insulator 40, and the two ends of the conductive member 18 are respectively bonded to the end point 24 of the wafer 20 and the circuit 30 of the circuit board 51. The chip 20 is electrically connected to the circuit board 51. Then, a plastic 60 is provided to encapsulate the surface of the chip 20, the conductive member 18, and the circuit board 51, and the package body 10 is formed. Then, as shown in FIG. 11-2 As shown, a removal process is provided to remove the carrier board 80. This removal process can be implemented by mechanical grinding, laser, chemical etching, and / or other applicable removal processes to separate the carrier board 80 from the circuit board 51, so that The upper surface 91 of the solder mask layer 90 of the circuit board 51 is exposed to the atmosphere. Since the circuit 30 is covered by the solder mask layer 90, the circuit 30 is not attacked by the etching solution. As a result, as shown in FIG. 11-3, a hole-opening process is provided to remove a portion 90F of the solder mask layer 90, so that the reserved hole 9F is converted into an opening 96, so that the end 30 of the line 30 is 3A. It is used for power supply connection, because the 3A4 located in the junction area 3 of the line 30 is still joined to the solder resist layer 90, so that the line 30 and the insulator 40 are more firmly joined together. According to this, the lower surface 32 of the line 30 and the insulation Between the edge bodies 40, it is difficult or not to cause the damage of layering or gaps as shown in FIG. 14-4, and this hole-opening process can be implemented by laser, chemical etching and / or other applicable hole-opening processes.

12-1 to 12-3 are cross-sectional views of a method for manufacturing the package 10. First, as shown in FIG. 12-1, a circuit board 51 and a carrier board 80 are first provided, and the circuit board 51 is provided. The structure and characteristics of the carrier board 80 are the same as those in FIG. 7. Please refer to FIG. 7 for explanation. Next, a wafer 20 is provided, and the wafer 20 is bonded to the circuit board 51. The wafer 20 shown in FIG. 12-1 is set on the insulator 40. Surface 41. Next, a conductive member 18 implemented as a wire is provided. The two ends of the conductive member 18 are respectively connected to the terminal 24 of the chip 20 and the circuit 30 of the circuit board 51, so that the chip 20 and the circuit board 51 are in electrical communication. Then, a plastic 60 is provided. The plastic 60 encapsulates the surface of the wafer 20, the conductive member 18, and the circuit board 51, and accordingly, the package body 10 has been formed; then, as shown in FIG. 12-2, a hole-opening process is provided to part of the solder resist layer 90 90F is removed, and the reserved opening 9F is converted into the opening 96, so that the terminal 3A of the line 30 can be used for power supply and communication. Among them, the junction area 3A4 located at the edge of the terminal 3A is still connected to the solder resist 90, so that The circuit 30 and the insulator 40 can be more firmly joined together. Accordingly, it is difficult or impossible for the lower surface 32 of the circuit 30 and the insulator 40 to be bonded together. As shown in Figure 14-4, the layer or gap is damaged. At the same time, at least a part of the opening 80 of the carrier board 86 and the side wall 85 can be exposed to the convex portion 99 of the solder resist layer 90 to open the carrier board 80 as required. The side wall 85 of the hole 86 can be in electrical communication with tin or other conductors. Then, as shown in FIG. 12-3, since the carrier board 80 can be implemented as a conductor, according to the requirements, as shown in FIG. 12-2, After the hole-opening process, a thin film 65 made of copper or nickel or other materials with electromagnetic shielding effect can be provided. The thin film 65 is set on the surface 6S of the plastic 60 and the side of the circuit board 51 by the process of bonding or coating or sputtering. The side 53 and the side 83 of the carrier board 80, wherein the package body 10 can increase the area of electromagnetic shielding by the carrier board 80 and improve the anti-electromagnetic interference effect. In addition, the upper surface 81 of the carrier board 80 can be joined with a second solder resist as required. Layer (see FIG. 7; reference number "95"), the second solder mask layer (95) is bonded to the upper surface 81 and the solder mask layer 90 of the carrier board 80, and the surface of the second solder mask layer (95) is further According to requirements, another carrier board can be bonded, as shown in the carrier board 8K shown in Figure 14-1. Among them, the other carrier board (ie, the carrier board 8K shown in Figure 14-1) is based on its bonding layer 8C1. With this The two solder resists (95) are joined. In addition, before the hole-opening process shown in FIG. 12-2 is performed, a removal process may be included, and the removal process is to move the other carrier board. In addition, after the removal process is completed and the hole-opening process is also completed, the second solder resist layer (95) is provided with a through-hole opening, and the through-hole opening is connected with the carrier plate opening 86, The solder mask opening 96 and the line terminal 3A are provided correspondingly.

13-1 to 13-3 are cross-sectional views of a method for manufacturing the package 10. First, as shown in FIG. 13-1, a circuit board 50 and a carrier board 88 are first provided, and the circuit board 50 is provided. The structure and features are the same as those of the circuit board 51 in FIG. 1-1, and the features and symbols of the carrier board 88 are the same as those of the carrier board 88 in FIG. 4, please refer to the description of FIGS. 1-1 and 4, and then provide the chip 20 and an implementation as Conduction of conductive bumps The electrical component 18 joins the chip 20 and the circuit board 50. The wafer 20 of FIG. 13-1 is located on the lower surface 32 of the circuit 30, and the two ends of the conductive member 18 are respectively connected to the end point 24 of the chip 20 and the circuit 30. The chip 20 is in electrical communication with the circuit board 50. Then, a plastic 60 is provided, which encapsulates the chip 20, the conductive member 18, and the circuit board 50. Based on this, the package body 10 is formed. Then, as shown in FIG. 13-2, A removal process is provided to remove the carrier board 88. The removal process can be implemented by mechanical grinding, laser, chemical etching, and / or other applicable removal processes to separate the carrier board 88 from the circuit board 50 and make the circuit board The upper surface 91 of the solder resist layer 90 is exposed to the atmosphere, and the adjustment layer 801 of the carrier plate 88 is also removed in this removal process. Then, as shown in FIG. 13-3, a hole-opening process is provided. The part 90F of the solder mask layer 90 is removed, and the reserved opening 9F is converted into the opening 96, so that the terminal 3A of the line 30 can be used for power supply and communication. The junction area 3A4 located at the edge of the line 30 is still connected to the The bonding layer 90 is bonded, so that the circuit 30 and the plastic 60 can be more firmly bonded together. According to this, the lower surface 32 of the circuit 30 and the plastic 60 are bonded together. For 60 rooms, it is difficult or impossible to cause layering or gap damage as shown in Figure 14-4, and this opening process can be implemented by laser and / or other applicable opening processes.

The above-mentioned FIGS. 1-1 to 13-3 are only examples of the method for manufacturing the circuit boards 50, 51, the carrier boards 80, 88, and the package 10 of the present invention. When the present invention cannot be limited in this way, as shown in FIG. 1- Any of the circuit boards 50 and 51 shown in 1 to 8 can be matched with any of the carrier boards 80 and 88 shown in Fig. 1-1 to Fig. 8 or the carrier board 8K shown in Fig. 9-1. The basic structure of the circuit board and the carrier board of the invention can reduce the thickness of the circuit board and the package body, thereby reducing the material and production costs, and reduce the damage of the layer or gap between the lower surface of the circuit and the insulator or plastic, and can Improve the quality of the circuit board; as shown in any of the package manufacturing methods shown in Figure 9-1 to Figure 13-3, you can match any of the circuit boards shown in Figure 1-1 to Figure 11-4 as required. , 51, and carrier plates 80, 88, or add other processes, such as: as described in Figure 0-1 and / or Figure 10-2, the opening process of the adjustment layer can be added to improve the efficiency of the manufacturing method, or Reduce production costs; therefore, any numerical change or equivalent component replacement, or equivalent changes and modifications made in accordance with the scope of the claims of the present application, should still be covered by the patent of the present invention Category.

Claims (39)

A circuit board and a carrier board structure. The circuit board is used for wafer bonding. The circuit board includes at least: a circuit and a solder mask; and the carrier board includes at least: a component; the circuit board and the carrier board are characterized by: This line is composed of at least one endpoint, and this line has an upper surface, a lower surface, and sides. The line is used for power transmission. The solder mask has reserved openings, upper surfaces, and lower surfaces. The reserved opening is composed of a part of the solder mask layer, and the reserved opening of the solder mask layer is set to correspond to the end of the line, the lower surface of the solder mask layer is connected to the upper surface of the circuit, and the solder mask layer is composed of an insulating material; And a carrier board, which has an upper surface, a lower surface, and side edges, and the lower surface of the carrier board is bonded to the upper surface of the solder resist layer, so that the surface of the carrier board is exposed to the atmosphere. The circuit board and carrier board structure described in item 1 of the scope of patent application, wherein the circuit of the circuit board has an extension portion, and the extension portion is disposed adjacent to the end point, so that the line is composed of the end point and the adjacent extension portion. The composition, wherein the upper surface of the end point is used for external electrical communication, and the edge region of the upper surface of the end point is implemented as a bonding area. For example, a circuit board and a carrier board structure described in item 1 of the scope of patent application, the circuit board further has an insulator, which has an upper surface, a lower surface, a side edge, and a through hole, and the lower surface of the insulator is bonded to the solder resist layer, and includes The lower surface of the line and the side of the line are covered, and the insulator through-holes are provided corresponding to the lower surface of the line. The area where the lower surface of the line and the insulator through-holes are provided is implemented as a contact, and this contact is exposed in the insulator through-hole. For external electrical connection. According to a circuit board and a carrier board structure described in item 3 of the scope of the patent application, the circuit board further includes a second circuit, the second circuit has an upper surface, a lower surface, a side edge, and a convex portion, wherein the convex portion is provided at The lower surface, and the lower surface of the second circuit is bonded to the upper surface of the insulator, so that the convex portion is accommodated in the through hole of the insulator, so that the second circuit is in electrical communication with the line contact by the convex portion. The circuit board and the carrier board structure described in item 1 of the scope of the patent application, wherein the carrier board further includes an adjustment layer, so that the carrier board is composed of multiple components, and the adjustment layer is connected with the carrier board to make adjustments. The surface of the layer exposed in the atmosphere is implemented as the upper surface of a carrier board. The circuit board and the carrier board structure described in item 5 of the scope of the patent application, wherein the adjustment layer of the carrier board has a blind hole, and the blind hole is provided corresponding to the line, and the blind hole has a width and a depth. A circuit board and a carrier board structure described in item 1 of the scope of the patent application, wherein the carrier board is composed of a plurality of components, and the carrier board is made of at least a copper foil substrate, cured glue and detachable copper foil The copper foil substrate is composed of two copper foils and an adhesive. The adhesive is interposed between the two copper foils. The detachable copper foil is composed of two copper foils and a thin film layer. Two copper foil Bonded together and the thin film layer is between two copper foils, wherein one copper foil bonded to the thin film layer is implemented as a bonding layer, and the other copper foil bonded to the thin film layer is implemented as a split Layer, and the split layer is combined with the copper foil substrate by the curing glue, and the carrier plate is connected with the solder resist layer by its bonding layer. The circuit board and the carrier board structure described in item 7 of the scope of the patent application, wherein the bonding layer has a thickness and the split layer has a thickness such that the thickness of the bonding layer is greater than the thickness of the split layer. The circuit board and the carrier board structure described in item 1 of the scope of the patent application, wherein the carrier board has openings, the openings are implemented as through-holes, and the openings have side walls. The openings and the solder mask are Corresponding opening holes and line end points are provided correspondingly. Among them, the solder resist layer further has a convex portion, which is accommodated in the opening of the carrier board and is connected with the side wall of the opening. A circuit board and a carrier board structure as described in item 9 of the scope of application for a patent, which further includes a second solder mask layer, and the second solder mask layer is bonded to the surface of the carrier board and the solder mask layer. . A circuit board and a carrier board structure as described in item 10 of the scope of the patent application, which further includes another carrier board, and the other carrier board is made of at least a copper foil substrate, a cured glue, and a detachable copper foil. The copper foil substrate is composed of two layers of copper foil and an adhesive, wherein the adhesive is between the two copper foils, and the detachable copper foil is composed of two copper foils and a thin film layer. The film Layer is to join two copper foils together and make the thin film layer be between two copper foils, wherein one copper foil joined to the thin film layer is implemented as a bonding layer and the other is joined to the thin film layer The copper foil is implemented as a separation layer, and the separation layer is combined with the copper foil substrate by a curing glue, and the other carrier board is bonded to the second solder resist layer by a bonding layer. The circuit board and the carrier board structure described in item 11 of the scope of the patent application, wherein the bonding layer has a thickness and the split layer has a thickness such that the thickness of the bonding layer is greater than the thickness of the split layer. The circuit board and the carrier board structure described in item 1 of the scope of patent application, wherein the thickness of the circuit board is ≦ 30 microns. The circuit board and the carrier board structure described in item 1 of the scope of patent application, wherein the thickness of the circuit board circuit is ≦ 10 μm. The circuit board and the carrier board structure described in item 3 of the scope of patent application, wherein the thickness of the circuit board insulator is ≦ 30 μm. The circuit board and the carrier board structure described in item 1 of the scope of the patent application, wherein the solder mask of the circuit board is a side of the circuit. For example, a circuit board and a carrier board structure described in item 16 of the scope of the patent application. The circuit board further includes an insulator and a second circuit. The insulator has an upper surface, a lower surface, and a through hole. The insulator is bonded to the lower surface of the solder mask. , And cover the lower surface of the line, where the insulator through hole and the line below The surface is provided correspondingly, so that a part of the lower surface of the line is exposed in the insulator through hole, and the part of the lower surface of the line that is exposed in the insulator through hole is implemented as a contact, and this contact is used for power supply and communication; the second circuit has an upper surface , The lower surface, the side and the convex portion, the convex portion is provided on the lower surface of the second circuit, and the lower surface of the second circuit is joined to the upper surface of the insulator, wherein the convex portion of the second circuit is accommodated in the insulator through hole, and The second line is connected to the line contact and is in electrical communication. The second line is used for power transmission. According to a circuit board and a carrier board structure described in item 16 of the scope of application for a patent, the circuit board further includes an insulator and a second circuit, wherein the circuit further has a convex portion, and the convex portion is located on the lower surface of the circuit. The second circuit has an upper surface, a lower surface, and a side, wherein a part of the lower surface of the second circuit is implemented as a contact, the insulator has an upper surface, a lower surface, and a through hole, and the insulator is connected to the lower surface of the solder resist layer and The lower surface of the circuit is bonded, wherein the second circuit is located on the upper surface of the insulator, the insulator covers the lower surface of the second circuit and its sides, and the upper surface of the second circuit is exposed on the upper surface of the insulator. The contacts of the line are exposed in the insulator through-holes, and the convex portions of the lines are located in the through-holes, so that the convex portions of the lines are in electrical communication with the contacts of the second line. A circuit board and a carrier board structure. The circuit board is used for wafer bonding. The circuit board includes: a circuit and a solder mask; and the carrier board includes at least: a component; the characteristics of the circuit board and the carrier board structure are: This line is composed of at least one end, and this line has an upper surface, a lower surface, and sides. The line is for power transmission; a solder mask has an upper surface, a lower surface, a convex portion, and an opening. The convex part is located on the upper surface of the solder mask layer. This opening is a penetration of the solder mask layer. The solder mask layer is composed of an insulating material. The lower surface of the solder mask layer is connected to the upper surface of the circuit, and the end of the line and the solder mask layer are opened. Correspondingly set; and a carrier plate having an upper surface, a lower surface, an opening and a side edge, the opening has a side wall, and the lower surface of the carrier plate is joined with the upper surface of the solder resist layer, wherein the convex portion of the solder resist layer It is accommodated in the opening of the carrier board, and the convex part of the solder mask layer is connected to the side wall of the opening of the carrier board. This solder mask opening is provided corresponding to the end point of the circuit and the opening of the carrier board, so that the circuit The endpoint is used for external electrical connection. According to a circuit board and a carrier board structure described in item 19 of the scope of the patent application, the circuit board further includes an insulator having an upper surface, a lower surface, a side edge and a through hole, and the lower surface of the insulator is bonded to the solder resist layer, and The lower surface of the line and the side of the line are covered, and the insulator through-holes are provided corresponding to the lower surface of the line. The area where the lower surface of the line and the insulator through-hole are provided is implemented as a contact, and this contact is exposed in the insulator through-hole. For external electrical connection. For example, a circuit board and a carrier board structure described in item 20 of the scope of patent application, the circuit board further includes a second circuit, the second circuit has an upper surface, a lower surface, a side edge, and a convex portion, wherein the convex portion is provided at The lower surface, and the lower surface of the second circuit is bonded to the upper surface of the insulator, so that the convex portion is accommodated in In the through hole of the insulator, the second line is electrically connected to the line through the convex portion. A method for manufacturing a package includes the following steps: Step 1: providing a circuit board and a carrier board structure, the circuit board having a circuit and a solder mask, wherein the circuit has an upper surface, a lower surface, and sides, and the circuit is at least It consists of an end point. The solder mask has an upper surface, a lower surface, a side edge and a reserved opening. The lower surface of the solder protection layer is connected to the upper surface of the circuit, and the reserved opening is provided corresponding to the end of the circuit. The carrier board has an upper surface, a lower surface, and side edges. The lower surface is bonded to the upper surface of the solder resist layer, so that the surface of the carrier board is exposed to the atmosphere. Step 2: Provide the chip, conductive parts, and plastic. The board is bonded, and the chip is electrically connected to the circuit board, and then the plastic is coated with the wafer, the conductive member and the circuit board; Step 3: Provide a removal process to remove the carrier board and expose the solder mask of the circuit board to In the atmosphere: and Step 4: Provide an opening process to convert the reserved openings in the solder mask layer into openings, so that the endpoints of the line can be electrically connected to the outside. The method for manufacturing a package according to item 22 of the scope of patent application, wherein, in step 1, the carrier board further has an adjustment layer, and the carrier board is composed of multiple components. The adjustment layer and the carrier The board is bonded, and the adjustment layer is removed in step three. The method for manufacturing a package according to item 23 of the scope of patent application, wherein the adjustment layer has a blind hole, and the blind hole has a width and a depth. The method for manufacturing a package according to item 22 of the scope of the patent application, wherein the solder mask of the circuit board covers the side of the circuit. According to a method for manufacturing a package as described in claim 22 of the scope of patent application, the circuit board further has an insulator having an upper surface, a lower surface, a side edge, and a through hole. The lower surface of the insulator is bonded to the solder resist layer, and the circuit is covered. The lower surface and the side, wherein the through hole of the insulator is provided corresponding to the lower surface of the line, so that a part of the lower surface of the line is exposed in the through hole of the insulator, and the area where the lower surface of the line is exposed in the through hole of the insulator is implemented as a contact. It is used for external electrical connection, and the upper surface of the insulator is joined with plastic. According to a method for manufacturing a package as described in item 26 of the scope of patent application, the circuit board further includes a second circuit, and the second circuit has an upper surface, a lower surface, a side edge, and a convex portion, wherein the convex portion is provided at the lower portion. Surface, and the lower surface of the second circuit is bonded to the upper surface of the insulator, so that the convex portion is accommodated in the insulator through hole, so that the second circuit is in electrical communication with the circuit by the convex portion. The method for manufacturing a package according to item 22 of the scope of patent application, wherein the carrier board is composed of a plurality of components, and the carrier board is made of at least a copper foil substrate, a curing glue and a detachable copper foil stack. The copper foil substrate is composed of two copper foils and an adhesive, wherein the adhesive is between Between two copper foils, the detachable copper foil is composed of two copper foils and a thin film layer. The thin film layer joins the two copper foils together, and the thin film layer is interposed between the two copper foils. One copper foil bonded to the thin film layer is implemented as a bonding layer, and the other copper foil bonded to the thin film layer is implemented as a split layer, and the split layer is combined with the copper foil substrate by a curing glue. The bonding layer is bonded to the solder mask. The method for manufacturing a package according to item 28 of the scope of the patent application, wherein the bonding layer has a thickness and the split layer has a thickness such that the thickness of the bonding layer is greater than the thickness of the split layer. The method for manufacturing a package according to item 25 of the scope of patent application, wherein the circuit board further includes an insulator and a second circuit, the insulator has an upper surface, a lower surface and a through hole, and the insulator and the lower surface of the solder resist layer Bonding and covering the lower surface of the line, wherein the insulator through-hole is provided corresponding to the lower surface of the line, so that a part of the lower surface of the line is exposed in the insulator through-hole, and the part of the lower surface of the line exposed in the insulator through-hole is implemented as a connection The second line has an upper surface, a lower surface, a side edge, and a convex portion, and the convex portion is located on the lower surface of the second line, and the lower surface of the second line is bonded to the upper surface of the insulator, Wherein, the convex part of the second line is accommodated in the through hole of the insulator, and the second line is connected with the line contact to be electrically connected, and the second line is used for power transmission. According to a method for manufacturing a package as described in claim 25 of the scope of patent application, the circuit board further includes an insulator and a second circuit, wherein the circuit further has a convex portion, which is located on the lower surface of the circuit. The second circuit has an upper surface, a lower surface, and a side. Among them, a part of the lower surface of the second circuit is implemented as a contact. The insulator has an upper surface, a lower surface, and a through hole. The insulator is connected to the lower surface of the solder resist layer and the circuit. The lower surface is bonded, wherein the second circuit is provided on the upper surface of the insulator, the insulator covers the lower surface of the second circuit and its sides, and the upper surface of the second circuit is exposed on the upper surface of the insulator. The contacts of the circuit board are exposed through the insulator through-holes, and the line convex portions are located in the through-holes, and accordingly, the line convex portions and the contacts of the second line are electrically connected. A method for manufacturing a package includes the following steps: providing a circuit board and a carrier board structure, the circuit board having a circuit and a solder mask, wherein the circuit is composed of at least one end point, and the circuit has an upper surface, Lower surface and sides; the solder mask layer has an upper surface, a lower surface, a side edge, a reserved opening and a convex portion, and the convex portion is provided on the upper surface of the solder mask layer, wherein the lower surface of the solder mask layer is connected to the upper surface of the circuit And the solder mask is provided with an opening corresponding to the end of the line, the solder mask is composed of an insulating material; the carrier board has an upper surface, a lower surface, sides and openings, and the opening has a side wall, under the carrier board The surface is joined with the solder mask layer, and the opening of the carrier board is set corresponding to the reserved opening of the solder mask layer and the end point of the line. Among them, the convex part of the solder mask layer is accommodated in the opening of the carrier board and The side walls of the openings of the carrier board are joined, so that the solder mask is connected to the lower surface of the carrier board. And the side wall of the opening of the carrier board; Step 2: Provide the chip, conductive member and plastic, first connect the chip to the circuit board, and make the chip and the circuit board electrically communicate, and then cover the chip, the conductive member and the circuit board with plastic ; And step three: providing an opening process to convert the reserved blind hole of the solder mask layer into an opening, so that the end of the line can be electrically connected to the outside. The method for manufacturing a package according to item 32 of the scope of the patent application, wherein after step 3 is completed, at least a part of the protruding portion of the solder mask layer of the circuit board is not joined to the side wall of the opening of the carrier board. The method for manufacturing a package according to item 32 of the scope of patent application, wherein the circuit board solder resist layer covers the side of the circuit. The method for manufacturing a package according to item 32 of the scope of patent application, wherein after step 3 is completed, a film with electromagnetic shielding effect is provided, and the film is disposed on a plastic surface, a circuit board side, and a carrier board side. The method for manufacturing a package as described in claim 32 of the scope of patent application, wherein the structure of the circuit board and the carrier board further includes a second solder mask layer and another carrier board, the second solder mask layer and The upper surface of the carrier board is bonded, and this other carrier board is at least composed of a copper foil substrate, a cured adhesive, and a detachable copper foil stack. The copper foil substrate is composed of two layers of copper foil and an adhesive, wherein the adhesive is Interposed between two copper foils, the detachable copper foil is composed of two copper foils and a thin film layer. The thin film layer joins the two copper foils together, and the thin film layer is interposed between the two copper foils. Among them, A copper foil bonded to the thin film layer is implemented as a bonding layer, and another copper foil bonded to the thin film layer is implemented as a split layer, and the split layer is combined with the copper foil substrate by a curing glue. The other carrier board is bonded to the second solder resist layer by a bonding layer. The method for manufacturing a package according to item 36 of the scope of the patent application, wherein the bonding layer has a thickness and the split layer has a thickness such that the thickness of the bonding layer is greater than the thickness of the split layer. The method for manufacturing a package according to item 36 of the scope of patent application, wherein after the step 2 is completed and before the step 3 is performed, the method further includes a removing step, and the removing step is to remove the other Carrier board removed. The method for manufacturing a package according to item 38 of the scope of patent application, wherein after the removal process is completed and after step 3 is completed, the second solder resist layer has a through-hole opening, and the through The openings are arranged corresponding to the openings of the carrier board, the openings of the solder mask layer and the end points of the line.