TW201903908A - Semiconductor package structure manufacturing method - Google Patents

Abstract

The prevent invention provides a manufacturing method of semiconductor packaging structure which comprising the steps of providing a plurality of lead frame units each including an inner pin portion and an outer pin portion, respectively. A plurality of inner lead portions, a first bonding material, a wafer, a second bonding material, and a heat sink are sequentially disposed in a plurality of receiving spaces of the first mold. Heating connection the lead frame units, the wafers and the heat sinks. Performing a package step, to cover the inner lead portions of the lead frame units, the wafers and a part of the heat sinks with an encapsulate colloid. Cutting off an interconnected portion of the outer pin portions.

Description

 Semiconductor package structure manufacturing method  

The present invention relates to a method of fabricating a semiconductor package structure, and more particularly to a method of fabricating a semiconductor package structure capable of effectively improving a process yield by sequentially connecting an inner lead portion of a leadframe unit, a wafer, and a heat sink.

Integrated circuits are typically designed to operate over a normal voltage range. However, in the case of, for example, electrostatic discharge (ESD), the voltage rapidly transients, and it is not expected at this time that an uncontrollable high voltage may accidentally break down the circuit. In the case of such a damage condition in which an integrated circuit is subjected to an excessive load voltage, a Transient Voltage Suppressor (TVS) is required to provide a protection function. Among them, some TVS applications must handle relatively high voltages (semiconductor devices that exceed 100 VAC, such as RMS voltages of 265 VAC or 415 VAC, etc.) in a relatively dense space. In view of the fact that such TVS components often need to consume considerable power and thus generate a large amount of thermal energy, the TVS wafer is typically mounted to a heat sink and electrically connected to the circuitry of the electronic device through the heat sink.

Take the DO-218 (AB) component released by the JEDEC Solid State Technology Association as an example. The existing TVS semiconductor process often connects a chip to a heat sink first, then one. The lead frame is connected to the wafer by means of reflow or the like, and after the integral package is completed, the lead frame unit is cut and bent to form an electrical connection between the external circuit and the external circuit. a contact. In the foregoing prior art process, in the step of connecting the lead frame unit and the wafer, the lead frame unit is often displaced, so that the electrical/thermal connection between the lead frame unit and the wafer is poor, which seriously affects the process yield. . As can be seen from the above description, it is obviously necessary to further improve the existing process.

The technical problem to be solved by the present invention is to provide a method for fabricating a semiconductor package structure in view of the deficiencies of the prior art, so that the process yield of the semiconductor package structure can be improved by the method.

In order to solve the above technical problem, one of the technical solutions adopted by the present invention is to provide a method for fabricating a semiconductor package structure, comprising the steps of: providing a plurality of lead frame units, wherein each of the lead frame units respectively includes a An inner lead portion and an outer lead portion, wherein the plurality of outer lead portions are connected to each other; and the plurality of the inner lead portions of the plurality of lead frame units are respectively placed in a plurality of first molds Locating a first bonding material on a top surface of the inner lead portion; placing a wafer on a top surface of the first bonding material; placing a second bonding material on the wafer a top surface; a heat sink is disposed on a top surface of the second bonding material; heating is performed to interconnect the lead frame unit and the wafer through the first bonding material, and the wafer is The heat sinks are connected to each other by the second adhesive material; the lead frame unit, the wafer and the heat sink connected to each other are placed in a second mold, so that the inner lead of the lead frame unit Foot, the crystal And a partial body is covered with a package of the heat sink; and a truncated portion of the outer lead portions interconnected to one another. In this way, since the lead frame unit and the wafer are connected first in the foregoing process, and the heat sink and the wafer are connected to each other, the lead frame unit, the wafer, and the heat sink are connected to each other. During the process, the stability of the connection process can be improved by the weight of the heat sink itself, and the offset phenomenon can be avoided, thereby improving the yield of the produced semiconductor package structure.

Further, the accommodating space has a difference portion, the step portion divides the accommodating space into an upper layer space and a lower layer space, and the lead frame unit and the wafer are placed in the lower layer space The heat sink is placed in the upper space. In this way, the upper layer space and the lower layer space distinguished by the step portion can avoid the heat sink seat located in the upper layer space in the foregoing process, and the opposite position in the lower layer space The lead frame unit and the wafer cause excessive compression, and the lead frame unit or the wafer can be prevented from being damaged or deformed.

Further, the height of the step portion is smaller than an overall height of the lead frame unit, the first bonding material, the wafer, and the second bonding material before the heating step, and the step portion The height is greater than the leadframe unit after the heating step, the first bonding material, and the overall height of the wafer. Thus, by appropriately designing the height of the step portion, it is ensured that the heat sink is made before the heat sink is placed in the upper space before the heat sink and the wafer are interconnected. The second bonding material can be surely contacted to avoid poor electrical/thermal connection between the heat sink and the wafer, and further, after the interconnection between the heat sink and the wafer is performed, It is ensured that the leadframe unit or the wafer is not excessively pressed by the heat sink, and the leadframe unit or the wafer can be prevented from being damaged or deformed.

Further, before the step of placing the plurality of the inner lead portions into the plurality of the accommodating spaces, the method further includes: bending an extension portion of the inner lead portion to make the The extension portion is formed with a first bending portion and a second bending portion, the second bending portion is interposed between the first bending portion and the outer lead portion, and the extension portion further comprises a a side wing portion, wherein the side wing portion is located at one side of the second bent portion and extends toward a direction perpendicular to the second bent portion. In this way, when the package body covers the inner lead portion, the bonding between the package body and the lead frame unit can be more stabilized, and the outer lead portion can be bent later. During the process, the first bending portion and the second bending portion of the lead frame unit prevent the pulling stress generated by the external force applied to the contact portion, affecting the lead frame unit and the The connection relationship between the wafers. Further, the degree of coupling stability between the lead frame unit and the package can be further increased by the mutual insertion of the side flap portions provided in the extension portion with the package.

Further, the first bonding material and the second bonding material are solder bumps. As such, the leadframe unit and the wafer may be interconnected by the first bonding material by a heating step, and the wafer and the heat sink may be interconnected by the second bonding material.

Still further, the step of providing a plurality of leadframe units includes stamping a metal strip to form the plurality of leadframe units, wherein the metal strip has a uniform thickness. Thus, compared with the prior art, a multi-piece, different thickness web or metal profiled material is used to fabricate the lead frame unit, and the metal strip having a uniform thickness can be made in a relatively simple manner to meet relevant specifications. Standardized products can effectively improve the competitiveness of products.

Further, after the step of cutting off the portions where the outer lead portions are connected to each other, the method further includes the step of bending the outer lead portion to form the outer lead portion to form a Contact part. In this way, the contact portion can be electrically connected to the external circuit.

In order to solve the above technical problem, another technical solution adopted by the present invention is to provide a method for fabricating a semiconductor package structure, comprising the steps of: providing a lead frame unit, wherein the lead frame unit includes an inner lead And an outer lead portion; a mold is provided, the mold has an accommodating space, and the accommodating space includes an upper layer space and a lower layer space; and the inner lead portion is sequentially followed by a material, a wafer is placed in the lower layer space; a second bonding material is placed on the wafer, wherein the second bonding material is partially or completely located in the upper layer space; a heat sink is placed in the upper layer And contacting the second bonding material in a space; performing a heating step to connect the lead frame unit, the wafer and the heat sink to each other; and performing a packaging step to make the lead frame unit The inner lead portion, the wafer, and a portion of the heat sink are covered by a package. In this way, in the foregoing process, the lead frame unit and the wafer are first placed in the lower layer space, and the heat sink is placed in the upper space, and the lead frame unit and the The wafer is connected to the heat sink, and during the process of connecting the lead frame unit, the wafer and the heat sink, the connection process can be made by the weight of the heat sink itself located in the upper space. The stability is improved to avoid the occurrence of offset phenomenon, thereby effectively improving the yield of the semiconductor package structure produced.

Further, wherein the heating step comprises: performing a first heating step to pass the lead frame unit and the wafer before the step of placing the second bonding material on the wafer The first bonding materials are connected to each other; and after the step of placing the heat sink into the upper space, performing a second heating step to pass the wafer and the heat sink through the second bonding material connection. In this way, by the two heating connection steps, the total height change of the first adhesive material and the second adhesive material can be prevented from being excessively changed, so that the stability of the joining process can be increased, and the yield of production can be further improved.

Further, wherein the semiconductor package structure is a package structure of a transient voltage suppressor.

One of the beneficial effects of the present invention is that the semiconductor package structure of the present invention can be fabricated by "putting the heat sink over the wafer and the inner lead portion of the lead frame unit The technical solution is such that the stability of the lead frame unit, the wafer and the heat sink can be mutually connected during the connection process by the weight of the heat sink itself, and the stability is prevented from occurring. The offset phenomenon can effectively improve the yield of the semiconductor package structure produced.

For a better understanding of the features and technical aspects of the present invention, reference should be made to the accompanying drawings.

Z‧‧‧Semiconductor package structure

1‧‧‧ lead frame unit

11‧‧‧Inside pin section

111‧‧‧ wafer connection

112‧‧‧Extension

113‧‧‧Flanking

12‧‧‧External lead

12'‧‧‧Contacts

A‧‧‧First bend

B‧‧‧Second bend

C‧‧‧Fixed through hole

2‧‧‧ wafer

3‧‧‧ Heat sink

4‧‧‧ First follow-up material

5‧‧‧second follow-up material

6‧‧‧First mould

61‧‧‧ accommodating space

611‧‧‧Upper space

612‧‧‧Under space

62‧‧‧Departure

7‧‧‧Package

H1‧‧‧ first height

H2‧‧‧second height

H3‧‧‧ third height

M‧‧‧Metal strip

1 is a schematic exploded view of a lead frame unit, a wafer, and a heat sink and a first mold according to an embodiment of the present invention.

2 is a partial perspective view of a first mold according to an embodiment of the present invention.

3 is a cross-sectional view showing the lead frame unit, the wafer, and the heat sink of the embodiment of the present invention before being connected to each other.

4 is a cross-sectional view showing the lead frame unit, the wafer, and the heat sink of the embodiment of the present invention connected to each other.

FIG. 5 is a perspective view of a semiconductor package structure according to an embodiment of the present invention.

FIG. 6 is a flow chart of a method of fabricating a semiconductor package structure according to an embodiment of the present invention.

FIG. 7 is another exploded view of a lead frame unit, a wafer, and a heat sink according to an embodiment of the present invention.

The embodiments of the present invention relating to the "method of fabricating a semiconductor package structure" are described by way of specific embodiments, and those skilled in the art can understand the advantages and effects of the present invention from the disclosure of the present specification. The present invention may be carried out or applied in various other specific embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention. In addition, the drawings of the present invention are merely illustrative and are not intended to be stated in the actual size. The following embodiments will further explain the related technical content of the present invention, but the disclosure is not intended to limit the scope of the present invention.

[Examples]

Please refer to the component symbols shown in FIG. 1 to FIG. 5 and FIG. 7 and refer to the flowchart shown in FIG. 6. The present invention provides a method of fabricating a semiconductor package structure Z (shown in FIG. 5), which includes the following steps. First, as shown in FIG. 1 and FIG. 6, FIG. 1 provides a metal strip M and is stamped by a metal strip. M to form a plurality of lead frame units 1 (step S100). Each of the lead frame units 1 includes an inner lead portion 11 and an outer lead portion 12, and the plurality of outer lead portions 12 are connected to each other. As shown in FIG. 7, the inner lead portion 11 includes a wafer connecting portion 111 and an extending portion 112. In the preferred embodiment of the present invention, after the metal strip M is stamped to form a plurality of lead frame units 1, The extending portion 112 of the inner lead portion of the lead frame unit 1 is bent so that the extending portion 112 is formed with the first bent portion A and the second bent portion B (step S102).

Furthermore, please refer to FIG. 7 again. In the preferred embodiment of the present invention, in the foregoing step S100, when the metal strip M is stamped to form a plurality of lead frame units 1, one of the extensions 112 The side also includes a side wing 113. Specifically, the side flap portion 113 is located on one side of the second bent portion B and extends in a direction perpendicular to the second bent portion B, and further, the position corresponding to the side flap portion 113 on the extending portion 112 can be fixed. Through hole C. However, it should be particularly noted that the present invention is not limited to the above-described method. In actual application, the side flap portion 113 may not be provided, or the extension portion 112 may not be bent into the first bent portion A and the second portion. The bent portion B, or the fixed through hole C may not be formed on the extending portion 112. The foregoing technical features are all necessary technical features that are indispensable for the main purpose of the present invention in order to further enhance the achievable effects of the present invention. .

Incidentally, in the preferred embodiment of the invention, the metal strips M have substantially the same thickness, in other words, they have a uniform thickness. Therefore, the preferred embodiment of the present invention uses a metal strip M having a uniform thickness, which can be compared with the prior art, in which the multi-piece, different-thickness web or metal profiled material is used to fabricate the lead frame. It is easy to make products that meet the relevant specifications and specifications, so it can effectively improve the competitiveness of the products.

Referring to FIG. 1 and FIG. 6 again, after completing the foregoing steps S100 and S102, the plurality of inner lead portions 11 of the plurality of lead frame units 1 are respectively placed in the plurality of accommodating spaces of the first mold 6. 61 (step S104).

The structure of the first mold 6 and the plurality of accommodating spaces 61 of the first mold 6 will be further described below. Referring to FIG. 2, in the preferred embodiment of the present invention, the accommodating space 61 has a step portion 62, and the step portion 62 divides the accommodating space 61 into an upper space 611 and a lower space 612, in the foregoing step S104. The inner lead portion 11 of the lead frame unit 1 is placed in the lower space 612.

Referring to FIG. 2, FIG. 3, FIG. 4 and FIG. 6, after completing the foregoing step S104, a plurality of first bonding materials 4, a plurality of wafers 2, a plurality of second bonding materials 5, and a plurality of The heat sinks 3 are respectively placed in the plurality of accommodating spaces 61 of the first mold 6 (step S106). In detail, the first bonding material 4 is placed on the top surface of the wafer connection portion 111 of the inner lead portion 11, and the wafer 3 is placed on the top surface of the first bonding material 4; then, the second bonding material 5 is Placed on the top surface of the wafer 3 and the heat sink 3 is placed on the top surface of the second subsequent material 5. In a preferred embodiment of the invention, the first bonding material 4 and the second bonding material 5 are solder bumps. Therefore, the lead frame unit 1 and the wafer 2 can be connected to each other by the first bonding material 4 by the heating step, and the wafer 2 and the heat sink 3 can be connected to each other by the second bonding material 5. The foregoing heating step may be performed at one time, or the first bonding material 4 (first heating step) may be heated before the step of placing the second bonding material 5 on the wafer 2 to interconnect the lead frame unit 1 and the wafer 2. Then, the second bonding material 5 and the heat sink 3 are placed, and after the step of placing the heat sink 3 into the upper space 611, the lead frame unit 1, the wafer 2, and the heat sink are reflowed (second heating step). The seats 3 are connected to each other. It should be noted that the first bonding material 4 and the second bonding material 5 may also be selected from other materials capable of providing an electric/thermal connection effect at the same time.

Referring to FIG. 2, FIG. 3, FIG. 4 and FIG. 6, in the preferred embodiment of the present invention, the lead frame unit 1 and the wafer 2 are placed in the lower space 612 of the first mold 6, and the heat is dissipated. The seat 3 is placed in the upper space 611 of the first mold 6, and the second adhesive material 5 is completely located in the upper space 611, or partially located in the upper space 611 and partially in the lower space 612. In addition, referring to FIG. 3, the height (the first height H1) of the step portion 62 is smaller than the overall height of the lead frame unit 1, the first bonding material 4, the wafer 2, and the second bonding material 5 before the heating step. (second height H2), and the height of the step portion 62 is larger than the lead frame unit 1, the first bonding material 4, and the overall height (third height H3) of the wafer 2 after the heating step. As such, since the first height H1 (ie, the height of the step portion 62) is smaller than the second height H2 (ie, the lead frame unit 1, the first bonding material 4, the wafer 2, and the second bonding material 5 before the heating step is performed) Therefore, before the heating step, it is ensured that the second bonding material 5 can be surely and directly contacted after the heat sink 3 is placed in the upper space 611, thereby preventing the heat sink 3 from being in sufficient contact. Second, the material 5 is followed, resulting in poor electrical/thermal connection between the heat sink 3 and the wafer 2; moreover, since the first height H1 (ie, the height of the step portion 62) is greater than the third height H3 (the lead frame unit 1) The first bonding material 4 and the overall height of the wafer 2), therefore, after the interconnection between the heat sink 3 and the wafer 2 is performed, the heat sink 3 can abut against the top surface of the step portion 62, and can be further ensured The lead frame unit 1 and/or the wafer 2 are not excessively pressed by the heat sink 3, whereby the lead frame unit 1 or the wafer 2 can be prevented from being damaged or deformed accordingly.

Next, please refer to FIG. 1, FIG. 5 and FIG. 6. After completing the foregoing step S106, a packaging step is performed to make the inner lead portion 11, the wafer 2 and the heat sink 3 of the lead frame unit 1 partially The package 7 is covered. Specifically, the lead frame unit 1, the wafer 2, and the heat sink 3 that are connected to each other are placed in a second mold (not shown), and an encapsulating material such as epoxy resin is injected to perform the lead frame unit 1 A step of packaging the wafer connection portion 111, the wafer 2, and a portion of the heat sink 3 covered by the package 7 (step S108). After the foregoing steps are completed, the portions where the outer lead portions 12 are connected to each other are cut off, and the outer lead portions 12 are bent so that the outer lead portions 12 form the contact portions 12' (step S110). Accordingly, the fabrication of the semiconductor package structure Z of the present invention is completed by the aforementioned steps S100 to S110. In the preferred embodiment of the present invention, the semiconductor package structure Z is a package structure of a transient voltage suppressor, but the invention is not limited thereto.

In the above manufacturing method, the lead frame unit 1 and the wafer 2 are connected first, and the heat sink 3 and the wafer 2 are connected to each other. Therefore, in the process in which the lead frame unit 1, the wafer 2, and the heat sink 3 are connected to each other, Through the weight of the heat sink 3 itself, a downward pressure is firmly applied, so that the stability of the overall structure is improved during the entire interconnection process, and the phenomenon of offset can be effectively avoided, thereby effectively improving the semiconductor package structure produced. The yield of Z enables a good electrical/thermal connection between the wafer connection portion 111 and the wafer 2, or between the wafer 2 and the heat sink 3.

It should be noted that, as shown in FIG. 5, FIG. 6 and FIG. 7, as in the foregoing, in the preferred embodiment of the present invention, when the metal strip M is stamped to form a plurality of lead frame units 1, The extending portion 112 of the inner lead portion is bent to form the first bent portion A and the second bent portion B, and the extending portion 112 further includes a side of the second bent portion B and faces perpendicular to the second bend The side flap portion 113 extending in the direction of the folded portion B.

Accordingly, the first bent portion A and the second bent portion B formed on the extending portion 112 can be used to wrap the inner lead portion 11 between the package body 7 and the lead frame unit 1 when the inner lead portion 11 is covered by the package 7. The combination is more stable, and in the process of bending the subsequent outer lead portion 12 (ie, the foregoing step S110), the first bent portion A and the second bent portion B of the lead frame unit 1 and the package body The mutual engraving between the 7 avoids the pulling stress generated by the external force applied to the contact portion 12', and affects the connection relationship between the lead frame unit 1 and the wafer 2. Further, by the mutual engraving between the side flap portions 113 provided in the extending portion 112 and the package body 7, the degree of coupling stability between the lead frame unit 1 and the package body 7 can be further increased. Furthermore, in the step of covering the lead frame unit 1 by the package 7, the package 7 can also be passed through the fixed through hole C of the extending portion 112, and a part of the package 7 can be embedded in the fixed through hole C. Further, the structure of the fixing post is formed to further block the external stress near the end of the contact portion 12' from being transmitted to the inner side of the package body 7, and the connection relationship between the lead frame unit 1 and the wafer 2 can be more effectively prevented from being subjected to the pulling stress. Negative impact. In other words, the above-described technical feature of bending the extending portion 112 into the first bent portion A and the second bent portion B, or opening the fixed through hole C in the extending portion 112, or providing the side wing portion 113 on the extending portion 112 side The connection yield between the lead frame unit 1 and the wafer 2, or between the wafer 2 and the heat sink 3 can be further directly or indirectly improved in the fabricated semiconductor package structure Z.

[Advantageous Effects of Embodiments]

An advantageous effect of the present invention is that a method of fabricating a semiconductor package structure according to the present invention can be performed by "putting the heat sink over the wafer and the inner lead portion of the lead frame unit" The technical solution is such that the stability of the lead frame unit, the wafer and the heat sink can be connected to each other during the connection process by the weight of the heat sink itself, and the offset is prevented from occurring. The phenomenon can further effectively improve the yield of the semiconductor package structure produced.

In addition, the manufacturing method of the semiconductor package structure provided by the present invention can pass the “the accommodating space has a step portion, and the step portion divides the accommodating space into an upper layer space and a lower layer space” and “ The height of the step portion is smaller than an overall height of the lead frame unit, the first bonding material, the wafer, and the second bonding material before the heating step, and the height of the step portion is greater than a technical solution of the leadframe unit, the first bonding material, and the overall height of the wafer after the heating step to ensure that the second bonding material can be surely contacted in the heat sink to avoid the heat dissipation The electrical/thermal connection between the socket and the wafer is not effective, and it is ensured that the leadframe unit or the wafer is not excessively pressed by the heat sink, and the leadframe unit or the wafer can be avoided Damaged or deformed.

The above disclosure is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Therefore, any equivalent technical changes made by using the present specification and the contents of the drawings are included in the application of the present invention. Within the scope of the patent.

Claims (10)

 A manufacturing method of a semiconductor package structure, comprising: providing a plurality of lead frame units, wherein each of the lead frame units respectively includes an inner lead portion and an outer lead portion, and the plurality of outer lead portions are mutually connected to each other Connecting a plurality of the inner lead portions of the plurality of lead frame units into a plurality of accommodating spaces of a first mold; placing a first bonding material on a top of the inner lead portion a wafer; placing a wafer on a top surface of the first bonding material; placing a second bonding material on a top surface of the wafer; placing a heat sink on a top surface of the second bonding material; heating So that the leadframe unit and the wafer are interconnected by the first bonding material, and the wafer and the heat sink are interconnected by the second bonding material; performing a packaging step to The inner lead portion of the lead frame unit, the wafer, and a portion of the heat sink are covered by a package; and a portion where the outer lead portions are connected to each other is cut off.    The manufacturing method of the semiconductor package structure of claim 1, wherein the accommodating space has a difference portion, and the step portion divides the accommodating space into an upper space and a lower space, the lead frame The unit and the wafer are placed in the lower space, and the heat sink is placed in the upper space.    The method of fabricating a semiconductor package structure according to claim 2, wherein the height of the step portion is smaller than the lead frame unit, the first bonding material, the wafer, and the first portion before the heating step And then the overall height of the material, and the height of the step portion is greater than the lead frame unit after the heating step, the first bonding material, and the overall height of the wafer.    The method of fabricating a semiconductor package structure according to claim 1, wherein before the step of placing the plurality of the inner lead portions into the plurality of the accommodating spaces, the method further includes: pairing the inner pins An extension portion of the portion is bent such that the extension portion is formed with a first bending portion and a second bending portion, wherein the second bending portion is interposed between the first bending portion and the outer portion Between the pin portions, and the extension portion further includes a side wing portion, wherein the side wing portion is located at one side of the second bent portion and extends toward a direction perpendicular to the second bent portion.    The method of fabricating a semiconductor package structure according to claim 1, wherein the first bonding material and the second bonding material are solder bumps.    The method of fabricating a semiconductor package structure according to claim 1, wherein the step of providing a plurality of leadframe units comprises: stamping a metal strip to form the plurality of leadframe units, wherein the metal strip has Uniform thickness.    The method of fabricating a semiconductor package structure according to claim 1, wherein after the step of cutting off portions of the outer lead portions that are connected to each other, the method further comprises the step of: bending the outer lead portion, So that the outer lead portion forms a contact portion.    A manufacturing method of a semiconductor package structure, comprising: providing a lead frame unit, wherein the lead frame unit includes an inner lead portion and an outer lead portion; and a mold is provided, the mold has a receiving space, The accommodating space includes an upper layer space and a lower layer space; the inner lead portion, a first bonding material and a wafer are sequentially placed in the lower layer space; and a second bonding material is placed on the On the wafer, wherein the second bonding material is partially or completely located in the upper space; a heat sink is placed in the upper space and in direct contact with the second bonding material; and a heating step is performed to The lead frame unit, the wafer, and the heat sink are connected to each other; and performing a packaging step such that the inner lead portion of the lead frame unit, the wafer, and a portion of the heat sink are partially encapsulated Wrapped.    The method of fabricating a semiconductor package structure according to claim 8, wherein the heating step comprises: performing a first heating step before the step of placing the second bonding material on the wafer; The lead frame unit and the wafer are interconnected by the first bonding material; and after the step of placing the heat sink into the upper space, performing a second heating step to make the wafer and the The heat sinks are connected to each other by the second adhesive material.    The method of fabricating a semiconductor package structure according to claim 8, wherein the semiconductor package structure is a package structure of a transient voltage suppressor.