TW201901811A - Vertical power transistor with improved conductivity and high reverse bias performance - Google Patents

Abstract

The present invention provides a vertical power transistor (200, 300) having at least one epitaxial layer (203, 303), the at least one epitaxial layer includes a first semiconductor material doped with a first charge carrier and has a complex number First grooves (207, 307) and second grooves (220, 320), the first grooves (207, 307) and the second grooves (220, 320) are arranged in an interactive manner and Extending from a surface of the epitaxial layer (103, 203) into the interior of the epitaxial layer (203, 303), wherein the second trenches (220, 320) are doped with second charge carriers A second semiconductor material (218, 318) is filled, the first charge carriers are different from the second charge carriers, and the epitaxial surface of one of the second trenches (220, 320) and the epitaxial A first well layer (219, 319) including a third semiconductor material doped with the second charge carriers is disposed between the layers (203, 303), and the trenches of the second trenches The surface includes the groove base of the respective grooves (207, 307) and the side walls of the respective grooves (207, 307).

Description

   Vertical power transistor with improved conductivity and high reverse bias efficiency   

The invention relates to a vertical power transistor with a trench structure, in which both a diode junction and a heterojunction are formed between the trench and at least one epitaxial layer.

With regard to vertical power transistors, shielding gate oxide from high field strength is problematic when there is a high positive voltage between the drain and the source during reverse bias operation and under short circuit conditions. In addition, it is difficult to limit the short-circuit current.

Various possibilities for shielding gate oxides are known from the prior art. One possibility is to insert or bury p-type doped regions in the epitaxial layer below the trench structure of the power transistor. These p-type doped regions are electrically connected to the source region of the power transistor. With its position below the top of the MOS, it keeps the top of the MOS shielded from high field strength and decisively promotes the limitation of short-circuit current.

The disadvantage here is that additional epitaxial steps are required to produce buried p-type regions. This causes high costs and other process risks.

Another possibility is to create deep extended p + regions by implanting to the side of the top of the MOS. In this case, the implantation of these areas is deeper than that of the top of the MOS, and therefore the top of the MOS is shielded from the high field strength.

The disadvantage here is that a large amount of energy must be consumed for deep implantation, and therefore leads to high costs.

The goal of the present invention is to improve the performance of vertical power transistors.

The vertical power transistor has at least one epitaxial layer. The at least one epitaxial layer includes a first semiconductor material doped with a first charge carrier and a plurality of first trenches and second trenches. The first trench and the second trench are arranged in an alternating manner and extend from the surface of the epitaxial layer into the interior of the epitaxial layer. In other words, the trench bases of the first trench and the second trench are disposed in or enclosed by the epitaxial layer. According to the invention, the second trench is at least partially filled with a second semiconductor material doped with second charge carriers. In this case, the first charge carrier is different from the second charge carrier. A first well layer including a third semiconductor material doped with second charge carriers is disposed between the trench surface of the second trench and the epitaxial layer. The groove surface of the second groove includes the groove base of each second groove and the side wall of each second groove.

The advantage here is that the p / n junction is positioned between the fifth semiconductor material and the first semiconductor material, and therefore the transistor can be exposed to high field strength. Therefore, a higher reverse bias voltage can be applied to the transistor or the same reverse bias voltage can be used to achieve better conductivity because the p / n junction is positioned between the epitaxial layer and the doped SiC well Of single crystal SiC.

In development, the first semiconductor material is different from the second semiconductor material. In particular, the first semiconductor material has a larger band gap than the second semiconductor material.

It is advantageous here that the second semiconductor material can be used as a terminal and the p / n junction is created between the first semiconductor material and the third semiconductor material, and therefore the p / n junction is in the semiconductor material with the largest band gap produce.

In a further improvement, the first trench has a smaller depth than the second trench.

The advantage here is to better protect the top of the MOS from high field strength.

In development, in each case, the first trench has an area extending from the trench base to a certain height. This region is at least partially filled with a fourth semiconductor material doped with second charge carriers. This region is electrically connected to the source region.

The advantage here is that these areas produce a shielding effect. The reverse operation can be advantageously performed by means of the second trench, because it can be directly connected to the source in each cell. The term reverse operation is understood to mean that the mode of operation of the transistor is a freewheeling diode, that is, the current of the transistor is reversed relative to the normal direction of the current. In other words, the reverse conductivity increases.

In development, a second well layer containing a fifth semiconductor material doped with second charge carriers is arranged between the trench surface of the region and the epitaxial layer. The trench surface of the region includes the trench base of each first trench and the sidewall of each first trench. In other words, the second well layer forms a kind of well between the trench surface and the epitaxial layer.

In a further improvement, a certain height includes 10% to 90% of the depth of each first trench.

In development, the first charge carrier is n-type conduction and the second charge carrier is p-type conduction.

The advantage here is that the vertical power transistor has a lower conduction loss due to the larger electron mobility.

In a further improvement, the first semiconductor material includes SiC and the second semiconductor material includes polysilicon.

In development, the third semiconductor material contains SiC.

In a further improvement, the epitaxial layer is configured on a semiconductor substrate including SiC.

In development, the vertical power transistor is a MOSFET.

The advantage here is that low conduction losses occur with a constant reverse bias resistance, for example compared to bipolar IGBTs.

Other advantages emerge from the following description of illustrative specific examples and the scope of patent applications from dependent patents.

100‧‧‧Vertical power transistor

101‧‧‧Semiconductor substrate

103‧‧‧Epitaxial layer

104‧‧‧channel layer

105‧‧‧n + doped source region

106‧‧‧Depth extension p + area

107‧‧‧Groove

108‧‧‧ First area

110‧‧‧Gate dielectric

111‧‧‧Gate electrode

112‧‧‧Structured insulating layer

113‧‧‧Metal layer

114‧‧‧ Drain metallization

200‧‧‧Vertical power transistor

201‧‧‧Semiconductor substrate

203‧‧‧Epitaxial layer

204‧‧‧channel layer

205‧‧‧n + doped source region

207‧‧‧The first groove

208‧‧‧Region

210‧‧‧ Gate dielectric

211‧‧‧Gate electrode

212‧‧‧Structured insulating layer

213‧‧‧Metal layer

214‧‧‧ Drain metal

215‧‧‧The second well

218‧‧‧Second semiconductor material

219‧‧‧The first well

220‧‧‧Second groove

300‧‧‧Vertical power transistor

301‧‧‧Semiconductor substrate

303‧‧‧Epitaxial layer

304‧‧‧channel layer

305‧‧‧Source area

307‧‧‧The first groove

308‧‧‧Region

309‧‧‧ Fourth semiconductor material

310‧‧‧ Gate dielectric

311‧‧‧Gate electrode

312‧‧‧Structured insulating layer

313‧‧‧Metal layer

314‧‧‧Drain metal

315‧‧‧Second well

318‧‧‧Second semiconductor material

319‧‧‧The first well

320‧‧‧Second groove

The present invention is explained below based on preferred specific examples and accompanying drawings. In the drawings: FIG. 1 shows a vertical power transistor from the prior art, FIG. 2 shows an embodiment of the vertical power transistor, and FIG. 3 shows another embodiment of the vertical power transistor.

Figure 1 shows a vertical power transistor 100 from the prior art. The vertical power transistor 100 includes a semiconductor substrate 101 on which an epitaxial layer 103 is arranged on the front side. The epitaxial layer 103 includes a first semiconductor material doped with first charge carriers, such as n-type doped SiC. In the upper region of the epitaxial layer 103, p-type doped ions, such as Al, are implanted. Therefore, in the upper region of the epitaxial layer 103, a channel layer 104 serving as a channel region is formed here. On the channel region 104, another semiconductor layer including the n + doped source region 105 is arranged. The vertical power transistor 100 has a trench structure, that is, a plurality or a plurality of trenches. A gate dielectric 110 and a gate electrode 111 are arranged in each trench 107. A structured insulating layer 112 that electrically insulates the gate electrode 111 and the source region 105 is disposed on each trench 107 (that is, above the trench structure). A depth extending p + region 106 is arranged laterally between the trenches 107. In other words, the depth extension p + region 106 is arranged on the side of the top of the MOS in a structured form. Compared to the trench 107, the p + region 106 has a larger depth, that is, it remains deeper than the top of the MOS and shields the top of the MOS from high field strength. A metal layer 113 is arranged on the structured insulating layer 112. A drain metallization 114 is arranged on the back side of the semiconductor substrate 101.

FIG. 2 shows an embodiment of a vertical power transistor 200. The vertical power transistor 200 includes a semiconductor substrate 201, and an epitaxial layer 203 is arranged on the front side of the semiconductor substrate. The epitaxial layer 203 includes a first semiconductor material doped with first charge carriers, such as n-type doped SiC. In the upper region of the epitaxial layer 203, p-type doped ions, such as Al, are implanted. Therefore, in the upper region of the epitaxial layer 203, a channel layer 204 serving as a channel region is formed here. Alternatively, a p-type doped epitaxial layer forming a channel region may be disposed on the epitaxial layer 203. On the channel layer 204, another semiconductor layer including the n + doped source region 205 is disposed. The vertical power transistor 200 has a trench structure. The trench structure includes a first trench 207 and a second trench 220. The first trench 207 and the second trench 220 are arranged in the trench structure in an alternating manner. In other words, the second trench 220 is arranged at a certain distance along the side of each first trench 207 in the lateral direction. The terms first trench 207 and second trench 220 are not understood here to mean the number of trenches, but to mean that the trench structure includes two different types of trenches. Compared with the first trench 207, the second trench 220 has a larger depth. In each first trench 207, a gate dielectric 210 and a gate electrode 211 are arranged. A structured insulating layer 212 electrically insulating the gate electrode 211 and the source region 205 is disposed on each first trench 207. The second trench 220 is filled with a second semiconductor material doped with second charge carriers. A first well layer 219 including a third semiconductor material doped with second charge carriers is disposed between the surface of the trench (that is, below and at the side of the trench) and the epitaxial layer 203. In other words, the first well layer 219 forms a well surrounding the filler of the second trench. A metal layer 213 is arranged on the channel layer 204. A drain metallization 214 is arranged on the back side of the semiconductor substrate 201.

The depth of the first trench 207 and the depth of the second trench 220 are 0.5 μm to 10 μm, and the depth of the first trench 207 is smaller than the depth of the second trench 220. The distance between the first trench 207 and the second trench 220 is substantially the same size and is in the range between 0.1 μm and 10 μm, the lower limit is specified by the process and the upper limit is insufficiently shielded by other aspects of the MOS complex Regulations. The region laterally located between the first trench 207 and the second trench 220 (that is, the horizontal region between the first trench 207 and the second trench 220, that is, the portion of the epitaxial layer 203) may have different Doping the rest of the epitaxial layer 203.

Alternatively, the depth of the first trench 207 may be greater than the depth of the second trench 220.

According to circumstances, another epitaxial layer may be configured between at least one epitaxial layer 203 and the top of the MOS or the MOS complex.

The first semiconductor material is different from the second semiconductor material.

In an exemplary embodiment, the semiconductor substrate 201 and the epitaxial layer 203 include SiC. The second semiconductor material includes polycrystalline silicon (polycrystalline silicon), hereinafter also referred to as polycrystalline silicon (poly silicon) or polycrystalline silicon (poly Si). The third semiconductor material contains highly p-type doped SiC. The gate dielectric 210 includes SiO ₂ and the gate electrode 211 includes polysilicon.

In another illustrative specific example, the semiconductor substrate 201 and the epitaxial layer 203 include GaN.

FIG. 3 shows another embodiment of the vertical power transistor 300. The vertical power transistor 300 includes the structure of the vertical power transistor 200, and the same last numbers of the reference numerals correspond to the same components as in FIG. In addition, in each case, the first trench 307 has a region 308 that extends from the trench base to a certain height of the first trench 307. These regions 308 are at least partially or completely filled with the fourth semiconductor material 309. The fourth semiconductor material 309 is electrically connected to at least one source region 305. Above the region 308, a gate dielectric 310 and a gate electrode 311 are respectively arranged. A second well layer 315 is respectively disposed between the trench surface of the region 308 and the epitaxial layer 303. The second well layer 315 includes a fifth semiconductor material doped with second charge carriers. In particular, the fourth semiconductor material is in-situ p-type doped polysilicon. The fifth semiconductor material contains, for example, SiC. The effective doping dose usually exceeds 1E13 cm ^-3 . The high doping dose has the effect of improving the shielding on top of the MOS. The thickness of the layer 315 is in the range between 0.01 μm and 4 μm.

The third semiconductor material and the fifth semiconductor material can be made in the same way, thereby saving the number of process steps.

The vertical power transistors 200 and 300 are preferably MOSFETs. However, it can also be designed or implemented as HEMT. The vertical power transistors 200 and 300 can be used in, for example, vehicle inverters, photovoltaic inverters, traction drives, or high-voltage rectifiers.

Claims (11)

    A vertical power transistor (200, 300) having at least one epitaxial layer (203, 303), the at least one epitaxial layer includes a first semiconductor material doped with a first charge carrier and has a plurality of first grooves Grooves (207, 307) and second trenches (220, 320), the first trenches (207, 307) and the second trenches (220, 320) are arranged in an interactive manner and from the epitaxial layer ( The surface of 103, 203) extends into the interior of the epitaxial layer (203, 303), wherein the second trench (220, 320) is doped with a second semiconductor material (218, 318 of a second charge carrier) ) Filling, the first charge carrier and the second charge carrier are different, and a doping is included between the trench surface of the second trench (220, 320) and the epitaxial layer (203, 303) The first well layer (219, 319) of the third semiconductor material with the second charge carrier, and the surface of the trench of the second trench includes the trench base of the respective trench (207, 307) and The side walls of the respective trenches (207, 307).         The vertical power transistor (200, 300) according to claim 1, wherein the first semiconductor material is different from the second semiconductor material, in particular, compared to the second semiconductor material (218, 318), the first A semiconductor material has a large band gap.         The vertical power transistor (200, 300) according to claim 1 or 2, wherein the first trench (207, 307) has a smaller depth than the second trench (220, 320).         The vertical power transistor (200, 300) of claim 1 or 2, wherein in each case, the first trench (207, 307) has a region (208) extending from the trench base to a certain height , 308), the region (208, 308) is at least partially filled with a fourth semiconductor material (209, 309) doped with second charge carriers, and the region (208, 308) is electrically connected to the source region (215,315).         The vertical power transistor (200, 300) as described in claim 4, wherein the second surface of the trench (203, 303) and the epitaxial layer (203, 303) are provided A second well layer (215, 315) of the fifth semiconductor material of the charge carrier, and the trench surface of the region (208, 308) includes the trench base of the respective first trench (207, 307) And the side walls of the respective first trenches (207, 307).         The vertical power transistor (200, 300) according to claim 4, wherein the certain height includes ten to ninety percent of the depth of the respective first trench (207, 307).         The vertical power transistor (200, 300) according to claim 1 or 2, wherein the first charge carrier is n-type conduction and the second charge carrier is p-type conduction.         The vertical power transistor (200, 300) of claim 1 or 2, wherein the first semiconductor material includes SiC and the second semiconductor material (218, 319) includes polycrystalline Si.         The vertical power transistor (200, 300) according to claim 1 or 2, wherein the third semiconductor material comprises SiC.         The vertical power transistor (200, 300) according to claim 1 or 2, wherein the epitaxial layer (203, 303) is disposed on a semiconductor substrate (201, 301) containing SiC.         The vertical power transistor (200, 300) according to claim 1 or 2, wherein the vertical power transistor (200, 300) is a MOSFET.