TW201908988A - Server system - Google Patents

Abstract

A server system according to this invention has a main board, a processor disposed on the main board, a plurality of first buses, a plurality of second buses and a plurality of storage medium. The processor has a plurality of processing cores and at least one platform controller hub (PCH) electrically connected to the plurality of processing cores. The first buses and the second buses are all disposed on the main board and electrically connected to the PCH. Parts of the plurality of storage medium are plugged in the first buses and the other parts are plugged in the second buses.

Description

Server system

The present invention is directed to a server system, and more particularly to a 1U server system.

The server generally has a complete chassis, power supply, motherboard, storage and other standard components. Generally, a rack can have a capacity of about 42 1U servers. With the development of the big data era, end users are paying more and more attention to the application of big data (cloud), and because of such applications, servers with high storage capacity are needed to improve the ability of data exchange communication. End users especially have the need for a solid state drive of the PCIE interface type. However, existing servers are often limited by the number of network communication capabilities and input and output ports, and cannot meet the needs of existing and future end users.

In view of the above problems, the present invention provides a server system. Based on the existing 1U server architecture, the configuration and connection relationship of components are changed, and some components are added, and the network communication capability and input/output connection of the 1U server are improved. quantity.

A server system according to an embodiment of the invention includes a main board, a processor disposed on the main board, a plurality of first bus bars, a plurality of second bus bars, and a plurality of storage media. The processor includes a plurality of processing cores and at least one platform controller hub (PCH) electrically connected to the plurality of processing cores. The plurality of first bus bars and the plurality of second bus bars are disposed on the main board and electrically connected to the platform path controller. The plurality of storage media are partially inserted into the plurality of first bus bars, and the other portion is inserted into the plurality of second bus bars.

The server system disclosed by the present invention can reserve more input and output components on the main board of the server system by integrating the platform path controller into the processor. This can increase the number of input/output ports or communication capabilities of the server system.

The above description of the disclosure and the following description of the embodiments of the present invention are intended to illustrate and explain the spirit and principles of the invention, and to provide further explanation of the scope of the invention.

The detailed features and advantages of the present invention are set forth in the Detailed Description of the Detailed Description of the <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; The objects and advantages associated with the present invention can be readily understood by those skilled in the art. The following examples are intended to describe the present invention in further detail, but are not intended to limit the scope of the invention.

Please refer to FIG. 1 , which is a schematic diagram of a server system architecture according to an embodiment of the invention. As shown in FIG. 1 , a server system 1000 according to an embodiment of the present invention has a main board 1100, a processor 1200 disposed on the main board, a plurality of first bus bars 1310~1340, and a plurality of second bus bars 1410~1480 and more. A storage medium of 1500A~1500L.

The processor 1200 has a plurality of processing cores 1210-1240 and a platform controller hub (PCH) 1250. Processing cores 1210~1240 have the ability to perform parallel instruction processing. The platform path controller 1250 is electrically connected to the plurality of processing cores 1210-1240. Since the platform path controller 1250 is built into the processor, the space reserved for the platform path controller 1250 on the main board 1000 can be freed to place other components as compared to the prior art. In an embodiment of the present invention, the processor 1200 is, for example, a Napoles processor (Naples®), but the invention is not limited thereto.

The first bus bars 1310~1340 and the second bus bars 1410~1480 are both disposed on the main board 1100 and electrically connected to the platform path controller 1250 in the processor 1200. The first bus bars 1310~1340 are, for example, slot slots, and the second bus bars 1410~1480 are, for example, slimline slots. The storage mediums 1500A-1500D are inserted in the first busbars 1310~1340, and the storage media 1500E-1500L are inserted in the second busbars 1410~1480. Although the configuration in FIG. 1 is such that the first bus bars 1310 to 1340 are located on the left side and the second bus bars 1410 to 1480 are located on the right side, those skilled in the art will understand that the configuration is not intended to be limited by the present invention.

Please refer to FIG. 2 , which is a schematic diagram of a server system architecture according to another embodiment of the present invention. As shown in FIG. 2, the server system 1000-1 in this embodiment has a storage medium controller (AROC) 1600 disposed on the main board 1100 and electrically connected to the server system 1000 of FIG. Platform path controller 1250 in 1200. The processor 1200 accesses the storage medium through the storage medium controller 1600. The storage medium controller 1600 can be electrically connected to a hard disk backplane 3000 other than the server system 1000-1 and is responsible for processing access to the storage medium on the hard disk backplane 3000.

In an embodiment, as shown in FIG. 2, the server system 1000-1 may further have a baseboard management controller (BMC) 1700 electrically connected to the processor 1200.

Referring to FIG. 2, the server system 1000-1 according to an embodiment of the present invention may further have a serial Gigabit Ethernet interface (SGMII) 1800 electrical connection substrate management controller 1700, and the substrate management controller 1700 transmits The Gigabit Ethernet interface 1800 is serially transmitted and received.

In addition, in another embodiment, as shown in FIG. 2, the server system 1000-1 further has a first read-only storage medium 1910 and a second read-only storage medium 1920. The first read-only storage medium 1910 is electrically connected to the baseboard management controller 1700 for storing the firmware of the baseboard management controller. Therefore, when the server system 1000-1 is activated, the baseboard management controller 1700 reads the firmware from the first read-only storage medium 1910 and executes the firmware to manage the server system 1000-1.

The second read-only storage medium 1920 is electrically connected to the substrate management controller 1700 and stores the firmware of the basic input/output system. Therefore, when the server system 1000-1 is started, the baseboard management controller 1700 controls the basic input/output system chip (BIOS chip) of the server system 1000-1 to be read from the second read-only storage medium 1920. Take and execute the basic input and output system firmware.

Referring to FIG. 2 again, the server system 1000-1 according to another embodiment of the present invention may further have a complex programmable logic device (CPLD) 2000, electrically connected to the substrate management controller 1700 and control the server system 1000-1. Timing. The timing here is not limited to the generation and division of the clock signal. The complex programmable logic device 2000 in this embodiment can be implemented as a finite state machine (FSM), and the state is switched according to the received signal, so that the substrate management controller 1700 is based on the current state. Decide how to control the operation of the various components on the server system 1000-1. For example, when the server system 1000-1 has been powered, the state can be divided into startup, maintenance, normal, and sleep. In the startup state, the baseboard management controller 1700 needs to sequentially control the activation of each component of the server system 1000-1. In the maintenance state, the baseboard management controller 1700 needs to disable some of the components of the control server system 1000-1. In the sleep state, the baseboard management controller 1700 only maintains some of the necessary elements of the server system 1000-1 in an enabled state to wait for a wakeup signal.

Referring to FIG. 2 again, the server system 1000-1 according to another embodiment of the present invention may further have an advanced light out manager (ALOM) 2100 disposed on the main board 1100 and electrically connected to the processor 1200. Platform path controller 1250, remote system controller 2100 has multiple network interfaces. Therefore, the server system 1000-1 can communicate with one or more external users of the outside while communicating with the main controller of the server chassis, thereby greatly improving the communication capability of the server system.

As shown in FIG. 2, in another embodiment of the present invention, the server system 1000-1 may further have a power supply 2200 to supply power to the processor 1200 and the storage medium in a single output manner. In one embodiment, the power supply 2200 has an electronic fuse function (effuse). Therefore, when the server manager maintains the server system 1000-1 and the wrong power supply, reverse connection, etc. occur, the electronic fuse function of the power supply 2200 will function to avoid the power supply 2200 or the server system 1000- 1 damaged.

In summary, the server system in one embodiment of the present invention integrates the platform path controller into the processor, and the motherboard retains more space for other electronic components such as a remote system controller and storage medium control. , thereby increasing the number of input and output ports or communication capabilities of the server system.

Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

1000, 1000-1‧‧‧ server system

1100‧‧‧ motherboard

1200‧‧‧ processor

1210~1240‧‧‧ Processing core

1250‧‧‧Platform Path Controller

1310~1340‧‧‧First bus

1410~1480‧‧‧Second bus

1500A~1500L‧‧‧ Storage medium

1600‧‧‧Storage Media Controller

1700‧‧‧Baseboard Management Controller

1800‧‧‧Gigabit Ethernet interface

1910, 1920‧‧‧ read-only storage media

2000‧‧‧Complex programmable logic device

2100‧‧‧Remote system controller

2200‧‧‧Power supply

3000‧‧‧hard disk backplane

FIG. 1 is a schematic diagram of a server system architecture according to an embodiment of the invention. 2 is a schematic diagram showing the architecture of a server system according to another embodiment of the present invention.

Claims (9)

A server system, comprising: a motherboard; a processor disposed on the motherboard, comprising: a plurality of processing cores; and at least one platform controller hub (PCH) electrically connected to the processing cores; a first bus bar is disposed on the motherboard and electrically connected to the platform path controller; a plurality of second bus bars are disposed on the motherboard and electrically connected to the platform path controller; and a plurality of storage media, and some of the storage media The first busbars are inserted into the first busbars, and the other parts of the storage medium are inserted into the second busbars. The server system of claim 1, further comprising a storage medium controller (AROC) disposed on the motherboard and electrically connected to the platform path controller. The server system of claim 1 further includes a baseboard management controller (BMC) electrically connected to the processor. The server system of claim 3 further includes a serial Gigabit Ethernet interface (SGMII) electrically connected to the baseboard management controller, and the baseboard management controller performs the serialized Gigabit Ethernet interface Signal transmission and reception. The server system of claim 3, the server system further comprising: a first read-only storage medium electrically connected to the baseboard management controller and storing a baseboard management controller firmware; and a second read-only storage The medium is electrically connected to the baseboard management controller and stores a basic input/output system firmware. The server system of claim 5 further includes a complex programmable logic device (CPLD) electrically connected to the baseboard management controller for controlling the timing of the server system. The server system of claim 1, further comprising an advanced light out manager (ALOM) disposed on the motherboard and electrically connected to the platform path controller, the remote system controller comprising multiple networks interface. The server system of claim 1 further includes a power supply that supplies power to the processor and the storage medium in a single output. The server system of claim 1, wherein the processor is a Napoles processor (Naples®).