WO2025077411A1 - Io expansion architecture, io switch and pcie device - Google Patents

Abstract

The present application relates to the technical field of computers, and provides an IO expansion architecture, an IO switch and a PCIe device. The IO expansion architecture comprises: at least one IO expansion unit, wherein the IO expansion unit comprises an expansion substrate, and the expansion substrate is provided with at least two PCIe Switch chips, a first preset number of internal connectors, and a second preset number of external connectors; one end of each internal connector is connected to any PCIe Switch chip on the expansion substrate, and the other end of the internal connector is used for interconnection between the PCIe Switch chips; and one end of each external connector is connected to any PCIe Switch chip on the expansion substrate, and the other end of the external connector is used for being connected to the PCIe device so as to complete interconnection between the plurality of PCIe devices. Extraction of a large amount of or sufficient amount of IO resources can be well supported, and the construction requirements of complex topologies in a fusion architecture system are better met.

Description

IO expansion architecture, IO switches and PCIe devices

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to the Chinese patent application filed with the China Patent Office on October 10, 2023, with application number 202311304011.4, and application name “IO expansion architecture, IO switch and PCIe device”, all contents of which are incorporated by reference in this application.

Technical Field

The present application relates to the field of computer technology, and in particular to an IO expansion architecture, an IO switch and a PCIe device.

Background Art

With the rapid development of computer technology, AI models are getting bigger and bigger, which has attracted widespread attention to the pooling of computing resources, and the converged architecture system has come into being. In the converged architecture system, Host, IO (Input/Output), GPU (Graphic Processing Unit), SSD (Solid State Drive), Memory, etc. are all decoupled into independent modules, becoming dedicated Host resource pools, IO resource pools, GPU resource pools, SSD resource pools, Memory resource pools, etc., in order to achieve rapid expansion and upgrading of equipment. Among them, the IO resource pool refers to the IO switch. In order to achieve the integrated management of a large number of PCIe device resources, such as Host resources, GPU resources, SSD resources and Memory resources, the IO switch plays a vital role.

Existing IO switches usually set a fixed number (such as 8) of PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) slots on the switch substrate, use standard full-height/half-height HBA (Host Bus Adapter) to lead IO resources from the PCIe slot, and then use the led IO resources to access and manage PCIe device resources. However, this method cannot well support the lead-out of a large number of IO resources, cannot well meet the construction requirements of complex topologies in converged architecture systems, and requires the use of HBA for protocol conversion, which is cumbersome to implement and has high costs.

Summary of the invention

The present application provides an IO expansion architecture, an IO switch and a PCIe device to solve the problem that the related technology cannot well support the extraction of a large number of IO resources and cannot well meet the construction requirements of complex topologies in a converged architecture system.

This application provides an IO expansion architecture, including:

At least one IO expansion unit, the IO expansion unit comprising an expansion base plate, the expansion base plate having at least two PCIe Switch chips, a first preset number of internal connectors, and a second preset number of external connectors;

One end of the internal connector is connected to any one of the PCIe Switch chips on the extension baseboard, and the other end of the internal connector is used for interconnection between the PCIe Switch chips; one end of the external connector is connected to any one of the PCIe Switch chips on the extension baseboard, and the other end of the external connector is used to connect a PCIe device to complete the interconnection between multiple PCIe devices.

The present application also provides an IO switch, comprising:

ID management unit, control module, and IO expansion architecture as described above;

The ID management unit is used to collect ID signals of all the internal connectors and the external connectors in the IO expansion architecture, and transmit the ID signals to the control module;

The control module is used to manage all the PCIe Switch chips in the IO expansion architecture based on all the ID signals.

According to an IO switch provided by the present application, each of the inner connector and the outer connector is respectively connected to an ID definition chip, and the ID definition chip is used to perform ID definition on the corresponding inner connector or the outer connector;

The ID management unit is specifically used to send an ID query instruction to each of the ID definition chips through the external connector or the internal connector;

The ID definition chip is also used to receive the ID query instruction, and based on the ID query instruction, feed back the ID signal to the corresponding internal connector or the external connector;

When receiving the ID signal, the internal connector or the external connector feeds back the ID signal to the ID management unit;

The ID management unit is connected to each of the external connectors, the internal connectors and the control module respectively.

According to an IO switch provided by the present application, the control module includes:

A multiplexer, used for receiving the ID signal transmitted by the ID management unit;

A logic control unit, configured to monitor the operating status of a baseboard management controller and all task management units; based on the operating status and the task management priorities corresponding to the baseboard management controller and the task management unit, determine one of the baseboard management controller and all the task management units as a target management unit; based on the determined target management unit, generate a target management unit instruction; and send the target management unit instruction to the multiplexer;

The multiplexer is further used to determine the target management unit based on the target management unit instruction and send the ID signal to the target management unit;

A baseboard management controller and at least one task management unit, wherein the baseboard management controller and the task management unit are used to perform PCIe topology identification based on the ID signal when receiving the ID signal to obtain a PCIe interconnection topology; and manage all the PCIe Switch chips based on the PCIe interconnection topology;

The ID management unit is connected to the multiplexer, and the multiplexer is respectively connected to the logic control unit, the baseboard management controller, and all the task management units.

According to an IO switch provided by the present application, at least one of the task management units includes: a first task management unit and a second task management unit;

The logic control unit is specifically used to determine the first task management unit as the target management unit when the first task management unit is in a normal operating state; to determine the second task management unit as the target management unit when the first task management unit is in an abnormal operating state and the second task management unit is in a normal operating state; and to determine the baseboard management controller as the target management unit when both the first task management unit and the second task management unit are in an abnormal operating state and the baseboard management controller is in a normal operating state.

According to an IO switch provided by the present application, the baseboard management controller and the task management unit are specifically used to send corresponding configuration information to each of the PCIe Switch chips respectively when the PCIe interconnection topology is identified; the configuration information includes type information of all connection interfaces of the PCIe Switch chip; the connection interface includes an interface for connecting to the internal connector or the external connector; the type information includes: uplink interface information, downlink interface information and internal interconnection interface information; the uplink interface information indicates that the corresponding connection interface is an uplink interface, The upstream interface is used to transmit PCIe signals to the PCIe device connected upstream; the downstream interface information indicates that the corresponding connection interface is a downstream interface, and the downstream interface is used to transmit the PCIe signal to the PCIe device connected downstream; the interconnection interface information indicates that the corresponding connection interface is an internal interconnection interface, and the internal interconnection interface is used to transmit the PCIe signal to the remaining PCIe Switch chips interconnected with the current PCIe Switch chip; the PCIe device connected upstream refers to a host, and the PCIe device connected downstream is a graphics processor, a solid-state drive or a memory;

The PCIe Switch chip is used to configure all of its own connection interfaces based on the received configuration information.

According to an IO switch provided by the present application, the PCIe Switch chip is used to obtain the target device type corresponding to the PCIe signal when receiving the PCIe signal sent by the PCIe device; based on the target device type, determine at least one target interface corresponding to the target device type from all the connection interfaces of the current PCIe Switch chip, and determine that the PCIe device connected to the target interface is the target PCIe device; send a status query instruction to the target PCIe device through the target interface; receive the task processing status fed back by each of the target PCIe devices, the task processing status being fed back by the target PCIe device based on the status query instruction; and send the PCIe signal to any of the target PCIe devices whose task processing status is an idle state.

According to an IO switch provided by the present application, the PCIe Switch chip is specifically used to transmit the PCIe signal to a preset message queue when the task processing status fed back by all the target PCIe devices is in the working state; and when any of the target PCIe devices is monitored to be in the idle state, based on the message queue, transmit the PCIe signal to the target PCIe device in the idle state.

According to an IO switch provided by the present application, it also includes: a network management unit, which is connected to the baseboard management controller, the task management unit and the IO expansion unit respectively to complete the two-to-two communication between the baseboard management controller, the IO expansion unit, and all the task management units.

An IO switch provided according to the present application further includes: a heat dissipation unit, which is used to dissipate heat for the IO switch.

According to an IO switch provided by the present application, the IO switch further includes: a power rail unit, wherein an input terminal of the power rail unit Used to be connected to the power supply unit, the output end of the power rail unit is respectively connected to the IO expansion unit, the ID management unit, the baseboard management controller and the task management unit, and is used to supply power to the IO expansion unit, the ID management unit, the baseboard management controller and the task management unit.

According to an IO switch provided by the present application, the logic control unit is further used to send a power switch signal to the power rail unit to control the power rail to start or stop supplying power.

According to an IO switch provided by the present application, the first preset number of internal connectors is distributed on a first side of the corresponding extended baseboard, the second preset number of external connectors is distributed on a second side of the corresponding extended baseboard, and the first side and the second side are opposite sides.

The present application also provides a PCIe device, including: a switch connector, wherein the switch connector is used to connect to the external connector in the above-mentioned IO expansion architecture, or to connect to the external connector in any of the above-mentioned IO switches.

According to a PCIe device provided by the present application, the switch connector and the external connector are the same type of connector.

According to a PCIe device provided by the present application, the PCIe device is a host, a graphics processor, a solid-state drive or a memory.

The present application also provides a PCIe fusion architecture system, including:

An IO switch as described in any one of the above, and a plurality of PCIe devices as described in any one of the above, wherein the plurality of PCIe devices are respectively connected to the corresponding external connectors.

The present application also provides a PCIe signal fusion management method based on the PCIe fusion architecture system as described above, comprising:

Receive PCIe signals sent by PCIe devices;

Obtaining the target device type corresponding to the PCIe signal;

Based on the target device type, determining at least one target interface corresponding to the target device type from all connection interfaces of the current PCIe Switch chip, and determining the PCIe device connected to the target interface as the target PCIe device;

Sending a status query instruction to the target PCIe device through the target interface;

Receiving a task processing status fed back by each of the target PCIe devices, wherein the task processing status information is fed back by the target PCIe device based on the status query instruction;

The PCIe signal is sent to any of the target PCIe devices whose task processing state is an idle state.

The present application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the PCIe signal fusion management method as described in any one of the above is implemented.

The present application also provides a non-transitory computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the PCIe signal fusion management method as described in any one of the above is implemented.

Beneficial effects of the present application: The IO expansion architecture, IO switch and PCIe device provided by the present application are provided with at least one IO expansion unit, the IO expansion unit includes an expansion substrate, the expansion substrate is provided with at least two PCIe Switch chips, a first preset number of internal connectors, and a second preset number of external connectors; one of the internal connectors One end of the internal connector is connected to any PCIe Switch chip on the expansion baseboard, and the other end of the internal connector is used for interconnection between PCIe Switch chips; one end of the external connector is connected to any PCIe Switch chip on the expansion baseboard, and the other end of the external connector is used to connect PCIe devices to complete the interconnection between multiple PCIe devices. The IO expansion architecture in this application can better support the extraction of a large or sufficient amount of IO resources, can better meet the construction requirements of complex topologies in converged architecture systems, has high flexibility, and provides the possibility of engineering implementation for the construction of complex topologies in converged architecture systems.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the present application or related technologies, the following is a brief introduction to the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

FIG1 is a schematic diagram of the structure of an embodiment of an IO expansion architecture provided by the present application;

FIG2 is a schematic diagram of the structure of an embodiment of an IO switch provided by the present application;

FIG3 is a schematic diagram of the structure of another embodiment of an IO switch provided by the present application;

FIG4 is a schematic diagram of a structure of an embodiment of a PCIe interconnection topology in a PCIe converged architecture system provided by the present application;

FIG5 is a flow chart of an embodiment of a PCIe signal fusion management method provided by the present application;

FIG. 6 is a schematic diagram of the structure of an electronic device provided in the present application.

Figure ID:

110- expansion baseboard; 120- PCIe Switch chip; 130- internal connector;

140-external connector; 210-ID management unit; 220-control module;

221-multiplexer; 222-logic control unit; 223-first task management unit;

224-a second task management unit; 225-a baseboard management controller;

310-network management unit; 320-heat dissipation unit; 330-power rail unit;

340-PSU power supply unit; 350-HVDC power supply unit.

DETAILED DESCRIPTION

In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

The following describes the IO expansion architecture, IO switch and PCIe device provided by the present application in the form of embodiments in combination with Figures 1 to 6.

Please refer to FIG1 , the IO expansion architecture provided in this embodiment includes:

At least one IO expansion unit, the IO expansion unit includes an expansion base plate 110, the expansion base plate has at least Two PCIe Switch chips (simplified as SW in FIG. 1 ), a first preset number of internal connectors 130 , and a second preset number of external connectors 140 .

One end of the internal connector 130 is connected to any one of the PCIe Switch chips 120 on the extension baseboard 110, and the other end of the internal connector 130 is used for interconnection between the PCIe Switch chips 120; one end of the external connector 140 is connected to any one of the PCIe Switch chips 120 on the extension baseboard 110, and the other end of the external connector 140 is used for connecting a PCIe device to complete the interconnection between multiple PCIe devices.

Specifically, the number of the IO expansion units can be set according to actual conditions, such as 1, 2, 3 or 4. PCIe adopts a point-to-point working mode. In the above embodiment, by adopting the PCIe Switch chip 120, the expansion of PCIe resources can be achieved, thereby facilitating communication between multiple PCIe devices.

Furthermore, by setting at least two PCIe Switch chips 120 on the expansion base plate 110, as many PCIe resources as possible can be expanded. By setting a first preset number of internal connectors 130, the interconnection between the PCIe Switch chips 120 in the IO expansion architecture can be better realized. By setting a second preset number of external connectors 140, the access of multiple PCIe devices can be better realized, thereby realizing the construction of the PCIe interconnection topology.

It should be noted that the first preset number can be determined according to the number of PCIe Switch chips 120 in the IO expansion architecture. For example: Assume that there are four IO expansion units in the IO expansion architecture, and each IO expansion unit includes two PCIe Switch chips 120, that is, there are a total of 8 PCIe Switch chips 120. Then, in order to achieve the interconnection between the 8 PCIe Switch chips 120, 32 internal connectors 130 need to be set to achieve the interconnection between the 8 PCIe Switch chips 120. Among them, each PCIe Switch chip 120 corresponds to 4 internal connectors 130. Considering that the server (the server where the IO expansion architecture is located) usually has a standard size restriction, after multiple experiments, it is found that the preferred value of the first preset number is 8, that is, 8 internal connectors 130 are set on each expansion substrate 110, and each PCIe Switch chip 120 corresponds to 4 internal connectors 130. The above-mentioned preferred value of the first preset number is for reference only, and in actual implementation, it can be set according to actual conditions.

In addition, the second preset number can also be set according to actual conditions, such as 8, 10, etc. Similarly, since the size of the server has a standard definition or limitation, after multiple tests, it is concluded that the preferred value of the second preset number is 10, that is, 10 external connectors 140 are set on each expansion base plate 110, wherein each PCIe Switch chip 120 corresponds to 5 corresponding external connectors 140, so as to expand as many PCIe resources as possible and connect as many PCIe devices as possible within the range of standard size.

The IO expansion architecture in the above embodiment can better support the extraction of a large or sufficient amount of PCIe resources or IO resources, can better meet the construction requirements of complex topologies in the converged architecture system, has high flexibility, provides the possibility of engineering implementation for the construction of complex topologies in the converged architecture system, has low cost and strong feasibility.

It should be mentioned that the inner connector 130 in the above embodiment may be an MCIO (Mini Cool Edge IO) connector. The outer connector 140 in the above embodiment may be a CDFP (Compact Duplex Fiber Pluggable, a high-density fiber optic connector) connector. By using the above MCIO connector as the inner connector 130 and the CDFP connector as the outer connector 140, the requirements of high bandwidth and high transmission rate of data transmission can be met.

It should be noted that the CDFP connector is used not only for receiving and sending PCIe signals (i.e., receiving PCIe signals sent by the PCIe device to which it is connected, and sending PCIe signals to the PCIe device to which it is connected), but also for sending Send multiple preset signals to meet different needs. Specifically, the CDFP connector also sends a VPP (Virtual Pin Port, Virtual Pin Interface)_I2C (Inter-Integrated Circuit, Integrated Circuit Bus) signal and an Alert (reminder) signal to the corresponding PCIe Switch chip 120, and the VPP I2C signal and the Alert signal are used for hot plugging of hard disks in the SSD resource pool. It can be understood that the VPP I2C signal can be used for hot plug PCIe management. The Alert signal can be used for hot plug reminders. In addition, in order to achieve synchronization with the corresponding PCIe Switch chip 120, the CDFP connector also sends a PCIe clock signal to the corresponding PCIe Switch chip 120 to achieve clock synchronization. In addition, the CDFP connector also sends a Mngt (Management, Management)_I2C signal to the baseboard management controller 225 (BMC, Baseboard Management Controller) and one of all task management units for device information interaction between multiple resource pools. Furthermore, the CDFP connector also sends a Power enable signal, a Box present signal, and a PERST signal to the logic control unit 222 in the control module 220, which are used for identification, power on and off, and reset of the entire cabinet system. In addition, the CDFP connector also sends a Cable_I2C signal to the preset ID (Identity document) management unit for reading the CDFP cable information and performing encryption and decryption operations, as well as an ID_I2C signal for identifying the preset ID of the CDFP connector. Through the above definition of the signal type sent by the CDFP connector, compatibility with the Host resource pool, GPU resource pool, SSD resource pool, and Memory resource pool can be achieved.

It should also be noted that the MCIO connector is a standard board edge connector used for signal interconnection between PCIe Switch chips 120. In addition to the PCIe signal, the signal sent by the MCIO connector also includes an ID_I2C signal for different PCIe Switch chips 120 to identify the preset ID of the MCIO connector.

By building the above IO expansion architecture, a large or sufficient amount of IO resources can be better brought out, which can better meet the construction requirements of complex topologies in converged architecture systems. It has high flexibility and provides the possibility of engineering implementation for the construction of complex topologies in converged architecture systems. And by defining the sending signals of the CDFP connector in multiple ways, it can meet diverse functional requirements.

In FIG1, four IO expansion units are taken as an example. Each IO expansion unit has an expansion base plate 110, and four expansion base plates 110 are stacked in sequence. Each expansion base plate 110 is provided with two PCIe Switch chips 120, 8 internal connectors 130, and 10 external connectors 140. By setting two PCIe Switch chips 120, 8 internal connectors 130, and 10 external connectors 140 on each expansion base plate 110, sufficient IO resources can be drawn out, which is helpful for the construction of a converged architecture. Among them, one end of each of the four internal connectors 130 is connected to a corresponding PCIe Switch chip 120 on the same expansion base plate 110, and the other end is connected to the internal connectors 130 of other IO expansion units. One end of each of the five external connectors 140 is connected to a corresponding PCIe Switch chip 120 on the same expansion base plate 110, and the other end is used to connect to an external PCIe device to complete the interconnection of multiple PCIe devices and form a PCIe interconnection topology. In this way, the construction of the IO expansion architecture in the above embodiment is completed. The IO expansion architecture in this example can support the extraction of 40 IO resources. It can meet the construction requirements of complex topologies in the converged architecture system, is more convenient to implement, and has higher feasibility.

In some embodiments, the IO expansion unit is also used to connect to a preset ID management unit 210. Specifically, the internal connector 130 and the external connector 140 in the IO expansion unit are respectively used to connect to the ID management unit 210. The external connector 140 in the IO expansion unit is used to access a PCIe device to obtain a PCIe signal. The PCIe signal is transmitted to the PCIe Switch chip 120.

In some embodiments, the external connector 140 and the internal connector 130 are also used to send their respective ID signals to the ID management unit 210. The ID management unit 210 sends the ID signal to a preset control module 220, and the control module 220 performs interconnection topology identification based on the ID signal to obtain a PCIe interconnection topology; and, based on the PCIe interconnection topology, manages all the PCIe Switch chips 120 in the IO expansion architecture.

In some embodiments, the ID signal received by the PCIe Switch chip 120 is sent by the target management unit in the control module 220, and the target management unit is one of the baseboard management controller 225 and all the task management units in the control module 220. The target management unit is determined as follows: the logic control unit 222 in the control module 220 monitors the operating status of the baseboard management controller 225 and all the task management units; based on the operating status and the task management priorities corresponding to the baseboard management controller 225 and the task management units, one of the baseboard management controller 225 and all the task management units is determined as the target management unit.

In some embodiments, the ID management unit 210 sends the ID signal to a preset control module 220, including: the ID management unit 210 sends the ID signal to a multiplexer 221 (MUX, Multiplex) preset in the control module 220, the multiplexer 221 determines the target management unit based on the target management unit control instruction sent by the logic control unit 222, and sends all the received PCIe signals to the target management unit.

The IO expansion architecture in the above embodiment is provided with at least one IO expansion unit, wherein the IO expansion unit includes an expansion base plate 110, wherein the expansion base plate is provided with at least two PCIe Switch chips (simplified as SW in FIG. 1 ), a first preset number of internal connectors 130, and a second preset number of external connectors 140. One end of the internal connector 130 is connected to any one of the PCIe Switch chips 120 on the expansion base plate 110, and the other end of the internal connector 130 is used for interconnection between the PCIe Switch chips 120; and one end of the external connector 140 is connected to any one of the PCIe Switch chips 120 on the expansion base plate 110, and the other end of the external connector 140 is used for connecting PCIe devices to complete the interconnection between multiple PCIe devices. It can better support the extraction of a large amount or sufficient amount of IO resources, can better meet the construction requirements of complex topologies in a converged architecture system, has high flexibility, provides the possibility of engineering implementation for the construction of complex topologies in a converged architecture system, and has low cost.

Referring to FIG. 2 , this embodiment further provides an IO switch, including:

The ID management unit 210, the control module 220, and the IO expansion architecture as described above.

The ID management unit 210 is used to collect ID signals of all the internal connectors 130 and the external connectors 140 in the IO expansion architecture, and transmit the ID signals to the control module 220 .

The control module 220 is used to manage all the PCIe Switch chips 120 in the IO expansion architecture based on all the ID signals. The IO switch in this embodiment has good IO resource expansion and sharing capabilities, sufficient system robustness and flexibility, and can maintain IO exchanges between many PCIe devices in the entire cabinet. It can better meet the construction requirements of complex topologies in the converged architecture system, and provides the possibility of engineering implementation for the construction of complex topologies in the converged architecture system at a low cost.

Specifically, by setting the ID management unit 210 in the IO switch, it is possible to collect the ID signals of all the internal connectors 130 and the external connectors 140 in the IO expansion architecture, and send the collected ID signals to the external connectors 140. The IO switch in this embodiment can not only support the extraction of a large or sufficient amount of IO resources, but also better meet the construction requirements of complex topologies in the converged architecture system, with high flexibility, providing the possibility of engineering implementation for the construction of complex topologies in the converged architecture system, with low cost, strong feasibility and high degree of automation.

In some embodiments, each of the inner connector 130 and the outer connector 140 is connected to an ID definition chip, and the ID definition chip is used to perform ID definition on the corresponding inner connector 130 or the outer connector 140;

The ID management unit is specifically used to send an ID query instruction to each of the ID definition chips through the external connector 140 or the internal connector 130;

The ID definition chip is also used to receive the ID query instruction, and based on the ID query instruction, feed back the ID signal to the corresponding internal connector 130 or the external connector 140;

When receiving the ID signal, the internal connector 130 or the external connector 140 feeds the ID signal back to the ID management unit 210 .

The ID management unit 210 is connected to each of the external connectors 140 , the internal connectors 130 , and the control module 220 , respectively.

It should be noted that the ID management unit 210 is a core management unit in the IO switch, which is used to collect ID signals from all the internal connectors 130 or the external connectors 140, and transmit the collected ID signals to the target management unit. The target management unit is the baseboard management controller 225 in the control module 220 and one of all the task management units.

It should also be noted that the ID signals of each internal connector 130 and external connector 140 are different. In addition, in order to simplify the ID recognition algorithm, each of the ID definition chips has the same I2C (Inter-Integrated Circuit) address and is in exactly the same I2C channel. That is, during the ID signal acquisition process, the ID management unit 210 does not need to switch the access address multiple times, which speeds up the recognition speed, reduces the program complexity, has strong feasibility, low cost, and high recognition efficiency.

Please refer to FIG. 3 , in some embodiments, the control module 220 includes:

A multiplexer 221, configured to receive the ID signal transmitted by the ID management unit 210;

The logic control unit 222 is used to monitor the operating status of the baseboard management controller 225 and all the task management units; based on the operating status and the task management priorities corresponding to the baseboard management controller 225 and the task management units, determine that one of the baseboard management controller 225 and all the task management units is a target management unit; based on the determined target management unit, generate a target management unit instruction; and send the target management unit instruction to the multiplexer 221;

The multiplexer 221 is further used to determine the target management unit based on the target management unit instruction and send the ID signal to the target management unit;

The baseboard management controller 225 and at least one task management unit are used to perform PCIe topology identification based on the ID signal when receiving the ID signal to obtain a PCIe interconnection topology; perform PCIe topology identification on all the PCIe Switch chips 120 based on the PCIe interconnection topology. Bank management;

The ID management unit 210 is connected to the multiplexer 221, and the multiplexer 221 is respectively connected to the logic control unit 222, the baseboard management controller 225, and all the task management units. The ID management unit 210 and the multiplexer 221 can perform signal transmission or communication based on any one of USB (Universal Serial Bus), I2C and UART (Universal Asynchronous Receiver/Transmitter). Similarly, signal transmission or communication can be performed between the multiplexer 221 and the logic control unit 222, between the multiplexer 221 and the baseboard management controller 225, and between the multiplexer 221 and each of the task management units based on any one of USB, I2C and UART. Based on the different types of signal transmission, corresponding communication protocols or communication methods can be adopted to meet different communication requirements and support functional diversification.

Specifically, the multiplexer 221 receives the PCIe signal transmitted by the ID management unit 210, and sends the PCIe signal to the target management unit. The determination of the target management unit is determined by the logic control unit 222. That is, the logic control unit 222 monitors the operating status of the baseboard management controller 225 and all the task management units in real time; based on the operating status and the task management priorities corresponding to the baseboard management controller 225 and the task management unit, one of the baseboard management controller 225 and all the task management units is determined as the target management unit; based on the determined target management unit, a target management unit instruction is generated; the target management unit instruction is sent to the multiplexer 221; the multiplexer 221 determines the target management unit based on the target management unit instruction, and sends the PCIe signal to the target management unit.

It should be noted that the baseboard management controller 225 and all the task management units in this embodiment can all realize the function of managing all the PCIe Switch chips 120. From this functional point of view, the baseboard management controller 225 and all the task management units are redundant. The above embodiment can maximize the reliability of the IO switch and avoid unnecessary losses caused by the failure of a single signal distribution functional unit by determining one of the baseboard management controller 225 and all the task management units as the target management unit.

It should also be noted that the management priority of all the PCIe Switch chips 120 lies mainly in the task management unit, that is, when all the task management units fail, that is, when all the task management units are in abnormal operation state, the baseboard management controller 225 is determined as the target management unit, and the baseboard management controller 225 as the target management unit performs subsequent signal allocation and processing.

It should be mentioned that, in addition to the function of managing all the PCIe Switch chips 120, the baseboard management controller 225 in this embodiment also needs to monitor the basic information of the entire IO switch, such as collecting information from the temperature sensor preset in the IO switch, and performing basic information monitoring, and performing corresponding adjustments based on basic information such as temperature, such as increasing or decreasing the heat dissipation level of the heat dissipation unit 320 preset in the IO switch.

In addition, in order to achieve information synchronization between the baseboard management controller 225 and all the task management units, and to reduce the difficulty of function switching of signal distribution between the baseboard management controller 225 and all the task management units, the baseboard management controller 225 and all the task management units communicate with each other to achieve real-time data exchange and backup, thereby greatly improving the stability and reliability of the IO switch.

In some embodiments, the baseboard management controller 225 complies with RunBMC (an open source hardware specification) The standardized daughter card facilitates the subsequent BMC chip upgrade. In addition, the BMC management unit supports a TF (Trans-flash, flash memory) card and related chassis management function interfaces.

In some embodiments, the task management unit refers to a CPU (Central Processing Unit) management unit.

In some embodiments, at least one of the task management units includes: a first task management unit 223 and a second task management unit 224. That is, a first CPU management unit and a second CPU management unit. By setting the first CPU management unit and the second CPU management unit, redundancy of the task management unit is formed, which helps to improve the stability and reliability of the IO switch. In order to better realize engineering, in some embodiments, the first CPU management unit and the second CPU management unit are both buckle cards that comply with the COMe (COM Express) specification, which is convenient for subsequent processor upgrades. In addition, each of the task management units supports a PCIe network card, a PCIe NVMe (Non-Volatile Memory express, non-volatile memory host controller interface specification) hard disk or SATA (Serial Advanced Technology Attachment, Serial ATA) hard disk, a PCIe debug interface (for PCIe Switch chip 120) and other IO resources.

It should be noted that the first task management unit 223, the second task management unit 224 and the baseboard management controller 225 are used for system management of the IO switch, and are mutually redundant. The redundancy setting between the three can better ensure the stable operation of the IO switch.

In some embodiments, the logic control unit 222 is specifically used to determine the first task management unit 223 as the target management unit when the first task management unit 223 is in a normal operating state; determine the second task management unit 224 as the target management unit when the first task management unit 223 is in an abnormal operating state and the second task management unit 224 is in a normal operating state; determine the baseboard management controller 225 as the target management unit when both the first task management unit 223 and the second task management unit 224 are in an abnormal operating state and the baseboard management controller 225 is in a normal operating state. That is, the task management priority in this embodiment is the first task management unit 223-the second task management unit 224-the baseboard management controller 225. By setting the above task management priority and using the task management priority, the first task management unit 223, the second task management unit 224 and the baseboard management controller 225 are task-switched, that is, which unit or controller is responsible for receiving ID signals, performing PCIe interconnection topology identification, and managing all the PCIe Switch chips 120. The stability and reliability of the IO switch can be well guaranteed, and the flexibility is high. The logic control unit 222 can well realize the redundant switching, power-on and power-off timing and reset logic control in the IO switch, and can accurately guarantee the operation of the IO switch.

It should be noted that, when the first task management unit 223 is in an abnormal operating state, and the second task management unit 224 is in a normal operating state, the second task management unit 224 is determined as the target management unit. At the same time, an attempt is made to restart the first task management unit 223. If the restart is completed, the multiplexer 221 will be notified to switch the control to the first task management unit 223, that is, the first task management unit 223 will be re-determined as the target management unit. Similarly, when the first task management unit 223 and the second task management unit 224 are both in an abnormal operating state, and the baseboard management controller 225 is in a normal operating state, the baseboard management controller 225 will be determined as the target management unit. At the same time, an attempt is made to restart the first task management unit 223 and the second task management unit 224. In the case where the first task management unit 223 is restarted successfully, the first task management unit 223 will be determined as the target management unit. When the second task management unit 224 is successfully restarted and the first task management unit 223 is not successfully restarted, the second task management unit 224 is determined as the target management unit. Thus, the stable operation of the IO switch can be better guaranteed.

During the specific implementation process, the number of task management units can be increased or decreased according to actual conditions to meet different actual needs.

In some embodiments, the baseboard management controller 225 and the task management unit are specifically used to send corresponding configuration information to each PCIe Switch chip when identifying the PCIe interconnection topology; the configuration information includes type information of all connection interfaces of the PCIe Switch chip; the connection interface includes an interface for connecting to the internal connector or the external connector; the type information includes: uplink interface information, downlink interface information and internal interconnection interface information; the uplink interface information indicates that the corresponding connection interface is an uplink interface, and the uplink interface is used to transmit PCIe signals to the PCIe device connected upstream; the downlink interface information indicates that the corresponding connection interface is a downlink interface, and the downlink interface is used to transmit the PCIe signal to the PCIe device connected downstream; the interconnection interface information indicates that the corresponding connection interface is an internal interconnection interface, and the internal interconnection interface is used to transmit the PCIe signal to the remaining PCIe Switch chips interconnected with the current PCIe Switch chip; the uplink PCIe device refers to the host, and the downlink PCIe device is a graphics processor, a solid state drive or a memory;

The PCIe Switch chip is used to configure all of its own connection interfaces based on the received configuration information.

Specifically, when the baseboard management controller 225 is the target management unit, the baseboard management controller 225 receives the ID signal, performs topology identification based on all the ID signals, and obtains the PCIe interconnection topology. When the PCIe interconnection topology is identified, corresponding configuration information is sent to each PCIe Switch chip 120 respectively; the configuration information includes type information of all connection interfaces of the PCIe Switch chip 120; the connection interface includes an interface for connecting to the internal connector or the external connector; the type information includes: uplink interface information, downlink interface information and internal interconnection interface information; the uplink interface information indicates that the corresponding connection interface is an uplink interface, and the uplink interface is used to transmit PCIe signals to the PCIe device connected upstream; the downlink interface information indicates that the corresponding connection interface is a downlink interface, and the downlink interface is used to transmit the PCIe signal to the PCIe device connected downstream; the interconnection interface information indicates that the corresponding connection interface is an internal interconnection interface, and the internal interconnection interface is used to transmit the PCIe signal to the remaining PCIe Switch chips 120 interconnected with the current PCIe Switch chip; the uplink PCIe device refers to the host, and the downlink PCIe device is a graphics processor, a solid state drive or a memory. The PCIe Switch chip 120 is used to configure all of its own connection interfaces based on the received configuration information.

Similarly, when the task management unit is the target management unit, the task management unit receives the ID signal, performs topology identification based on all the ID signals, and obtains the PCIe interconnection topology. When the PCIe interconnection topology is identified, corresponding configuration information is sent to each PCIe Switch chip 120; the configuration information includes type information of all connection interfaces of the PCIe Switch chip 120; the connection interface includes an interface for connecting to the internal connector or the external connector; the type information includes: uplink interface information, downlink interface information, and internal interconnection interface information; the uplink interface information refers to the corresponding connection interface information. The connection interface is an upstream interface, and the upstream interface is used to transmit PCIe signals to the upstream connected PCIe device; the downstream interface information indicates that the corresponding connection interface is a downstream interface, and the downstream interface is used to transmit the PCIe signal to the downstream connected PCIe device; the interconnection interface information indicates that the corresponding connection interface is an internal interconnection interface, and the internal interconnection interface is used to transmit the PCIe signal to the remaining PCIe Switch chips 120 interconnected with the current PCIe Switch chip; the upstream connected PCIe device refers to the host, and the downstream connected PCIe device is a graphics processor, a solid state drive or a memory. The PCIe Switch chip 120 is used to configure all of its own connection interfaces based on the received configuration information.

In some embodiments, the PCIe Switch chip 120 is used to obtain the target device type corresponding to the PCIe signal when receiving the PCIe signal sent by the PCIe device; based on the target device type, determine at least one target interface corresponding to the target device type from all the connection interfaces of the current PCIe Switch chip 120, and determine that the PCIe device connected to the target interface is the target PCIe device; send a status query instruction to the target PCIe device through the target interface; receive the task processing status fed back by each of the target PCIe devices, the task processing status being fed back by the target PCIe device based on the status query instruction; and send the PCIe signal to any of the target PCIe devices whose task processing status is an idle state.

In some embodiments, the PCIe Switch chip 120 is specifically used to transmit the PCIe signal to a preset message queue when the task processing status fed back by all the target PCIe devices is in the working state; and when any of the target PCIe devices is detected to be in the idle state, based on the message queue, transmit the PCIe signal to the target PCIe device in the idle state.

Through the above method, the transmission efficiency of PCIe signals can be improved well, and the feasibility is strong.

It should be noted that each type of target PCIe device corresponds to a message queue. For example: when the type of the target PCIe device is a solid-state drive, and all target PCIe devices are in working state, the current PCIe signal is placed in the message queue corresponding to the solid-state drive. In addition, the task processing status of all target PCIe devices (solid-state drives) is monitored in real time. When the task processing status of any of the target PCIe devices is the idle state, the PCIe signal in the message queue is sent to the target PCIe device in the idle state.

In some embodiments, when acting as target management units, the baseboard management controller 225 and the task management unit both manage and schedule the PCIe Switch chip 120 in the IO expansion unit to achieve the exchange of the PCIe signals, which has high flexibility.

In some embodiments, it also includes: a network management unit 310, which is connected to the baseboard management controller 225, the task management unit and the IO expansion unit respectively to complete the intercommunication between the baseboard management controller 225, the IO expansion unit, and all the task management units.

Specifically, the baseboard management controller 225, the IO expansion unit, and all the task management units can communicate with each other through the network management unit 310, that is, realize Ethernet communication between each other, so as to complete real-time data exchange and data backup, which helps to improve the task switching speed between the baseboard management controller 225 and all the task management units (the task refers to the signal distribution or processing task), and helps to improve the stability of the IO switch. Based on the network management unit 310 in the above embodiment, the baseboard management controller 225, the task management unit and the IO expansion unit can be connected in a star shape, and any two devices can access each other.

It should be noted that each PCIe Switch chip 120 of the IO expansion unit is provided with a network interface for realizing network connection.

In some embodiments, the network management unit 310 is also externally connected to a plurality of network interfaces, which can be used to access any device among the baseboard management controller 225, the task management unit, and the PCIe Switch chip 120. The network interface can be an RJ45 (Registered Jack 45, a type of connector) network interface.

The baseboard management controller 225 and the task management unit both transmit configuration information to the IO expansion unit through the network management unit 310 .

In some embodiments, it also includes: a heat dissipation unit 320 for dissipating heat for the IO switch. Specifically, the heat dissipation unit 320 is composed of 4 dual-rotor fans, supports forward and reverse rotation, supports fan redundancy design, ensures the heat dissipation of the IO switch, and helps to improve the stability of the IO switch. It should be noted that the number of the dual-rotor fans can be increased or decreased according to actual conditions to meet the needs of different scenarios.

In some embodiments, it further includes: a power rail unit 330, the input end of the power rail unit 330 is used to connect to the power supply unit, and the output end of the power rail unit 330 is respectively connected to the IO expansion unit, the ID management unit 210, the baseboard management controller 225 and the task management unit, and is used to supply power to the IO expansion unit, the ID management unit 210, the baseboard management controller 225 and the task management unit. In some embodiments, the power rail unit 330 is also used to supply power to the heat dissipation unit 320. Specifically, a 12V power supply can be used to supply power to the heat dissipation unit 320. By setting the power rail unit 330, the power supply requirements of multiple devices in the IO switch can be met.

In some embodiments, the power supply unit includes: a PSU (Power Supply Unit, power supply, alternating current) power supply unit 340 and an HVDC (High Voltage Direct Current, high voltage direct current) power supply unit 350. By being compatible with the PSU power supply unit 340 and the HVDC power supply unit 350, a variety of power supply requirements can be met. The PSU power supply unit 340 is connected to an external alternating current (AC) power supply, and the HVDC power supply unit 350 is connected to an external direct current (DC) power supply (DC power supply). In a compatible manner between the AC power supply and the DC power supply, the external power supply is converted into 12V used inside the IO switch to meet different power supply scenarios. The above-mentioned AC power supply can be 220V, etc., and the DC power supply can be 380V, etc.

In some embodiments, the logic control unit 222 is further configured to send a power switch signal (PWREN) to the power rail unit 330 to control the power rail to start or stop supplying power.

In some embodiments, the first preset number of the inner connectors 130 are distributed on the first side of the corresponding extension base 110, and the second preset number of the outer connectors 140 are distributed on the second side of the corresponding extension base 110, and the first side and the second side are opposite sides. By adopting the above method to arrange the inner connectors 130 and the outer connectors 140, the wiring difficulty and complexity can be reduced.

The IO switch in the above embodiment can realize the extraction of a large number or sufficient IO resources to connect upstream and downstream PCIe devices by adopting a highly flexible IO expansion architecture. In addition, by adopting a multiplexer 221, a logic control unit 222, a first task management unit 223 and a second task management unit 224, the stability and reliability of the IO switch operation can be better guaranteed, with low cost, high feasibility, and high density, robustness and flexibility. It has strong system robustness to maintain the stability of the IO switch system and ensure IO data exchange between many devices in the entire cabinet. It has flexible scalability and is compatible with different power supply methods and different forms of PCIe Switch interconnection topologies. flutter.

The PCIe device provided in the present application is described below. The PCIe device described below and the IO switch described above can refer to each other.

This embodiment further provides a PCIe device, including: a switch connector, the switch connector is used to connect to the external connector 140 in the above-mentioned IO expansion architecture, or to connect to the external connector 140 in any one of the above-mentioned IO switches. The PCIe device in this embodiment can better realize the interaction and intercommunication between different PCIe resources by connecting to the external connector 140 in the above-mentioned IO expansion architecture, or to connect to the external connector 140 in any one of the above-mentioned IO switches, and has high flexibility.

In some embodiments, the switch connector is the same type of connector as the external connector 140. Specifically, the switch connector is a CDFP connector.

In some embodiments, the PCIe device is a host, a graphics processing unit (GPU), a solid state drive (SSD), or a memory.

The PCIe fusion architecture system provided by the present application is described below. The PCIe fusion architecture system described below and the IO switch and PCIe device described above can be referenced to each other.

This embodiment also provides a PCIe fusion architecture system, including:

The IO switch as described in any one of the above, and the multiple PCIe devices as described in any one of the above, the multiple PCIe devices are respectively connected to the corresponding external connector 140. The PCIe converged architecture system in this embodiment can better support the extraction of a large number or sufficient IO resources, can better meet the construction requirements of complex topologies in the converged architecture system, has high flexibility, strong feasibility, and low cost.

Please refer to FIG4 . Taking eight PCIe Switch chips 120 as an example, each PCIe Switch chip 120 (in FIG4 , SW is used as a simplified representation) is connected to five external connectors 140 (in FIG4 , H/D is used as a simplified representation) and four internal connectors 130 (in FIG4 , F is used as a simplified representation). Each internal connector 130 is used to connect to the internal connectors 130 of other PCIe Switch chips 120 to form an interconnection between the PCIe Switch chips 120. Each external connector 140 is connected to a PCIe device, which can be a host, a solid-state drive, a graphics processor, or a memory. In FIG4 , eight PCIe Switch chips 120 are exemplarily divided into four upper and four lower chips, and the external connectors 140 of the four upper PCIe Switch chips 120 are connected to the host (such as Host0...Host4, Host5...Host9, Host10...Host14, Host15...Host19 in FIG4 ). And the external connectors 140 of the four lower PCIe Switch chips 120 are connected to the solid state drive, graphics processor or memory (such as Device 0...Device4, Device5...Device9, Device10...Device14, Device15...Device19 in FIG4 ), that is, the Device in FIG4 can be a solid state drive, a graphics processor or a memory. In the Host-IO switch-Device mode, a PCIe fusion architecture system is built, which has strong real-time performance and better meets the construction requirements of complex topologies. It can schedule and allocate many GPU resources, SSD resources and Memory resources between different hosts. It should be mentioned that in the specific implementation process, other topological forms can also be used for topological construction.

For another example, taking six PCIe Switch chips 120 as an example, each PCIe Switch chip 120 is connected to five external connectors 140 and three or four internal connectors 130. Each internal connector 130 is used to connect to the internal connector 130 of other PCIe Switch chips 120 to form interconnections between the PCIe Switch chips 120. Each external connector 140 is connected to a PCIe device, which may be a host, a solid-state drive, a graphics processor, or a memory. The six PCIe Switch chips 120 may be divided into three upper and three lower ones, and the external connectors 140 of the three upper PCIe Switch chips 120 may be connected to the host. The external connectors 140 of the three lower PCIe Switch chips 120 may be connected to a solid-state drive, a graphics processor, or a memory. This may enable the construction of a converged architecture or a PCIe interconnection topology based on six PCIe Switch chips 120. It may be possible to schedule and allocate a number of GPU resources, SSD resources, and Memory resources between different Hosts to meet different converged architecture construction requirements.

In addition, taking four PCIe Switch chips 120 as an example, correspondingly, every two PCIe Switch chips 120 are arranged on the same expansion substrate 110. Each PCIe Switch chip 120 is connected to five external connectors 140 and two, three or four internal connectors 130. Each internal connector 130 is used to connect to the internal connectors 130 of other PCIe Switch chips 120 to form an interconnection between the PCIe Switch chips 120. Each external connector 140 is connected to a PCIe device, which can be a host, a solid state drive, a graphics processor or a memory. The four PCIe Switch chips 120 can be divided into two upper and two lower ones, and the external connectors 140 of the two upper PCIe Switch chips 120 are connected to the host. And the external connectors 140 of the two lower PCIe Switch chips 120 are connected to the solid state drive, the graphics processor or the memory. This enables the construction of a fusion architecture or PCIe interconnection topology based on four PCIe Switch chips 120, with high flexibility.

Take two PCIe Switch chips 120 as an example. Correspondingly, the two PCIe Switch chips 120 are arranged on the same expansion substrate 110. Each PCIe Switch chip 120 is connected to five external connectors 140 and one internal connector 130. Each PCIe Switch chip 120 is connected to the internal connector 130 of other PCIe Switch chips 120 through its own internal connector 130 to form an interconnection between the two PCIe Switch chips 120. Each external connector 140 is connected to a PCIe device, which can be a host, a solid state drive, a graphics processor or a memory. Connect the external connector 140 of one PCIe Switch chip 120 to the host. And connect the external connector 140 of another PCIe Switch chip 120 to the solid state drive, the graphics processor or the memory. This enables construction of a fusion architecture or PCIe interconnection topology based on two PCIe Switch chips 120, with high flexibility and low cost.

The above examples are respectively given with 8, 6, 4 and 2 PCIe Switch chips 120. It can be seen that the PCIe fusion architecture system in the above embodiment has a high degree of flexibility. In the specific implementation process, the above PCIe interconnection topology can be adaptively modified according to actual needs, which will not be repeated here.

It should be noted that the PCIe converged architecture system in the above embodiment can better support the extraction of a large or sufficient amount of IO resources, can better meet the construction requirements of complex topologies in the converged architecture system, has high flexibility, and provides the possibility of engineering implementation for the construction of complex topologies in the converged architecture system. It has high density, robustness and flexibility, and can meet the application requirements of different scenarios.

The PCIe signal fusion management method provided in the present application is described below. The PCIe signal fusion management method described below and the PCIe fusion architecture system described above can be referenced to each other.

Please refer to FIG. 5 , this embodiment further provides a PCIe signal fusion management method based on the PCIe fusion architecture system as described above, including:

S510: Receive a PCIe signal sent by a PCIe device.

S520: Obtain a target device type corresponding to the PCIe signal.

S530: Based on the target device type, determine at least one target interface corresponding to the target device type from all connection interfaces of the current PCIe Switch chip, and determine that the PCIe device connected to the target interface is the target PCIe device.

S540: Send a status query instruction to the target PCIe device through the target interface.

S550: Receive a task processing status fed back by each of the target PCIe devices, where the task processing status information is fed back by the target PCIe device based on the status query instruction.

S560: Send the PCIe signal to any target PCIe device whose task processing state is idle. This method can improve the transmission efficiency of PCIe signals in a PCIe converged architecture system, has high flexibility, strong feasibility and low cost.

In some embodiments, the PCIe signal fusion management method further includes: when the task processing status fed back by all the target PCIe devices is in a working state, transmitting the PCIe signal to a preset message queue; when any of the target PCIe devices is monitored to be in an idle state, based on the message queue, transmitting the PCIe signal to the target PCIe device in an idle state.

It should be noted that the PCIe signal fusion management method in the above embodiment is based on the PCIe fusion architecture system in the above embodiment. The PCIe fusion architecture system can better support the extraction of a large or sufficient amount of IO resources, can better meet the construction requirements of complex topologies in the fusion architecture system, has high flexibility, provides the possibility of engineering implementation for the construction of complex topologies in the fusion architecture system, has low cost, and has both high density, robustness and flexibility.

In summary, the IO expansion architecture, IO switch and PCIe device provided by the present application are provided with at least one IO expansion unit, the IO expansion unit includes an expansion substrate, the expansion substrate is provided with at least two PCIe Switch chips, a first preset number of internal connectors, and a second preset number of external connectors; one end of the internal connector is connected to any PCIe Switch chip on the expansion substrate, and the other end of the internal connector is used for interconnection between PCIe Switch chips; one end of the external connector is connected to any PCIe Switch chip on the expansion substrate, and the other end of the external connector is used to connect PCIe devices to complete the interconnection between multiple PCIe devices. It can better support the extraction of a large number or sufficient amount of IO resources, can better meet the construction requirements of complex topologies in converged architecture systems, has high flexibility, provides the possibility of engineering implementation for the construction of complex topologies in converged architecture systems, and has low cost. In addition, through multiple experiments, a construction plan for PCIe interconnection topology with high feasibility is proposed, which can meet the construction requirements of complex topologies in different scenarios while supporting the standard definition of server size. It has both high density, robustness and flexibility. It has enough PCIe expansion capabilities to connect upstream and downstream PCIe devices. It also has strong system robustness to maintain the stability of the IO switch system and ensure the exchange of IO data or PCIe signals between many devices in the entire cabinet.

FIG6 illustrates a schematic diagram of the physical structure of an electronic device. As shown in FIG6 , the electronic device may include: a processor 610, a communications interface 620, a memory 630, and a communications bus 640, wherein the processor 610, the communications interface 620, and the memory 630 communicate with each other via the communications bus 640. The processor 610 may call the logic instructions in the memory 630 to execute a PCIe signal fusion management method, the method comprising: receiving a PCIe signal sent by a PCIe device; obtaining a target device type corresponding to the PCIe signal; based on the target device type, determining at least one target interface corresponding to the target device type from all connection interfaces of the current PCIe Switch chip, and determining the PCIe device connected to the target interface as a target PCIe device; sending a status query instruction to the target PCIe device through the target interface; receiving the task processing status fed back by each of the target PCIe devices, wherein the task processing status information is fed back by the target PCIe device based on the status query instruction; sending the PCIe signal to any of the target PCIe devices whose task processing status is an idle state.

In addition, the logic instructions in the above-mentioned memory 630 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the relevant technology. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

On the other hand, the present application also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the PCIe signal fusion management method provided by the above methods, the method comprising: receiving a PCIe signal sent by a PCIe device; obtaining a target device type corresponding to the PCIe signal; based on the target device type, determining at least one target interface corresponding to the target device type from all connection interfaces of the current PCIe Switch chip, and determining that the PCIe device connected to the target interface is a target PCIe device; sending a status query instruction to the target PCIe device through the target interface; receiving a task processing status fed back by each of the target PCIe devices, the task processing status information being fed back by the target PCIe device based on the status query instruction; and sending the PCIe signal to any of the target PCIe devices whose task processing status is an idle state.

The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, by hardware. Based on this understanding, the above technical solution can be essentially or in other words, the part that contributes to the relevant technology can be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as ROM/RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiment.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims (20)

An IO expansion architecture, characterized by comprising: At least one IO expansion unit, the IO expansion unit comprising an expansion base plate, the expansion base plate having at least two PCIe Switch chips, a first preset number of internal connectors, and a second preset number of external connectors; One end of the internal connector is connected to any one of the PCIe Switch chips on the extension baseboard, and the other end of the internal connector is used for interconnection between the PCIe Switch chips; one end of the external connector is connected to any one of the PCIe Switch chips on the extension baseboard, and the other end of the external connector is used to connect a PCIe device to complete the interconnection between multiple PCIe devices. An IO switch, characterized by comprising: An ID management unit, a control module, and an IO expansion architecture as claimed in claim 1; The ID management unit is used to collect ID signals of all the internal connectors and the external connectors in the IO expansion architecture, and transmit the ID signals to the control module; The control module is used to manage all the PCIe Switch chips in the IO expansion architecture based on all the ID signals. The IO switch according to claim 2, characterized in that: Each of the inner connector and the outer connector is connected to an ID definition chip, and the ID definition chip is used to perform ID definition on the corresponding inner connector or the outer connector; The ID management unit is specifically used to send an ID query instruction to each of the ID definition chips through the external connector or the internal connector; The ID definition chip is also used to receive the ID query instruction, and based on the ID query instruction, feed back the ID signal to the corresponding internal connector or the external connector; When receiving the ID signal, the internal connector or the external connector feeds back the ID signal to the ID management unit; The ID management unit is connected to each of the external connectors, the internal connectors and the control module respectively. The IO switch according to claim 2, wherein the control module comprises: A multiplexer, used for receiving the ID signal transmitted by the ID management unit; A logic control unit, configured to monitor the operating status of a baseboard management controller and all task management units; based on the operating status and the task management priorities corresponding to the baseboard management controller and the task management unit, determine one of the baseboard management controller and all the task management units as a target management unit; based on the determined target management unit, generate a target management unit instruction; and send the target management unit instruction to the multiplexer; The multiplexer is further used to determine the target management unit based on the target management unit instruction and send the ID signal to the target management unit; A baseboard management controller and at least one task management unit, wherein the baseboard management controller and the task management unit are both used to perform PCIe topology identification based on the ID signal when receiving the ID signal, and obtain PCIe interconnection topology; based on the PCIe interconnection topology, managing all the PCIe Switch chips; The ID management unit is connected to the multiplexer, and the multiplexer is respectively connected to the logic control unit, the baseboard management controller, and all the task management units. The IO switch according to claim 4, characterized in that at least one of the task management units comprises: a first task management unit and a second task management unit; The logic control unit is specifically used to determine the first task management unit as the target management unit when the first task management unit is in a normal operating state; to determine the second task management unit as the target management unit when the first task management unit is in an abnormal operating state and the second task management unit is in a normal operating state; and to determine the baseboard management controller as the target management unit when both the first task management unit and the second task management unit are in an abnormal operating state and the baseboard management controller is in a normal operating state. The IO switch according to claim 4 is characterized in that the baseboard management controller and the task management unit are specifically used to send corresponding configuration information to each of the PCIe Switch chips when the PCIe interconnection topology is identified; the configuration information includes type information of all connection interfaces of the PCIe Switch chip; the connection interface includes an interface for connecting to the internal connector or the external connector; the type information includes: uplink interface information, downlink interface information and internal interconnection interface information; the uplink interface information indicates that the corresponding connection interface is an uplink interface , the upstream interface is used to transmit PCIe signals to the PCIe device connected upstream; the downstream interface information indicates that the corresponding connection interface is a downstream interface, and the downstream interface is used to transmit the PCIe signal to the PCIe device connected downstream; the interconnection interface information indicates that the corresponding connection interface is an internal interconnection interface, and the internal interconnection interface is used to transmit the PCIe signal to the remaining PCIe Switch chips interconnected with the current PCIe Switch chip; the PCIe device connected upstream refers to the host, and the PCIe device connected downstream is a graphics processor, a solid-state drive or a memory; The PCIe Switch chip is used to configure all of its own connection interfaces based on the received configuration information. The IO switch according to claim 6 is characterized in that the PCIe Switch chip is used to obtain the target device type corresponding to the PCIe signal when receiving the PCIe signal sent by the PCIe device; based on the target device type, determine at least one target interface corresponding to the target device type from all the connection interfaces of the current PCIe Switch chip, and determine that the PCIe device connected to the target interface is the target PCIe device; send a status query instruction to the target PCIe device through the target interface; receive the task processing status fed back by each of the target PCIe devices, the task processing status being fed back by the target PCIe device based on the status query instruction; and send the PCIe signal to any of the target PCIe devices whose task processing status is an idle state. The IO switch according to claim 7 is characterized in that the PCIe Switch chip is specifically used to transmit the PCIe signal to a preset message queue when the task processing status fed back by all the target PCIe devices is in a working state; and when it is monitored that any of the target PCIe devices is in an idle state, based on the message queue, transmit the PCIe signal to the target PCIe device in an idle state. The IO switch according to claim 6 or 7, characterized in that it also includes: a network management unit, The network management unit is connected to the baseboard management controller, the task management unit and the IO expansion unit respectively to achieve two-to-two communication between the baseboard management controller, the IO expansion unit and all the task management units. The IO switch according to claim 2, further comprising: a heat dissipation unit for dissipating heat from the IO switch. The IO switch according to claim 4 is characterized in that it further comprises: a power rail unit, the input end of the power rail unit is used to connect to the power supply unit, and the output end of the power rail unit is respectively connected to the IO expansion unit, the ID management unit, the baseboard management controller and the task management unit, for supplying power to the IO expansion unit, the ID management unit, the baseboard management controller and the task management unit. The IO switch according to claim 11, characterized in that the logic control unit is further used to send a power switch signal to the power rail unit to control the power rail unit to start or stop power supply. The IO switch according to claim 2, characterized in that the first preset number of the internal connectors are distributed on a first side of the corresponding extension base plate, the second preset number of the external connectors are distributed on a second side of the corresponding extension base plate, and the first side and the second side are opposite sides. A PCIe device, characterized in that it includes: a switch connector, wherein the switch connector is used to connect to the external connector in the IO expansion architecture described in claim 1, or to connect to the external connector in the IO switch described in any one of claims 2 to 13. The PCIe device according to claim 14, wherein the switch connector and the external connector are the same type of connector. The PCIe device according to claim 14 is characterized in that the PCIe device is a host, a graphics processor, a solid-state drive or a memory. A PCIe fusion architecture system, comprising: An IO switch according to any one of claims 2 to 13, and a plurality of PCIe devices according to any one of claims 14 to 16, wherein the plurality of PCIe devices are respectively connected to the corresponding external connectors. A PCIe signal fusion management method based on the PCIe fusion architecture system according to claim 17, characterized in that it includes: Receive PCIe signals sent by PCIe devices; Obtaining the target device type corresponding to the PCIe signal; Based on the target device type, determining at least one target interface corresponding to the target device type from all connection interfaces of the current PCIe Switch chip, and determining the PCIe device connected to the target interface as the target PCIe device; Sending a status query instruction to the target PCIe device through the target interface; Receiving a task processing status fed back by each of the target PCIe devices, wherein the task processing status information is fed back by the target PCIe device based on the status query instruction; The PCIe signal is sent to any of the target PCIe devices whose task processing state is an idle state. An electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to claim 18 when executing the program. PCIe signal fusion management method. A non-transitory computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the PCIe signal fusion management method as described in claim 18 is implemented.