TW201831246A - Method for manufacturing wiring structure - Google Patents
Method for manufacturing wiring structure Download PDFInfo
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- TW201831246A TW201831246A TW107100549A TW107100549A TW201831246A TW 201831246 A TW201831246 A TW 201831246A TW 107100549 A TW107100549 A TW 107100549A TW 107100549 A TW107100549 A TW 107100549A TW 201831246 A TW201831246 A TW 201831246A
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C2/00—Hot-dipping or immersion processes for applying the coating material in the molten state without affecting the shape; Apparatus therefor
- C23C2/04—Hot-dipping or immersion processes for applying the coating material in the molten state without affecting the shape; Apparatus therefor characterised by the coating material
- C23C2/08—Tin or alloys based thereon
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Abstract
本發明旨在提供一種配線構造的製造方法。其包括準備夾著絕緣層(11)在表面上形成有配線層(13)的基板(10)的製程;蝕刻基板的背面而形成通孔(20)的製程,該通孔(20)沿厚度方向貫通絕緣層(11)且具有底部,配線層(13)位於底部的下方;在通孔的底部且配線層上依次形成第一金屬層(15)與第二金屬層(16)的製程;以及將Sn類熔融金屬17填充至通孔(20)內的製程。配線層由Al、Al合金或者Cu形成;第一金屬層由與Sn類熔融金屬形成合金之材料形成;第二金屬層由防止第一金屬層氧化之材料形成。 The present invention is directed to a method of manufacturing a wiring structure. It comprises a process of preparing a substrate (10) having a wiring layer (13) formed on the surface thereof with an insulating layer (11); a process of etching the back surface of the substrate to form a via hole (20), the via hole (20) along the thickness The direction penetrates the insulating layer (11) and has a bottom portion, and the wiring layer (13) is located below the bottom portion; a process of sequentially forming the first metal layer (15) and the second metal layer (16) on the bottom of the via hole and on the wiring layer; And a process of filling the Sn-based molten metal 17 into the via hole (20). The wiring layer is formed of Al, an Al alloy, or Cu; the first metal layer is formed of a material that forms an alloy with the Sn-based molten metal; and the second metal layer is formed of a material that prevents oxidation of the first metal layer.
Description
本發明係關於包括沿厚度方向貫通基板之貫通電極的配線構造的製造方法。 The present invention relates to a method of manufacturing a wiring structure including a through electrode that penetrates a substrate in a thickness direction.
經貫通電極將形成於基板之兩面的配線層間電連接起來的配線構造已為業界所知曉。這裡,貫通電極係藉由形成沿厚度方向貫通基板的通孔(via)並將導電材料填充至該通孔內而形成的。 A wiring structure in which wiring layers formed on both surfaces of a substrate are electrically connected via a through electrode is known in the art. Here, the through electrode is formed by forming a via penetrating through the substrate in the thickness direction and filling a conductive material into the through hole.
包括貫通電極的配線構造之形成方法例如有被稱為後鑽孔(via last)之方法。該方法係為:於基板的表面上形成積體電路後,再形成沿厚度方向貫通基板之貫通電極。於此情形,形成貫通電極之前,於基板的表面夾著絕緣膜形成配線層。而且,通孔係從背面蝕刻且貫通絕緣層而形成的。此時,配線層在通孔的底部露出來,藉由將導電材料填充至通孔內,便能夠將配線層與貫通電極電連接起來。 A method of forming a wiring structure including a through electrode is, for example, a method called via last. In this method, after the integrated circuit is formed on the surface of the substrate, a through electrode that penetrates the substrate in the thickness direction is formed. In this case, before the through electrodes are formed, a wiring layer is formed on the surface of the substrate with an insulating film interposed therebetween. Further, the via hole is formed by etching from the back surface and penetrating through the insulating layer. At this time, the wiring layer is exposed at the bottom of the via hole, and the wiring layer and the through electrode can be electrically connected by filling the conductive material into the via hole.
例如利用電解電鍍填充銅這一技術就是將導電材料填充至通孔內的技術之一。然而,因為沿厚度方向貫通基板之通孔的直徑小且縱橫比(aspect ratio)高,故很難可靠地將銅填充至通孔的底部,而且,若利用電解電鍍用銅填 充沿厚度方向貫通基板的通孔,則需要花費很長的時間。 For example, the technique of filling copper by electrolytic plating is one of techniques for filling a conductive material into a through hole. However, since the diameter of the through hole penetrating the substrate in the thickness direction is small and the aspect ratio is high, it is difficult to reliably fill the bottom of the through hole with copper, and if it is filled with copper by electrolytic plating, it is penetrated in the thickness direction. The through hole of the substrate takes a long time.
將熔融金屬填充至通孔內後再使其固化的技術(例如參照專利文獻1)係為業界所熟知之將導電材料填充至通孔內的其它技術之一。根據該技術,即使是高縱橫比的通孔,也很容易將熔融金屬填充至通孔的底部。而且,也能夠縮短將熔融金屬填充至通孔內的時間。 A technique of filling a molten metal into a through hole and then solidifying it (for example, refer to Patent Document 1) is one of other techniques well known in the art for filling a conductive material into a through hole. According to this technique, even a high aspect ratio through hole can easily fill the molten metal to the bottom of the through hole. Moreover, the time for filling the molten metal into the through hole can also be shortened.
[先前技術文獻] [Previous Technical Literature]
[專利文獻] [Patent Literature]
專利文獻1:日本特開2002-158191號公報。 Patent Document 1: Japanese Laid-Open Patent Publication No. 2002-158191.
將錫(Sn)系熔融金屬填充至通孔內而形成貫通電極之情形下,如果配線層係由鋁(Al)形成,則存在以下問題:在貫通電極與配線層之間會發生接觸不良的現象。如果配線層係由銅(Cu)形成,則又存在以下問題:在貫通電極附近會發生配線層導通不良的現象。 When a tin (Sn)-based molten metal is filled in a through hole to form a through electrode, when the wiring layer is formed of aluminum (Al), there is a problem in that contact failure occurs between the through electrode and the wiring layer. phenomenon. When the wiring layer is formed of copper (Cu), there is a problem that the wiring layer is poorly connected in the vicinity of the through electrode.
本發明正是鑑於上述問題而完成者。其主要目的在於:提供一種配線構造的製造方法,做到:於包括將Sn類熔融金屬填充至通孔內而形成之貫通電極的配線構造中,該貫通電極與配線層之間接觸良好,配線層也不會導通不良。 The present invention has been accomplished in view of the above problems. A main object of the invention is to provide a method for manufacturing a wiring structure in which a contact structure between a through electrode and a wiring layer is good in a wiring structure including a through electrode formed by filling a Sn-based molten metal into a via hole. The layer will not be poorly connected.
本發明之一種配線構造的製造方法,其包括:製程(A),準備基板,該基板夾著絕緣層在第一主面上形成有 配線層;製程(B),選擇性地蝕刻前述基板的第二主面而形成通孔,該通孔沿厚度方向貫通前述絕緣層,且具有底部,前述配線層位於前述底部的下方;製程(C),在與前述通孔的至少底部相對應的前述配線層上依次形成第一金屬層與第二金屬層;以及製程(D),將Sn類熔融金屬填充至前述通孔內。前述配線層由Al、Al合金或者Cu形成;前述第一金屬層在前述製程(D)中由與前述Sn類熔融金屬形成合金之材料形成;前述第二金屬層由防止前述第一金屬層氧化之材料形成。 A manufacturing method of a wiring structure according to the present invention, comprising: a process (A) for preparing a substrate having a wiring layer formed on the first main surface with an insulating layer interposed therebetween; and a process (B) for selectively etching the substrate a through hole formed in the second main surface, the through hole penetrating the insulating layer in a thickness direction, and having a bottom portion, the wiring layer being located below the bottom portion; and a process (C) at the bottom portion corresponding to at least a bottom portion of the through hole A first metal layer and a second metal layer are sequentially formed on the wiring layer; and a process (D) is performed to fill the through-holes of the Sn-based molten metal. The wiring layer is formed of Al, an Al alloy or Cu; the first metal layer is formed of a material which forms an alloy with the Sn-based molten metal in the process (D); and the second metal layer prevents oxidation of the first metal layer The material is formed.
本發明之另一種配線構造的製造方法,其包括:製程(A),準備基板,夾著絕緣層在該基板的第一主面上依次形成第二金屬層、第一金屬層以及配線層;製程(B),選擇性地蝕刻前述基板的第二主面而形成通孔,該通孔貫通前述絕緣層且具有底部,前述配線層位於前述底部的下方;以及製程(C),將Sn類熔融金屬填充至前述通孔內。前述配線層由Al、Al合金或者Cu形成;前述第一金屬層係在前述製程(C)中由與前述Sn類熔融金屬形成合金之材料形成;前述第二金屬層由防止前述第一金屬層氧化之材料形成。 Another manufacturing method of the wiring structure of the present invention comprises: a process (A), preparing a substrate, and sequentially forming a second metal layer, a first metal layer and a wiring layer on the first main surface of the substrate with an insulating layer interposed therebetween; a process (B) of selectively etching a second main surface of the substrate to form a via hole penetrating the insulating layer and having a bottom portion, the wiring layer being located below the bottom portion; and a process (C) of class Sn The molten metal is filled into the aforementioned through holes. The wiring layer is formed of Al, an Al alloy, or Cu; the first metal layer is formed of a material that forms an alloy with the Sn-based molten metal in the process (C); and the second metal layer is formed by preventing the first metal layer The oxidized material is formed.
根據本發明,能夠提供一種配線構造的製造方法,做到:於包括將Sn類熔融金屬填充至通孔內而形成之貫通電極的配線構造中,該貫通電極與配線層之間接觸良好,配線層也不會導通不良。 According to the present invention, it is possible to provide a method of manufacturing a wiring structure in which the contact between the through electrode and the wiring layer is good in a wiring structure including a through electrode formed by filling a Sn-based molten metal into a via hole. The layer will not be poorly connected.
10‧‧‧基板 10‧‧‧Substrate
10a‧‧‧基板的表面(第一主面) 10a‧‧‧ Surface of the substrate (first main surface)
10b‧‧‧基板的背面(第二主面) 10b‧‧‧Back side of the substrate (second main surface)
11‧‧‧絕緣層 11‧‧‧Insulation
12‧‧‧緊密附著層 12‧‧‧ Tight adhesion layer
13‧‧‧配線層 13‧‧‧Wiring layer
14‧‧‧絕緣膜 14‧‧‧Insulation film
15‧‧‧第一金屬層 15‧‧‧First metal layer
16‧‧‧第二金屬層 16‧‧‧Second metal layer
17‧‧‧Sn類熔融金屬(貫通電極) 17‧‧‧Sn class molten metal (through electrode)
18‧‧‧第一金屬層 18‧‧‧First metal layer
19‧‧‧第二金屬層 19‧‧‧Second metal layer
20‧‧‧通孔 20‧‧‧through hole
20a‧‧‧通孔的底部 20a‧‧‧Bottom of the through hole
30‧‧‧支撐體 30‧‧‧Support
40‧‧‧光阻圖案 40‧‧‧resist pattern
50‧‧‧支撐部 50‧‧‧Support
51、71‧‧‧驅動部 51, 71‧‧‧ Drive Department
60‧‧‧筒狀部 60‧‧‧Cylinder
70‧‧‧加壓部 70‧‧‧ Pressurization
80‧‧‧容器 80‧‧‧ container
81‧‧‧配管 81‧‧‧Pipe
82‧‧‧熔融金屬 82‧‧‧ molten metal
90、91‧‧‧密封部件 90, 91‧‧‧ Sealing parts
100‧‧‧處理室 100‧‧‧Processing room
圖1中的(a)至圖1中的(c)係為剖視圖,示意地顯示本發明第一實施方式之配線構造的製造方法。 (a) to (c) of FIG. 1 are cross-sectional views, and schematically show a method of manufacturing the wiring structure according to the first embodiment of the present invention.
圖2中的(a)至圖2中的(d)係為剖視圖,示意地顯示本發明第一實施方式之配線構造的製造方法。 (a) to (d) of FIG. 2 are cross-sectional views, and schematically show a method of manufacturing the wiring structure according to the first embodiment of the present invention.
圖3中的(a)至圖3中的(c)係為剖視圖,示意地顯示本發明第二實施方式之配線構造的製造方法。 (a) to (c) of FIG. 3 are cross-sectional views, and schematically show a method of manufacturing the wiring structure according to the second embodiment of the present invention.
圖4中的(a)至圖4中的(c)係為剖視圖,示意地顯示本發明第二實施方式之配線構造的製造方法。 4(a) to 4(c) are cross-sectional views schematically showing a method of manufacturing the wiring structure according to the second embodiment of the present invention.
圖5中的(a)與圖5中的(b)係為說明本發明之將Sn類熔融金屬填充至通孔內之方法的圖。 (a) of FIG. 5 and (b) of FIG. 5 are diagrams for explaining a method of filling a Sn-based molten metal into a through hole according to the present invention.
圖6中的(a)與圖6中的(b)係為說明本發明之將Sn類熔融金屬填充至通孔內之方法的圖。 (a) of FIG. 6 and (b) of FIG. 6 are diagrams for explaining a method of filling a Sn-based molten metal into a via hole according to the present invention.
作為填充至通孔內的熔融金屬,係採用熔點比形成配線層的鋁(Al)、銅(Cu)等低的錫(Sn),並由Sn形成貫通電極,本申請發明人對包括該貫通電極的配線構造進行了研究與探討,發現了會發生以下問題。 As the molten metal filled in the through hole, tin (Sn) having a lower melting point than aluminum (Al) or copper (Cu) which forms a wiring layer is used, and a through electrode is formed by Sn, and the inventors of the present application include the through The wiring structure of the electrode was studied and discussed, and the following problems were found.
亦即,於用鋁形成配線層之情形,在配線層與貫通電極之間發生了接觸不良的現象。於用銅形成配線層之情形,在貫通電極附近發生了配線層導通不良的現象。 That is, in the case where the wiring layer is formed of aluminum, a contact failure occurs between the wiring layer and the through electrode. In the case where the wiring layer is formed of copper, a phenomenon in which the wiring layer is poorly connected is generated in the vicinity of the through electrode.
一般認為發生這些問題之原因如下。亦即,沿厚度方向貫通基板而形成通孔之際,配線層會在通孔的底部露出來。然而,因為將熔融金屬填充至通孔內的製程不是緊接 著沿厚度方向貫通基板而形成通孔的製程(讓配線層露出的製程)在真空下進行,故熔融金屬的填充就是在配線層的表面被氧化之狀態下進行的。因此,難以在配線層與貫通電極之間形成良好的接觸。於用鋁形成配線層之情形,因為鋁係難以與錫形成合金的材料,所以配線層與貫通電極之間的接觸電阻會增大。另一方面,於用銅形成配線層之情形,雖然銅係易於與錫形成合金的材料,但形成配線層之銅的一部分會擴散到貫通電極的Sn中。因此,配線層的內部會在貫通電極附近產生空洞。其結果是,配線層的導通性下降。 The reasons for these problems are generally considered to be as follows. That is, when the through hole is formed by penetrating the substrate in the thickness direction, the wiring layer is exposed at the bottom of the through hole. However, since the process of filling the molten metal into the through hole is not performed by the process of forming the through hole through the substrate in the thickness direction (the process of exposing the wiring layer) is performed under vacuum, the filling of the molten metal is in the wiring layer. The surface is oxidized. Therefore, it is difficult to form a good contact between the wiring layer and the through electrode. In the case where a wiring layer is formed of aluminum, since aluminum is difficult to form an alloy with tin, the contact resistance between the wiring layer and the through electrode is increased. On the other hand, in the case where the wiring layer is formed of copper, the copper is likely to form an alloy with tin, but a part of the copper forming the wiring layer is diffused into the Sn of the through electrode. Therefore, a void is formed in the vicinity of the through electrode in the inside of the wiring layer. As a result, the conductivity of the wiring layer is lowered.
本申請發明人在以上認識之基礎上,在貫通電極之與露出在通孔底部的配線層接觸的表面上,形成與Sn形成合金的第一金屬層,並且在與貫通電極接觸的表面上,形成防止第一金屬層氧化的第二金屬層,發現由此能夠解決上述問題,從而做出了本發明。 On the basis of the above knowledge, the inventors of the present application form a first metal layer which is alloyed with Sn on the surface of the through electrode which is in contact with the wiring layer exposed at the bottom of the through hole, and on the surface in contact with the through electrode, The second metal layer which prevents oxidation of the first metal layer is formed, and it has been found that the above problems can be solved by the above, and the present invention has been made.
下面,參照圖式對本發明的實施方式做詳細的說明。需要說明的是,本發明並不限於以下實施方式。能夠在不脫離獲得本發明効果之範圍內進行適當的變更。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. It should be noted that the present invention is not limited to the following embodiments. Appropriate changes can be made without departing from the scope of the invention.
(第一實施方式) (First embodiment)
圖1中的(a)至圖1中的(c)、圖2中的(a)至圖2中的(d)係為剖視圖,示意地顯示本發明第一實施方式之配線構造的製造方法。 (a) to (c) of FIG. 1 and (a) of FIG. 2 to (d) of FIG. 2 are cross-sectional views, and schematically show a method of manufacturing the wiring structure according to the first embodiment of the present invention. .
首先,如圖1中的(a)所示,準備基板10(製程A),在該基板10的表面(第一主面)10a上夾著絕緣層11形成有配線 層13。基板10例如能夠使用矽(Si)等半導體基板。本實施方式中,配線層13能夠使用由Al、Al合金或者Cu形成的配線層。絕緣層11例如能夠使用氧化矽膜等。本實施方式中,在絕緣層11與配線層13之間形成有緊密附著層12,但還可以不形成緊密附著層12。緊密附著層12例如能夠使用由鈦(Ti)、氮化鈦(TiN)等材料形成的層。 First, as shown in Fig. 1 (a), the substrate 10 (process A) is prepared, and a wiring layer 13 is formed on the surface (first main surface) 10a of the substrate 10 with the insulating layer 11 interposed therebetween. As the substrate 10, for example, a semiconductor substrate such as bismuth (Si) can be used. In the present embodiment, the wiring layer 13 can use a wiring layer formed of Al, an Al alloy, or Cu. As the insulating layer 11, for example, a hafnium oxide film or the like can be used. In the present embodiment, the adhesion layer 12 is formed between the insulating layer 11 and the wiring layer 13, but the adhesion layer 12 may not be formed. As the adhesion layer 12, for example, a layer formed of a material such as titanium (Ti) or titanium nitride (TiN) can be used.
接下來,如圖1中的(b)所示,選擇性地蝕刻基板10的背面(第二主面)10b,而形成沿厚度方向貫通絕緣層11與緊密附著層12且具有讓配線層13露出的底部20a的通孔(貫通孔)20(製程B)。此時,為支撐基板10,在基板10的表面10a一側,夾著黏著層(未圖示)事先貼有支撐體30。例如,在基板10的背面10b形成光阻圖案40,然後以其為光罩,以非等向性之乾蝕刻等對基板10進行選擇性蝕刻。需要說明的是,本實施方式中,也形成沿厚度方向貫通緊密附著層12的通孔20,但還可以將緊密附著層12的一部分留下來,這樣來形成通孔20。該情形下,通孔20具有底部,配線層13位於該底部的下方。 Next, as shown in (b) of FIG. 1, the back surface (second main surface) 10b of the substrate 10 is selectively etched, and the insulating layer 11 and the adhesion layer 12 are formed to penetrate in the thickness direction and have the wiring layer 13 The through hole (through hole) 20 of the exposed bottom portion 20a (process B). At this time, in order to support the substrate 10, the support 30 is attached to the surface 10a side of the substrate 10 with an adhesive layer (not shown) interposed therebetween. For example, the photoresist pattern 40 is formed on the back surface 10b of the substrate 10, and then the photomask is used as a mask, and the substrate 10 is selectively etched by dry etching such as non-isotropic. In the present embodiment, the through hole 20 penetrating the adhesion layer 12 in the thickness direction is also formed. However, a part of the adhesion layer 12 may be left, and the through hole 20 may be formed. In this case, the through hole 20 has a bottom, and the wiring layer 13 is located below the bottom.
接下來,如圖1中的(c)所示,除去光阻圖案40後,再在通孔20的底面與側面、基板10的背面10b形成絕緣膜14。例如,利用CVD(化學氣相沈積)法形成氧化矽膜、氮化矽膜等,即可形成絕緣膜14。需要說明的是,於基板10為絕緣性基板之情形下,可以省略形成絕緣膜14之製程。 Next, as shown in (c) of FIG. 1, after the photoresist pattern 40 is removed, the insulating film 14 is formed on the bottom surface and the side surface of the via hole 20 and the back surface 10b of the substrate 10. For example, the insulating film 14 can be formed by forming a hafnium oxide film, a tantalum nitride film, or the like by a CVD (Chemical Vapor Deposition) method. In the case where the substrate 10 is an insulating substrate, the process of forming the insulating film 14 can be omitted.
接下來,如圖2中的(a)所示,選擇性地除去形成在通孔20的底部20a的絕緣膜14,而讓配線層13在通孔20的底 部20a露出來。例如,藉由非等向性之乾蝕刻等能夠選擇性地除去絕緣膜14。需要說明的是,於在圖1中的(b)所示的製程(B)中讓緊密附著層12的一部分殘留於通孔20底部之情形,可以在除去絕緣膜14的同時,除去殘留著的緊密附著層12。 Next, as shown in (a) of Fig. 2, the insulating film 14 formed on the bottom portion 20a of the via hole 20 is selectively removed, and the wiring layer 13 is exposed at the bottom portion 20a of the via hole 20. For example, the insulating film 14 can be selectively removed by dry etching such as anisotropic. It should be noted that, in the process (B) shown in (b) of FIG. 1, a part of the adhesion layer 12 is left at the bottom of the through hole 20, and the insulating film 14 can be removed while removing the remaining Tight adhesion layer 12.
接下來,如圖2中的(b)所示,通孔20的底面與側面、基板10的背面10b上,依次形成第一金屬層15與第二金屬層16(製程C)。這裡,第一金屬層15係由與填充至通孔20內的Sn類熔融金屬形成合金之材料形成。第一金屬層15例如能夠使用由鈦(Ti)、氮化鈦(TiN)、鉑(Pt)、鎳(Ni)、鈷(Co)等材料形成的金屬層。需要說明的是,較佳為,第一金屬層15的厚度在0.01μm至1μm的範圍內。 Next, as shown in FIG. 2(b), the first metal layer 15 and the second metal layer 16 are sequentially formed on the bottom surface and the side surface of the via hole 20 and the back surface 10b of the substrate 10 (process C). Here, the first metal layer 15 is formed of a material that forms an alloy with a Sn-based molten metal filled in the through hole 20. As the first metal layer 15, for example, a metal layer formed of a material such as titanium (Ti), titanium nitride (TiN), platinum (Pt), nickel (Ni), or cobalt (Co) can be used. It is to be noted that the thickness of the first metal layer 15 is preferably in the range of 0.01 μm to 1 μm.
第二金屬層16係由防止第一金屬層15氧化之材料形成。第二金屬層16例如能夠使用由銅(Cu)、銀(Ag)、金(Au)、鉑(Pt)、鎳(Ni)、鈷(Co)等材料形成的金屬層。需要說明的是,較佳為使用Cu、Ag、Au作易於擴散到貫通電極17中之材料用。較佳為,第二金屬層16的厚度在0.01μm至1μm的範圍內。 The second metal layer 16 is formed of a material that prevents oxidation of the first metal layer 15. As the second metal layer 16, for example, a metal layer formed of a material such as copper (Cu), silver (Ag), gold (Au), platinum (Pt), nickel (Ni), or cobalt (Co) can be used. It is to be noted that Cu, Ag, and Au are preferably used as the material which is easily diffused into the through electrode 17. Preferably, the thickness of the second metal layer 16 is in the range of 0.01 μm to 1 μm.
例如能夠利用濺鍍法形成第一金屬層15與第二金屬層16。為了不使第一金屬層15的表面氧化,較佳為,連續形成第一金屬層15與第二金屬層16。而且,較佳為,在形成第一金屬層15以前,事先利用逆向濺鍍等除去形成於在通孔20的底部20a露出之配線層13的表面上的氧化物。 For example, the first metal layer 15 and the second metal layer 16 can be formed by sputtering. In order not to oxidize the surface of the first metal layer 15, it is preferable to form the first metal layer 15 and the second metal layer 16 continuously. Further, it is preferable that the oxide formed on the surface of the wiring layer 13 exposed at the bottom portion 20a of the through hole 20 is removed by reverse sputtering or the like before the first metal layer 15 is formed.
需要說明的是,第一金屬層15與第二金屬層16至少形 成在通孔20的底部即可。可以不像圖2中的(b)所示的那樣,在通孔20的側面與基板10的表面形成第一金屬層15與第二金屬層16。 It should be noted that the first metal layer 15 and the second metal layer 16 may be formed at least at the bottom of the through hole 20. The first metal layer 15 and the second metal layer 16 may be formed on the side surface of the via hole 20 and the surface of the substrate 10, as shown in (b) of FIG.
於圖1中的(b)所示的製程(B)中,緊密附著層12的一部分殘留於通孔20的底部之情形下,如果緊密附著層12由第一金屬層15所用之材料(例如Ti、TiN等)形成,則第一金屬層15便會已形成在通孔20的底部。因此,於此情形,在製程(C)中不形成第一金屬層15也無妨。惟,利用逆向濺鍍等除去形成於緊密附著層12表面上的氧化物以後,需要形成第二金屬層16。 In the process (B) shown in (b) of FIG. 1, a part of the adhesion layer 12 remains in the bottom of the via hole 20, if the adhesion layer 12 is made of the material used for the first metal layer 15 (for example) When Ti, TiN, etc. are formed, the first metal layer 15 is formed at the bottom of the through hole 20. Therefore, in this case, it is not necessary to form the first metal layer 15 in the process (C). However, after the oxide formed on the surface of the adhesion layer 12 is removed by reverse sputtering or the like, it is necessary to form the second metal layer 16.
接下來,如圖2中的(c)所示,將Sn類熔融金屬17填充至通孔20內(製程D)。例如,讓熔融金屬17從通孔20的開口面流入通孔20內,邊對熔融金屬17加壓邊冷却該熔融金屬17,由此即能夠進行熔融金屬17的充填。是以,會在通孔20內形成熔融金屬17固化而成的貫通電極。需要說明的是,之後用與熔融金屬相同的符號17表示貫通電極。 Next, as shown in (c) of FIG. 2, a Sn-based molten metal 17 is filled into the via hole 20 (Process D). For example, the molten metal 17 is allowed to flow into the through hole 20 from the opening surface of the through hole 20, and the molten metal 17 is cooled while pressurizing the molten metal 17, whereby the molten metal 17 can be filled. Therefore, a through electrode in which the molten metal 17 is solidified is formed in the through hole 20. It should be noted that the through electrode is denoted by the same reference numeral 17 as the molten metal.
此時,與貫通電極17接觸的第二金屬層16中的金屬擴散到貫通電極17中,與貫通電極17中的錫形成合金。其結果是,如圖2中的(d)所示,在通孔20的底部20a露出的配線層13經第一金屬層15與貫通電極17接觸。 At this time, the metal in the second metal layer 16 that is in contact with the through electrode 17 is diffused into the through electrode 17 and alloyed with tin in the through electrode 17 . As a result, as shown in (d) of FIG. 2, the wiring layer 13 exposed at the bottom portion 20a of the via hole 20 is in contact with the through electrode 17 via the first metal layer 15.
這裡,Sn類熔融金屬17係為以Sn為主要成分的熔融金屬,Sn類熔融金屬17還可以是含有Bi、In、Cu、Ag、Ga、Ni等的合金。 Here, the Sn-based molten metal 17 is a molten metal containing Sn as a main component, and the Sn-based molten metal 17 may be an alloy containing Bi, In, Cu, Ag, Ga, Ni, or the like.
根據本實施方式之配線構造的製造方法,在通孔20 的底部20a露出的配線層13係經由與Sn形成合金之材料形成的第一金屬層15與貫通電極17接觸。因此,即使不在真空下進行將熔融金屬填充至通孔20內的製程,也能夠使表面尚未氧化的第一金屬層15與貫通電極17合金化。是以,即使用鋁形成配線層13,也能夠使配線層13與貫通電極17之間具有良好的接觸。於用銅形成配線層13之情形,第一金屬層15會防止形成配線層13的銅擴散到貫通電極17的Sn中。是以,能夠防止配線層13的內部在貫通電極17附近產生空洞。其結果是,能夠防止配線層13發生導通不良。 According to the method of manufacturing the wiring structure of the present embodiment, the wiring layer 13 exposed at the bottom portion 20a of the through hole 20 is in contact with the through electrode 17 via the first metal layer 15 formed of a material forming an alloy with Sn. Therefore, even if the process of filling the molten metal into the through hole 20 is not performed under vacuum, the first metal layer 15 whose surface has not been oxidized can be alloyed with the through electrode 17. Therefore, even if the wiring layer 13 is formed using aluminum, it is possible to provide good contact between the wiring layer 13 and the through electrode 17. In the case where the wiring layer 13 is formed of copper, the first metal layer 15 prevents the copper forming the wiring layer 13 from diffusing into the Sn of the through electrode 17. Therefore, it is possible to prevent voids from occurring in the vicinity of the through electrode 17 in the inside of the wiring layer 13. As a result, it is possible to prevent the wiring layer 13 from being poor in conduction.
需要說明的是,本實施方式中,如圖2中的(d)所示,與貫通電極17接觸的第二金屬層16中之金屬擴散到貫通電極17中,與貫通電極17中之錫形成合金,但可以讓第二金屬層16的一部分殘留下來。於此情形,第二金屬層16也不會妨礙第一金屬層15與貫通電極17的合金化。 In the present embodiment, as shown in (d) of FIG. 2, the metal in the second metal layer 16 in contact with the through electrode 17 is diffused into the through electrode 17 and formed with tin in the through electrode 17. Alloy, but a portion of the second metal layer 16 can remain. In this case, the second metal layer 16 does not interfere with the alloying of the first metal layer 15 and the through electrode 17.
(第二實施方式) (Second embodiment)
第一實施方式中,如圖1中的(b)所示,形成通孔20時,配線層13在通孔20的底部20a露出來。如圖2中的(b)所示,在露出的配線層13上形成有第一金屬層15與第二金屬層16。亦即,結構為:在將Sn類熔融金屬17填充至通孔20內以前,在配線層13上形成第一金屬層15與第二金屬層16。 In the first embodiment, as shown in FIG. 1(b), when the via hole 20 is formed, the wiring layer 13 is exposed at the bottom portion 20a of the via hole 20. As shown in (b) of FIG. 2, the first metal layer 15 and the second metal layer 16 are formed on the exposed wiring layer 13. That is, the structure is such that the first metal layer 15 and the second metal layer 16 are formed on the wiring layer 13 before the Sn-based molten metal 17 is filled into the via hole 20.
本發明第二實施方式所採用的結構為:形成通孔20以前,形成與配線層13接觸的第一金屬層18與第二金屬層19。 The second embodiment of the present invention adopts a structure in which the first metal layer 18 and the second metal layer 19 which are in contact with the wiring layer 13 are formed before the via holes 20 are formed.
以下,參照圖3中的(a)至圖3中的(c)、圖4中的(a)至圖4中的(c),說明本發明第二實施方式之配線構造的製造方法。需要說明的是,用同一符號表示與第一實施方式相同的部分,並省略詳細說明。 Hereinafter, a method of manufacturing the wiring structure according to the second embodiment of the present invention will be described with reference to (a) to (c) of FIG. 3, (a) of FIG. 4, and (c) of FIG. In the same manner, the same portions as those in the first embodiment are denoted by the same reference numerals, and the detailed description thereof will be omitted.
首先,如圖3中的(a)所示,準備基板10(製程A),在該基板10的表面(第一主面)10a上,夾著絕緣層11依次形成有緊密附著層12、第二金屬層19、第一金屬層18以及配線層13。基板10例如有矽(Si)等半導體基板等,但並不限於此。 First, as shown in FIG. 3(a), the substrate 10 (process A) is prepared, and on the surface (first main surface) 10a of the substrate 10, a close adhesion layer 12 is formed in this order with the insulating layer 11 interposed therebetween. The second metal layer 19, the first metal layer 18, and the wiring layer 13. The substrate 10 is, for example, a semiconductor substrate such as germanium (Si), but is not limited thereto.
本實施方式中,配線層13能夠使用由Al、Al合金或者Cu形成的配線層。第一金屬層18係由與Sn類熔融金屬形成合金之材料形成。第一金屬層18例如能夠使用由鈦(Ti)、氮化鈦(TiN)、鉑(Pt)、鎳(Ni)、鈷(Co)等材料形成的金屬層。第二金屬層19由防止第一金屬層18氧化之材料形成。第二金屬層19例如能夠使用由銅(Cu)、銀(Ag)、金(Au)等材料形成的金屬層。於此情形,藉由蝕刻形成通孔時,較佳為選擇比較大。 In the present embodiment, the wiring layer 13 can use a wiring layer formed of Al, an Al alloy, or Cu. The first metal layer 18 is formed of a material that forms an alloy with a Sn-based molten metal. As the first metal layer 18, for example, a metal layer formed of a material such as titanium (Ti), titanium nitride (TiN), platinum (Pt), nickel (Ni), or cobalt (Co) can be used. The second metal layer 19 is formed of a material that prevents oxidation of the first metal layer 18. As the second metal layer 19, for example, a metal layer formed of a material such as copper (Cu), silver (Ag), or gold (Au) can be used. In this case, when the via hole is formed by etching, it is preferable to select it relatively large.
第二金屬層19、第一金屬層18以及配線層13例如能夠利用濺鍍法形成。需要說明的是,較佳為連續形成緊密附著層12、第二金屬層19、第一金屬層18以及配線層13。 The second metal layer 19, the first metal layer 18, and the wiring layer 13 can be formed, for example, by a sputtering method. It should be noted that the adhesion layer 12, the second metal layer 19, the first metal layer 18, and the wiring layer 13 are preferably formed continuously.
較佳為,第一金屬層18的厚度在0.01μm至1μm的範圍內。較佳為,第二金屬層19的厚度在0.01μm至1μm的範圍內。絕緣層11例如能夠使用氧化矽膜等。緊密附著層12例如能夠使用由鈦(Ti)、氮化鈦(TiN)等材料形成的膜。需要說明的是,本實施方式中,在絕緣層11與第二金屬層 19之間形成有緊密附著層12,但也可以沒有緊密附著層12。 Preferably, the thickness of the first metal layer 18 is in the range of 0.01 μm to 1 μm. Preferably, the thickness of the second metal layer 19 is in the range of 0.01 μm to 1 μm. As the insulating layer 11, for example, a hafnium oxide film or the like can be used. As the adhesion layer 12, for example, a film formed of a material such as titanium (Ti) or titanium nitride (TiN) can be used. Incidentally, in the present embodiment, the adhesion layer 12 is formed between the insulating layer 11 and the second metal layer 19, but the adhesion layer 12 may not be provided.
接下來,如圖3中的(b)所示,選擇性地蝕刻基板10的背面(第二主面)10b,而形成沿厚度方向貫通絕緣層11與緊密附著層12且具有讓第二金屬層19露出的底部20a的通孔(貫通孔)20(製程B)。此時,為了支撐基板10,在基板10的表面10a一側夾著黏著層(未圖示)事先貼有支撐體30。例如,能夠在基板10的背面10b形成光阻圖案40,然後以其為光罩,以非等向性之乾蝕刻等對基板10進行選擇性蝕刻。需要說明的是,本實施方式中,也形成沿厚度方向貫通緊密附著層12的通孔20,但還可以讓緊密附著層12的一部分留下來,這樣來形成通孔20。於此情形,通孔20具有底部,第二金屬層19位於該底部的下方。 Next, as shown in (b) of FIG. 3, the back surface (second main surface) 10b of the substrate 10 is selectively etched to form the insulating layer 11 and the adhesion layer 12 in the thickness direction and has the second metal A through hole (through hole) 20 of the bottom portion 20a exposed by the layer 19 (process B). At this time, in order to support the substrate 10, the support 30 is attached to the surface 10a side of the substrate 10 with an adhesive layer (not shown) interposed therebetween. For example, the photoresist pattern 40 can be formed on the back surface 10b of the substrate 10, and then used as a photomask to selectively etch the substrate 10 by dry etching such as non-isotropic. In addition, in the present embodiment, the through hole 20 penetrating the adhesion layer 12 in the thickness direction is also formed, but a part of the adhesion layer 12 may be left, and the through hole 20 may be formed. In this case, the through hole 20 has a bottom, and the second metal layer 19 is located below the bottom.
接下來,如圖3中的(c)所示,除去光阻圖案40後,再在通孔20的底面與側面、基板10的背面10b形成絕緣膜14。例如,利用CVD(化學氣相沈積)法形成氧化矽膜、氮化矽膜等,即可形成絕緣膜14。 Next, as shown in (c) of FIG. 3, after the photoresist pattern 40 is removed, the insulating film 14 is formed on the bottom surface and the side surface of the via hole 20 and the back surface 10b of the substrate 10. For example, the insulating film 14 can be formed by forming a hafnium oxide film, a tantalum nitride film, or the like by a CVD (Chemical Vapor Deposition) method.
接下來,如圖4中的(a)所示,選擇性地除去形成在通孔20的底部的絕緣膜14,讓第二金屬層19在通孔20的底部20a露出來。需要說明的是,在圖3中的(b)所示的製程(B)中,如果讓緊密附著層12的一部分殘留在通孔20的底部,在除去絕緣膜14的同時,也要將殘留著的該緊密附著層12除去。 Next, as shown in (a) of FIG. 4, the insulating film 14 formed at the bottom of the via hole 20 is selectively removed, and the second metal layer 19 is exposed at the bottom portion 20a of the via hole 20. In addition, in the process (B) shown in (b) of FIG. 3, if a part of the adhesion layer 12 is left at the bottom of the through hole 20, the insulating film 14 is removed, and the residue is also left. The adhesion layer 12 is removed.
接下來,如圖4中的(b)所示,將Sn類熔融金屬17填充 至通孔20內(製程C)。例如,讓熔融金屬17從通孔20的開口面流入通孔20內,邊對熔融金屬17加壓邊冷却該熔融金屬17,由此即能夠進行熔融金屬17的充填。是以,即會在通孔20內形成熔融金屬17固化而成的貫通電極。需要說明的是,之後用與熔融金屬相同的符號17表示貫通電極。 Next, as shown in (b) of Fig. 4, a Sn-based molten metal 17 is filled into the via hole 20 (Process C). For example, the molten metal 17 is allowed to flow into the through hole 20 from the opening surface of the through hole 20, and the molten metal 17 is cooled while pressurizing the molten metal 17, whereby the molten metal 17 can be filled. Therefore, a through electrode in which the molten metal 17 is solidified is formed in the through hole 20. It should be noted that the through electrode is denoted by the same reference numeral 17 as the molten metal.
此時,與貫通電極17接觸的第二金屬層19中之金屬擴散到貫通電極17中,與貫通電極17中的錫形成合金。其結果是,如圖4中的(c)所示,位於通孔20的底部之下方的配線層13係經第一金屬層18與貫通電極17接觸。 At this time, the metal in the second metal layer 19 that is in contact with the through electrode 17 is diffused into the through electrode 17 and alloyed with tin in the through electrode 17 . As a result, as shown in (c) of FIG. 4, the wiring layer 13 located under the bottom of the via hole 20 is in contact with the through electrode 17 via the first metal layer 18.
這裡,Sn類熔融金屬17係以Sn為主要成分的熔融金屬,Sn類熔融金屬17還可以是含有Bi、In、Cu、Ag、Ga、Ni等的合金。 Here, the Sn-based molten metal 17 is a molten metal containing Sn as a main component, and the Sn-based molten metal 17 may be an alloy containing Bi, In, Cu, Ag, Ga, Ni, or the like.
根據本實施方式之配線構造的製造方法,位於通孔20的底部之下方的配線層13係經由與Sn形成合金之材料形成的第一金屬層18與貫通電極17接觸。因此,即使不在真空下進行將熔融金屬填充至通孔20內的製程,也能夠使表面尚未氧化的第一金屬層18與貫通電極17合金化。是以,即使用鋁形成配線層13,也能夠使配線層13與貫通電極17之間具有良好的接觸。於用銅形成配線層13之情形,第一金屬層18能夠防止配線層13的銅擴散到貫通電極17的Sn中。是以,能夠防止配線層13的內部在貫通電極17附近產生空洞。其結果是,能夠防止配線層13發生導通不良。而且,能夠在形成配線層13的製程中同時形成第一金屬層18與第二金屬層19,故能夠將配線構造的製造製程簡化。 According to the method of manufacturing the wiring structure of the present embodiment, the wiring layer 13 located below the bottom of the via hole 20 is in contact with the through electrode 17 via the first metal layer 18 formed of a material forming an alloy with Sn. Therefore, even if the process of filling the molten metal into the through hole 20 is not performed under vacuum, the first metal layer 18 whose surface has not been oxidized can be alloyed with the through electrode 17. Therefore, even if the wiring layer 13 is formed using aluminum, it is possible to provide good contact between the wiring layer 13 and the through electrode 17. In the case where the wiring layer 13 is formed of copper, the first metal layer 18 can prevent the copper of the wiring layer 13 from diffusing into the Sn of the through electrode 17. Therefore, it is possible to prevent voids from occurring in the vicinity of the through electrode 17 in the inside of the wiring layer 13. As a result, it is possible to prevent the wiring layer 13 from being poor in conduction. Moreover, since the first metal layer 18 and the second metal layer 19 can be simultaneously formed in the process of forming the wiring layer 13, the manufacturing process of the wiring structure can be simplified.
需要說明的是,本實施方式中,如圖4中的(c)所示,與貫通電極17接觸的第二金屬層19的形成金屬擴散到貫通電極17中,與貫通電極17中的錫形成合金,但可以讓第二金屬層19的一部分殘留下來。於此情形,第二金屬層19也不會妨礙第一金屬層18與貫通電極17的合金化。 In the present embodiment, as shown in FIG. 4( c ), the formation metal of the second metal layer 19 that is in contact with the through electrode 17 is diffused into the through electrode 17 and formed with tin in the through electrode 17 . Alloy, but a portion of the second metal layer 19 can remain. In this case, the second metal layer 19 does not interfere with the alloying of the first metal layer 18 and the through electrode 17.
(Sn類熔融金屬的填充方法) (filling method of Sn-based molten metal)
參照圖5中的(a)、圖5中的(b)與圖6中的(a)、圖6中的(b),說明本實施方式之將Sn類熔融金屬填充至通孔20內的方法。當然,本實施方式中,Sn類熔融金屬的填充方法並不限於此。 Referring to (a) of FIG. 5, (b) of FIG. 5, (a) of FIG. 6, and (b) of FIG. 6, the filling of the Sn-based molten metal into the through hole 20 of the present embodiment will be described. method. Of course, in the present embodiment, the filling method of the Sn-based molten metal is not limited thereto.
圖5中的(a)係顯示熔融金屬的填充裝置之概要的圖。 (a) of FIG. 5 is a view showing an outline of a filling device for molten metal.
如圖5中的(a)所示,熔融金屬的填充裝置包括:支撐基板10的支撐部50、被佈置成將基板10周緣圍起來的筒狀部60以及緊貼著筒狀部60的內側而設的加壓部70。與收納有熔融金屬82的容器80連通的配管81沿徑向貫通筒狀部60。支撐部50與加壓部70分別由驅動部51、71控制而能夠上下移動。需要說明的是,如圖2中的(b)或圖4中的(a)所示,基板10上形成有通孔20。 As shown in (a) of FIG. 5, the filling device of the molten metal includes a support portion 50 that supports the substrate 10, a cylindrical portion 60 that is arranged to surround the periphery of the substrate 10, and an inner side that is in close contact with the cylindrical portion 60. The pressurizing portion 70 is provided. The pipe 81 that communicates with the container 80 in which the molten metal 82 is housed penetrates the tubular portion 60 in the radial direction. The support portion 50 and the pressurizing portion 70 are controlled by the drive portions 51 and 71, respectively, and are movable up and down. It should be noted that, as shown in (b) of FIG. 2 or (a) of FIG. 4, the through hole 20 is formed in the substrate 10.
圖5中的(b)係顯示讓支撐基板10的支撐部50朝著筒狀部60上昇而讓基板10的上表面頂在筒狀部60的下表面上的狀態。是以,便會形成由筒狀部60與加壓部70劃分出的處理室100。需要說明的是,由密封部件90、91確保處理室100的氣密性。藉由加壓部70上下移動來調節處理室100的容積。 (b) of FIG. 5 shows a state in which the support portion 50 of the support substrate 10 is raised toward the tubular portion 60 and the upper surface of the substrate 10 is placed on the lower surface of the tubular portion 60. Therefore, the processing chamber 100 defined by the tubular portion 60 and the pressurizing portion 70 is formed. It should be noted that the airtightness of the processing chamber 100 is ensured by the sealing members 90 and 91. The volume of the processing chamber 100 is adjusted by moving the pressurizing portion 70 up and down.
圖6中的(a)為部分放大圖,顯示於圖5中的(a)所示狀態下,讓收納在容器80內的熔融金屬82經由配管81供向處理室100的狀態。此時,供至處理室100的熔融金屬82被填充至形成在基板10上的通孔20的內部。需要說明的是,這裡,省略了形成在基板10上的通孔20以外的部分。藉由用加壓部70對處理室100內的熔融金屬82加壓,便能夠效率良好地將熔融金屬82填充至通孔20的底部。藉由邊對熔融金屬82加壓邊將該熔融金屬82冷卻,則會如圖6中的(b)所示,在通孔20內形成熔融金屬82固化而成的貫通電極17。需要說明的是,圖6中的(b)係顯示已除去在基板10的表面上固化之熔融金屬82的狀態,但也可以留下熔融金屬82的一部分並使其成為與貫通電極17連接的配線層。 (a) of FIG. 6 is a partially enlarged view showing a state in which the molten metal 82 accommodated in the container 80 is supplied to the processing chamber 100 via the pipe 81 in the state shown in (a) of FIG. 5 . At this time, the molten metal 82 supplied to the process chamber 100 is filled to the inside of the through hole 20 formed on the substrate 10. It should be noted that the portions other than the through holes 20 formed in the substrate 10 are omitted here. By pressurizing the molten metal 82 in the processing chamber 100 by the pressurizing portion 70, the molten metal 82 can be efficiently filled in the bottom portion of the through hole 20. When the molten metal 82 is cooled while pressurizing the molten metal 82, the through electrode 17 in which the molten metal 82 is solidified is formed in the through hole 20 as shown in FIG. 6(b). In addition, (b) of FIG. 6 shows a state in which the molten metal 82 solidified on the surface of the substrate 10 has been removed, but a part of the molten metal 82 may be left and connected to the through electrode 17. Wiring layer.
以上,利用較佳實施方式對本發明做了說明,以上記述並非限定事項,當然可以做各種各樣的改變。例如,上述實施方式中,作為基板10示例出的是Si等半導體基板,但並不限於此。例如,還可以是玻璃、樹脂等絕緣性基板。於此情形,可以省略於圖1中的(c)、圖3中的(c)所示的通孔20的內表面等上形成絕緣膜14之製程。 The present invention has been described above by way of preferred embodiments, and the above description is not a limitation, and various changes can of course be made. For example, in the above-described embodiment, the semiconductor substrate such as Si is exemplified as the substrate 10, but the invention is not limited thereto. For example, it may be an insulating substrate such as glass or resin. In this case, the process of forming the insulating film 14 on the inner surface or the like of the via hole 20 shown in (c) of FIG. 1 and (c) of FIG. 3 can be omitted.
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| Application Number | Priority Date | Filing Date | Title |
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| JP2017015413A JP2018125376A (en) | 2017-01-31 | 2017-01-31 | Method for manufacturing wiring structure |
| JP2017-015413 | 2017-07-18 |
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| TW201831246A true TW201831246A (en) | 2018-09-01 |
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| JP (1) | JP2018125376A (en) |
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| WO (1) | WO2018142720A1 (en) |
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| TWI809464B (en) * | 2020-12-30 | 2023-07-21 | 穩懋半導體股份有限公司 | Semiconductor structure and method for forming the same |
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| US11158519B2 (en) * | 2018-12-06 | 2021-10-26 | Corning Incorporated | Method of forming capped metallized vias |
| CN116169096B (en) * | 2022-08-12 | 2024-08-13 | 本源量子计算科技(合肥)股份有限公司 | Method for preparing superconducting interconnect structure and method for preparing superconducting quantum circuit |
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| JP3627856B2 (en) * | 2000-11-22 | 2005-03-09 | 株式会社フジクラ | Metal filling apparatus and metal filling method for fine space |
| JP3967239B2 (en) * | 2001-09-20 | 2007-08-29 | 株式会社フジクラ | Method for producing member with filled metal part and member with filled metal part |
| JP2004095849A (en) * | 2002-08-30 | 2004-03-25 | Fujikura Ltd | Method of manufacturing semiconductor substrate with through electrode, method of manufacturing semiconductor device with through electrode |
| JP5407316B2 (en) * | 2008-12-12 | 2014-02-05 | パナソニック株式会社 | Manufacturing method of semiconductor device |
| JP5754209B2 (en) * | 2011-03-31 | 2015-07-29 | 大日本印刷株式会社 | Manufacturing method of semiconductor device |
| JP2012227210A (en) * | 2011-04-15 | 2012-11-15 | Fujikura Ltd | Electronic component, electronic component manufacturing method and substrate |
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| TWI809464B (en) * | 2020-12-30 | 2023-07-21 | 穩懋半導體股份有限公司 | Semiconductor structure and method for forming the same |
| US11949008B2 (en) | 2020-12-30 | 2024-04-02 | Win Semiconductors Corp. | Semiconductor structure and method for forming the same |
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| WO2018142720A1 (en) | 2018-08-09 |
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