TW201823902A - Voltage regulator - Google Patents

Abstract

A low-dropout voltage regulator 102 is arranged to convert an input voltage to an output voltage Vout and comprises a pass field-effect-transistor MP having a first terminal connected to the input voltage 114 and a second terminal arranged to produce the output voltage Vout. An error amplifier circuit portion 104 is arranged to produce an error signal proportional to a difference between a feedback voltage Vfb and a reference voltage Vref, the feedback voltage Vfb being derived from the output voltage. The error amplifier circuit portion 104 is arranged to apply the error signal to the gate terminal of the pass field-effect-transistor MP via an error amplifier output terminal 116. A diode-connected field-effect-transistor M4 is connected to the error amplifier output terminal 116.

Description

 Stabilizer  

The invention relates to a voltage regulator, in particular a low dropout voltage regulator.

Low-dropout (LDO) regulators are linear DC (DC) regulators that operate with very low input-output differential voltages. The advantages of this regulator include lower minimum operating voltage, higher power efficiency, and lower heat dissipation than other types of regulators.

A conventional LDO regulator consists of an error amplifier and a pass field-efect-transistor (pass-FET). The error amplifier compares the output voltage produced by the LDO regulator (or the voltage drawn from it) to a reference voltage and changes the conductivity of the pass-FET to drive the output voltage to the desired value.

Two important design parameters that must be considered when designing an LDO regulator are the accuracy and stability of the output voltage of the LDO regulator. As with any circuit, the error amplifier of the LDO regulator has an associated transfer function that describes the frequency response of the circuit. The transfer function typically has a pole at a particular frequency called the Corner frequency. Once the lowest frequency or "primary" pole frequency is reached, the gain of the circuit begins to decrease at a frequency of 20 dB every ten times (ie, the gain is reduced by 20 dB for every ten times increase in frequency). Any subsequent poles will then increase by 20 dB every ten times. Each pole will also introduce a 90 degree phase shift. Thus, for both poles, the output then forms an inversion with the input (ie, 180 degrees non-in phase), which can cause circuit instability. Therefore, in order to stabilize the circuit, the gain should be reduced to one unit (Unity) at the frequency of the second (or any subsequent) pole (ie, the first "non-master" pole).

The first pole is the capacitance from the (usually large) output capacitor and the output resistance of the transmission FET, while the second pole is the gate capacitance from the transmission FET and the output resistance of the error amplifier.

In some conventional LDO regulators, a source follower stage is placed at the output of the error amplifier. This source follower stage drives the gate of the transfer FET and pushes the second pole to a relatively high frequency to improve the stability of the LDO regulator. However, with a large transfer FET, the bias current required to drive the second pole to reach this high frequency is significantly increased, thus increasing the current consumption of the device as a whole.

According to a first aspect, the present invention provides a low dropout voltage regulator configured to convert an input voltage into an output voltage, the low dropout voltage regulator comprising: a transmission type field effect transistor having a connection a first end of the input voltage and a second end configured to generate the output voltage; an error amplifier circuit component configured to generate an error signal between the feedback voltage and a reference voltage The voltage difference is proportional to the output voltage, wherein the error amplifier circuit component is configured to apply the error signal to the gate terminal of the transmission type field effect transistor via an error amplifier output; and The body is connected to the field effect transistor, which is connected to the output of the error amplifier.

Accordingly, those skilled in the art will appreciate that in accordance with an embodiment of the present invention, a low dropout (LDO) voltage regulator is provided that is configured such that the output impedance of the error amplifier circuit component scales with the output current due to A pole-connected field effect transistor (FET) is connected to its output. Due to the output impedance of the error amplifier (and the gate capacitance of the transfer FET), the scaled output current of the error amplifier drives the frequency of the pole to be very high above the unity gain frequency. This improves the overall stability of the LDO regulator over a wide range of load currents compared to conventional LDO regulators.

Those skilled in the art should understand that the term "diode-connected transistor" as used in this specification means that the drain of a potent transistor is connected to the gate terminal, and the two-terminal transistor effectively forms both ends. One of the characteristics of a diode-connected transistor is that it always operates in a saturated region. Although it should be understood that there are many transistor technologies suitable for implementing a diode-connected field effect transistor, in at least some embodiments, the diode-connected field effect transistor includes a p-channel metal oxide semiconductor field effect transistor. (p-channel Metal-Oxide-Semiconductor Field-Effect-Transistor, pMOSFET), wherein the source terminal of the diode connected to the field effect transistor is connected to the input voltage.

In at least some preferred embodiments, the transmission type field effect transistor includes a p-channel metal oxide semiconductor field effect transistor, wherein a source terminal of the transmission type field effect transistor is coupled to the input voltage. In some such embodiments, the error amplifier is configured such that the feedback voltage is applied to a non-inverting input of the error amplifier and the reference voltage is applied to an inverting input of the error amplifier. In such embodiments, the error amplifier is configured to detect if the feedback voltage has dropped to the reference voltage, and if so, reduce its output voltage such that the conductivity of the pMOS transmission type FET transistor increases.

However, it should be understood that in an alternative embodiment, the transmission type field effect transistor includes an n-channel Metal-Oxide-Semiconductor Field-Effect-Transistor (nMOSFET), wherein the transmission The 汲 terminal of the field effect transistor is connected to the input voltage. In some such embodiments, the error amplifier is configured such that the reference voltage is applied to a non-inverting input of the error amplifier and the feedback voltage is applied to an inverting input of the error amplifier. In such embodiments, the error amplifier is configured to detect if the feedback voltage has dropped to the reference voltage, and if so, increase its output voltage such that the conductivity of the nMOS pass-type FET increases.

Although the output voltage can directly compare the reference voltage (ie, by being the feedback voltage of the output voltage), in some embodiments, the transmission type field effect transistor system is connected in series with a voltage divider circuit component, The voltage divider circuit component includes at least first and second resistors, wherein the feedback voltage includes a voltage at a node between the first and second resistors. Thus, it should be understood that in this embodiment, the voltage divider circuit component acts as a feedback for the error amplifier. The feedback voltage taken from the node will be proportional to the output voltage and will depend on the ratio between the resistance of the first resistor and the resistance of the second resistor. While the resistance of the resistors can be fixed, in some embodiments, the voltage divider circuit has an adjustable resistance ratio. Those skilled in the art will appreciate that the adjustable resistance ratio (i.e., the ratio between the resistance of the first resistor and the resistance of the second resistor) can be made by having one of the resistors having a variable Or both. This can be accomplished using an actual variable resistor (e.g., a potentiometer), but in practice this can be more easily accomplished by using a fixed resistor array that can be "switched", such as using a control signal.

In some embodiments, the error amplifier includes: a differential pair circuit component including first and second differential field effect transistors; and a bias current circuit component coupled to the first and second differences The source terminals of the field effect transistor, the differential field effect transistors are configured to provide a bias current thereto; and a current mirror load connecting the first and second differential field effect transistors The extremes of such awkwardness.

In some such embodiments, the current mirror load includes first and second mirror field effect transistors, wherein: a drain terminal of the first mirror field effect transistor is coupled to the first differential field effect transistor Extremely; the 汲 terminal of the second mirror field effect transistor is connected to the 汲 terminal of the second differential field effect transistor; and the gate terminal of the first mirror field effect transistor is connected to the 镜像 of the first mirror field effect transistor Extremely, with the gate end of the second mirror field effect transistor.

In some embodiments, the bias current circuit component includes a current source coupled between the source and ground ends of the first and second differential field effect transistors. This current source provides a constant quiescent bias current to the LDO regulator.

While it is sufficient to provide an LDO regulator with a constant bias current, Applicants have recognized that this is not necessarily the best way to bias the regulator. In some possible superimposed embodiments, the bias current circuit component includes an adaptive bias circuit component configured to increase the bias current in response to the error voltage.

In some such embodiments, the adaptive bias circuit component includes: a scaled field effect transistor having a gate terminal coupled to an output of the error amplifier output; an adaptive bias current mirror circuit component including a first and a second adaptive bias mirror field effect transistor, wherein: the first adaptive bias mirror field effect transistor has a drain terminal connected to the first and second adaptive bias mirror field effect transistor gates Extremely, with the 汲 extreme of the scaled field effect transistor; the 自 terminal of the second adaptive bias mirror field effect transistor is connected to the source terminals of the first and second differential field effect transistors; The source terminal of the second adaptive bias mirror field effect transistor is connected to the ground.

Applicants have recognized that it is novel and innovative to scale the output impedance of the error amplifier in response to the output current of the LDO regulator. Therefore, according to a second aspect, the present invention provides a low dropout voltage regulator configured to convert an input voltage into an output voltage, the low dropout voltage regulator comprising: an error amplifier circuit component configured to generate An error signal proportional to a voltage difference between a feedback voltage and a reference voltage, the feedback voltage being from the output voltage; and an impedance scaling circuit component configured to be responsive to the low voltage An output current of the difference regulator changes an output impedance of the error amplifier circuit component.

In one set of embodiments of this aspect of the invention, the impedance scaling circuit component includes a diode-connected field effect transistor coupled to an output of the error amplifier circuit component. However, there are other ways to do this.

102‧‧‧Low-dropout regulator

104‧‧‧Error amplifier circuit components

106‧‧‧Adaptive bias circuit components

108‧‧‧Output circuit components

110‧‧‧Variable output impedance circuit components

112‧‧‧current source

114‧‧‧Input voltage

116‧‧‧ Output

118‧‧‧current source

120‧‧‧Regulator output

Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which FIG. 1 is a circuit diagram of a low dropout voltage regulator in accordance with an embodiment of the invention; The voltage simulation at each node in the voltage regulator shown in Figure 1 is shown; and Figure 3 shows a comparison of the transient step response and load current step variation of the regulator shown in Figure 1.

1 shows a low dropout (LDO) voltage regulator 102 in accordance with an embodiment of the present invention. Although it should be understood that the LDO regulator 102 will typically be implemented as a single integrated circuit, it is divided into a number of logic circuit components for illustrative purposes only. The LDO regulator 102 includes an error amplifier circuit component 104, an adaptive bias circuit component 106, an output circuit component 108, and a variable output impedance circuit component 110. Each of these circuit components will be described in the following order.

The error amplifier circuit component 104 is constructed as a "long tail pair" and includes a differential pair of n-channel metal oxide semiconductor field effect transistors (nMOSFET) M0, M1 configured such that their individual source terminals are connected together and further connected to a current source 112. Current source 112 is also coupled to the ground. The error amplifier circuit component 104 further includes a current mirror load that is comprised of two p-channel metal oxide semiconductor field effect (pMOSFET) transistors M2, M3. The individual gate terminals of the two pMOSFET transistors M2, M3 are connected to the individual 汲 terminals of the nMOSFET transistor M1 and the pMOSFET transistor M2. The 汲 terminal of the pMOSFET transistor M3 is connected to the 汲 terminal of the nMOSFET transistor M0.

The source terminals of both pMOSFET transistors M2, M3 are connected to an input voltage 114. The gate terminals of the differential pair nMOSFET transistors M0, M1 are respectively connected to a reference voltage V _ref and a feedback voltage V _fb , as will be described in further detail below. The error amplifier circuit component 104 also includes an output 116 coupled to the adaptive bias circuit component 106 and the output circuit component 108, as will also be described in further detail below.

The adaptive bias circuit component 106 includes a scaled pMOSFET transistor M6 configured such that its gate terminal is coupled to the output 116 of the error amplifier circuit component 104. The adaptive bias circuit component 106 further includes a current mirror device that is constructed using a first adaptive bias mirror nMOSFET transistor M7 and a second adaptive bias mirror nMOSFET transistor M8. The first adaptive bias current mirror nMOSFET transistor M7 is configured as a diode connected to the transistor, that is, its gate terminal and the gate terminal are connected together. The gate and drain terminals of the nMOSFET transistor M7 are further connected to the gate terminal of the nMOSFET transistor M8, to the drain terminal of the pMOSFET transistor M6, and the source terminal of the nMOSFET transistor M7 is connected to the ground terminal. The source terminal of the nMOSFET transistor M8 is also connected to the ground terminal, but the drain terminal of the nMOSFET transistor M8 is connected to the source terminal of the differential pair transistors M0, M1 in the error amplifier circuit section 104.

When current source 112 provides a constant quiescent current to error amplifier circuit component 104, adaptive bias circuit component 106 provides additional current to error amplifier circuit component 104, depending on the voltage at output 116.

Output circuit component 108 includes a buffered nMOSFET transistor M5 and an output driven pMOSFET transistor MP. The buffer transistor M5 is configured such that its drain terminal is connected to the input voltage 114 and its source terminal is connected to the ground via a current source 118. The gate terminal of the buffer transistor M5 is coupled to the output 116 of the error amplifier circuit component 104. The source terminal of the buffer transistor M5 is further connected to the gate terminal of the output driving transistor MP. The source terminal of the output drive transistor MP is connected to the input voltage 114, and its drain terminal is connected to the ground terminal via a load capacitor CL. LDO regulator output voltage V _{out of} 102 from the drain terminal of an output terminal of the regulator 120 MOP. The feedback voltage V _fb applied to the gate terminal of the nMOSFET transistor M1 is also taken from the regulator output 120, but it should be understood that, in fact, a voltage divider (not shown) can be connected to the regulator. The output terminal 120 is between the gate terminal of the nMOSFET transistor M1.

The variable output impedance circuit component 110 includes a diode-connected pMOSFET transistor M4 configured such that the source terminal of the transistor is coupled to the input voltage 114 and its gate and drain terminals are coupled to the output 116 of the error amplifier circuit component 104. As will be described in further detail below, the diode-connected transistor M4 provides an error amplifier circuit component 104 having an output resistance that varies with load current I _load .

Figure 1 also shows some exemplary indications that can be observed showing where the poles of the system occur, i.e., which correspond to the output resistance of the components of the associated LDO regulator 102 that result in each pole. Individual locations of the capacitor. A first pole P _ota , which is caused by the output resistance of the error amplifier circuit component 104 and the gate capacitance of the buffer transistor M5 , appears at the output 116 of the error amplifier circuit component 104. A second pole P _buf is caused by the output resistance of the buffer transistor M5 and the gate capacitance of the output driving transistor MP, and appears at the source terminal of the buffer transistor M5 and the gate terminal of the output driving transistor MP. A third pole _Pout , which is caused by the output resistance of the output drive transistor MP and the load capacitor CL, appears at the regulator output 120. This third pole _Pout is the main pole of the LDO regulator 102.

By way of example only, if the LDO regulator 102 is to deliver a 150 mA current, the size of the output drive transistor MP needs to be relatively large, such as 7.2 mm (mm) / 400 nm (nano). This results in a relatively large parasitic gate capacitance at the output drive transistor MP. Buffer transistor M5 helps isolate the output of error amplifier circuit component 104 from the large gate capacitance of output drive transistor MP. This helps to provide a larger possible signal swing at the gate terminal of the output drive transistor MP.

In a conventional LDO regulator, the output resistance of a source follower buffer (such as buffer transistor M5) is sufficiently low (1/g _m ) such that the pole P of the gate terminal of the output drive transistor MP is _{The buf} rises to a high enough frequency to obtain the stability of the regulator. However, in this design, the output drive transistor MP is too large to move the pole _Pbuf to this high frequency, and the buffer transistor M5 requires a relatively high bias current; or, its size must also be substantially increased. However, by increasing the size of the buffer transistor M5, its gate capacitance will also increase, pushing the pole P _ota at the output 116 of the error amplifier circuit component 104 to a lower frequency, which may result in further instability.

Applicants have appreciated that the resistance of the bond wires connecting the output terminal 120 of the LDO regulator 102 to the equivalent series resistance of the load capacitor CL will result in a zero in the transfer function, which increases the unity gain frequency of the LDO regulator 102. The pole Pota is placed at the output of the error amplifier circuit component 104 to cancel this zero point, which is known in the art in nature, but since the gate capacitance of the output drive transistor MP is so large, it is difficult to pole _Pbuf Pushing to high frequencies, the Applicant has understood that it is advantageous to place the pole _Pbuf so that it is better to use this zero point to cancel.

Therefore, in order to reduce the output resistance of the error amplifier circuit section 104, the diode-connected transistor M4 is connected in parallel to the output terminal 116 of the error amplifier circuit section 104 instead of placing the pole _{Pbuf at} a high frequency. This pushes the frequency of the pole _{Point ota} at the output 116 of the error amplifier circuit component 104 very high above the unity gain frequency. If the load current I _load increases and the main pole _Pout at the regulator output 120 of the LDO regulator 102 _shifts to a higher frequency, the diode connected transistor M4 will cause the output resistance of the error amplifier circuit component 104. Decreasing, thus moving the pole P _ota up to a high frequency, thereby improving the overall stability of the LDO regulator 102.

It will be appreciated that as the load current I _load increases, the voltage at the gate terminal of the output drive transistor MP pulls down to the ground, which will also pull down the voltage at the gate terminal of the buffer transistor M5. When the voltage at the gate terminal of the buffer transistor M5 is equal to the voltage at the output 116 of the error amplifier circuit component 104, the voltage drop across the diode-connected transistor M4 will increase, which causes it to pull more Current. This leads to an increase the transconductance (g _m. Error amplifier circuit output resistance member 104 is equal to the diode 1 / g _m output resistance of transistor M4 is connected dominated. Thus, by increasing the diode connection of transistor M4 Transconductance, this pole P _out will be pushed to a higher frequency.

The adaptive bias circuit component 106 provides a transconductance increase of the differential pair nMOSFET transistors M0, M1, and thereby increases the gain of the error amplifier circuit component 104 to compensate for the reduced output impedance at higher load currents I _load . Some loss gains caused.

Figure 2 is a graph showing the voltage simulation at each node in the voltage regulator of Figure 1 as a function of load current I _load . Those skilled in the art will appreciate that the various values of voltage and current shown in the simulation results are merely exemplary. As can be seen from Fig. 2, when the load current I _load increases, the current I _M4 connected to the transistor M4 through the diode also increases (note that the negative ratio in the current-current pattern). This increase in diode connection transistor M4 transconductance (g _m), then reducing the output resistance of the error amplifier circuit member 104.

As can be seen, increasing the load current I _load also causes the voltage V ₁₁₆ at the node 116 to decrease. When the gate voltage V _{MPGATE of the} output driving transistor MP tracks the voltage V ₁₁₆ at the node 116, the voltage is simultaneously lowered. Output voltage V _out in response to the load current I _load increases linearly decreased. However, it can be seen that when the load current I _{load is} about 3 mA, the voltage V ₁₁₆ , the gate voltage V _{MPGATE ,} and the current I _M4 are nonlinear. When the load current I _load is 0 mA, the output drive transistor MP is almost turned off, and its operation is quite far from the weak inversion region. When the load current I _load increases, the output drive transistor MP moves to the strong inversion working region. When the load current I _{load is} about 3 mA, this transition from weak to strong inversion will result in a sudden change in voltage V ₁₁₆ , gate voltage V _MPGATE and current I _M4 . The abrupt change shown in Figure 2 is due to the limitations of the simulation software used to generate the schema, and in fact (or has a higher analog quasi-precision), this conversion is generally smoother. In the weak reversal working region, the voltage-current relationship is an exponential relationship, and in the strong reversal working region, it is a square relationship.

Figure 3 shows a comparison of the transient steps of the regulator shown in Figure 1 in response to changes in the load current I _load step. Those skilled in the art will appreciate that the various values of voltage and current shown in the simulation results are merely exemplary. More particularly, when the system, Figure 3 shows the transient response of a voltage corresponding to a typical compared to conventional regulator voltage V _out and V ₁₁₆ * *, the node with the output voltage V _out exemplary regulator shown in FIG. 102 116 A comparison of the transient response of voltage V ₁₁₆ at the location.

As can be seen from Figure 3, the load current I _{load is} increased from 0 mA to 150 mA in 10 ms (milliseconds) steps. Since the diode in the variable output impedance circuit component 110 of the regulator 102 is connected to the transistor M4, the voltage V ₁₁₆ at the node 116 is at a voltage V ₁₁₆ * in the conventional regulator, Experience a significantly reduced decline. The voltage V ₁₁₆ at node 116 also remains smooth throughout the transient response process, however "ringing" is typically seen in the voltage V ₁₁₆ * of the conventional regulator. This ring is then also found now this conventional regulator output voltage V _out *. This ringing indicates operational instability due to low phase margins associated with conventional regulators. At the same time, it can be seen that the output voltage V _out and the voltage V ₁₁₆ at the node 116 reach their final values (i.e., stabilize) earlier than the voltage V _out * and the voltage V ₁₁₆ * of the conventional regulator.

Thus, it can thus be seen that embodiments of the present invention provide an improved low dropout voltage regulator configured to vary the output impedance of the error amplifier in response to changes in load current. It is to be understood by those skilled in the art that the foregoing embodiments are merely illustrative and not limiting.

Claims (15)

 A low dropout voltage regulator configured to convert an input voltage into an output voltage, the low dropout voltage regulator comprising: a transmission type field effect transistor having a first end connected to the input voltage and configured Generating a second end of the output voltage; an error amplifier circuit component configured to generate an error signal proportional to a voltage difference between a feedback voltage and a reference voltage, the feedback voltage From the output voltage, wherein the error amplifier circuit component is configured to apply the error signal to a gate terminal of the transmission type field effect transistor via an error amplifier output; and a diode connected to the field effect transistor, It is connected to the error amplifier output.    The low-dropout voltage regulator according to claim 1, wherein the diode-connected field effect transistor comprises a p-channel metal oxide semiconductor field effect transistor, wherein the diode is connected to the source terminal of the field effect transistor. The input voltage.    The low dropout voltage regulator of claim 1 or 2, wherein the transmission type field effect transistor comprises a p-channel metal oxide semiconductor field effect transistor, wherein a source terminal of the transmission type field effect transistor is connected to the input voltage .    The low dropout voltage regulator of claim 3, wherein the error amplifier is configured such that the feedback voltage is applied to a non-inverting input of the error amplifier, and the reference voltage is applied to a reverse of the error amplifier Phase input.    The low dropout voltage regulator of claim 1 or 2, wherein the transmission type field effect transistor comprises an n-channel metal oxide semiconductor field effect transistor, wherein a drain terminal of the transmission type field effect transistor is connected to the input voltage .    The low dropout voltage regulator of claim 5, wherein the error amplifier is configured such that the reference voltage is applied to a non-inverting input of the error amplifier, and the feedback voltage is applied to a reverse of the error amplifier Phase input.    The low dropout voltage regulator of any one of the preceding claims, wherein the transmission type field effect transistor is connected in series with a voltage divider circuit component, the voltage divider circuit component comprising at least a first resistor and a second resistor The feedback voltage includes a voltage at a node between the first and second resistors.    A low dropout voltage regulator according to claim 7, wherein the voltage divider circuit has an adjustable resistance ratio.    The low dropout voltage regulator of any one of the preceding claims, wherein the error amplifier comprises: a differential pair circuit component comprising a first differential field effect transistor and a second differential field effect transistor; a bias current circuit component coupled to the source terminals of the first and second differential field effect transistors, the bias current circuit component configured to provide a bias current thereto; and a current mirror load, It connects the germanium extremes of the first and second differential field effect transistors.    The low-dropout voltage regulator of claim 9, wherein the current mirror load comprises a first mirror field effect transistor and a second mirror field effect transistor, wherein: the first mirror field effect transistor has a drain terminal connected thereto a 汲 extreme of the first differential field effect transistor; a 汲 terminal of the second mirror field effect transistor is coupled to a 汲 terminal of the second differential field effect transistor; and a gate terminal connection of the first mirror field effect transistor The 汲 extreme of the first mirror field effect transistor and the gate terminal of the second mirror field effect transistor.    The low dropout voltage regulator of claim 9 or 10, wherein the bias current circuit component comprises a current source coupled to the source terminals of the first and second differential field effect transistors Between the ground and the ground.    The low dropout voltage regulator of any one of claims 9 to 11, wherein the bias current circuit component includes an adaptive bias circuit component configured to increase the bias in response to the increase in the error voltage Voltage current.    The low-dropout voltage regulator of claim 12, wherein the adaptive bias circuit component comprises: a scaled field effect transistor having a gate terminal connected to an output of the error amplifier output; an adaptive bias current mirror circuit a component comprising a first adaptive bias mirror field effect transistor and a second adaptive bias mirror field effect transistor, wherein: the first adaptive bias mirror field effect transistor has a first terminal connected to the first And a gate terminal of the second adaptive bias mirror field effect transistor, and a drain terminal of the scaled field effect transistor; the first and second terminals of the second adaptive bias mirror field effect transistor are connected to the first and second The source terminals of the differential field effect transistor; and the source terminal of the second adaptive bias mirror field effect transistor are connected to the ground end.    A low dropout voltage regulator configured to convert an input voltage into an output voltage, the low dropout voltage regulator comprising: an error amplifier circuit component configured to generate an error signal, the error signal being associated with one The voltage is proportional to a voltage difference between a reference voltage from the output voltage; and an impedance scaling circuit component configured to change the error in response to an output current of the low dropout regulator An output impedance of the amplifier circuit components.    A low dropout regulator as claimed in claim 14 wherein the impedance scaling circuit component comprises a diode connected field effect transistor coupled to an output of the error amplifier circuit component.