CN115268550B - Quick-response low-dropout linear voltage stabilizing circuit - Google Patents

Abstract

The invention discloses a low dropout linear voltage stabilizing circuit with quick response, and belongs to the field of power supply circuits. The quick-response low-dropout linear voltage stabilizing circuit comprises an operational amplifier part, a super source follower part, a load current detection part and a voltage-controlled resistor part. Due to the introduction of the super source follower, the output driving capability of the circuit is greatly enhanced; the load current detection section may convert a change in the load current into a control amount to control the circuit. Converting the current change into a control voltage to control the voltage-controlled resistor; there are many ways to implement a voltage controlled resistor. The invention realizes the LDO design with low output ripple and high response speed, can quickly pull the output voltage back to the required value under the condition of wide-range load current change, and has small ripple.

Description

A Quick Response Low Dropout Linear Regulator Circuit

technical field

The invention relates to the technical field of power supply circuits, in particular to a fast-response low-dropout linear voltage regulator circuit.

Background technique

转换为一个较低的参考电压

，给后续电路使用。LDO的关键指标有压差

、噪声Noise、电源电压抑制比PSRR、静态电流

。好的LDO设计应当满足低纹波、响应速度快、电源电压抑制比高等特点。The function of LDO (Low Dropout regulator, low dropout linear regulator) is to convert the power supply voltage

converted to a lower reference voltage

, for subsequent circuits. The key indicator of the LDO is the pressure drop

, Noise Noise, Power Supply Voltage Rejection Ratio PSRR, Quiescent Current

. A good LDO design should meet the characteristics of low ripple, fast response speed, and high power supply voltage rejection ratio.

The current common LDO design structure is shown in Figure 1. The operational amplifier of the circuit is connected to a unity gain negative feedback mode, so the output voltage V _out is equal to the input reference voltage V _ref . When the output voltage V _out changes, the operational amplifier amplifies the difference between the output voltage V _out and the input reference voltage V _ref to change the gate voltage of the M1 tube, control the current of the M1 tube, and then control the current flowing to the load. The output voltage V _out is pulled back to the normal value.

The LDO is usually used to supply power to the on-chip low-voltage module, and requires a large on-chip filter capacitor _CL to stabilize the output voltage and meet certain ripple requirements. However, if a small-scale digital circuit is supplied with a load with a large transient current and a small average current, for example, the current will jump from 1mA to about 500mA within 1ns, and the bandwidth of the op amp is usually narrow and the loop cannot respond quickly. LDO The output impedance is only about 1/g _m1 . For such a large current change, the output ripple will jump to hundreds of millivolts, so a very large filter capacitor _CL (>10nF) is required to stabilize the output voltage, which is relatively large for the on-chip capacitor The area is very large.

处，两个极点大小分别为：

The loop of the circuit in Figure 1 has been marked, and there are two poles, which are respectively at the gate of the M1 tube, and the output voltage

At , the magnitudes of the two poles are:

指的是运放的输出电阻，该电阻数值较大，所以环路的主极点为P1，次极点为P2。低纹波性能要求负载电容C_L很大，P2会很小，为了满足稳定要求，主极点P1需要减小，所需的补偿电容

变大，又需要很大的电路面积，同时也会让带宽变窄，响应速度变慢。in

Refers to the output resistance of the op amp, which has a large value, so the main pole of the loop is P1, and the secondary pole is P2. Low ripple performance requires a large load capacitance _CL , and P2 will be very small. In order to meet the stability requirements, the main pole P1 needs to be reduced, and the required compensation capacitance

If it becomes larger, it requires a large circuit area, and at the same time, the bandwidth will be narrowed and the response speed will be slowed down.

Contents of the invention

The purpose of the present invention is to provide a fast-response low-dropout linear regulator circuit to solve the problems in the background technology.

In order to solve the above technical problems, the present invention provides a fast-response low-dropout linear voltage regulator circuit, including an operational amplifier A1, an NMOS transistor M1, an NMOS transistor M4, an NMOS transistor M5, a PMOS transistor M2, a PMOS transistor M3, and a PMOS transistor M6. , current source I1, current source I2, voltage-controlled resistor Rx, load resistor RL, capacitor Cx, filter capacitor CL, compensation capacitor Cc; the gate terminal of the NMOS tube M1 is connected to the output terminal of the operational amplifier A1, and the source terminal is connected to the output terminal of the current source I2 The input terminal and the drain terminal are connected to the output terminal of the current source I1; the gate terminal of the PMOS transistor M2 is connected to the output terminal of the current source I1, the source terminal is connected to the power supply voltage VDD, and the drain terminal is connected to the source terminal of the NMOS transistor M1; the gate terminal of the PMOS transistor M3 The output terminal of the current source I1 is connected, the source terminal is connected to the power supply voltage VDD, and the drain terminal is connected to the drain terminal of the NMOS transistor M4; the source terminal of the NMOS transistor M4 is grounded, and both the drain terminal and the gate terminal are connected to the gate terminal of the NMOS transistor M5; the NMOS transistor M5 The source terminal is grounded, and the drain terminal is connected to the drain terminal of the PMOS transistor M6; the source terminal of the PMOS transistor M6 is connected to the power supply voltage VDD, and both the drain terminal and the gate terminal are connected to the control terminal of the voltage-controlled resistor Rx; the first terminal of the voltage-controlled resistor Rx is connected to the power supply voltage VDD is connected, and the tail end is connected to the gate end of the PMOS transistor M2;

The positive input terminal of the operational amplifier A1 is connected to the reference voltage Vref, and the negative input terminal is connected to the source terminal of the NMOS tube M1; one end of the load resistor RL is connected to the source terminal of the NMOS tube M1, and the other end is grounded; one end of the filter capacitor CL is connected to the NMOS tube M1 source, and the other end is grounded.

Optionally, one end of the capacitor Cx is connected to the gate end of the PMOS transistor M2, and the other end is grounded.

Optionally, one end of the compensation capacitor Cc is connected to the gate end of the NMOS transistor M1, and the other end is grounded.

In the fast-response low-dropout linear regulator circuit provided by the present invention, it has the following beneficial effects:

(1) Realized an LDO design with low output ripple and fast response speed, which can quickly pull the output voltage back to the required value under a wide range of load current variation conditions, and the ripple is very small;

(2) The area required for the circuit is very small. Compared with the general LDO design, the area of the filter capacitor is greatly reduced;

(3) The structure is exquisite, and the LDO circuit is innovatively improved. The new detection circuit is added, and the stability of the circuit is improved by controlling the pole of the loop.

Description of drawings

Figure 1 is a schematic diagram of a traditional LDO circuit structure;

Fig. 2 is a kind of quick-response low-dropout linear regulator circuit structure schematic diagram provided by the present invention;

FIG. 3 is a schematic diagram of the structure of the loop Loop B;

FIG. 4 is a schematic structural diagram of a loop Loop B with a current detection module and a voltage-controlled resistor Rx.

detailed description

A fast-response low-dropout linear voltage regulator circuit proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

The present invention provides a fast-response low-dropout linear voltage regulator circuit, the structure of which is shown in Figure 2, including an operational amplifier, a Super Source Follower (SSF, Super Source Follower), a current detection module and a voltage-controlled resistor structure.

The first part is the operational amplifier part, which is connected into a unity gain negative feedback mode, so that the output voltage V _out and the input reference voltage V _ref are equal, the operational amplifier A1 provides the high gain required by the circuit, and the NMOS transistor M1 acts as a source follower , the gate-source voltage difference of the NMOS transistor M1 is a V _GS , and the compensation capacitor C _C improves loop stability.

比普通的源极跟随器（SF，Source Follower）要小一个数量级（R_out=1/(g_m1×g_m2×r_O1)），所以环路带宽通常会比普通LDO环路带宽要宽很多，因此对于较快的负载电流变化，响应速度会很快。The second part is the super source follower part. Compared with the ordinary LDO structure, the power transistor PMOS transistor M2 is added. When the current required by the load becomes larger, the current of the PMOS transistor M2 can be increased to provide high driving capability. In Figure 2, ro1 and ro2 refer to the equivalent resistance seen from the drains of the NMOS transistor M1 and the PMOS transistor M2 respectively, which are drawn in the figure as a representative, and no additional parallel resistance is required. At the same time, the introduction of SSF will make the changing load current flow through the PMOS transistor M2, while the current of the NMOS transistor M1 is almost constant, so the static operating point of the output position of the op amp will not change with the load current. Also, since the output impedance of the SSF

It is an order of magnitude smaller than the ordinary source follower (SF, Source Follower) (R _out =1/(g _m1 ×g _m2 ×r _O1 )), so the loop bandwidth is usually much wider than the ordinary LDO loop bandwidth , so for faster load current changes, the response speed will be fast.

The third part is the structure of the current detection module and the voltage-controlled resistor, which introduces the voltage-controlled resistor R _X . The current detection module converts the load current into a control voltage by detecting the current change of the PMOS transistor M2, and then controls the resistance value of the resistor to keep the pole relatively unchanged, which improves the stability of the loop under different load currents.

The main loops included in the entire circuit have been marked in the figure, namely Loop A and Loop B.

When the load resistance _RL is infinite, the magnitude of the current flowing through the PMOS transistor M2 is I _{M2_0} , and the current source I ₁ provides static current for the normal operation of the NMOS transistor M1 in the saturation region, and the current source I ₂ =I ₁ +I _{M2_0} . When the load resistance _RL gradually decreases, the load current is V _out / _RL and gradually increases, all of which flow through the PMOS transistor M2. If the load resistance _RL changes greatly, the current flowing through the PMOS transistor M2 will also change greatly, so the gate voltage V _X of the PMOS transistor M2 will change with the current of the PMOS transistor M2. The larger the current of the PMOS transistor M2, the V _X smaller. The current flowing through the NMOS transistor M1 remains unchanged, which is still I ₁ , so the gate voltage V _G of the NMOS transistor M1 remains unchanged, which can ensure that the operational amplifier maintains a high gain. V _X will decrease as the load current V _out / _RL increases, so as long as V _X -V _out >V _dsat1 is guaranteed, V _dsat1 is the overdrive voltage when the NMOS transistor M1 is turned on, the LDO can guarantee a higher output voltage accuracy and power supply rejection ratio. Since V _X =V _DD -V _GS2 (V _GS2 is the gate-source voltage of PMOS transistor M2), it can be deduced that V _DD >V _out +V _{th_M2} +V _dsat1 +V _dsat2 (V _{th_M2} is the turn-on threshold of PMOS transistor M2 voltage, V _dsat1 and V _dsat2 are the overdrive voltages when M1 and M2 are turned on respectively), so this structure LDO is more suitable for occasions where V _DD is high and V _out is low.

在NMOS管M1的栅极处，大小为：

For Loop A, the output voltage Vout is connected to the inverting input terminal of the operational amplifier, which is a unity gain negative feedback structure, V _out =V _ref . The loop has two poles, because the output resistance R _{out_AMP} of the operational amplifier is generally relatively large, so the main pole

At the gate of NMOS transistor M1, the size is:

在V_out处，大小为：

Secondary pole

At V _out , the magnitude is:

When the sub-pole is the smallest, _RL is infinite, at this time the sub-pole:

Since the output resistance of SSF is very small, R _out =1/(g _m1 ×g _m2 ×r _O1 ), where gm1 is the transconductance of NMOS transistor M1, gm2 is the transconductance of PMOS transistor M2, and ro1 is the transition from NMOS transistor M1 to The equivalent resistance seen by the drain terminal D is a common definition in the semiconductor field; P _{2_loopB} will be relatively large, so a small compensation capacitor C _C can meet the stability requirements of the primary and secondary poles.

在PMOS管M2的栅极处，即图中的X位置，大小为：

When there is no current detection module and voltage-controlled resistor module, FIG. 3 shows a schematic diagram of the loop Loop B. For Loop B, two poles are also included, the first pole

At the gate of the PMOS transistor M2, that is, the X position in the figure, the size is:

在V_out处，大小为：

second pole

At V _out , the magnitude is:

Among them, R _y is the resistance seen from V _out to the source of NMOS transistor M1, and its size is:

Among them, R _X is the output impedance of the current source I ₁ , the value is very large, so R _y is very large, and the parallel connection value of _RL and R _y is about _RL .

The introduction of SSF makes the pole at V _out larger, which is conducive to fast response. The output pole P _{2_loopB is} used as the main pole, and the secondary pole P _{1_loopB} is analyzed. In order to meet the stability requirements, it is necessary to meet:

，整理可以得到：

Among them, GBW (Gain–bandwidth product) refers to the gain-bandwidth product of the operational amplifier, specifically referring to the value obtained by the low-frequency gain of the operational amplifier × -3dB gain bandwidth, that is, the -3dB bandwidth (main pole) × gain A after the equal sign _DC ; A _DC is the DC gain of the loop Loop B, and its value is

, finishing can get:

Through the principle analysis, it can be obtained that the change of the load resistance will cause the change of the load current, and the load current will all flow through the PMOS transistor M2, which will cause the transconductance g _m2 of the PMOS transistor M2 to change, and the source-leakage current I _M2 flowing through the PMOS transistor M2 will become larger When , g _m2 will also become larger, which may make the ratio of _CL and C _X not meet the stability requirements.

In order to solve this problem, as shown in Figure 4, a voltage-controlled resistor R _X and a current detection module are added to the gate of the PMOS transistor M2, and a current detection module is formed by the PMOS transistors M3 and M6 and the NMOS transistors M4 and M5 on the left. The module generates a voltage V _control that is inversely proportional to the load current to control Rx, and Rx is proportional to V _control , so when the load current is large, R _X is small; when the load current is small, R _X is large. At the same time, since the resistance of R _X is relatively large, the current flowing through R _X will not have a great influence on the current of the NMOS transistor M1, and the current of the NMOS transistor M1 can still be considered to remain unchanged.

After the resistor R _X is introduced, the pole expression at the gate of the PMOS transistor M2 becomes:

The pole must also satisfy:

Bringing it into _ADC can get:

The arrangement is:

It can be seen that after adding the resistor R _X , it is equivalent to making a correction to g _m2 . When the load current is small, R _X is very large, which can be ignored in the expression; when the load current increases, the current flowing through the PMOS transistor M2 will also increase, so g _m2 increases, and R _X will decrease at the same time, so the right side of the above inequality remains almost unchanged. As long as 2·g _m1 g _m2 ·r _O1 /(1+r _O1 /R _X ) remains relatively constant within the range of load current variation, the stability of Loop B can be guaranteed, thus realizing the compensation method following the change of load current .

The invention proposes a new circuit structure and realizes the design of a low-dropout linear regulator circuit with low ripple and fast response. The circuit includes an operational amplifier part, a super source follower part, a load current detection part and a voltage-controlled resistor part. The introduction of the super source follower greatly enhances the output drive capability of the circuit; the load current detection part can convert the change of the load current into a control quantity to control the circuit. In this example, the current change is converted into a control voltage to control the voltage-controlled resistor; there are many ways to realize the voltage-controlled resistor, and in this example, it is referred to as the resistor Rx, and the claims are not limited to the voltage-controlled variable resistor Rx, Realization of similar functions is within the scope of patent protection.

Any limitation of the scope of the claims, and any changes and modifications made by those of ordinary skill in the field of the invention based on the above disclosures shall fall within the scope of protection of the claims.

Claims (3)

1. A fast-response low-dropout linear regulator circuit is characterized in that it comprises operational amplifier A1, NMOS tube M1, NMOS tube M4, NMOS tube M5, PMOS tube M2, PMOS tube M3, PMOS tube M6, current source I1 , current source I2, voltage-controlled resistor Rx, load resistor RL, capacitor Cx, filter capacitor CL, compensation capacitor Cc; The gate terminal of the NMOS transistor M1 is connected to the output terminal of the operational amplifier A1, the source terminal is connected to the input terminal of the current source I2, and the drain terminal is connected to the output terminal of the current source I1; the gate terminal of the PMOS transistor M2 is connected to the output terminal of the current source I1, and the source terminal Connected to the power supply voltage VDD, the drain terminal is connected to the source terminal of the NMOS tube M1; the gate terminal of the PMOS tube M3 is connected to the output terminal of the current source I1, the source terminal is connected to the power supply voltage VDD, and the drain terminal is connected to the drain terminal of the NMOS tube M4; the NMOS tube M4’s The source terminal is grounded, the drain terminal and the gate terminal are connected to the gate terminal of the NMOS transistor M5; the source terminal of the NMOS transistor M5 is grounded, and the drain terminal is connected to the drain terminal of the PMOS transistor M6; the source terminal of the PMOS transistor M6 is connected to the power supply voltage VDD, and the drain terminal and the gate terminal Both terminals are connected to the control terminal of the voltage-controlled resistor Rx; the first end of the voltage-controlled resistor Rx is connected to the power supply voltage VDD, and the tail end is connected to the gate terminal of the PMOS transistor M2; The positive input terminal of the operational amplifier A1 is connected to the reference voltage Vref, and the negative input terminal is connected to the source terminal of the NMOS tube M1; one end of the load resistor RL is connected to the source terminal of the NMOS tube M1, and the other end is grounded; one end of the filter capacitor CL is connected to the NMOS tube M1 source, and the other end is grounded. 2. The fast-response low-dropout linear voltage regulator circuit according to claim 1, wherein one end of the capacitor Cx is connected to the gate end of the PMOS transistor M2, and the other end is grounded. 3. The fast-response low-dropout linear voltage regulator circuit according to claim 1, wherein one end of the compensation capacitor Cc is connected to the gate end of the NMOS transistor M1, and the other end is grounded.

Images