TW201818478A - Masking method of semiconductor package - Google Patents

Abstract

Provided is a method for masking a semiconductor package, which can accurately mask a portion other than the predetermined region in order to accurately perform a specific process, such as an electromagnetic shielding process, on a predetermined region of the semiconductor package.

The holding jig J having the recessed portion 61 divided by the partition wall 63 is adsorbed and held on the porous stage 11, and each of the semiconductor packages P is arranged in each of the recessed portions 61. Regarding the semiconductor package P stably held in the recess 61, the masking tape T is attached to completely cover the bump 59. By performing electromagnetic shielding processing or the like on the semiconductor package P that has been covered in a predetermined area, various processes such as electromagnetic shielding processing or laser marking processing can be accurately performed on areas other than the portion covered by the masking tape.

Description

   Masking method of semiconductor package   

The present invention relates to a masking method for a semiconductor device, particularly a semiconductor package for masking a predetermined portion of a sealed semiconductor package.

In wireless communication equipment such as smart phones, electromagnetic waves generated from built-in semiconductor elements may interfere with the antenna and the like, which may affect reception performance. As a method to prevent the adverse effects caused by such electromagnetic waves, the mainstream in the past is to use a sheet metal shield to cover the circuit or equipment to suppress the generation of electromagnetic waves.

However, in recent years, sheet metal shields, which have a strong demand for thinning of communication equipment, etc., and a large installation area, have become a cause of hindering the miniaturization and thinning of equipment. Therefore, instead of the method of suppressing the use of sheet metal shields, a method of suppressing the generation of electromagnetic waves at a semiconductor element level, that is, a component level, is being explored.

In semiconductor devices, a semiconductor package is formed by sealing a small-sized (packaged) semiconductor wafer with an insulating resin or the like to protect the semiconductor wafer (for example, Patent Document 1). The semiconductor packaging system includes a plurality of small-sized semiconductor wafers on a support tape. After the semiconductor wafers are sealed with an insulating material, bumps or circuits are formed, and the wafers are manufactured by dicing again. As a method for suppressing electromagnetic waves at a semiconductor level, a method has been proposed in which each of the semiconductor packages is covered by a shielding material (electromagnetic shield) that blocks electromagnetic waves by a process such as a sputtering process, a plating process, and a spray process. (For example, Patent Document 2).

    [Prior technical literature]    

[Patent Document 1]

Japanese Patent Application Publication No. 2012-49502

[Patent Document 2]

Japanese Patent Application Publication No. 2012-39104

However, there are the following problems with the conventional method described above.

That is, when the semiconductor package is covered with an electromagnetic shield, it is difficult to accurately cover the target area of the semiconductor package with the electromagnetic shield, so there is a concern that it is difficult to improve the electromagnetic wave reduction performance of the semiconductor element level.

Here, the problems of the conventional method will be described using the drawings. As shown in FIG. 20 (a), the semiconductor package 101 has a structure in which a substrate layer 103 and a sealing resin layer 105 formed by covering a small-sized semiconductor wafer with an insulating resin are stacked. A circuit 107 is formed on the surface of the substrate layer 103 and is provided with a bump 109.

As shown in FIG. 20 (b), when each of the semiconductor packages 101 is covered with a shielding layer 111 made of an electromagnetic shielding material, the shielding layer 111 does not contact the bumps 109 and needs to be formed to sufficiently cover the sealing resin layer 105. And the side of the substrate layer 103. However, as shown in FIG. 20 (c), when the shield layer 111 is excessively formed, the shield layer 111 made of a conductor is formed in contact with the bump 109, and a short circuit of the bump 109 occurs.

Since the size of the semiconductor package is very small, it is accompanied by the difficulty in achieving electromagnetic shielding treatment with the required accuracy in each semiconductor package. The subject of achieving precise processing limited to a required range in a semiconductor package is not limited to electromagnetic shielding processing, and may occur in various processing steps such as laser marking processing.

The present invention has been made in view of this situation, and its main object is to provide a method for masking a semiconductor package, which is capable of accurately performing a specific process such as an electromagnetic shielding process on a predetermined area in the semiconductor package. Mask the part outside the given area accurately.

In order to achieve this object, the present invention adopts the following configuration.

That is, the method for masking a semiconductor package according to the present invention includes a holding step for holding the semiconductor package. The semiconductor package system includes a substrate layer having bumps formed on the surface thereof, and a semiconductor device for insulating small pieces. And a masking step in which a masking tape is attached to the semiconductor package held and at least the bump is covered.

(Action / Effect) According to this method, a semiconductor package is held in a holding step, and a masking tape is attached in a masking step so as to cover at least a bump. Since the bump portion of the semiconductor package is covered in the masking process, when the semiconductor package is subjected to a treatment such as electromagnetic shielding treatment, the treatment of the bump portion can reliably prevent the occurrence of product defects.

Further, in the above invention, it is preferable that the holding portion is provided with a holding portion installation step of providing a holding portion having a cell portion having the same shape as the semiconductor package and a partition wall that partitions the groove portions from each other. In the holding step, each of the semiconductor packages is held inside each of the groove portions with respect to the holding portion provided in the holding portion providing step.

(Action / Effect) According to this configuration, each of the semiconductor packages is attached with a masking tape in a state of being held inside the groove portion defined by the partition wall. The groove portion has the same shape as the semiconductor package, and a positional deviation of the semiconductor package is prevented by a partition wall. Therefore, each semiconductor package is more stably held inside the groove portion, so that the mask process can be performed more accurately.

In the above invention, preferably, in the holding step, the height of the upper surface of the partition wall is lower than the height of the top of the bump and higher than the height of the surface of the substrate layer. Way to keep each of the aforementioned semiconductor packages.

(Operation / Effect) According to this configuration, in the holding step, the height of the upper surface of the partition wall is lower than the height of the top of the bump, and is higher than the height of the surface of the substrate layer. Therefore, the bumps can be reliably covered with the masking tape in the masking step. On the other hand, since the masking tape can be prevented from being applied to a low position of the substrate layer, the portion to be treated by the masking does not become excessively enlarged. As a result, since the target range of the mask processing can be precisely defined, a specific process such as an electromagnetic shielding process can be performed on a wider portion of the semiconductor package.

Further, in the above invention, it is preferable that the groove portion is tapered from the upper portion to the lower portion, and the leading end is tapered.

(Operation / Effect) According to this configuration, since the groove portion has a tapered shape that is tapered from the top to the bottom, the gap between the groove and the semiconductor package is narrowed at the bottom. Therefore, the semiconductor package held in the state of the groove portion can more reliably prevent positional displacement.

On the other hand, since the gap between the semiconductor package and the semiconductor package is widened at the upper portion of the groove portion, the adhesive used to form the masking tape in the masking process easily enters the gap. As a result, a masking portion, such as a surface of a bump or a substrate layer, can be more reliably covered with a masking tape. Therefore, the stability of the semiconductor package and the reliability of the mask can be enjoyed.

In the above invention, it is preferable that the outer shape of the holding portion is circular.

(Action / Effect) According to this configuration, since the outer shape of the holding portion is circular, the holding portion can be processed in the same manner as a disc-shaped structure such as a semiconductor wafer regardless of the position where the groove portion is provided. Therefore, it is possible to more easily and surely carry out handling, placement, and the like of the holding portion.

Moreover, in the said invention, it is preferable that the said masking process WHEREIN: The said adhesive tape is rotated to a predetermined direction, and the said masking tape is attached to a semiconductor package.

(Action / Effect) According to this configuration, since the masking tape is attached to the semiconductor package by the rotation of the application roller, masking of the semiconductor package can be performed more appropriately and reliably.

In the above invention, it is preferable that, in the masking step, the pressing force of the application roller is controlled by the rotation position of the application roller.

(Action / Effect) According to this configuration, since the pressing force of the applicator roller is controlled by the rotational position of the applicator roller, it is possible to reliably avoid the occurrence of the mask deviation due to the arrangement position of each of the semiconductor packages.

In the above invention, preferably, in the masking step, the chamber is decompressed, and the masking tape is attached to the semiconductor package by a pressure difference.

(Action / Effect) According to this configuration, since the chamber is decompressed, and the masking tape is attached to the semiconductor package by a pressure difference, the semiconductor package can be more appropriately and reliably masked. In addition, variations in the mask due to the arrangement position of the semiconductor package can be further reduced.

1‧‧‧ Masking tape attachment device

3‧‧‧ Jig Supply / Recycling Department

5‧‧‧ robotic arm

9‧‧‧ Alignment Stage

11‧‧‧ Porous Table

12‧‧‧ adsorption hole

14‧‧‧ Attraction device

17‧‧‧ Attachment Unit

19‧‧‧ with cutting device

21‧‧‧ stripping unit

25‧‧‧Blade

35‧‧‧ sticking roller

51‧‧‧1st substrate layer

53‧‧‧ ground plane

57‧‧‧Sealing layer

59‧‧‧ bump

61‧‧‧concave

63‧‧‧ partition wall

65‧‧‧ adsorption hole

T‧‧‧Masking tape

J‧‧‧ holding fixture

P‧‧‧Semiconductor Package

N‧‧‧ incision

FIG. 1 is a perspective view showing a basic configuration of a masking tape attaching device according to an embodiment.

FIG. 2 is a side view showing a configuration of an attachment unit according to the embodiment.

FIG. 3 is a side view illustrating the structure of the semiconductor package of the embodiment.

FIG. 4 is a diagram illustrating the configuration of a holding jig of the embodiment. (a) is a plan view of the holding jig, and (b) is an A-A sectional view of the holding jig J shown in (a).

FIG. 5 is a diagram illustrating the configuration of a holding jig and a semiconductor package according to the embodiment. (a) is a cross-sectional view showing a state of a semiconductor package arranged on a holding jig, and (b) is a cross-sectional view showing a correlation between a recessed portion of the holding jig and a size of the semiconductor package.

FIG. 6 is a flowchart illustrating the operation of the masking tape attaching device according to the embodiment.

FIG. 7 is a diagram illustrating a state where the holding jig is placed in step S1.

FIG. 8 is a diagram illustrating a state where the semiconductor package is disposed in the recessed portion in step S2.

FIG. 9 is a diagram showing the configuration in step S3. (a) is a figure which shows the state which attached the masking tape, (b) is an enlarged figure of the area shown by A in (a).

FIG. 10 is a diagram showing the configuration in step S4.

FIG. 11 is a diagram showing the configuration in step S6. (a) is a figure which shows the state in which the masking tape was sucked and held by the tape conveying device, and (b) is a figure which shows the state in which the semiconductor package and the masking tape package were conveyed by the tape conveying device after suction holding.

FIG. 12 is a diagram showing a configuration of a comparative example. (a) is a plan view showing a position where a semiconductor package is arranged in a comparative example not partitioned by a partition wall, and (b) is a diagram showing a relationship between the pressing force of an applicator roller and the position where a semiconductor package is arranged in a comparative example (C) is a diagram showing a state in which the required range is masked beyond the required range by excessive pressing force, and (d) is a diagram showing a state in which the required range is not masked due to insufficient pressing force .

FIG. 13 is a diagram showing a configuration of a modification (1). (a) is a diagram showing a state before the chamber is decompressed, and (b) is a diagram showing a state where the chamber is decompressed and a tape is attached to the semiconductor package.

FIG. 14 is a diagram showing a configuration of a modification (2). (a) is a figure which shows the structure of a device in step S3, (b) is a figure which shows the state which conveyed a semiconductor package and a masking tape by holding a ring frame in step S6.

FIG. 15 is a diagram showing a configuration of a modification. (a) is a figure which shows the structure of modification (3), (b) is a figure which shows a structure of modification (4).

FIG. 16 is a diagram showing a configuration of a perforated stage according to a modification (6).

FIG. 17 is a diagram showing a configuration of a modification (7). (a) is a figure which shows the structure which isolate | separated a semiconductor package and a recessed part by deforming a masking tape, (b) is a figure which shows the structure which isolate | separated a semiconductor package and a recessed part by deforming a holding jig.

FIG. 18 is a cross-sectional view showing the configuration of a recessed portion in a modification (8).

FIG. 19 is a diagram showing a configuration of a holding jig according to a modification (9).

FIG. 20 is a diagram illustrating a conventional problem with respect to processing of a semiconductor package. (a) is a cross-sectional view showing the structure of a semiconductor package, (b) is a view showing an example of a state in which a required range is correctly processed, and (c) is an example of a state in which a process is performed beyond a required range Illustration.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a perspective view showing the overall configuration of a masking tape attaching device 1 according to the embodiment.

<Explanation of the overall structure>

The masking tape attaching device 1 of this embodiment includes a jig supply / recovery unit 3 for loading a cassette C1 containing a disc-shaped holding jig J, and a jig transfer mechanism 7 having a robot arm 5; Alignment table 9; porous table 11 for holding and holding fixture J and semiconductor package P for adsorption and holding; and a masking tape for storing the semiconductor package P attached thereto ) The package recovery unit 12 of the cassette C2 of T.

In addition, as a configuration not shown, the masking tape attaching device 1 includes a package storage section for storing the semiconductor package P and a package transfer section for transferring the semiconductor package P to the porous stage 11. As an example of the package transfer unit, a pick and place robot, a die bonder, or the like can be mentioned. In addition, as an example, the masking tape T has a structure in which an adhesive layer and a substrate layer are laminated. The adhesive layer contains an adhesive and covers the target area.

The tape supply unit 13 is provided for supplying a masking tape T for a mask to the semiconductor package P mounted on the porous stage 11, and the masking tape T with a release tape supplied from the tape supply unit 13 is used to peel the release tape s. The recovered separation tape recovery unit 15 attaches a masking tape T attaching unit 17 to the semiconductor package P placed on the perforated stage 11 and sucked and held, and cuts off the masking tape T attached to the semiconductor package P A tape cutting device 19 having a predetermined shape, a peeling unit 21 for peeling an unnecessary masking tape attached to the semiconductor package P and being subjected to a cutting process, and a roll of a masking tape T for peeling off the peeling unit 21 Take the recovered tape recovery section 23 and the like.

The cassette C1 constituting the jig supply / recovery unit 3 can insert and hold the disc-shaped holding jig J in multiple levels in a horizontal posture. The robot arm 5 provided in the jig conveying mechanism 7 is configured to be able to move forward and backward horizontally, and can be driven to rotate and lift as a whole. A horseshoe-shaped vacuum suction jig holder 5 a is provided at the tip of the robot arm 5.

The jig holding portion 5a is inserted into the gap between the holding jigs J stored in the cassette C in a plurality of layers. It is drawn out and carried in the order of the alignment stage 9, the multi-well stage 11, and the jig supply / recovery part 3. The alignment table 9 is for positioning the holding jig J, which is carried in by the jig transfer mechanism 7, based on a notch N or the like formed on the outer periphery thereof.

As described below, the perforated stage 11 has a plurality of suction holes, and the holding jig J for holding is transferred from the jig conveying mechanism 7 and placed in a predetermined alignment posture. The porous stage 11 is configured to vacuum-suck each semiconductor package P provided in the recessed portion of the holding jig J. In addition, instead of the porous stage 11, a table composed of a metal, a resin, or the like and having a plurality of adsorption holes having a larger diameter (for example, a diameter of about 1 mm) may be used.

As shown in FIG. 2, the tape supply unit 13 is configured such that a masking tape T with a release tape s sent from a supply spool 29 is wound and guided on a guide roller 31 having 1 or 2 or more, and the The masking tape T guides the attachment unit 17. The supply bobbin 29 is configured to impart appropriate rotational resistance without excessively pulling out the belt.

The release tape recovery unit 15 is formed so that a take-up spool 33 for winding the release tape s peeled from the masking tape T is rotated and driven in the winding direction. The attaching unit 17 is provided with an attaching roller 35 horizontally forward, and is reciprocally driven horizontally to the left and right by a slide guide mechanism 37 shown in FIG. 2 and a screw feed type drive mechanism (not shown).

In the peeling unit 21, the peeling roller 39 is arranged horizontally forward. The peeling roller 39 is configured to be reciprocally driven horizontally to the left and right by a slide guide mechanism 37 and a screw feed drive mechanism (not shown).

The tape take-up section 23 is formed to take up a useless masking tape T, that is, a take-up spool 41 for unnecessary tape T 'is rotationally driven in the winding direction. The unnecessary tape T 'may be, for example, a residual mask tape cut out along the outer shape of the wafer W.

As shown in Fig. 1, the tape cutting device 19 includes a movable table 43, a rotating shaft 44, and a pair of support arms 45. The movable table 43 is configured to be movable in the vertical direction (z direction). The rotating shaft 44 is provided at a free end portion of the movable table 43 and is capable of rotating about an axis in the up-down direction (z direction). The support arm 45 is provided at a lower end portion of a support member extending downward from the rotation shaft 44 and penetrates through the support so as to be slidably adjustable in the horizontal direction.

A cutter unit 47 is provided on the free end side of the support arm 45, and the cutter unit 47 is provided with a cutting edge 25 having a downwardly pointed tip. That is, by rotating the rotation shaft 44 with the longitudinal axis P as the rotation center, the support arm 45 is also rotated around the axis in the z direction. The masking tape T cut by moving the blade 25 along the outer periphery of the holding jig J by the rotational movement of the support arm 45.

In addition, the distance between the blade 25 and the longitudinal axis P serving as the rotation center is adjusted by sliding adjustment of the support arm 45. With this configuration, the rotation radius of the adjustment blade 25 can be changed in accordance with the diameter of the holding jig J.

Here, the configuration of the semiconductor package P and the holding jig J will be described. The semiconductor package P of the embodiment has a generally rectangular parallelepiped structure. As shown in FIG. 3, the semiconductor package P includes a first substrate layer 51, a ground layer 53 including a ground for earth, a second substrate layer 55, and a sealing layer 57. The structure of sequential stacking. The first substrate layer 51 has bumps 59 on its surface. A circuit (not shown) is formed on the surface of the first substrate layer 51. The sealing layer 57 has a structure that seals a semiconductor wafer (not shown) that has been formed into small pieces with an insulating material. The semiconductor wafer is electrically connected to the second substrate layer 55 via bumps or the like (not shown).

The holding jig J has a disc-like outer shape as shown in FIG. 4 (a), and a notch N for positioning is formed. The shape of the holding jig J is not limited to a circular shape, and is preferably the same shape as that of a wafer defined by the SEMI standard or the Japan Semiconductor Manufacturing Apparatus Association. As a preferred example of the shape of the holding jig J, Examples are roughly rectangular.

A plurality of recessed portions 61 are formed on the surface of the holding jig J. As an example, each of the recesses 61 is arranged in a two-dimensional matrix, and each of the recesses 61 is partitioned by a partition wall 63. The shape of the recessed portion 61 is substantially the same as the outer shape of the semiconductor package P. That is, each semiconductor package P is arranged in each of the recessed portions 61, so that the semiconductor package P can be stably held inside the recessed portion 61 defined by the partition wall 63.

The material constituting the holding jig J is preferably a material having flexibility and bendability, such as a resin, and particularly preferably made of elastic rubber or the like. As shown in FIG. 4 (b), a suction hole 65 is provided in the bottom 61 a of each recessed portion 61. The holding jig J corresponds to a holding portion in the present invention. The recessed portion 61 corresponds to a cell portion of the present invention.

FIG. 5 (a) shows a state where each semiconductor package P is arranged in the recess 61 of the holding jig J held by the multi-well stage 11. The multi-well stage 11 has a plurality of adsorption holes 12, and each adsorption hole 12 is connected to a suction device 14. When the positioning holding jig J is placed on the porous table 11, each suction hole 65 provided in the holding jig J communicates with the suction hole 12 of the porous table 11.

In the semiconductor package P, the height from the bottom surface of the sealing layer 57 to the surface of the first base material layer 51 is H1, and the height from the bottom surface of the sealing layer 57 to the top of the bump 59 is H2. In the holding jig J of the embodiment, the height R from the bottom surface of the recess 61 to the upper surface 63a of the partition wall 63 is preferably higher than the height H1 of the semiconductor package P as shown in FIG. 5 (b). Lower than H2.

The upper surface 63a of the partition wall 63 is preferably subjected to non-adhesive treatment. As an example of the non-adhesive treatment, a structure in which the upper surface 63a made of aluminum is coated with Teflon (registered trademark), or the like can be mentioned. In addition, the height R from the bottom surface of the recessed portion 61 to the upper surface 63 a of the partition wall 63 may be appropriately changed by using the range of the cover (mask) of the masking tape T as required. In the embodiment, since the range of the required mask is the entire bump 59 and the entire surface of the first substrate layer 51, the height R is adjusted to the extent shown in FIG. 5 (b).

<Description of Device Operation>

Next, a series of operations for attaching the masking tape T to each of the semiconductor packages P using the masking tape attaching device 1 of the embodiment will be described. FIG. 6 is a flowchart illustrating a process of attaching a protective masking tape T to a semiconductor package P. FIG.

Step S1 (placement of holding jig)

When an attaching instruction is issued, first, the robot arm 5 in the jig transfer mechanism 7 moves toward the cassette C1 placed on the cassette table. The robot arm 5 inserts the jig holding part 5a into the gap between the holding jigs stored in the cassette C, and the disc holding jig J is sucked and held from the back surface (lower surface) by the jig holding part 5a and held. Take it out, and transfer the removed holding jig J to the alignment table 9.

The holding jig J system placed on the alignment table 9 is aligned using a cutout N formed on the outer periphery of the holding jig J. The holding jig J for which alignment has been completed is carried out again by the robot arm 5 and placed on the multi-well stage 11 as shown in FIG. 7. The holding jig J placed on the perforated table 11 is rotated and aligned so that the center of the holding jig J is positioned above the center of the perforated table 11. At this time, each of the suction holes 65 provided on the bottom surface of the recessed portion 61 is aligned so as to communicate with and be connected to the suction holes 12.

The holding jig J which is positioned on the perforated table 11 is sucked and held on the perforated table 11 by the suction device 14. That is, the suction device 14 sucks the holding jig J through the suction hole 12. The step of step S1 corresponds to the holding portion installation step in the present invention.

In addition, as shown in FIG. 2, the attaching unit 17 and the peeling unit 21 are located at the initial positions on the left. In addition, the blade 25 with the cutting device 19 is waiting at the initial positions above.

Step S2 (supply of a semiconductor package)

After the holding jig J is sucked and held on the porous stage 11, the semiconductor package P is supplied. The package transfer unit supplies and transfers the semiconductor package P stored in the package storage unit to the multi-well stage 11. Then, as shown in FIG. 8, one semiconductor package P is placed in each of the recessed portions 61 of the holding jig J held by the porous stage 11 by suction.

Since each of the adsorption holes 65 is in communication with the adsorption hole 12, each of the semiconductor packages P disposed inside the recess 61 is adsorbed and held on the porous stage by the suction device 14 through the adsorption holes 65 and the adsorption holes 12. 11. In addition, each of the recessed portions 61 is divided by a partition wall 63, and the internal shape of the recessed portion 61 is substantially the same as the outer shape of the semiconductor package P. Therefore, by disposing in the recessed portion 61 of the holding jig J, it is possible to prevent the semiconductor package P from being displaced on the porous stage 11. Therefore, each of the semiconductor packages P is stably held in the recess 61 of the holding jig J. The semiconductor package P is arranged in each of the recesses 61, and the semiconductor package P is stably held in the porous stage 11 via the holding jig J, thereby completing the step S2. The step of step S2 corresponds to the holding step of the present invention.

Step S3 (with attaching process)

Next, as shown by an imaginary line (two-dot chain line) in FIG. 2, the attaching roller 35 of the attaching unit 17 is lowered, and by this the attaching roller 35 presses the masking tape T on the wafer while pressing it down. W turns forward (right in Figure 2). As a result, as shown in FIG. 9 (a), the masking tape T is attached to the entire surface of the semiconductor package P.

As shown in FIG. 5 (b), the height R of the partition wall 63 is adjusted to be lower than the height H2 and higher than the height H1 in the semiconductor package P. Therefore, in a state where the semiconductor package P is stably held inside the recessed portion 61, the upper surface 63 a of the partition wall 63 is positioned on the top of the bump 59 and the upper surface of the first substrate portion 51 in the height direction (z direction). between.

Therefore, as shown in FIG. 9 (b), the adhesive layer of the attached masking tape T covers at least the entire surface of the semiconductor package P by the pressing force of the attaching roller 35 (the entire bump 59 and the first (The entire upper surface of the substrate portion 51). On the other hand, the ground layer 53 provided with the ground is not covered by the adhesive layer of the masking tape T. Therefore, the adhesive layer of the masking tape T can completely cover (mask) portions other than the target area of the electromagnetic shielding treatment, that is, the upper surfaces of the bumps 59 and the first substrate portion 51. The tape attaching process of step S3 is completed by shielding the entire surface of each semiconductor package P with a masking tape T. The process of step S3 is equivalent to the mask process in this invention.

Step S4 (with cutting process)

After the tape attaching process is completed, the tape cutting process of step S4 is started. That is, when the applicator roller 35 is rotated and the applicator unit 17 reaches the end position, as shown in FIG. 10, the blade 25 waiting above is lowered and penetrates the masking tape T. Then, the support arm 45 is rotated by rotating the rotation shaft 44 about an axis in the z direction. Accompanying this, the blade edge 25 rotates while slidingly contacting the outer periphery of the holding jig J, so that the masking tape T is cut along the outer periphery of the holding jig J.

Step S5 (recycling useless tape)

When the tape cutting operation is completed along the outer periphery of the holding jig J, the blade 25 is raised to the original standby position. Next, as the peeling unit 21 moves forward, it cuts and cuts the wafer W, and the remaining waste tape T 'is rolled up and peeled. When the peeling unit 21 reaches the end position of the peeling operation, the peeling unit 21 and the attaching unit 17 move in opposite directions and return to the initial position. At this time, the waste tape T 'is wound on the collection spool 41, and a certain amount of the mask tape T is drawn out from the tape supply section 13.

Step S6 (Recycling of processed packages)

When the processes up to step S5 are completed, the semiconductor package having been subjected to the tape attach process is recovered. First, the suction device 14 is controlled to release the semiconductor package P from being held on the porous stage 11. After that, as shown in FIG. 11 (a), the tape conveying device G sucks the upper surface of the masking tape Tp that is cut along the outer periphery of the holding jig J.

The masking tape Tp is attached so as to cover the entire surface of each semiconductor package P. In addition, since the upper surface 63a of the partition wall 63 is subjected to non-adhesive treatment, the masking tape T is easily peeled from the holding jig J. Therefore, as shown in FIG. 11 (b), the tape conveying device G holding the masking tape Tp is moved upward by suction, and each semiconductor package P is separated from the recess 61 of the holding jig J, and the masking tape is attached together. Tp moves upward together.

At this time, it is preferable that the holding jig J is sucked and held in the multi-hole table 11. That is, the suction hole 12 for suction-holding the holding jig J and the suction hole 65 connected to the suction hole 65 and connecting the semiconductor package P to the suction-holding of the semiconductor package P are respectively connected to other suction devices 14, and more preferably, It is a structure which controls the adsorption holding of the holding jig J and the adsorption holding of the semiconductor package P independently.

The mask tape Tp that has been moved upward is transferred to the tape transfer device G together with each semiconductor package P, and is collected in the cassette C2 of the package collection unit 12 shown in FIG. 1. The holding jig J remaining on the perforated table 11 is recovered into the jig supply / recovery unit 3 by the robot arm 5 as necessary. In the above, the mask tape attaching process is completed once, and then the above operations are repeated in order.

The semiconductor package P recovered in the package recovery unit 12 is in a state where the entire bump 59 and the entire surface of the first substrate layer 51 are covered. On the other hand, the ground layer 53 and the second substrate layer 55 are not covered by the masking tape T by appropriately adjusting the height of the partition wall 63 and the pressing force of the application roller.

Therefore, by masking and recovering the semiconductor package P and then performing electromagnetic shielding treatment, it is possible to reliably avoid the formation of an electromagnetic shielding layer on the surface of the bump 59 or the first substrate layer 51, and it is possible to reliably use the electromagnetic shielding layer. The electromagnetic shielding material covers the ground layer 53 and the sealing layer 57 and the like. That is, contact between the electromagnetic shielding layer and the bump 59 can be reliably avoided, and the electromagnetic shielding layer is surely grounded by the ground layer 53. Therefore, it is possible to manufacture a device that can prevent a short circuit and can reliably prevent electromagnetic waves from occurring at the semiconductor component level.

In addition, since the semiconductor package P to be masked is reduced to pieces, the surfaces of the ground layer 53 and the sealing layer 57 to be masked are exposed, and the distance between the semiconductor packages P can be increased. Therefore, the formation process of the electromagnetic shielding layer after the mask can be performed more easily and appropriately.

In addition, various processes not limited to the electromagnetic shielding process can be performed on the semiconductor package P after the mask process. As an example, laser marking processing and the like can be mentioned. That is, a desired portion such as the bump 59 or a circuit formed on the upper surface of the first substrate layer 51 can be reliably protected by the mask, and a laser marking process can be applied to the portion other than the protected portion.

In addition, as another example of the process, an installation process based on a stacked package on package (PoP) may be exemplified. That is, in a case where the individualized semiconductor packages P are stacked and mounted, the bumps 59 and the like are masked in advance for the semiconductor package P on the lower layer side, so that the package on the lower layer side can be appropriately avoided. The bump 59 has a problem that the semiconductor package P on the upper layer side receives stress.

<Effects of the structure according to the embodiment>

As described above, the masking tape attaching device 1 of the present invention attaches a masking tape to the surface of a semiconductor package in a small-sized state. By the attachment of the masking tape, the entire bumps 59 formed on the surface of each semiconductor package are appropriately covered with the adhesive layer of the masking tape. Therefore, the masking tape can reliably protect a predetermined portion of the bumps 59 and the like, and accurately perform specific processing such as electromagnetic shielding treatment other than the predetermined portion (the sealing layer 57 and the ground layer 53). In addition, since the masking processing is performed on each of the semiconductor packages after the miniaturization, specific processing can be more easily performed on the unmasked portions.

In the embodiment, when the masking tape is attached, by using the holding jig J, the semiconductor package P can be held on the porous stage 11 more stably. That is, each semiconductor package P is arranged for each of the recessed portions 61 divided by the partition wall 63. Since the shape of the recessed portion 61 is the same as the outer shape of the semiconductor package P, the position of each semiconductor package P on the perforated stage 11 is more accurately maintained by the partition wall 63. Therefore, when the masking tape T is attached, it is possible to appropriately prevent the occurrence of mask failure due to the positional shift of the semiconductor package P.

The partition wall 63 is provided so as to extend in the height direction of the semiconductor package P. The height of the upper surface of the partition wall 63 is adjusted at an appropriate position so as to be between the top of the bump 59 and the surface of the first substrate layer 51. Therefore, it is possible to prevent the pressing force of the application roller 35 from acting on the semiconductor package P in directions other than the height direction (z direction). That is, the partition wall 63 of the holding jig J can reliably prevent the semiconductor package P from falling or deforming due to the pressing force acting on the semiconductor package P in directions other than the height direction. Therefore, the mask processing can be appropriately and surely completed in a small number of steps for the plurality of semiconductor packages P after being chipped, thereby greatly improving the efficiency of the mask processing.

In addition, by arranging the semiconductor package P inside the recessed portion 61 divided by the partition wall 63, the effect of preventing the mask deviation for each semiconductor package P can be further obtained. For example, as shown in FIG. 12 (a), when the semiconductor package P is arranged without the partition wall 63 on the table D, the center package M is compared with the left and right end sections E. More semiconductor packages P are arranged.

At this time, as shown in FIG. 12 (b), depending on the rotation position of the attaching roller 35, the pressing force C exerted on the semiconductor package P from the attaching roller 35 may vary, so there is a concern that the semiconductor package P may be covered. The problem of uneven hood. That is, since a relatively large pressing force C acts on the semiconductor package P disposed at the end E, there is a concern that the adhesive layer of the masking tape T is covered with the ground layer 53 (FIG. 12 (c )). When the subsequent electromagnetic shielding treatment is performed on the semiconductor package P with the ground layer 53 masked, since the formed electromagnetic shielding layer is not grounded, a problem due to poor grounding occurs.

On the other hand, in the semiconductor package arranged at the center M of the holding jig J, there is a concern that the bump 59 is not completely covered during the masking due to insufficient pressing force C (FIG. 12 ( d). When the subsequent electromagnetic shielding treatment is performed in a state where the mask of the bump 59 is incomplete, the electromagnetic shielding layer contacts the bump 59, so a short circuit may occur (see FIG. 20 (c)). When the masks are not uniform, it is difficult to accurately perform processing after the masking process for each of the plurality of semiconductor packages P.

In this embodiment, the partitions 63 are used to partition the semiconductor packages, and the height of the partitions 63 is higher than the surface of the semiconductor package P (the surface of the first substrate layer 51). At this time, since the deviation of the pressing force of the attaching roller 35 is appropriately reduced due to the upper surface 63a of the partition wall 63 adjusted to an appropriate height, it is possible to more reliably avoid occurrence due to the arrangement position of the semiconductor package P The mask is uneven.

In addition, the external shape of the holding jig J is circular like the external shape of the semiconductor wafer. Specifically, the shape is the same as the shape of a wafer as defined by the SEMI standard, the Japan Semiconductor Manufacturing Equipment Association, and the like. Therefore, in the case where the holding jig J is transported, arranged, or aligned, a configuration of a device that performs the same processing on a semiconductor wafer can be applied, and the masking tape attaching device 1 can be more easily performed. Optimization of the operation of the holding jig J.

The present invention is not limited to the above-mentioned embodiments, and can be modified as follows.

(1) In the embodiment, the masking tape attaching device 1 is described by taking the configuration of a roller shape in which the applying roll 35 is rotated and the masking tape T is attached, but it is also applicable to use a chamber and A structure in which the masking tape T is attached under a pressure difference under vacuum.

In the chamber-type configuration of the modification (1), as shown in FIG. 13 (a), the upper case 71 a and the lower case 71 b sandwich the masking tape T to form the cavity 71. Then, in a state where the semiconductor package P held by the porous stage 11 is housed in the chamber 71, the pressure reduction of both the upper case 71 a and the lower case 71 b is started using a vacuum device (not shown).

At this time, the air pressure in the space of the lower case 71b is controlled to be lower than the air pressure in the space of the upper case 71a. As shown in FIG. 13 (b), the masking tape T covers the semiconductor package P by the pressure difference Sp. The surface of each. By adopting a configuration in which the masking tape is attached while reducing the pressure in the chamber, a plurality of semiconductor packages P can be appropriately attached with the masking tape T without being affected by the deviation of the pressing force of the application roller.

(2) In each of the embodiment and the modification, a ring frame f may be further arranged around the perforated stage 11. That is, as shown in FIG. 14 (a), a configuration in which the upper surface of the ring frame f and the entire surface of the semiconductor package P are covered with the masking tape T may be applied.

In such a modification (2), in step S5, the masking tape T is cut along the ring frame f. Then, as shown in FIG. 14 (b), in step S6, the ring frame f is gripped and moved upward by using a transfer arm H or the like, so that the semiconductor can be transferred without holding and holding the entire upper surface of the masking tape Tp. Each of the packages P. That is, during transportation, unnecessary force can be prevented from acting on the masking tape Tp and the semiconductor package P, so that the tape or the semiconductor package can be prevented from being damaged.

(3) In each of the embodiment and the modification, the depth of each of the recesses 61 is the same configuration, but it is not limited to this. That is, a configuration in which the height of the bottom portion 61 a of the concave portion 61 is changed depending on the position of the concave portion 61 may be applied. There may be cases where the deviation of the mask can be reduced by the partition wall 63 of the holding jig J, but the deviation may not be zero.

As an example, as shown in FIG. 12 (b), in a configuration in which the masking tape is attached using a roller, the rotation position of the application roller 35 is above the end E of the holding jig J In the case where the pressing force C is larger than the rotation position of the applicator roller 35, the position is at the center M of the holding jig J. Therefore, the semiconductor package P arranged at the end portion E tends to be covered with the masking tape T lower than the semiconductor package P arranged at the center portion M.

Therefore, as shown in FIG. 15, in accordance with the deviation of the pressing force C acting on the semiconductor package P, the height of the bottom portion 61 a of the recess 61 in the end portion E of the holding jig J is relatively low, and In the center portion M of the jig J, the height of the bottom portion 61a is relatively high.

By changing the height of the bottom portion 61 a in accordance with the position of the recessed portion 61 in this manner, the height of the position where the semiconductor package P is held by suction can be appropriately adjusted. Therefore, even if there is a deviation in the pressing force C, the problem of deviation in the mask due to the arrangement position of the semiconductor package P can be reliably avoided.

(4) In addition, the structure for adjusting the height of the semiconductor package P is not limited to a structure in which the thickness of the bottom portion 61a of the holding jig J is changed. As shown in FIG. 15 (b), at least the holding jig may be used. A part of the bottom 61 a of J is omitted, and a pin 75 that moves up and down in the z direction is arranged in the perforated stage 11 at a lower portion of each of the recesses 61. By controlling the height of the pin 75 in accordance with the position at which the semiconductor package P is disposed, the height of the position where the semiconductor package P is adsorbed and held can be appropriately adjusted. In addition, the pin 75 may be provided so as to penetrate the porous stage 11 in the vertical direction.

(5) In the embodiment and each modification, a configuration in which the operation of the application roller 35 is controlled by changing the pressing force of the application roller 35 depending on the rotational position of the application roller 35 may be applied.

As an example, when the application roller 35 rotates on the end E of the holding jig J in step S3, control is performed so that the pressing force C of the application roller 35 with respect to the masking tape T becomes larger. On the other hand, when the application roller 35 is rotated on the central portion M of the holding jig J, control is performed so that the pressing force C becomes smaller.

In this way, the size of the pressing force C is controlled by the rotation position of the attaching roller 35, and even if the height of the bottom 61a of the holding jig J is fixed, it is possible to appropriately prevent the shielding due to the placement position of the semiconductor package P Hood deviation.

(6) In the embodiment and each modification, as shown in FIG. 16, the recessed portion 61 and the partition wall 63 may be formed integrally with the porous stage 11.

(7) In the configuration in which the semiconductor package P is separated from the holding jig J in step S6, the masking tape is not limited to being held by the holding of the tape conveying device G as shown in FIG. 11 (b). The entire structure of Tp moves away from the holding jig J as a whole. That is, as shown in FIG. 17 (a), the semiconductor package P may be separated from the holding jig J by deforming the end portion of the masking tape Tp by applying a force.

As shown in FIG. 17 (b), the semiconductor package P can be separated from the holding jig J by bending and deforming the holding jig J. In this configuration, since the masking tape T is not deformed, the problem that stress is applied to the semiconductor package P and the problem that the masking tape Tp is peeled from the semiconductor package can be appropriately avoided. In particular, when the holding jig J is a material (rubber or the like) having flexibility and elasticity, the bending deformation of the holding jig J shown in FIG. 17 (b) can be more easily performed.

(8) In the embodiment and each modification, as shown in FIG. 18, the concave portion 61 may be tapered toward the bottom portion 61 a and the front end thereof may be tapered. At this time, since the width W1 of the bottom portion 61 a is relatively narrow, the gap between the semiconductor package P and the partition wall 63 becomes smaller. Therefore, the positional deviation of the semiconductor package P can be more appropriately avoided in the state provided in the recessed portion 61. Therefore, in the modification (8), it is more preferable that the width W1 of the bottom portion 61 a and the width of the bottom portion of the semiconductor package P are substantially the same.

Further, in the upper portion 61b of the recessed portion 61, the width W2 becomes wider. Therefore, the adhesive layer constituting the masking tape T easily enters the gap Ga between the semiconductor package P and the upper portion 61b. Therefore, in the tape attaching process of step S3, at least the entire bump 59 and the entire surface of the first substrate layer 51 can be reliably covered with the adhesive layer of the masking tape T.

(9) In the embodiment and each modification, it has been described that the holding jig J is configured as a disc-like structure as shown in FIG. 4, but the shape of the holding jig J is not limited to a circle, as shown in FIG. 19. It is also possible to appropriately change the outer shape in accordance with the position and number of the recesses 61.

(10) In the embodiment and each modification, the batch type attaching device has been described as an example, but the configuration of the present invention can also be applied to a continuous type device.

(11) In the embodiments and the modifications, the porous stage 11 is configured to be held by adsorbing the semiconductor package P or the like, but is not limited thereto. That is, a configuration in which a holding jig J or a semiconductor package P is held in place of the porous stage 11 using a table having no adsorption function can be applied.

(12) In the embodiment and each modification, the configuration in which the holding jig J is provided with the suction hole 65 has been described. However, the configuration without the suction hole 65 may be applied to the holding jig J.

(13) In the embodiment and each modification, after the holding jig J is placed on the porous stage 11, each of the semiconductor packages P is arranged and held in the recess 61 of the holding jig J, respectively. However, it is not limited to a configuration in which the holding jig J and the semiconductor package P are individually arranged. That is, the holding jig J in which the semiconductor package P is arranged in each of the recesses 61 in advance may be loaded into the cassette C1, and the holding jig J may be placed on the perforated stage 11 before A structure in which the masking tape T is attached.

In such a modified example, a holding jig (for example, a tray or the like) holding a plurality of singulated semiconductor packages P is transported toward the multi-well stage 11. Therefore, the time and process required for the masking process can be shortened, and the yield can be greatly improved.

Claims (8)

    A masking method for a semiconductor package, comprising: a holding step for holding the semiconductor package; a substrate layer having bumps formed on a surface of the semiconductor packaging system; and a semiconductor device having a small piece covered with an insulating material and applied. And a masking step, in which a masking tape is attached to the semiconductor package held and at least the bumps are covered.         For example, the method for masking a semiconductor package according to claim 1, further comprising a holding portion setting step of providing a holding portion, the holding portion having a groove portion having the same shape as the semiconductor package, and a partition wall defining the groove portions from each other. In the holding step, each of the semiconductor packages is held inside each of the groove portions with respect to the holding portion provided in the holding portion setting step.         The masking method for a semiconductor package according to claim 2, wherein in the holding step, the height of the upper surface of the partition wall is lower than the height of the top of the bump and higher than the surface of the substrate layer. The height position holds each of the aforementioned semiconductor packages.         The masking method for a semiconductor package according to claim 2, wherein the groove is tapered from the top to the bottom, and the front end is tapered.         The mask method for a semiconductor package according to claim 2, wherein the outer shape of the holding portion is circular.         The masking method for a semiconductor package according to claim 1, wherein in the masking step, the application roller is rotated in a predetermined direction to attach the masking tape to the semiconductor package.         The masking method for a semiconductor package according to claim 6, wherein in the masking step, the pressing force of the bonding roller is controlled by the rotation position of the bonding roller.         The masking method for a semiconductor package according to claim 1, wherein in the masking step, the chamber is decompressed, and the masking tape is attached to the semiconductor package by a pressure difference.