TW201818392A - Power supply line voltage drop compensation for active matrix displays - Google Patents

Abstract

Driving system circuitry for an active matrix display comprises: a data driver module for receiving a digital data bit stream representing an image to be displayed by pixels of the active matrix display, one or more power supply lines for powering a plurality of pixels each comprising at least one light emitting element, a voltage source connected to the one or more power supply lines, and calibration means for compensating for power drop over the one or more supply lines. The calibration means comprise means for flowing a current through an individual pixel, means for determining a voltage drop across the pixel and for comparing this to a pre-determined reference voltage for that pixel, means for determining, from the comparison, calibration values for that pixel which take into account resistance of wiring connected to the voltage source and to ground, and means for applying the calibration values to a received digital data bit stream to generate therefrom data driver voltages to be applied to the data driver module for representation of a corrected image.

Description

Power line voltage drop compensation for active matrix displays

The present invention relates to the field of active matrix LED panels. More particularly, the present invention relates to methods for driving and compensating for non-uniformities in digitally driven AMLED or AMOLED displays.

Active matrix light-emitting diode (AMLED) display panels and versions including organic light-emitting diodes (AMOLEDs) typically include three main components: a front panel containing LEDs or OLEDs, and a backplane with active matrix pixel arrays (including TFTs). And an electronic driver that is usually at the edge of the display. There is a significant degradation in both the front and bottom panels during display operation, and the production process of the flat panel display is not uniform. The lack of uniform or homogeneous manufacturing conditions currently seems inevitable, as such inhomogeneities in displays come from a variety of uncontrollable sources: inhomogeneities in the manufacturing process (for example, across the thickness of the dielectric of the panel) Variations and dielectric properties of the semiconductor, changes in deposition and formation of (O) changes in the material of the LED, etc.), inhomogeneities in the matrix material (eg, grain boundaries in LTPS), and other sources. The degradation of the display can be manifested in a number of ways : for example, shifting of OLED characteristics (degraded due to use, degradation due to elapsed time), shifting of TFT characteristics (usually dominated by bias stress (voltage or illumination)), etc. . Another effect that causes degradation and non-uniformity can result from supply variations in current distribution across all pixels and ground line resistance. To compensate for the shift and variation caused by the degradation, the current in each pixel needs to match the desired digital value of the pixel to be displayed. An introduction strategy has been developed to accurately set the pixel current. Conventional and most commonly used techniques for driving a drive transistor as a source of saturation current (ie, by applying a source-drain voltage (VDS) that is substantially greater than one of VGS-VT) Use fine tuning. This high source-drain voltage results in higher power consumption due to a significant portion of the power being lost across the bottom plate of the drive transistor acting as a current source. In addition, parasitic effects are typically introduced by contact leads and power supplies between sets of pixels, such as rows in a display. These parasitic effects (such as voltage drop) can be compensated by adding a digital to analog converter (DAC) in each row. However, this adds complexity to the circuit and introduces other parasitic effects and voltage drops. This can result in degradation of one of the image quality since the currents in all of the pixels should be equal in all cases of a one-bit (PWM) driven active matrix display. Other techniques have been developed that use a PWM scheme to set a particular brightness level in each pixel. However, this requirement can accurately set the pixel current to zero or a fixed value (based on pixel size and desired display luminosity). WO 2014/080014 describes how a current source can be used for each line to achieve a uniform current. However, this requires twice as many contact pads to drive the display (and therefore introduces additional parasitic effects) compared to an analog drive scheme, since both the data line and the power supply are on a per-column basis in the solution. Must be provided by the 矽 drive. In addition, the solution requires a large amount of current source in the driver, which will occupy a significant area of the wafer. This is the best, because fewer pixels per unit area are produced, resulting in sub-optimal display resolution. Furthermore, the solution is not a cost-effective way to drive one of the displays.

One object of embodiments of the present invention is to provide a good method and apparatus for driving an AMOLED (Active Matrix OLED) display or an AMLED (Active Matrix LED) display. One of the advantages of an embodiment of the present invention is that the display is driven in a uniform manner for good image quality. In a first aspect, the present invention provides a drive system circuit for an active matrix display. The driving system circuit comprises: - a data driver module for receiving a digital data bit stream representing one of the images to be displayed by the pixel of the active matrix display, - one or more power lines, And supplying a plurality of pixels each including at least one of the light-emitting elements, a voltage source coupled to the one or more power lines, and a calibration component for compensating for power drops on the one or more supply lines. The calibration member includes - means for flowing a current through a different pixel - means for determining a voltage drop across the pixel and for comparing the voltage drop to a predetermined reference voltage of the pixel - for The comparison determines a component of the calibration value of the pixel, the calibration value is connected to the voltage source and is connected to the grounding resistance of the grounded wiring, and - is used to apply the current to a received digital bit stream The calibration value is the component from which the data driver voltage is generated, and the data driver voltage is to be applied to the data driver module for representing a corrected image. An advantage of an embodiment of the present invention is that the correction can be performed dynamically, thereby correcting the difference in characteristics of the light-emitting elements and the characteristics of the light-emitting elements by considering the voltages at the power lines and the ground lines of the plurality of columns together. The difference in output caused by temperature change and time degradation. In an embodiment of the invention, the drive system may further comprise a variable impedance (eg, a tunable resistor) coupled in series with the LED or OLED in each pixel, adapted to be immediately after the pixel is activated Provides the same current flowing through one of each pixel. In a drive system in accordance with an embodiment of the present invention, the calibration member can include a memory for storing the determined calibration value. In a drive system in accordance with an embodiment of the present invention, the calibration member can include a reference current source coupled to a feedback loop and further coupled to the at least one power line via a "calibration mode" switching member. An advantage of one of the embodiments of the present invention is that the current source can be fabricated with high accuracy and can be implemented in an integrated circuit that can be easily distributed among several data drivers in an active matrix panel Above the wafer. An additional advantage is that the internally generated voltage can be used as a reference, so the impedance matching is independent of the germanium wafer. In a driving system according to an embodiment of the present invention, the calibration component may include an interpolation unit and a ground voltage drop multiplication unit, and the interpolation unit and the ground voltage drop multiplication unit are adapted via a summation unit to be the active The data driver module of the matrix panel provides voltage regulation. Thus, voltage regulation and compensation can be provided through data drivers already present in active matrix displays without the need for additional current sources, DACs, etc., which saves wafer area and allows for displays with high resolution. An additional advantage is that impedance variations due to grounding can be taken into account. In a drive system in accordance with an embodiment of the present invention, the voltage source and the calibration member are connectable to a first side of the at least one power line. The at least one power cord can further include a second side connectable to the one of the voltage sources via a second "drive mode" switching member. In a drive system in accordance with an embodiment of the present invention, the voltage source can include a DC/DC converter. In this way, a high efficiency voltage source can be obtained without the need for an ADC or DAC and its extra voltage drop. In a second aspect, the present invention provides an active matrix display comprising: an array of pixels logically organized into columns and rows, each pixel comprising at least one light emitting element; and in accordance with the present invention One of the embodiments of the first aspect drives the system circuitry. In an active matrix display in accordance with an embodiment of the present invention, the pixels may comprise a 2T1C structure. With few components (this reduces losses), this embodiment has a simple layout and is easily controlled. In an active matrix display in accordance with an embodiment of the present invention, the array can be divided into two sets of pixels, each set including drive system circuitry in accordance with any of the embodiments of the first aspect. An advantage of an embodiment of the present invention is that multiple pixels on different columns can be calibrated in parallel by replicating the number of reference current I _ref sources, mode select switches, and comparators. In a third aspect, the present invention provides a method of calibrating an active matrix display comprising an array of pixels logically organized into columns and rows. The method includes flowing a current through an individual pixel of one of the pixel columns of the array, determining a voltage drop across the pixel and comparing the voltage drop to a predetermined reference voltage of the pixel, and determining the pixel based on the comparison Calibration values that are connected to the voltage source and connected to the grounding resistance of the grounded wiring, and store the calibration values. In a fourth aspect, the present invention provides a method of driving an active matrix display. The method includes receiving a digital data bit stream representing one of an image to be displayed on the active matrix display, applying a previously determined calibration value to the received data bit stream to generate a data driver voltage therefrom, The data driver voltages are to be applied to one of the active matrix display data driver modules to indicate that at least one of the images is corrected for power reduction on the supply line. In this method, the drive transistor acts as a variable impedance, more specifically as a variable (tunable) resistor. In this method, the calibration values can be determined according to the method of the third aspect. Particular and preferred aspects of the invention are set out in the accompanying independent technical solutions and the associated technical solutions. Features from the subsidiary technical solutions may be combined with features of the independent technical solutions and combined with features of other subsidiary technical solutions as appropriate, and not only as explicitly stated in the scope of the patent application. These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments illustrated herein.

The invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto but only by the scope of the claims. The drawings are merely illustrative and are non-limiting. In the figures, the size of some of the elements may be exaggerated and not necessarily drawn to scale. The dimensions and relative dimensions do not correspond to the actual reductions used to practice the invention. The terms first, second, and the like in the scope of the description and claims are used to distinguish between the like elements and are not necessarily used to describe a sequence in time, space, in a ranking, or in any other manner. It is to be understood that the terms so used are interchangeable, and the embodiments of the invention described herein are capable of operation in other sequences than those illustrated or illustrated herein. In addition, the terms top, bottom, and the like in the description and claims are used for illustrative purposes and are not necessarily used to illustrate relative positions. It is to be understood that the terms so used are interchangeable as appropriate, and the embodiments of the invention described herein are capable of operation in other orientations other than those illustrated or illustrated herein. It should be noted that the term "comprising", used in the claims, is not to be construed as limited Accordingly, the present invention is to be construed as a limitation of the nature of the claimed features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps, components or groups thereof. Therefore, the scope of expressing "a device including components A and B" should not be limited to devices consisting only of components A and B. It means that with respect to the invention, the only relevant components of the device are A and B. References to "an embodiment" or "an embodiment" in this specification means that a particular feature, structure or characteristic described in connection with the embodiments is included in at least one embodiment of the invention. The phrase "in one embodiment" or "in an embodiment" or "an embodiment" or "an" Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments, as will be apparent to those skilled in the art. Similarly, it will be appreciated that in the description of the exemplary embodiments of the invention, various features of the present invention are sometimes combined together for the purpose of simplifying the invention and assisting in understanding one or more of the various aspects of the invention. A single embodiment, a drawing or an illustration thereof. However, this method of the invention should not be construed as reflecting the intention that the claimed invention requires more features than those explicitly recited in each claim. Rather, the scope of the invention as reflected in the following claims is intended to be limited to all features of the single disclosed embodiments. Therefore, the scope of the patent application, which is hereby incorporated by reference in its entirety, is hereby expressly incorporated herein Furthermore, although some embodiments set forth herein include some of the features of other embodiments, and other features, combinations of features of different embodiments are intended to be within the scope of the invention, and Different embodiments are formed, as will be understood by those skilled in the art. For example, in the scope of the following claims, any of the claimed embodiments can be used in any combination. In the description provided herein, numerous specific details are set forth. However, it is understood that the embodiments of the invention may be practiced without the specific details. In other instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure one of the description. An OLED display includes a display of an array of light emitting diodes in which an emissive electroluminescent layer emits light of an organic compound film in response to a current. OLED displays may use passive-matrix (PMOLED) or active-matrix (AMOLED) addressing schemes. In the case of an OLED display, the present invention is directed to an AMOLED display. A corresponding thin film transistor backplane is used to switch each individual OLED pixel to on or off. AMOLED displays allow for higher resolution than PMOLED displays and larger display sizes than PMOLED displays. However, the invention is not limited to AMOLED displays, but is limited to a broader concept associated with active matrix displays. While AMOLED displays are particularly advantageous in terms of current switching speed of their pixel elements, any type of active matrix display can use the concepts of embodiments of the present invention. If the pixel elements of the active matrix display can be switched faster, it is advantageous, which therefore allows for a higher frame rate and therefore less flickering of the image. An active matrix display (eg, an AMLED or AMOLED display) in accordance with an embodiment of the present invention includes a plurality of pixels each including a light emitting element (eg, a light emitting diode (LED) or an organic LED (OLED) )element). The light emitting elements are arranged in an array and are logically organized into columns and rows. Throughout the description of the present invention, the terms "horizontal" and "vertical" (respectively related to the terms "column" and "row", respectively) are used to provide a standard system and are merely illustrative. It does not need (but can) refer to the actual physical orientation of one of the devices. In addition, the terms "row" and "column" are used to describe the set of array elements that are linked together. The links may be in the form of a Cartesian array of one of the rows; however, the invention is not limited thereto. As will be understood by those skilled in the art, the rows and columns are readily interchangeable and are intended to be interchangeable in the present description. Also, non-Cartesian arrays can be constructed and included within the scope of the present invention. Therefore, the terms "column" and "row" should be interpreted broadly. To facilitate this broad interpretation, the description and scope of the patent application are logically organized into columns and rows. By this it is meant that the collection of pixel elements are linked together in a topological linear crossover; however, physical or topological configurations need not be. For example, the columns may be rounded and the radius of the circle of the circle and the circles and radii described in the present invention are set forth as "logically organized" columns and rows. Also, the specific names of various lines (e.g., selection lines and data lines) are intended to facilitate the interpretation and understanding and are intended to refer to the generic names of a particular function. The specific choice of words is not intended to limit the invention in any way. In an embodiment of the invention, the invention relates to a driving circuit for an active matrix LED (AMLED) or OLED (AMOLED) display panel, which allows uniform pixel supply and thus reduces display degradation and non-uniformity . The present invention is also directed to an AMLED and AMOLED display panel including one of the drive circuits in accordance with embodiments of the present invention. The present invention is also directed to a method for power line voltage drop compensation for digitally driving an AM(O) LED display. In an embodiment of the invention, the voltage mode digital drive is used to drive the display panel. Impedance matching based on block level provides a compensation scheme to substantially reduce or eliminate non-uniformity and degradation of both the front and bottom plates. When using voltage mode digital driving, the pixel array can be calibrated in a variety of ways. Essentially, there is some way to check or program a feedback of the current flowing in an individual pixel. The present invention encompasses all introduction mechanisms based on this concept. As a core principle, the current in the pixel is determined by varying the pixel impedance, as also set forth in WO 2014/080014, which is incorporated herein by reference. The techniques described in this document can also be used for this concept. Impedance matching is performed to eliminate variations in the TFT and OLED and to compensate for the voltage drop across the line. To obtain a calibration value, a first solution includes monitoring current during a calibration cycle, wherein a current sensor monitors the current consumed by a single pixel. This would require starting a pixel (column or row, determined by the direction of the power line defining the voltage drop) per channel per calibration cycle and tuning the drive transistor until the pixel current reaches a predetermined reference value. This will result in each current sensor tuning a single pixel during the calibration cycle. This is not a preferred solution because a large amount of current measurement data will be obtained and only a single current is required in the digital driving method. A second preferred solution includes transmitting a current during a calibration cycle and adapting a tunable resistor until an effective supply voltage V is reached for the system in which it is designed _DD So far, the number of pixels per column and its resistive model are taken into account. An advantage of this embodiment is that the current source can be made very accurately (for example in a crucible) and in that the current source can be easily distributed over several wafers. The internally generated voltage is used as a reference, so the impedance matching is independent of the (矽) wafer. These two options have the advantage of considering the wiring connected to the power supply and the wiring connected to the ground of several columns, thereby reducing the number of semiconductor (eg, germanium) contacts and (in) the wafer. The number of calibration circuits. However, this reduces the update speed of the calibration because less hardware is available to perform the calibration. The calibration renew time depends on the number of pixels per calibration channel (ie, a column or a plurality of columns) and the time between pixel calibrations. The time between calibrations of different pixels depends on whether calibration is only done at startup or during display runtime. In the case of run-time calibration of a digitally driven display (and in the case where the power line is perpendicular to the data line), any unused time slots within the digital drive scheme can be used for calibration. This gives the advantage of having a better hidden calibration. For example, one of the working cycles, as described in page 15, line 10 to page 16, line 15 of WO 2014 068017, shows one of the first sub-frames, the first time slot system 0, and the remaining time slots will be 1 (if the most significant bit is 1) or 0 (if the most significant bit is 0). Even for an 8-bit number, the digital signal is 11111111, but the first time slot in this type of duty cycle will be 0, as seen on page 16, line 23 to line 28 of the same document. This unused time slot can be used for calibration in accordance with embodiments of the present invention. In one aspect, one method of digitally driving and calibrating an AM(O) LED display is provided. Embodiments of the method can provide shifting (O) degradation of LED characteristics (degraded by time, degradation due to use) and TFT characteristics, which are generally dominated by bias stress (voltage or illumination bias). Bit compensation, thus obtaining a good image quality of one of the AM(O) LED displays. In general for (O) LEDs, the current in each pixel needs to match the digital value of the pixel to be displayed. A strategy for accurately setting the pixel current and compensating for the voltage drop along the power line will be set forth in the method. In some embodiments, a calibration value is obtained for each pixel, for example by using a reference current I _Ref And measuring and adjusting the voltage drop across the pixel; or directly measuring the current through the pixel by means of a current sensor. Each of the calibration values required to obtain a calibrated pixel is stored in a calibration memory. When the AM(O) LED display is actually used, a data stream representing one of the images to be displayed is obtained and introduced into a data driver for driving the active matrix in a compensation manner. The AM(O) LED display is then driven by considering the calibration value of each pixel previously determined. The same hardware block can be used to obtain calibration data and perform calibration and voltage correction. 4 shows an exemplary system diagram of one of a digitally driven active matrix display in accordance with an embodiment of the present invention. It includes an image interface hardware 107, a first data driver hardware 401, and optionally a second data driver hardware 402 (for example, all or a portion of a data driver that can be implemented in the wafer), a first dedicated line driver A set 403 and a second dedicated line driver (e.g., embedded line driver) set 404 and a pixel backplane 405, the second set of dedicated line drivers 404, in accordance with a second aspect of the present invention, includes A "select" line of pixels, a first "voltage distribution and voltage drop calibration" block or "power distribution" block 109, and a second voltage distribution unit or block 108 are selected in the array. A voltage distribution unit (e.g., including voltage source 101 and switches 103, 104 for power distribution) can form a single unit 108 (Fig. 1). The voltage distribution unit, together with the voltage compensation unit (eg, current source 106 and image interface hardware 107), may also form a compact unit 109, such as an integrated unit. In an alternate embodiment, only unit 109 is present. The actual front plate containing the pixels comprising the LED or OLED is not illustrated in FIG. During normal use of the active matrix display (ie, during image display), an image input in the form of digital data representing one of the images to be displayed is transmitted through an input 406 (eg, a wire or a bus) to the image interface. Body 107. Control and data signals are sent from image interface hardware 107 to data driver hardware 401 and optionally 402, and control signals are sent to first dedicated line driver set 403 and optionally second dedicated line driver set 404. Moreover, the signal can be returned as a feedback from the voltage drop calibration block 109 toward the image interface hardware 107. Figure 5 shows two possible embodiments of data driver routing. In the left hand side embodiment 500, the first data driver 401 and the second data driver 402 are respectively present on both sides of the display for respectively controlling a subset of the pixels. For example, each data driver can control a collection of data lines 501, 502 that can be stretched up to the middle of the display. In the right hand side embodiment 510, only the data driver 401 is present on one side of the display and its corresponding data line 511 extends across the entire display up to the other side of the display. In both embodiments, the data drive can be multiplexed if the drive is fast enough. In this case, the display backplane technology can be implemented as part of a data drive block, such as a multiplexer. Selecting a wiring may have options similar to some of the data wires in the data wire (data line). It may for example be stretched perpendicular to the data conductor of Figure 5 (this example does not limit the invention). For example, the select wires (select lines) can be extended from the dedicated line drivers 403, 404 on either side of the display to the middle of the display, or can be extended from the line driver 403 on one side of the display to the other side of the display ( Only one dedicated line driver set 403) will be needed in this case. The active matrix display further includes a drive circuit that includes, on the one hand, a set of power supply to voltage sets 102 and, on the other hand, a voltage distribution and voltage drop calibration unit 109 and optionally a second voltage distribution unit 108, depending on the design The voltage lines may be extended parallel to the selection line or extended in any other suitable manner in embodiments of the invention. In an embodiment of the invention, the power supply line includes both VDD connections and GND connections for each pixel of the array. Figure 1 shows two examples of drive circuits. The upper circuit 100 has a voltage source 101 connected to one side of a power line set 102 for supplying power to a display. However, in some embodiments, the power source is only connected to one side of the panel. In any case, this connection may be provided by a switch (eg, one or more "drive mode" switches 103, 104, such as a transistor) for selecting (enabling or disabling) the driving of the panel. Thus, a voltage source can be used to drive the display panel, and this eliminates the need to introduce a DAC into each column, thereby reducing the amount of components and saving space in the display, thus improving the design scale. In addition, the display is not limited by the DAC bit resolution (the DAC bit resolution typically needs to be greater than the number of pixels being manipulated). The drive can be simply made to reduce costs. Using a voltage source and avoiding the use of a DAC offers the added benefit of reducing or eliminating the extra voltage drop due to the connection. When using a DAC, a certain amount of voltage drop is required for DAC operation, and this loses power. On the other hand, the voltage source 101 can be made with high efficiency (for example, a DC/DC converter). In addition, including one of the voltage source drive circuits facilitates energy saving. During the drive mode of the display, one or more "drive mode" switches 103, 104 are turned on so that the power supply VDD is connected to both sides of the power line 102, and when inactive, the one or more "drive mode" switches are off. Broken. During calibration, the "drive mode" is turned off and the "calibration mode" switch 105 is active, for example, a current source 106 is used to apply a unit current I. _Ref Drive through the power cord. The lower portion of Figure 1 shows a dual drive circuit configuration in which there are two sets of "drive mode" switches 103, 113 and "calibration mode" switches 105, 115 and two reference current sources 106, 116. It can form two integrated units 109, 119 that are connected to each side of the panel. This configuration can divide the columns, and each set can drive a subset of the pixels in panel 112 (eg, each half of the pixels). In this configuration, the calibration and power supply can be parallel. In one aspect, the invention relates to a drive circuit for an active matrix display, such as an AMLED or AMOLED display panel. The driving circuit includes a set 102 of power lines (eg, wires, other electronic paths of the bus bars) for powering a group of pixels, the group of pixels being configurable into a plurality of columns, each group of pixels being connected to one of the sets 102 Separate power cord. In a particular embodiment of the invention, wherein the pixels are arranged in a number of columns and rows, all of the pixels on one column are connected to the same power line, and the pixels of the different columns are connected to different power lines. In an embodiment of the invention, for example as illustrated in Figure 1, a set of supply lines 102 is provided such that there is one power line for each pixel column in the array. In an embodiment of the invention, the power supply line includes both a line connected to the power supply VDD and a line connected to the ground GND. In an embodiment of the invention, a voltage source VDD is used to supply power to the panel. The voltage source VDD can be connected to either side of the set 102 of power lines via switches 103, 104, 113 or disconnected from both sides of the set 102 of power lines. During the "normal drive" mode of the display, one of the signals labeled "Drive Mode Selection" is active, the switches 103, 104 are closed, and the power supply VDD is coupled to both sides of the set 102 of power lines. When "drive mode selection" is inactive, the power supply VDD is disconnected from both sides of the set 102 of power supply lines. Because of the fact that a voltage source can be used to power the display (although a current source is actually required), there is no need to include a current mode digital to analog converter (DAC) for all columns. This also improves the size of the design, because for larger displays, a larger number of pixels need to be supplied from such DACs, and the accuracy of the DAC needs to be greater than the number of pixels being manipulated. In addition, one of the other advantages of using a voltage supply is to eliminate the voltage drop within the current DAC. The voltage source can be made with high efficiency, for example with a DCDC converter. In a current DAC, a predetermined amount of voltage drop will be required for DAC operation and this will lose power. Furthermore, from a power point of view, the use of a voltage source as in one embodiment of the invention is a preferred solution. When "calibration mode selection" is active, another switch 105 is closed and a unit current I is _Ref Drive through a power cord. In this regard, a reference current source is provided at one side of the set 102 of power lines. This is used for calibration, as explained in more detail below. Measuring a voltage at the same side of the power line for injecting current, and transmitting the measured voltage to a comparator unit, where the measured voltage and the reference voltage V are compared in the comparator unit _Ref(i) One set, where i is from 1 to p, and p is already for the number of predefined reference voltages for calibration. The result of this comparison is provided to the digital logic in the image interface hardware 107. Since the illumination in an active matrix display (such as an LED or OLED panel of the present invention) is reduced by degradation, the pixels may include a relatively simple configuration such as 2T1C (a circuit with 2 transistors and 1 capacitor), as shown in the figure Shown in 6. However, the present invention is not limited to the 2T1C configuration, and other configurations (e.g., 4T2C, 5T2C, 6T2C) may be applied for maintaining the TFT voltage threshold shift to be extremely low, thus reducing variations in pixel brightness. The invention is applicable to p-type transistors and n-type transistors and is applicable to any type of substrate including, for example, hydrogenated amorphous Si (a-Si:H), polycrystalline germanium, organic semiconductor, (amorphous) indium. Drive circuit for gallium zinc oxide (a-IGZO, IGZO) TFT or other). 6 shows two basic configurations of a pixel structure of an AM(O) LED display in accordance with an embodiment of the present invention. The illustrated embodiment is a 2T1C (2 transistors, 1 capacitor) configuration, but any other suitable configuration can be applied. The pixel structure includes one LED or an OLED 601 connected in series with a driving transistor M1. The (O) LED 601 can be coupled between the ground line 603 coupled to the ground GND and the transistor M1 (shown in the left-hand side portion of FIG. 6), or coupled to the power supply V. _DD Between the power line 604 and the transistor M1 (shown on the right hand side of Figure 6). (O) The sum of the voltages across the LED and transistor M1 results in a voltage across the pixel. The transistor M1 acts as a switch for supplying power to the (O) LED 601 with power from the power line 604. The transistor M2 is selected to connect a data line 606 to the gate of the driving transistor M1. The gate of the selected transistor M2 is coupled to a select line 607 which is shown extending parallel to the power line 604 and the ground line 603. Selection line 607 extends perpendicular to data line 606. The capacitor C1 is connected between the gate and the source of the driving transistor M1. In an AM(O) LED display, a plurality of such pixels as represented in FIG. 6 can be logically arranged in a number of columns and rows. The pixels arranged in the same row can be connected to the same data line 606, and the pixels arranged in the same column can be connected to the same selection line 607. The voltage, current, impedance and related parameters used for calibration in each pixel will have different values depending on the position of each pixel in the column, since the resistance between the power supply and each pixel depends on its contact lead The position between the pixels, etc., in the column. Embodiments of the present invention provide impedance matching per pixel during normal use of the display (i.e., during display of an image). In this regard, first measuring the voltage on each pixel while introducing a reference current into the pixel according to a predetermined calibration scheme (as will be described below), and then controlling the current in each pixel via impedance matching to eliminate the active matrix and (O) The change in LED and compensate for the voltage drop across the column. Impedance matching is achieved for each pixel by tuning one of the variable impedances in series with the LED or OLED of the pixel. In an embodiment of the invention, the drive transistor of each pixel is used as a variable resistor. Figure 7 shows that each pixel in a column is subjected to a voltage drop that depends on the position of the pixel in a column of N pixels, which is due to the resistance connected in series between the pixel and the connection to the power supply. The distance increases and increases. The two possible configurations of the pixel columns connected to power line 604 and the resistance between the pixels are shown in Figure 7 as a resistive model. The upper embodiment of Figure 7 illustrates one resistive model driving one pixel column from both sides, while the lower embodiment illustrates one resistive model of one pixel column driven from a single side. In a column having N pixels, each of which includes an (O) LED 601, 611 (only the LED of each pixel and the driving transistor M1) has a power line resistance R1 (located adjacent to each other) Between the pixels) and a ground line resistor R2 (between adjacent pixels). These resistors R1, R2 are derived from metal wiring and may be well known (e.g., modeled, measured, etc.). These resistors can be calculated based on the layout. The sum of the resistances between the two pixels in the power line and the ground line is the reference resistance, R1 + R2 = Rref. Usually, the wiring to the external power supply VDD and to the ground GND will have a resistance R greater than the inter-pixel lead resistances R1 and R2, respectively. _S1 , R _S2 . The ratio M is defined as the resistance ratio with respect to the internal pixel resistance. R _S1 And R _S2 Usually defined by: The upper embodiment 700 of Figure 7 includes power lines that are in contact from both sides such that the pixels at the far end of the column are connected to the power supply VDD. The resistive voltage drop for this situation (the power line is in contact with the power supply VDD at both distal ends) is illustrated in FIG. Figure 8 illustrates three scenarios: graph 201 - no (O) LED on; graph 202 - (O) LED on a typical assignment along the column; and graph 203 - along the column ( O) The LEDs are all on. As can be seen from these graphs, the power drop on the power line increases as the number of pixels turned on between the connection point to the power supply line of the power supply and the pixel at the position n being considered. The resistive voltage drop for the case where the power line is contacted from both sides can be calculated as follows. During calibration, a current source (e.g., current source 106 of FIG. 1) is introduced through a power line to introduce a current by opening switches 103, 104; closing switch 105; and routing by means of power distribution blocks 109, 108 Current. Therefore, during calibration, only one pixel (calibrated pixel) is turned on per current source, and the remaining pixels in the column are turned off. If two or more reference current sources (106, 116) are used, it will be possible to calibrate two or more pixels simultaneously. Self-injection reference current I _Ref The resistive voltage drop across the pixel at position n in the column of N pixels (the number of pixels n is a number between 1 and the total number of pixels on the column (which is N)). First as the current I at the contact at the pixel in position n ₀ And when to define when a pixel is turned on (and therefore draw current I) _Ref ) binary code b _i A function of (b subscript i) is used to calculate the current flowing in the column. The algorithm thus uses one of the N-bit streams from one of the columns of image data. This N-bit stream system b _N ... b _i+1 b _i ... b ₁ . Resistance R of the wiring between two pixels _Ref Define the voltage drop between two pixels . All of these voltage drops up to pixel n are summed and added with resistance R _s =R _S1 +R _S2 In the case of a voltage drop at the contact lead, an equation for the voltage drop up to pixel n is obtained: In this expression, the factor M is introduced as R _s With R _Ref The ratio between: . However, I ₀ It must be determined based on the fact that the voltage at the last position N corresponds to the resistive voltage drop across other power contact wires: This translation is: Will I ₀ Substitute In the equation, the result is: So by R _Ref I _Ref Express voltage drop for the unit. The only constant required in the calculation is the number M as defined above. . This number M depends on the geometry of the layout to the external wiring of the display. When there are more than 1000 pixels in a column, the voltage drop calculated using it is less than 1 microvolt. Due to this high degree of accuracy, some of the least significant bits of the least significant bits can be ignored in the final result. For example, the calculation of the voltage drop can be done in two steps. In a first step, calculate a number A _N : During operation, this number A can be calculated in a column before the actual drive. _N . Therefore, the number A is calculated for column x+1 during the driving of column x _N . Use A _N A binary number B representing the voltage drop in the power line at each pixel is obtained _n . Considering A _N The previously calculated value may be calculated in real time for each pixel of column x+1 while the data is loaded into the first data driver hardware 401 and/or the second data driver hardware 402: The expression of the voltage drop can be separated into two terms A _N And B _n You can iteratively calculate each of the two items. Can calculate values in a hardware block . This hardware block may be present in the image interface hardware 107. It can include a counter and two adders. The algorithm implementing this approach can be iterated as follows: s ₀ =0 p ₀ = 0 loop (i, 1, N) s _i = s _I-1 + b _i p _i = p _I-1 + s _i If (b _i =1): p _i = p _i + M ends loop A _N =C*p _i The result of the C = 1/(2M + N) iteration can be multiplied by the constant C = 1 / (2M + N) at the end, but this constant C can be calculated in advance, which enables a compact multiplication. All in all, this is a very compact hardware block. Provide results only at the end of the column. Once the value A is obtained _N Alternatively, the power line voltage drop at each pixel in a column can be calculated in real time in a hardware block (which may also be present in the image interface hardware 107). The collection. It can include a counter and two adders and a multiplier. All in all, this is a very compact hardware block. The algorithm for implementing this method can be as follows: Iteration: s ₀ =0 p ₀ = M*A _N Loop (i, 1, N) s _i = s _I-1 + b _i p _i = p _I-1 - s _i p _i = p _i + A _N B _i =p _i End loop this loop definition B _n Different values. 8 illustrates how a power line voltage drop reference level V is defined in accordance with an embodiment of the present invention. _Ref(1..N) . The maximum power line voltage drop (curve 203) and the minimum power line voltage drop (graph 201) are known (depending on the resistance and the applied reference current I) _Ref The value is accurately calculated and defined between a voltage drop reference level set 801 at which an equidistant interval can occur during operation (the number of levels is defined by the required accuracy or maximum cost of the system). For convenience, the level corresponding to the most significant bit (MSB) of the calculated number of Bn is defined. Each voltage drop level defined in 801 will be aligned during the calibration phase of the display and a calibration will be performed for each pixel. A binary value is obtained during calibration, which, if supplied to the data driver, produces a voltage across the gate of the drive transistor such that the previously determined reference voltage on the pixel is obtained. A reference voltage is provided for each MSB of Bn. The LSB is obtained by interpolation. As a specific example, Bn is considered to represent a binary number of voltage drops of one of the bit strings in a pixel n, and for example three MSBs are selected. This selection determines the number of voltage drop reference levels, and the number of reference levels for the three MSB voltage drops corresponds to eight voltage drop reference levels 801. During calibration, only one pixel (per current source 106, 116) is turned on in the column and only eight possible voltage drops are measured. The value "000" corresponds to the non-resistive voltage drop (in the case of the minimum voltage drop 201), and the value "111" corresponds to the maximum resistive voltage drop (obtained only in the middle of the maximum voltage drop map 203). In the memory that interfaces the hardware 107, one of each pixel and each of the eight levels is stored to calibrate the voltage value. The actual Bn number includes one string longer than its three MSBs. Therefore, the actual value used for calibration is a linear interpolation between the associated pixel n and the next pixel n+1. The rest of the string (least significant bit) can be used to improve interpolation. It should be noted that for each pixel, all calibration levels are obtained so as not to affect the hardware speed, even pixels that are theoretically closer to the power source (eg, at the side of the display in Figure 8) will not reach all possible reference levels. . Figure 10 shows a calibration method for one pixel, which is similar to the method disclosed on page 13, line 23 to page 14, line 10 of WO 2014/080014. During calibration, the display is thus driven column by column (by selecting the transistor M2 by the line drivers 403, 402 and making the reference current I _Ref Flow through the power cord). Reference current I through a single active pixel _Ref Applied to only one pixel column, leaving the remaining pixels in the column inactive. Due to I _Ref The system is injected through both the (O) LED and the transistor M1, so the total voltage is the sum of the voltage V* on the (O) LED and the voltage on the transistor, which is between V* and _Ref Pixel V below _L Between the voltages on. The voltage at the gate of the driving transistor M1 of the active pixel is set at its lowest correlation value for switching by the driving transistor M1 becoming turned on, and thus the voltage V on the pixel _L Specific supply voltage V _DD high. Increasing the voltage at the gate of the transistor results in a lower V _L . Increase the gate voltage until the voltage on the pixel is the same as the supply voltage. Therefore, the voltage at the gate of the driving transistor M1 is gradually increased until the power voltage V is obtained. _L * (= supply voltage V _DD ) as the voltage on the pixel. This value corresponds to the power cord (for example, V _DD The smallest voltage drop in a cell, which typically occurs in the pixel at the beginning of the power line (ie, directly connected to the power supply). This value is stored as the minimum power line voltage drop in the calibration memory of the pixel. The process can be illustrated as sweeping one of the gate voltages during calibration, as indicated by arrow 1001 in FIG. This is done for each pixel until all power line voltage drop reference levels are obtained and stored in the calibration memory. Therefore, for each pixel, the increments of n voltage drop calibration levels are stored in the calibration memory of the pixel. One of the differences from the method of WO 2014/080014 is that the pixel is now driven by a voltage source and the calibration value can be used to directly adjust the voltage of the data line. By copying the reference current I as illustrated in Figure 1 _Ref The number of sources, the mode selection switch, and the comparator are used to perform parallel calibration of multiple pixels on different columns. Figure 9 shows how the actual data drive can be addressed. The hardware block may be present in the image interface hardware 107. It has two input data streams: power line voltage drop 901 (B _N .... B _{i+1Bi ....} B ₁ And a digital data bit stream 902 representing the image to be displayed (b) _N .... b _i+1 b _i .... b ₁ ). As an output, obtain one of the data driver voltage values, stream 903 D _N .... D _i+1 D _i .... D ₁ And it can be introduced into the data driver module 904 of the active matrix panel display. The power line voltage drop most significant bit (MSB) is sent to the calibration memory 905 for each pixel. A calibration value of the voltage drop of the pixel n and a voltage drop of the next pixel n+1 are supplied to an interpolation unit 906. The least significant bit (LSB) of the same voltage drop of pixel n is also provided to interpolation unit 906 and interpolation unit 906 is enabled to perform an accurate interpolation between the two calibrations. In both cases, when calculating the voltage drop, the ground line voltage drop can be advantageously considered, for example, to drive the gate of the transistor M1 (see Figure 6) that powers the LED. Typically, the ratio between the ground line voltage drop and the total supply line voltage drop is known (which is typically 0.5), so the ground line voltage drop is obtained by multiplying this known ratio in multiplication unit 907. This voltage needs to be added to summing unit 908 to the voltage that drives the gate to M1. Finally, based on digital data bit stream (b _N .... b _i+1 b _i .... b ₁ The output multiplexer 909 selects an output which is the calculated gate voltage when the bit is "1" and when the bit is "0". The same module can be used during the calibration procedure. A counter 910 can be included for adjusting the calibration process and/or storing the values in the calibration memory. The counter 910 is set to be at a value corresponding to the lowest possible gate voltage at the beginning of the calibration procedure, and when the obtained pixel voltage is higher than the first reference voltage, the corresponding counter value is stored in the first calibration value address in. Since the calibration value is also applied to the MSB input of the calibration lookup table 905, its value is also obtained at the output. During calibration, the LSB bit is set to 0 (thus the interpolation is disabled) and the digital data stream 902 is set to "1", thus turning on each pixel to derive the desired data driver voltage at the output. This is increased until the required reference voltage is obtained. This is then done for all reference voltages. The per-pixel calibration shown in FIG. 10 can be performed in a recursive manner for each pixel, including storing the values in memory 905 (eg, a lookup table) of the computing unit of FIG. The relationship between the power line voltage drop and the desired gate voltage (the voltage introduced through the data line for controlling the gate of M1) has a 1/(ax) behavior, where "a" is greater than that illustrated in Figure 8. Describe the maximum power line resistive voltage drop. This will require multiple calibration reference levels to accurately perform the calibration. However, the data driver can advantageously be implemented with a 1/(ax) behavior, thus reducing the required number of calibration levels and increasing accuracy. This correction can be performed occasionally (e.g., periodically) by trimming the gamma response curve that can be implemented in some existing display material drivers. Modulation of the gamma curve is known in the art, for example, it can be implemented as interpolation of values that can be uploaded by software, and it can be easily integrated into embodiments of the present invention. An exemplary sequence of driving pixel turn-on and turn-off in FIG. 8 shows a power line voltage drop along a column of N pixels, and the top left upper graph 200 of FIG. Driving one of the pixel columns shows the power line voltage drop along the N pixel column. The number of pixels n is a number between 1 and the total number of pixels (N) on the column. The algorithm may use an N-bit stream from one of the columns of image data as defined in the prior art (for example, in document WO2014068017A1). This N-bit stream system b _N .... b _{i+1bi ....} b ₁ . These bits may represent pixel intensity data, which represents an image. The connections between the pixels, the connections between the pixels and the power source, and the connections between the pixels and the ground GND are electrically conductive connections (typically metal connections and leads) that have electrical resistance and create a voltage drop along the column. The voltage drop depends on the location of the pixel. Pixels that are close to the center of the display (eg, farther from the connection to the power supply) will exhibit (by average) a voltage drop that is higher than the pixel close to the power supply. Figure 2 shows the voltage drop curve of the minimum voltage drop 201 (all (O) LEDs are off), the voltage drop curve of a typical voltage drop 202 (several (O) LEDs on, other turn-off) for three scenarios. And a voltage drop curve of the maximum voltage drop 203 (all (O) LEDs are turned on): - in the upper left diagram 200, for an embodiment in which the power line is connected from both sides to the voltage source 101 (eg for In the embodiment 100 of Figure 1 connected to the power supply on both sides, both sides of the quantum curve end with a voltage level VDD. - In the upper right diagram 210, the power cord is not connected from one side but only from one side. In a practical implementation, a single side alternative is advantageous where power cannot be connected to both sides of the display. However, the voltage drop is usually high. - In the lower diagram 220, a dual drive circuit is used. In this alternative, the power VDD and the ground GND line are not connected to both sides of the panel, but the panel is divided, and each divided portion includes only one connection to the voltage source and GND. This embodiment divides the power line into two parts. The voltage drop curve corresponds to the lower portion 110 of FIG. It requires twice as many calibration units and there is a high voltage drop, but it requires less calculation. In certain cases, the power voltage and ground voltage may not be equal in the middle of the power line (even the maximum voltage drop is not equal; especially if each subset does not include the same number of pixels and (and therefore) resistors, the maximum voltage drop Can be very different, as explained with reference to Figure 7. This embodiment has the advantage that it requires a somewhat lower amount of calculation, but (in some cases) may have a higher voltage drop. It also doubles the number of calibration units. In the case where the power line is only connected from one side (corresponding to the graph in the upper right diagram 210 of FIG. 2), the corresponding resistive model is illustrated in the lower embodiment 710 at the bottom of FIG. The resistive voltage drop can be calculated in a process similar to the previous one. As mentioned before, first as the current I at the contact at the position of the pixel n ₀ And when to define when a pixel is turned on and therefore draw current I _Ref Binary code b _i One function to calculate the current flowing in the column: Use the resistance R of the wiring between two pixels _Ref Define the voltage drop between two pixels . In the case where all such voltage drops up to pixel n are summed and the voltage drop at the contact leads is added, an equation up to the voltage drop of pixel n is obtained, which is: In this equation, the factor M is obtained as R as described previously. _S With R _Ref Ratio between (R _S = MR _Ref ). Still need to determine the current I ₀ But the current at the end of the power line: Considering this, this translation is And therefore: As previously mentioned, two units can be used to sequentially calculate AN and Bi for each pixel on one of the columns of the display. Calculate A for this embodiment _N The unit may include only one counter (or two counters for parallelization of the calculation (in the case where the panel is driven by two voltage sources and two calibration units), as illustrated in the lower diagram of FIG. Description). Iteration: s ₀ =0 cycle (i, 1, N) s _i = s _I-1 + b _i End loop A _N =s _i Calculate B for this embodiment _n The unit includes only one counter and two adders (this can be duplicated for parallelization in a dual configuration, as illustrated in Figure 1 below in Figure 1). As such, these are extremely compact hardware implementations. This iteration is equivalent to B _n The previous instance of iteration. So in summary, a data bit stream containing one bit b per pixel in a column with one N pixel is used to calculate parameter A _N . Then bit stream and parameter A _N Both are used to calculate one voltage drop per pixel (and therefore N voltage drops) for each data bit. In an alternate embodiment of the invention, the voltage can be swept during calibration and the current can be directly measured (as shown in Figure 3) using a current source and an ADC configuration by means of a current sensor. The current sensor will monitor the current through a single pixel during a calibration cycle, and the drive transistor acting as a tunable resistor can be used to tune the current until the pixel current is the same as the reference pixel current. 3 shows an embodiment of a current sensor 302, 303 that includes a variable voltage source 301 (and thus sweeps the voltage during calibration) and for measuring current. This embodiment is compatible with a drive circuit having a dual connection to the voltage source (FIG. 1 top diagram 100) or a dual drive circuit (FIG. 1 lower diagram 110). The implementation of Figure 3 requires complex and accurate analog-to-digital converters (ADCs) 304, 305 and double sweeps during calibration (this is due to the need to change both the gate voltage and VDD of M1) to arrive through the pixel The exact current. In another alternative embodiment, the power is connected to only one side of the display, and the drive circuit includes a single current sensor 302 and a single ADC 304. The simulation results are an evaluation of the operation and timing and the effectiveness of the calibration method of the embodiment of the present invention on the digitally driven display. The analog electronic circuit simulator has been used to program SPICE ("Integrated Analog Circuit Simulator") to simulate the calibration for the first line. . Figure 11 shows a practical implementation of a digitally driven OLED display. Power and grounding are connected from one side, which is the worst case scenario for calibration methods. Calibration is expected to be much better when power and ground are connected from both sides. In addition, the simulation has been performed using a blue OLED in order to have the worst case of simulation. It is expected that calibration for other OLEDs (red, green) that require lower currents will be better. The resistivity of the power line is an important factor in the quality of the calibration. Analog power line at 4 Ω/pixel (4 ohms/pixel) (15.4 kΩ for a full power line of 3840 pixels). A better calibration is expected with a lower power line resistivity. V _T And V _OLED The selected values are significantly expanded. So for a V with +0.4 _T One of the transistors also has a V of -0.4V _T One of the transistors will be effective. The same applies to OLED extensions. If these extensions are lower, the rate of change will be lower, so calibration is expected to be better in practical applications. The display of Figure 11 and the pixels of Figure 6 have been used for simulation. In the case where the marked display line 1101 is fully turned on, the calibration of the marked display line is simulated with respect to the following characteristics (this is because of the representation of all lines): Display: 4K resolution: 3840×2160; Pixel Size: three colors 60μm = 423ppi; pixels: standard IGZO (n-type) with common cathode OLED. Output brightness: 500 nits Blue OLED sub-pixel current: 0.15 μA (calculation of dominance) Resistivity per pixel on the supply line: 4 Ω/pixel TFT: Assume that the mobility of IGZO does not undergo a change in current simulation. V only _T Change: average V _T = 1V, OLED: = 0.15μA (microamperes), average V _OLED = 3.5V, = 0.1V Compares pixel current versus pixel position in an uncalibrated display (Figure 12), compares one of the resistivity corrections without power line correction in the calibration method (Level 1) (Figure 13) and the calibration method Includes full calibration of the resistivity of the power cord correction (Level 2) (Figure 14). The graph shows that the pixel current according to Figure 11 varies with the pixel position along the column of the display, with the first pixel 1102 of column 1101 at the 0 position (closest to the power connector) and the last pixel 1103 of the column (in the middle of the display) At position 1920, this is the maximum distance from the power connector. The absolute pixel current is shown in solid lines in FIGS. 12 to 14 and the relative error with respect to the reference current (predetermined to be 0.15 μA) is shown in dashed lines. Figure 12 shows that for uncalibrated cases, the standard global deviation on one line and the relative difference between adjacent pixels are: Adjacent pixels: Therefore, the maximum difference in light output between two adjacent pixels can be as large as 50% without calibration. This system is extremely high and indicates that calibration is strictly required. In addition, it should be noted that the effect of the voltage drop along the power line is visible, but the current is dominated by local expansion. Figure 13 shows that for a calibrated case (level 1), the standard global deviation and the relative difference between adjacent pixels are: ; adjacent pixels: These results do not include the step of compensating for the resistive voltage drop of the power line. Therefore, the following characteristics can be observed: a) In the case where all the pixels on the column are turned on (the highest display output, 500 nits), the current in the middle of the display is higher than the edge due to the resistive voltage drop. The current is low. b) In addition, the calibration also becomes poor: in the case of comparison with pixels at the edge of the display, the pixels in the middle of the display have a poor calibration. The effect of the resistive voltage drop in the calibration procedure can be advantageously introduced in the case of high light output and/or high resistivity of the power line. Figure 14 shows that for a calibrated case (level 2), the standard global deviation and the relative difference between adjacent pixels are respectively global: ; adjacent pixels: The SPICE simulation demonstrates the high uniformity of the display after taking into account the resistance of the power line. The expansion on the transistor and OLED is equal to the extension in the former simulation. The resulting pixel output is extremely uniform and does not depend on the location on the display. The pixel in the middle of the display (position close to 1920) has an intensity that is nearly equal to the pixel at the edge of the display. Also, in the case where one 8-bit per color coding is used, the global spread over the pixel current is less than the least significant bit (LSB). The maximum difference between the two pixels corresponds to 1.5 times the LSB. This calibration has been done in the worst case scenario, so calibration will be better in other situations (eg lower power line resistivity further reduces the resulting expansion after calibration). Figure 15 shows a comparison of three methods for the same column of the display (thin line 1501 for uncalibrated results, thick line 1502 for level 1 calibration, and dashed line 1503 for level 2 calibration). The upper graph shows the absolute pixel current and the lower graph shows the relative error with respect to the reference current (0.15 μA). The encircled region 1510 that is closest to the power connection exhibits an initial change. In the case where the resistive voltage drop is not taken into account (level 1 calibration), the initial change existing in the uncalibrated current mostly disappears, and a uniform current is obtained. However, the current drops linearly toward the center of the display (the end of the column). However, in the case where the resistive voltage drop is taken into account (level 2), the change disappears from the simulation and the current remains equal between the edge and the center of the display. The surrounded area 1511 shows the change at the end of the column. In the case where the resistive voltage drop is not taken into account (Level 1), all initial changes in the uncalibrated current after calibration are still present in the current. It is only small. In addition, the average current is about 20% lower (in the end of the column) than in the center of the display. In the case where the resistive voltage drop is taken into account in the calibration (level 2), the change disappears from the simulation and the current remains almost equal between the edge and the center of the display. In summary, embodiments of the method of the present invention seek to reduce pixel variations and intensity gradients from the edge to the end of the column or from the edge to the middle of the display. For example, in the case where there are more than 640 pixels on one of the 4 Ω/pixel power lines of the display, this is advantageous because the method can take into account the resistance drop. In the case of added compensation with a drop in resistance, it is possible to obtain a better uniformity than 1 LSB (8-bit) on a 3840×2160 (Ultra High Density) display.

100‧‧‧Upper Circuit / Upper Drawing / Example

101‧‧‧voltage source

102‧‧‧Power cord set/collection/power cord

103‧‧‧Switch/"Drive Mode" Switch

104‧‧‧Switch/"Drive Mode" Switch

105‧‧‧"Calibration Mode" Switch/Switch

106‧‧‧Reference current source/current source

107‧‧‧Image interface hardware/interface hardware

108‧‧‧Select second voltage distribution unit/block/unit/second voltage distribution unit/power distribution block

109‧‧‧"Power Distribution" Block/Compact Unit/Unit/Voltage Drop Calibration Block/Integral Unit/Power Distribution Block

110‧‧‧lower schema

112‧‧‧ panel

113‧‧‧"Drive Mode" Switch/Switch

115‧‧‧"Calibration Mode" Switch

116‧‧‧Reference current source/current source

119‧‧‧Integrated unit

200‧‧‧Last left upper picture / upper left picture

201‧‧‧Minimum voltage drop/curve

202‧‧‧Curve diagram / typical voltage drop

203‧‧‧Chart / Maximum Power Line Voltage Drop / Maximum Voltage Drop Diagram / Maximum Voltage Drop

210‧‧‧Upper upper graphic

220‧‧‧lower schema

301‧‧‧Variable voltage source

302‧‧‧ Current Sensor

303‧‧‧ Current Sensor

304‧‧‧ Analog to Digital Converter

305‧‧‧ Analog to digital converter

401‧‧‧First Data Drive Hardware/Data Drive Hardware/First Data Drive/Data Drive

402‧‧‧Second data driver hardware/second data driver/line driver

403‧‧‧First dedicated line driver set/dedicated line driver/line driver

404‧‧‧Second dedicated line driver set/dedicated line driver

405‧‧‧pixel bottom plate

406‧‧‧ input

500‧‧‧ left hand side embodiment

501‧‧‧Information line

502‧‧‧Information line

510‧‧‧right hand side embodiment

511‧‧‧Information line

601‧‧‧Light Emitting Diode/Organic Light Emitting Diode

603‧‧‧ Grounding wire

604‧‧‧Power cord

606‧‧‧Information line

607‧‧‧Selection line

611‧‧‧Light Emitting Diode/Organic Light Emitting Diode

700‧‧‧Upper implementation

710‧‧‧Lower implementation

801‧‧‧Isometric interval voltage drop reference level set / voltage drop reference level

901‧‧‧Power cord voltage drop

902‧‧‧Digital data bit stream/digital data stream

903‧‧‧ Streaming

904‧‧‧Data Drive Module

905‧‧‧Calibration Memory/Calibration Lookup Table/Memory/Lookup Table

906‧‧‧Interpolation unit

907‧‧‧Multiplication unit

908‧‧‧Summing unit

909‧‧‧Output multiplexer

910‧‧‧ counter

1001‧‧‧ arrow

1101‧‧‧Marked display lines/columns

1102‧‧‧first pixel

1103‧‧‧Last pixel

1501‧‧‧ Thin line

1502‧‧‧ thick line

1503‧‧‧dotted line

1510‧‧‧rounded area

1511‧‧‧rounded area

B _N .... B _i+1 B _i .... B ₁ .. B ₁ ‧‧‧Power cord voltage drop

b _N .... b _{i+ 1} b _i .... b ₁ ‧‧‧ digit data bit stream

C1‧‧‧ capacitor

GND‧‧‧ Grounding

I ₀ ‧‧‧current

I _ref ‧‧‧reference current / unit current / current

M1‧‧‧Drive transistor/transistor

M2‧‧‧Selective crystal

R ₁ ‧‧‧Power cord resistance / wire resistance / resistance

R ₂ ‧‧‧resistance

R _S1 ‧‧‧resistance

R _S2 ‧‧‧resistance

VDD‧‧‧Power/Voltage Source/External Power/Voltage Level/Power

V _DD ‧‧‧effective supply voltage / power / supply voltage

V _L ‧‧‧ voltage

V _L *‧‧‧Power voltage

V _ref(1..N) ‧‧‧reference voltage/power line voltage drop reference level

V*‧‧‧ voltage

1 illustrates two illustrative embodiments of power distribution and calibration circuits for two types of AM(O) LED displays, each having a single panel and being divided into two One of the subsets of pixels. Figure 2 shows a voltage drop curve for three power line connection embodiments: the sides of the connection panel, connected to a single side connected to the sides of one of the panels divided into two subsets of pixels. FIG. 3 shows, in a schematic manner, an illustrative embodiment including a variable voltage source and current sensor. 4 shows an illustrative diagram of one of the digitally driven displays in accordance with an embodiment of the present invention. Figure 5 shows an illustrative option for the configuration of the data drive wiring. Figure 6 shows two embodiments of a pixel configuration suitable for use in embodiments of the present invention. Figure 7 shows two resistive models of a display in accordance with an embodiment of the present invention. 8 shows an exemplary reference level of a voltage drop that can be calculated and used during calibration, in accordance with an embodiment of the present invention. Figure 9 illustrates a schematic block diagram showing the calibration of the power line voltage drop for addressing the data drive. Figure 10 shows a calibration method for a single pixel in accordance with an embodiment of the present invention. Figure 11 illustrates one practical embodiment of a digitally driven OLED display. Figures 12 through 15 illustrate the simulation results. The drawings are merely schematic and are non-limiting. In the figures, the size of some of the elements may be exaggerated and not necessarily drawn to scale. Any reference signs in the scope of patent application should not be construed as limiting. In the different figures, the same reference symbols are used to refer to the same or similar elements.

Claims (12)

A driving system circuit for an active matrix display, the driving system circuit comprising: a data driver module for receiving a digital data bit string representing one of the images to be displayed by the pixel of the active matrix display a plurality of power lines for supplying power to a plurality of pixels each including at least one light emitting element; a voltage source coupled to the one or more power lines; a calibration member for compensating the at least one power line The power is reduced, the calibration component comprising: means for causing a current to flow through the other pixel for determining a voltage drop across the pixel and comparing the voltage drop to a predetermined reference voltage of the pixel for use in The comparison determines a component of the calibration value of the pixel, the calibration value being connected to the voltage source and connected to the grounded wiring for electrical resistance considerations, and for applying to a received digital bit stream The calibration value is the component from which the data driver voltage is generated, and the data driver voltage is to be applied to the data driver module for use. It represents a corrected image. The drive system circuit of claim 1, further comprising a variable impedance coupled in series with one of the light-emitting elements of each pixel, adapted to provide flow through each of the pixels immediately after activation of the pixel The same current. A drive system circuit as in any one of the preceding claims, wherein the calibration means comprises a memory for storing the determined calibration value. The drive system circuit of claim 1 or claim 2, wherein the calibration component comprises a reference current source coupled to a feedback loop and further coupled to the at least one power line via a "calibration mode" switching member. The drive system circuit of claim 1 or claim 2, wherein the calibration component comprises an interpolation unit and a ground voltage drop multiplication unit, and the interpolation unit and the ground voltage drop multiplication unit are both adapted via a summation unit The data driver module of the active matrix display provides voltage regulation. The drive system circuit of claim 1 or claim 2, wherein the voltage source and the calibration member are connectable to a first side of the at least one power line, the at least one power line further comprising a second "drive mode" A switching member is coupled to the second side of one of the voltage sources. An active matrix display comprising a pixel array logically organized into a plurality of columns and a plurality of rows, each pixel comprising at least one light emitting element, the active matrix display further comprising a drive as claimed in claim 1 or claim 2 System circuit. The active matrix display of claim 7, wherein the pixels comprise a 2T1C structure. The active matrix display of claim 7, wherein the array is divided into two sets of pixels, each set comprising a drive system circuit such as request item 1 or request item 2. A method of calibrating an active matrix display, the active matrix display comprising an array of pixels logically organized into a plurality of columns and a plurality of rows, the method comprising: flowing a current through one of the pixel columns of the array Individual pixels; determining a voltage drop across the pixel and comparing the voltage drop to a predetermined reference voltage of the pixel; determining a calibration value for the pixel based on the comparison, the calibration value being connected to the voltage source and connected to ground The resistance of the wiring is considered, and the calibration values are stored. A method of driving an active matrix display, the method comprising receiving a digital data bit stream representing an image to be displayed on the active matrix display, applying the previously determined data to the received data bit stream The calibration value is derived from the data driver voltage from which the data driver voltage is to be applied to one of the active matrix displays to indicate that at least one of the images is corrected for power reduction on the supply line. The method of claim 11, wherein the calibration values are determined according to the method of claim 10.