TW201817005A - Releasing a resonator employing a thermally formable film - Google Patents

Abstract

Techniques are disclosed for releasing a resonator device employing a thermally formable layer. In some cases, a resonator device is formed on or above a thermally formable layer that can be heated to decrease the volume of that layer and form an air cavity below the resonator device. The thermally formable layer can include any suitable material that decreases in volume in response to increased temperature. For instance, in some example cases, the thermally formable layer includes thermoplastic material, porous material, material with a negative coefficient of thermal expansion (CTE) and/or any other material that shrinks or contracts (or otherwise reduces in volume) when heat is applied to it. The resonator devices formed using the techniques described herein may only require an air cavity having a maximum vertical dimension of only 2 nm to effectively resonate, although a broad range of cavity dimensions can be provisioned.

Description

 Release of a thermally filmable resonator  

The present invention relates to a resonator that uses a thermally filmable film.

Radio frequency (RF) filters are an important part of modern communication systems. With more and more communication bands and modes, the number of RF filters at the front end of mobile devices can grow rapidly. Resonators, such as thin film bulk acoustic resonators (FBARs), sometimes referred to as thin FBARs (TFBARs), are components used to fabricate RF filters. Typically, resonators are configured to have increased oscillations at certain frequencies, which are referred to as their resonant frequencies. FBAR or TFBAR is a device consisting of a piezoelectric material located between two electrodes, wherein the device is acoustically isolated from the surrounding medium to allow the device to oscillate/vibrate/resonate.

100‧‧‧ method

200‧‧‧Substrate

210‧‧‧Isolation

211‧‧‧ trench

212‧‧‧Adhesive increase layer

214‧‧‧Adhesive lowering layer

220‧‧‧ Thermoformable layer

232‧‧‧ bottom electrode

233‧‧‧Interconnection

234‧‧‧Piezoelectric layer

236‧‧‧Top electrode

240‧‧‧Interlayer dielectric (ILD) layer

250‧‧‧ air cavity

260‧‧‧ access trench

220'‧‧‧ Thermoformable layer

234'‧‧‧ piezoelectric layer

250’‧‧‧ Air cavity

1000‧‧‧Computation System

1002‧‧‧ motherboard

1004‧‧‧ processor

1006‧‧‧Communication chip

Figure 1 shows a method of forming a resonator employing a thermoformable layer in accordance with some embodiments of the present invention.

2A-E show an example integrated circuit structure (IC) formed when the method of FIG. 1 is implemented in accordance with some embodiments of the present invention.

Figures 2B' and 2C' show enlarged portions of Figures 2B and 2C, respectively, in accordance with some embodiments to illustrate an exemplary optional adhesion increase/decrease technique that may be employed.

2E' shows an example structure of FIG. 2E, including example variations that may occur in an IC structure, and also shows that if a conventional etch undercut technique is used to release the access trench that would exist for the resonator, it is shown in accordance with some embodiments. Imaginary location.

3 shows a computing system implemented with integrated circuit structures and/or resonator devices formed using the techniques disclosed herein, in accordance with some embodiments of the present invention.

These and other features of the prior embodiments will be more readily understood from the following detailed description. In the figures, each identical or nearly identical component shown in the various figures may be represented by the same numeral. For the sake of clarity, not every component may be labeled in every drawing. In addition, the accompanying drawings are not necessarily to For example, while some of the figures generally indicate straight lines, right angles, and smooth surfaces, actual implementations of the disclosed techniques may have imperfect straight lines and right angles, and some features may have surface topography or unevenness in view of the real world limitations of the manufacturing process. Still further, some of the features in the figures may include patterning and/or shading fills, which are primarily provided to help visually distinguish between different features. In short, the drawings are only intended to show example structures.

 SUMMARY OF THE INVENTION AND EMBODIMENT  

When fabricating a resonator (eg, FBAR) for a radio frequency (RF) filter, an air cavity formed under each resonator device is required to release the device and isolate it from the surrounding medium, thereby resonating The device effectively oscillates/vibrates/resonates. In other words, the resonator device needs to float between the air chambers to allow physical vibration in the vertical direction. The cavity under the resonator that allows it to oscillate or resonate is typically formed using an etch undercut technique. This etch undercut technique involves first forming a resonator device over the substrate that has an intervening sacrificial layer (eg, an isolation oxide) between the resonator and the substrate. After the resonator device has been formed, a trench is formed adjacent the resonator to provide access to the underlying sacrificial layer. Assuming that the underlying sacrificial layer is accessed via a nearby trench, an etch process can be used (eg, a wet etch process) to laterally remove material from the sacrificial layer beneath the resonator device, which can be referred to as a release etch . However, such a release etch technique can cause the resonator device to collapse. Moreover, the access trenches used to cause the release etch to perform increase the total area required to form the resonator device, thereby reducing the total amount of resonators that can be formed in a given space. Further aggravating this problem is the need for a large number of resonator devices for various RF applications such as RF front end applications (eg, greater than 100 resonators).

Thus, and in accordance with one or more embodiments of the present invention, techniques are provided for releasing a resonator device employing a thermoformable layer. In some embodiments, the resonator device is formed on or over a thermoformable layer that can be heated or otherwise heat treated to reduce the volume of the layer and form an air cavity below the resonator device. In some such embodiments, the thermoformable layer can comprise any suitable material that reduces volume in response to elevated temperatures. For example, in some embodiments, the thermoformable layer can comprise a thermoplastic material (eg, polypropylene, polyester fiber, polyethylene), a porous material (eg, a porous dielectric material), a material having a negative coefficient of thermal expansion (CTE) (e.g., cubic zirconium tungstate, bismuth molybdate), and/or any other material that will be reduced or shrunk (or otherwise reduced in volume) when heat is applied thereto as will be apparent to the present invention. In some embodiments, a resonator device formed using the techniques described herein may only require an air cavity having a maximum threshold vertical dimension of 5, 4, 3, or 2 nm, for example, to effectively vibrate/oscillate/resonate. Thus, in some such example embodiments, the configuration and conditions for the thermoformable layer may be selected to ensure that a suitable air cavity is formed. For example, in some embodiments, it will be apparent from the present invention that the material of the thermoformable layer, the vertical thickness of the thermoformable layer, and/or the temperature applied to the thermoformable layer can be adjusted to ensure a suitable air cavity Formed under the resonator device to enable the device to operate effectively.

In some embodiments, it may be desirable for the thermoformable layer to shrink/shrink upon heating such that the formed air cavity (due to the reduction/contraction) is between the thermoformable layer and the resonator device (eg, relative to heat) Between the molding layer and the substrate). Thus, in some such embodiments, the techniques may include reducing the bond between the thermoformable layer and the overlying material (eg, the material of the bottom electrode of the resonator device) and/or increasing the thermoformable layer and Adhesion between materials on other sides of the layer, such as an underlying material (eg, a substrate material) and an adjacent material (eg, an isolating material on either side of the thermoformable layer). For example, in some embodiments, as will be described in greater detail herein, between the thermoformable film and adjacent features, by including an intermediate layer, employing surface treatment, and/or modifying the properties/structure of the thermoformable film Adhesion can be increased and/or decreased. In some embodiments, the techniques may include a particular positional application of increased and/or decreased temperature to increase the likelihood that the thermoformable film will shrink/contract in a desired manner. For example, in some such embodiments, an elevated temperature (eg, heat) can be applied to the top of the IC structure (or the side closest to the resonator device) and, optionally, the reduced temperature (eg, Reduced heat or cold can be applied to the bottom of the IC structure (or the side closest to the substrate) to help create an air cavity between the thermoformable layer and the resonator device (rather than relative to heat) Other locations of the molded layer).

The techniques can provide many benefits that will be apparent to the present invention. For example, using the techniques described herein reduces the footprint of a given resonator (eg, relative to a similar resonator formed using the previously described etch undercut technique), thereby increasing the resonator for a given area. Density is achieved and allows for smaller RF device form factors. Furthermore, the techniques described herein for forming an air cavity under a resonator can avoid the collapse of the resonator (whether during fabrication or use) relative to the etch undercut technique, as some embodiments of the various heat treatments not provided herein are The access trench used in the etch undercut technique removes material adjacent to the resonator (thus affecting the structural integrity of the device) and the release etch used in the etch undercut technique is typically under the resonator A large air cavity is formed (eg, an air cavity having a vertical dimension of up to 100 nm or more). Furthermore, the techniques described herein for using a thermoformable layer to release a resonator can also save vertical space as compared to the space required for conventional techniques (eg, etching undercut techniques), which may be, for example, using stacked IC devices or Important considerations in a solution that otherwise takes into account the vertical footprint of the IC device. Still further, the techniques described herein for using a thermoformable layer to release a resonator can reduce the process for fabricating a resonator device (eg, relative to a program included in an etch undercut technique), thereby, for example, saving processing time. And cost. In some embodiments, the highest temperature applied to the IC structure to shrink/shrink the thermoformable layer may be limited based on heat applied during back end or back end (BEOL) processing, where the thermal margin may be, for example, less than 500, 450 Or 400 degrees Celsius. Thus, in some embodiments, the material and/or thickness of the thermoformable film can be adjusted based on those BEOL limitations and/or any other maximum temperature limitations that may be present.

Using the techniques and structures provided herein can be detected using tools such as electron microscopy, including scanning/transmission electron microscopy (SEM/TEM), scanning transmission electron microscopy (STEM), nanobeam electron diffraction (NBD or NBED), and Reflected electron microscopy (REM); composition mapping; X-ray crystallography or diffraction (XRD); energy dispersive X-ray spectroscopy (EDS); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe Imaging or tomography; local electrode atom probe (LEAP) technique; 3D tomography; or high-resolution physical or chemical analysis to enumerate some suitable paradigm analysis tools. In particular, in some embodiments, such a tool may indicate an integrated circuit comprising various thermoformable films or layers between a resonator and a substrate as described herein. Moreover, in some such embodiments, an air cavity may be located between the thermoformable layer and the resonator to allow the resonator to vibrate/oscillate/resonate into the air cavity space. Still further, in some embodiments, the thermoformable layer can be detected based on, for example, a material that is different from the adjacent isolation material. In some embodiments, as will be apparent from the present invention, an air cavity formed by heat treating a thermoformable layer can have a unique shape and/or size (eg, compared to an air cavity formed using conventional techniques). In some embodiments, the techniques may be based on the lack of access trenches (eg, to facilitate conventional etch undercut release etch), which would otherwise be detected adjacent to each resonator device and will be visible in the structure. In some embodiments, the techniques and IC structures described herein can be detected based on the benefits from their use, such as benefiting from the use of a thermoformable layer (eg, relative to the use of an etch undercut technique). The reduced IC footprint/increased density is just a few example benefits. Many configurations and variations will be apparent to the invention.

 Method and architecture  

1 shows a method 100 of forming a resonator employing a thermoformable layer in accordance with some embodiments of the present invention. 2A-E show an example integrated circuit structure (IC) formed when the method 100 of FIG. 1 is implemented, in accordance with some embodiments of the present invention. Figures 2B' and 2C' show enlarged portions of Figures 2B and 2C, respectively, in accordance with some embodiments to illustrate an exemplary optional adhesion increase/decrease technique that may be employed. 2E' shows an example structure of FIG. 2E, including example variations that may occur in an IC structure, and also shows that if a conventional etch undercut technique is used to release the access trench that would exist for the resonator, it is shown in accordance with some embodiments. Imaginary location. Please note that Figures 2A-E are all cross-sectional IC views intended to show the layers and features formed. Recall that in some embodiments, as can be understood based on the present invention, a resonator is formed over the thermoformable layer and a heat treatment is applied to the IC structure (and, therefore, the thermoformable layer) to reduce thermoformability The volume of the layer is such that an air cavity to which the resonator can vibrate/oscillate/resonate (or otherwise move) is formed to cause efficient operation of the resonator. As can be appreciated based on the present disclosure, the techniques described herein can be used to form resonators that include a variety of geometries and configurations. In some embodiments, a resonator formed using the techniques described herein can be included in an RF device, such as an RF filter, and the RF device can be used in a variety of applications, such as, for example, in RF front end applications. . In some embodiments, the technique can be used to facilitate devices of different sizes, such as IC devices having critical dimensions in the nanometer (nm) range and/or in the micrometer (um) range (eg, formed at 22, 14, 10, 7, 5 or 3 nm or other process nodes).

According to an embodiment, the method 100 of FIG. 1 includes forming 102 an isolation layer on a substrate and patterning the trenches in the isolation layer. In this exemplary embodiment, substrate 200 and patterned isolation layer 210 are shown in the resulting IC structure of the example of FIG. 2A. In some embodiments, the substrate 200 may comprise: a body substrate comprising a Group IV semiconductor material such as germanium (Si), germanium (Ge), germanium (SiGe), or germanium carbide (SiC) and/or at least one III a Group V semiconductor material and/or sapphire and/or any other suitable material that will be apparent to the present invention; an X(XOI) structure on insulator, where X is one of the above materials (eg, Group IV and/or III-V) Family and/or sapphire), and the insulator material is an oxide material or a dielectric material or some other electrically insulating material; or the top layer comprises one of the above materials (for example, Group IV and / or III-V and / or sapphire) Some other suitable multilayer structures. As used herein, a "Group IV semiconductor material" (or "Group IV material", or usually "IV") comprises at least one Group IV element (eg, lanthanum, cerium, carbon, tin, lead) such as Si, Ge, SiGe or SiC, etc. As used herein, "III-V semiconductor material" (or "III-V material", or usually "III-V") comprises at least one group III element (eg, aluminum, gallium, indium, boron, germanium) and at least A group V element (such as nitrogen, phosphorus, arsenic, antimony, tellurium) such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium phosphide (GaP), gallium antimonide (GaSb), and indium phosphide ( InP) and so on. Note that, for example, Group III may also be referred to as Boron or IUPAC Group 13, Group IV may also be referred to as Carbon Group or IUPAC Group 14, and Group V may also be referred to as Nitrogen or IUPAC Group 15.

In some embodiments, as will be apparent from the present invention, substrate 200 can comprise a surface crystalline orientation as described by the Miller Index of <100>, <110>, or <111>. Although the substrate 200 is shown to have a thickness relatively similar to the isolation layer, in some cases, the substrate 200 may have a significantly larger relative thickness (dimension in the Y-axis direction), such as a thickness in the range of 50 to 950 microns, For example, or any other suitable thickness that will be apparent from the present invention. In embodiments where the substrate 200 is not a base layer in which the IC is being formed (eg, if it is a dummy substrate for auxiliary resonator fabrication), it may have a relatively smaller base die/wafer than it is formed thereon The thickness of the die/wafer may have a thickness (e.g., 50 to 950 microns) as described in the previous sentence. For example, where the substrate 200 is a top layer formed on a substrate body wafer (eg, a substrate body 矽 substrate body), such a substrate layer may have a thickness, for example, in the range of 50 nm to 2 microns, or will be apparent to the present invention Any other suitable thickness. In some embodiments, substrate 200 can be used with one or more other IC devices, such as various diodes (eg, light emitting diodes (LEDs) or laser diodes), various transistors (eg, MOSFETs or TFET), various capacitors (eg, MOSCAP), various microelectromechanical systems (MEMS), various nanoelectromechanical systems (NEMS), various sensors, various RF devices, and/or any other suitable semiconductor or IC device, Depending on the end use or target application. Thus, in some embodiments, as will be apparent from the present disclosure, the structures described herein can be included in a system single-chip (SoC) application.

In some embodiments, the isolation layer 210 can be formed using any suitable technique. For example, the material of the isolation layer 210 may have been deposited using any suitable procedure, which may include metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), atomic layer deposition ( ALD), physical vapor deposition (PVD) and/or any other suitable procedure that will be apparent to the present invention. The isolation layer 210 can then be patterned using any suitable lithography and etching process, such as forming trenches 211 in the isolation layer. In some embodiments, for example, the isolation layer 210 can comprise any suitable material, such as a dielectric, an oxide (e.g., hafnium oxide), a nitride (e.g., tantalum nitride), and/or an electrically insulating material. In some embodiments, the isolation layer 210 can comprise any suitable thickness (dimension in the Y-axis direction), such as a thickness in the range of 10 nm to 2 microns (eg, 20 to 200 nm) or some that will be apparent to the present invention. Other suitable thicknesses. As can be appreciated based on the present invention, the thickness of the isolation layer 210 can be selected such that a desired thickness of, for example, a subsequently depositable thermoformable layer can be formed in the trench 211. While the isolation layer trench 211 extends completely through the isolation layer 210 and down to the substrate 200, in other embodiments where that is not the case, for example, at least a portion of the isolation layer 210 may remain at the bottom of the trench 211. Moreover, in some embodiments, as shown in FIG. 2A, the isolation layer 210 can be formed in the first example such that no patterning process is required (eg, using a hard mask where the trench 211 is located, The hard mask is then removed). Still further, in some embodiments, the isolation layer 210 may not be patterned such that subsequent processing is formed on the isolation layer 210. Still further, in some embodiments, the isolation layer 210 need not be present. However, in embodiments in which the isolation layer 210 is present, for example, it may be present to assist in isolating the subsequently formed resonator device from adjacent IC devices.

According to an embodiment, the method 100 of FIG. 1 continues by forming 104 the thermoformable layer 220 in the isolation layer trench 211, thereby forming the example resulting IC structure of FIG. 2B. In some embodiments, the thermoformable layer 220 can be formed using any suitable technique, such as depositing a material of the thermoformable layer 220 in the trench 211 (eg, by MOCVD, MBE, CVD, ALD, PVD), And the planarization/grinding process is selectively performed to form, for example, the example structure of FIG. 2B. In some embodiments, the material of the thermoformable layer 220 may be grown only or primarily on the substrate 200 such that it is not formed on the material of the isolation layer 210 or minimally on the isolation layer 210, or at a low quality The way is formed such that it can be easily removed (for example, by cleaning/grinding). Recall that in some embodiments, isolation layer 210 need not be present. In some such embodiments, the thermoformable layer 220 can also function as a barrier layer depending on the material of the layer 220. Moreover, in some such embodiments, the heat treatment can be directed to the position of the resonator such that when heated, the thermoformable layer is only (or primarily) reduced in volume below the resonator to form an air cavity of the resonator, but The volume of the thermoformable layer at other locations is not reduced (or the volume is minimally reduced) so that, for example, it can still provide support for the resonator device.

In some embodiments, for example, when an elevated temperature (heat) is applied to the material, the thermoformable layer 220 can comprise any suitable material, such as a material that shrinks or shrinks (or otherwise reduces the volume). In some embodiments, the thermoformable layer 220 can comprise a thermoplastic material that typically comprises a polymer (relative to a thermoset material) that becomes plastic at a particular temperature and that returns to a solid state upon cooling below a certain temperature. For example, exemplary thermoplastic materials include, but are not limited to, polypropylene (PP), polyester fibers, polyethylene (PE), poly(methyl methacrylate) (PMMA) (eg, acrylic acid), acrylonitrile-butyl Alkene-styrene (ABS), polyamine (for example, nylon), polylactic acid (PLA), polycarbonate (PC), polyether oxime (PES), polyetheretherketone (PEEK), polyether quinone (PEI), polyphenylene oxide (PPO), polyphenylene sulfide (PPS), polystyrene (PS), polyvinyl chloride (PVC), and polytetrafluoroethylene (PTFE) to provide some examples. In some embodiments, the thermoformable layer 220 can comprise a porous material, such as a porous dielectric material (eg, a porous oxide or nitride) having a range of 5% to 90% (eg, 10% to 50%) The amount within or some other suitable amount of porosity (or void ratio) that will be apparent to the present invention. In some such embodiments, the presence of holes in the material of the thermoformable layer 220 that may be introduced or otherwise formed using any suitable technique may help to bring the thermoformable layer 220 to an elevated temperature in response to the application (heat ) and reduce the volume. Moreover, in some such embodiments, the porosity may be introduced only or may be present in a higher percentage of a portion of the thermoformable layer 220, such as at a portion near the resonator (eg, at the top of the layer or The upper portion, for example, helps to ensure the subsequent formation of an air cavity formed at this location. Thus, for example, in such embodiments employing a porous material, the void fraction of the material used for the thermoformable layer 220 can comprise a percent layer of voids throughout the material.

In some embodiments, the thermoformable layer 220 can comprise a material having a negative coefficient of thermal expansion (CTE) that is a physical chemistry that causes the material to shrink in response to increased temperature (thermal) rather than expanding (which is more common for materials). nature. In some such embodiments, for example, a negative CTE can comprise a linear CTE value of less than 0 ppm/° C. (eg, at about 20 ° C, wherein about 20 ° C includes from 5 ° C plus or minus 5 ° C or 15-25 ° C). For example, exemplary negative CTE materials include, but are not limited to, tantalum tungsten, bismuth molybdate, zirconium tungstate (or zirconium tungstate), zirconium molybdate, and zirconium vanadate, to name a few. In embodiments where the negative CTE material is included in the thermoformable layer 220, the entire IC structure can be fabricated in a low temperature environment (eg, relative to the average room temperature and/or operating temperature of the resonator device) such that when the IC structure Subsequent to being brought to room temperature (eg, about 21 degrees Celsius) and/or the operating temperature of the resonator device, the material of the negative CTE will shrink/shrink (or otherwise reduce the volume) to form a gas below the resonator. The cavity, as can be understood based on the present invention. Thus, in some such embodiments, for example, temperature processing (described herein with reference to block 110 of FIG. 1) may include fabricating the device in an environment that is cooler than normal. Note that in some embodiments, for example, the thermoformable layer 220 can comprise one or more of the materials/characteristics described above, such as comprising a porous thermoplastic material or a porous negative CTE material. Generally, according to an embodiment, the thermoformable layer 220 can comprise any suitable material that can be heat treated to reduce the volume of the material. In some embodiments, for example, the thermoformable layer 220 can have a multilayer structure comprising at least two layers of material. For example, in some such embodiments, for example, the thermoformable layer 220 can comprise an upper material sub-layer (in response to heat treatment) that is reduced in volume or amount at a higher rate or amount than the lower sub-layer of material to assist in the layer 220 and An air cavity is formed between the overlying resonators. In some embodiments, for example, the thermoformable layer 220 can comprise a graded (eg, increased and/or decreased) concentration of at least one material throughout at least a portion of the layer. For example, in some such embodiments, one or more materials may be layered throughout the thermoformable layer 220 to reduce adhesion between the layer 220 and the overlying resonator and/or to increase adhesion elsewhere, such as It helps to form an air cavity between layer 220 and the overlying resonator.

In some embodiments, the thermoformable layer 220 can comprise any suitable thickness (dimension in the Y-axis direction), such as a thickness in the range of 10 nm to 2 microns (eg, 20 to 200 nm), or will be in accordance with the present invention. Any other suitable thickness is evident. In some embodiments, for example, the thickness of the thermoformable layer 220 can be based on the material contained in the thermoformable layer 220, the desired height/size of the air cavity to be formed, the temperature treatment used to form the air cavity, and the use Any adhesion increase/decrease technique, and/or a decrease in the volume percentage of the material contained in the thermoformable layer 220 exhibited when the temperature treatment is applied is selected. For example, if it is desired to have an air cavity of at least 10 nm size between the thermoformable layer 220 and the cover resonator, and the material for the thermoformable layer is reduced by 10% at a temperature of 400 degrees Celsius, then the thermoformable layer The thickness of 220 can be chosen to be at least 100 nm to meet the required 10 nm. However, in the case of this example, the thickness may be chosen to be relatively thick to address the inability to obtain 400 degrees Celsius due to thermal margin limitations due to, for example, incomplete volume reduction occurring between the thermoformable layer 220 and the resonator. The associated error caused by the temperature, and/or any other suitable reason. In some embodiments, as can be appreciated based on the present invention, thermoformable based on a configuration that can form thermal layer 220 (eg, such as its thickness and/or material), temperature processing, and/or other conditions for the technology Layer 220 may be capable of reducing the volume (eg, shrinking or shrinking) by a certain percentage (eg, a percentage in the range of 1% to 25%), for example, or some other suitable percentage volume reduction.

According to an embodiment, the method 100 of FIG. 1 optionally continues with performing 106 an increase and/or decrease technique regarding adhesion of the thermoformable layer 220. In some embodiments, the adhesion increase/decrease technique 106 can be performed to help create an air cavity between the resonator and the substrate, and/or to help, for example, form an air cavity at a desired location. For example, in some embodiments, it may be desirable to form an air cavity between the thermoformable layer 220 and the overlying resonator. In some such embodiments, the adhesion between the thermoformable layer 220 and the bottom electrode of the resonator can be reduced and/or by adding adhesion elsewhere (eg, in the thermoformable layer 220 and substrate) Achieved between 200 and one or both of the isolation layers 210). As can be understood in accordance with the present invention, by reducing the adhesion between the thermoformable layer 220 and the overlying resonator (e.g., overlying the bottom electrode), the thermoformable layer 220 will be lowered in the thermoformable layer 220 and The volume formed between the bottom electrodes 232 (in response to the heat treatment described herein) increases the likelihood of air cavity formation. In other words, in some embodiments, techniques can be employed to reduce the adhesion at the interface between the thermoformable layer 220 and the overlying bottom electrode. As can also be appreciated, by increasing the thermoformable layer 220 and layer 220 not (or will not) approach the bottom electrode (in this example embodiment, for example, the left and right sides, which are near or closest to isolation) Layer 210, as well as the bottom side, is the adhesion between one or more sides of the substrate 200), as the thermoformable layer 220 reduces the volume that will be formed at those locations (in response to the heat treatment described herein) ), which reduces the possibility of air cavity formation and thus increases the likelihood that an air cavity will be formed at the thermoformable layer-bottom electrode interface. In other words, in some embodiments, techniques can be employed to increase the adhesion at the interface between the thermoformable layer 220 and one or more of the adjacent portions of the substrate 200 and the isolation layer 210. For example, as will be described in more detail below, the increase/decrease in adhesion can be accomplished using any suitable technique, such as by surface treatment, intermediate layers, configuration selection, and/or material selection.

In embodiments where the adhesion is between the thermoformable layer 220 and the substrate 200 and/or between one or both portions of the thermoformable layer 220 and the adjacent isolation layer 210 (eg, as in Figure 2B) As shown, portions of the isolation layer 210 to the left and right sides of the thermoformable layer 220, such increased adhesion can be achieved using a variety of suitable techniques. For example, in some embodiments, prior to forming the thermoformable layer 220, a surface treatment can be applied to the substrate 200 and/or the isolation layer 210 in the structure of FIG. 2A, wherein such surface treatment is relative to not performing surface treatment, The adhesion of one or more of these locations is increased. Moreover, in some embodiments, the material of the thermoformable layer 220 and the substrate 200 and/or the material of the thermoformable layer 220 and the isolation layer 210 may be selected such that one or both of the groups of materials have a relatively high relative to each other The degree of adhesion. Still further, in some embodiments, the surface area of the interface between the thermoformable layer 220 and one or both of the substrate 200 and the isolation layer 210 may be increased to increase one or more of the interfaces. Adhesiveness. For example, in some such embodiments, the upper/exposed surface of the substrate 200 in FIG. 2A can include a texture (eg, a depression) that increases the surface area between the substrate 200 and the thermoformable layer 220 as it is formed on the substrate 200. , curve, groove). As can be appreciated based on the present invention, this relative increase in surface area can increase the energy required to break the bond at the interface, thereby increasing the bond at the interface. In some embodiments, one or more adhesion enhancing layers can be formed between the thermoformable layer 220 and the substrate 200 and/or between the one or both portions of the thermoformable layer 220 and the barrier layer 210. For example, FIG. 2B' is an enlarged portion of FIG. 2B, and as shown, an alternative structure including an adhesion-increasing layer 212 formed between the thermoformable layer 220 and the right portion of the substrate 200 and the isolation layer 210 is shown. In some embodiments, such adhesion enhancing layer 212 can comprise any suitable material, such as, for example, any suitable adhesive, epoxy, adhesive, or glue.

In embodiments where the adhesion between the thermoformable layer 220 and the overlying resonator is reduced (e.g., the overlying bottom electrode layer 232 shown in Figure 2C), such reduced adhesion can be achieved in a variety of suitable manners. achieve. For example, in some embodiments, a surface treatment can be applied to the thermoformable layer 220 prior to forming the overlying bottom electrode 232, wherein such surface treatment reduces adhesion at locations where surface treatment is not performed. Moreover, in some embodiments, the materials of the thermoformable layer 220 and the bottom electrode 232 can be selected such that one or both of the sets of materials have a relatively low degree of adhesion to each other. For example, in some embodiments, the bottom electrode can comprise a stabilizing material (eg, having a relatively high tensile strength, melting point, and/or hardness), such as tungsten (W) or graphene, to provide just a few examples. Still further, in some embodiments, the surface area at the interface between the thermoformable layer 220 and the bottom electrode 232 can be reduced (eg, relative to all possible surface areas), for example, by not being in a thermoformable layer The bottom electrode 232 is formed as a whole (as in the case shown in Fig. 2C). In some embodiments, one or more layers of reduced adhesion may be formed between the thermoformable layer 220 and the bottom electrode 232. For example, Fig. 2C' is an enlarged portion of Fig. 2C, and as shown, an alternative structure including an adhesion reducing layer 214 formed between the thermoformable layer 220 and the bottom electrode 232 is shown. In some embodiments, such an adhesion reducing layer 214 can comprise any suitable material, such as a material formed by an ALD process (eg, to increase the surface roughness of the layer) or a material that contains defects (or It is easier to break the bond in other ways). Recall that in some embodiments, various implementation 106 adhesion enhancement and/or reduction techniques described herein are not required. However, in some cases, as may be understood based on the present invention, the techniques used to form the structure of FIG. 2C may essentially include the effect of increased/decreased adhesion, such as due to materials used for different features.

According to an embodiment, the method 100 of FIG. 1 continues by forming a resonator layer on the thermoformable layer 220 to form the resulting IC structure of FIG. 2C. As shown in FIG. 2C, in this exemplary embodiment, the resonator layer includes a bottom electrode layer 232, a piezoelectric layer 234, and a top electrode layer 236. As also shown, the bottom electrode 232 extends through the layer of resonator stacks (in the case of this example, to the left or negative X-axis direction) such that contact to the bottom electrode 232 can be accomplished, which is done using interconnect 233 . In some embodiments, bottom electrode 232, piezoelectric layer 234, and top electrode 236 can be formed using any suitable technique, such as using any of the foregoing procedures to deposit the layers (eg, MOCVD, MBE, CVD, ALD, PVD), and/or any other suitable procedure that will be apparent to the present invention. In some embodiments, the interlayer dielectric (ILD) layer 240 can be formed before or after forming the layers 232, 234, 236 of the resonator stack, wherein such ILD layer 240 comprises any suitable material, such as, for example, a dielectric , oxides, nitrides and/or electrically insulating materials. Note that the ILD layer 240 is shown as a continuous feature in Figure 2C; however, the features of the ILD 240 may include a multi-layer structure that utilizes different layers of resonator stacking. For example, according to an example embodiment, the right ILD 240 portion may actually be three different layers, and the three layers may be formed before or after forming a layer of the resonator stack, such as forming the first ILD layer 240, Patterning, forming bottom electrode layer 232, forming second ILD layer 240, patterning it, and forming piezoelectric layer 234 and adjacent portions of interconnect 233, then forming a third ILD layer 240, patterning it, A top electrode layer 236 is formed, as well as adjacent portions of interconnect 233. However, in other embodiments, according to another example embodiment, the layers 232, 234, 236 of the resonator stack may have been blanket deposited on the underlying thermoformable layer 220 (and the isolation layer 210), followed by patterning To form the stack shown, the ILD material 240 is subsequently deposited and the IC structure 233 is formed. A variety of different processing schemes for forming a resonator layer will be apparent to the present invention.

In some embodiments, bottom electrode 232 and top electrode 236 can comprise any suitable material that will be apparent to the present invention. For example, in some embodiments, one or both of the electrodes 232, 236 can comprise a metal or metal alloy material (or some other suitable electrically conductive material), such as tungsten (W), molybdenum (Mo), or tantalum (Ta). Only a few examples are provided. In some embodiments, one or both of the electrodes 232, 236 can have a multilayer structure comprising at least two layers of material. For example, in some embodiments, one or both of the electrodes 232, 236 can comprise multiple layers of alternating metal (or metal alloy) material and insulating material, such as in a metal/insulator/metal (MIM) configuration or as a metal/insulator/ Metal/Insulator/Metal (MIMIM) configuration, just to provide some examples. For example, such a multilayer MIM or MIMIM electrode configuration can be used to act as a reflector for sound waves. In other embodiments in which one or both of the electrodes 232, 236 comprise a multilayer structure, the multilayer structure can comprise a heterojunction of a III-V semiconductor material to establish a two-dimensional electron gas (2DEG) configuration. For example, such a configuration may include a gallium nitride (GaN) base layer having an overlying polarized charge sensing layer (or multilayer structure) comprising a material having a larger band gap than GaN, such as, for example, nitridation Aluminum (AlN), indium aluminum nitride (InAlN), aluminum gallium nitride (AlGaN) material, and/or indium aluminum gallium nitride (InAlGaN). In some embodiments, for example, one or both of the electrodes 232, 236 can include a gradual concentration (eg, increase and/or decrease) of at least one material throughout at least a portion of the feature. In some embodiments, bottom electrode 232 and top electrode 236 can have any suitable thickness (dimension in the Y-axis direction), such as a thickness in the range of 0.01 to 2 microns (eg, 0.05 to 1 micron), or Any other suitable thickness that is apparent to the present invention. In some embodiments, interconnect 233 can comprise any suitable material, such as any suitable conductive material, such as copper (Cu), titanium (Ti), gold (Au), or tungsten (W), to name a few.

In some embodiments, piezoelectric layer 234 can comprise any suitable material that will be apparent to the present invention. For example, in some embodiments, the piezoelectric layer can comprise any suitable piezoelectric material, such as, for example, aluminum nitride (AlN), zinc oxide (ZnO), gallium nitride (GaN), and/or indium nitride (InN). ). Generally, any semiconductor crystal having non-central symmetry may be included in the piezoelectric material, such as III-V and II-VI semiconductor materials. However, other suitable piezoelectric materials may include quartz (SiO2), aluminophosphate (AlPO4), gallium orthophosphate (GaPO4), barium titanic acid (BaTiO3), lead titanic acid (PbTiO3), lead zirconium titanate (PZT). Lithium niobate (LiNbO3), lithium niobate (LiTaO3), potassium niobate (KNbO3), sodium tungstate (Na2WO3) and polyvinylidene fluoride (PVDF) provide only an additional example. Please note that the use of "III-V semiconductor materials" (or "III-V materials" or, generally, "III-V") includes at least one Group III element (eg, aluminum, gallium, indium, boron). , 铊) and at least one group V element (eg, nitrogen, phosphorus, arsenic, antimony, antimony), such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium phosphide (GaP), gallium antimonide ( GaSb) and indium phosphide (InP) and the like. It should also be noted that the use of "II-VI semiconductor materials" (or "II-VI materials" or generally, "II-VI") includes at least one Group II element (eg, zinc, cadmium). And at least one group VI element (for example, oxygen, sulfur, selenium) such as cadmium sulfide (CdS), zinc oxide (ZnO), and zinc sulfide (ZnS). Note that, for example, Group II can also be referred to as Zinc or IUPAC Group 12, Group III can also be referred to as Boron or IUPAC Group 13, and Group V can also be referred to as Nitrogen or IUPAC Group 15, The VI family can also be referred to as oxygen (or chalcogen) or IUPAC group 16. In some embodiments, for example, piezoelectric layer 234 can have a multilayer structure comprising at least two layers of material. In some embodiments, for example, piezoelectric layer 234 can comprise a graded (eg, increased and/or decreased) concentration of at least one material throughout at least a portion of the layer. In some embodiments, piezoelectric layer 234 can comprise any suitable thickness (dimension in the Y-axis direction) such that the thickness is in the range of 0.05 to 4 microns (eg, 0.1 to 2 microns), or will be apparent to the present invention. Any other suitable thickness.

According to an embodiment, as shown in FIG. 2D, the method 100 of FIG. 1 continues with applying 110 a temperature treatment to reduce the volume of the thermoformable layer 220, thereby forming the example resulting IC structure of FIG. 2E including the gas cavity 250. As shown in FIG. 2D, in this exemplary embodiment, temperature processing 110 is represented as ΔT to indicate that a change in temperature is applied to the structure of FIG. 2C. In some embodiments, an increase in temperature (heat) is applied to the structure of the IC, specifically increasing the temperature of the thermoformable layer 220. In some such embodiments, the increase in temperature (heat) can be applied using any suitable technique, such as via one or more annealing procedures, providing only an example. In embodiments where an increased temperature is applied, the increase may be at least an increase of 50, 100, 200, 300, 400 or 500 degrees Celsius, or some other suitable minimum threshold increase as will be apparent from the present invention. In some embodiments, the temperature applied to the IC structure such that the thermoformable layer 220 is reduced in volume may be in the range of 20 to 600 degrees Celsius, or any other suitable temperature that will be apparent to the present invention. For example, recall that in embodiments where the thermoformable layer 220 comprises a negative CTE material, the IC structure of FIG. 2C (or at least the thermoformable layer 220) can be formed under low temperature conditions (eg, less than 10 degrees Celsius) such that when When the IC structure is exposed to a higher temperature (eg, a temperature range from room temperature to operating temperature), the negative CTE material can be reduced in volume to form the air cavity 250. However, in some embodiments, for example, if the thermoformable layer 220 comprises an embodiment of a thermoplastic material, a single heat treatment (eg, thermal application in the range of 100 to 600 degrees Celsius) may cause the thermoformable layer 220 to The volume is reduced in a permanent manner such that, for example, when the IC structure is present at any temperature, the air cavity 250 is still present.

In some embodiments, the highest temperature that can be applied during the process 110 of the method 100 can be limited in some manner. For example, in some embodiments, temperature processing 110 may be applied during a phase that is considered to be a back end or back end (BEOL) process, where the allowable thermal margin is limited (eg, by the melting temperature of the material of interconnect 233) limit). In some such embodiments, temperature processing 110 will be limited by thermal margin (eg, to not affect other features of the IC structure), which may allow for a maximum temperature of, for example, 500, 450, 400, 350, or 300 degrees Celsius. Thus, in some embodiments, such thermal margins can help determine the material, thickness, and other characteristics of the thermoformable layer 220 such that the desired air cavity 250 can be effectively formed during the temperature processing program 110. Please note that in some embodiments, temperature processing 110 may be performed by one or more other conventional programs included in the IC manufacturing process flow. For example, in some such embodiments, the anneal performed after the IC structure of FIG. 2C has been formed, such as forming a gas anneal (which can be used to fix the gate dielectric of the transistor contained on the IC) The purpose of the temperature processing program is to help reduce the volume of the thermoformable layer 220 and form the air cavity 250 such that, for example, the temperature processing program that only targets the air cavity 250 does not need to be performed.

In some embodiments, the applied position of the temperature treatment 110 can be selected to enhance the program and/or increase the likelihood that the air cavity 250 will be formed as desired. For example, such positioning may increase the likelihood that the air cavity 250 is formed between the thermoformable layer 220 and the bottom electrode 232 relative to the other side of the layer 220. It is noted that although some locations of such an air cavity 250 may be desirable in some embodiments (ie, between features 220 and 232), according to some embodiments, if the volume of the thermoformable layer 220 is reduced, The air cavity is formed elsewhere (eg, such as if the air cavity 250 is formed below the layer 220), then the resonator device can still operate. However, in some embodiments, heat may be applied to the IC structure specifically shown in FIG. 2D such that heat is applied to the top of the IC structure (rather than the bottom) and is thermoformable at a target using a laser annealing procedure. The location of layer 220, for example, attempts to increase the likelihood that air cavity 250 will form between features 220 and 232. In some embodiments, other techniques may include applying a relatively lower temperature to the bottom of the IC structure (eg, by cold treatment) to reduce the likelihood that, for example, the thermoformable layer 220 will reduce the volume near the bottom side of the layer. (ie, in the vicinity of the interface with the substrate 200).

In some embodiments, for example, the thermoformable layer 220 can reduce the volume (eg, 5% to 20%) in a range of 1% to 50%, or some other suitable percentage that will be apparent to the present invention. An air cavity 250 is formed. As can be understood in accordance with the present invention, the isolation material used in conventional etch undercut techniques, which will be located in the thermoformable layer 220 shown in FIG. 2D, will not and the thermoformable layer 220 that will respond to the temperature treatment 110. The material is effectively reduced in volume in the same manner, as such conventional insulation materials may, for example, comprise hafnium oxide or tantalum nitride. These conventional isolation materials can be included in the isolation layer 210 as can also be understood based on the present invention. Regardless, in some embodiments, the barrier layer 210 and the thermoformable layer 220 comprise different materials such that the thermoformable layer 220 can be more easily detected (eg, due to material breakage between layers 210 and 220). In some embodiments, the air cavity may result in a maximum separation of the dimension D between the thermoformable layer 220 and the bottom electrode 232 as shown in Figure 2E. In some such embodiments, the maximum separation dimension D can be at least 2, 3, 4, 5, 6, 7, 8, 9, or 10 nm, or some other suitable threshold amount that enables the resonator to operate effectively. Note that while the air cavity in the configuration of FIG. 2E is shown only between the thermoformable layer 220 and the bottom electrode 232, in some embodiments, for example, the thermoformable layer 220 can be lowered in any suitable manner. The volume is such that one or more air pockets can be formed around other locations of the thermoformable layer 220. Moreover, recall that, according to some embodiments, the air cavity does not even need to be formed between the thermoformable layer 220 and the bottom electrode 232 for the resonator to operate effectively.

Figure 2E' shows the example IC structure of Figure 2E with multiple variations, in accordance with some embodiments. One such variation is the shape and size of the layers in the resonator stack. Specifically, the bottom electrode 232' does not extend farther in the positive X-axis direction than in the structure of FIG. 2E (eg, the thermoformable layer 220) It does not extend as much as the bottom electrode 232). As shown, another variation for the resonator stack is that the piezoelectric layer 234' extends through the bottom electrode 232' (in the positive X-axis direction) and on the bottom electrode 232' so that it is partially formed at Thermoformed layer 220' and isolation layer 210. Another variation shown in Figure 2E' is the shape of the air chamber 250' compared to the air chamber 250 of Figure 2E. As shown, the air chamber 250' has a generally curved concave shape rather than the rectangular and flat shape of the air chamber 250. In other words, in the configuration of Figure 2E, the thermoformable layer 220 reduces volume from top to bottom in a substantially homogeneous manner, while in the configuration of Figure 2E', the thermoformable layer 220' reduces volume in a heterogeneous manner, It shrinks more in the middle of layer 220' than on the outside. Such a shape may be caused, for example, by a relatively large bond between the thermoformable layer 220 and the barrier layer 210. However, in this exemplary embodiment, the resonator can still vibrate/oscillate/resonate to the air chamber 250&apos; and thereby operate effectively. As can be understood based on the present invention, the formed air cavity can comprise a variety of different shapes and/or sizes and still allow the overlying resonator to operate effectively.

For example, Figure 2E' also includes a dashed line showing the imaginary location of the access trench 260 that would be present if a conventional etch undercut process was used to form the plenum 250'. As shown, the imaginary access trench 260 includes a width W (dimension in the X-axis direction) that would need to be considered when considering the overall size of the resonator device, because if conventional etch undercut techniques are employed, the Each resonator device will require such an access trench to perform a release etch for forming an air cavity below the resonator. However, the use of thermoformable layer 220 removes this need for such access trenches 260 because the underlying air cavity 250/250' may not have an area under the resonator stack that physically accesses the layer (eg, Formed under the bottom electrode 232/232'). Thus, as can be understood based on the present invention, these techniques allow the air cavity 250 to be completely enclosed (compared to conventional etch undercut techniques employing access grooves). Such a closed system can provide advantages such as, for example, reducing the likelihood of a resonator device collapse during formation and/or use.

According to an embodiment, the method 100 of FIG. 1 continues to complete 112 IC processing, if desired. Such additional processing to complete the IC may include back end or back end (BEOL) processing to, for example, form one or more metallization layers and/or interconnect the resonator devices. Any other suitable processing that will be apparent to the present invention can be performed, for example, such as forming an air cavity over the resonator device. Please note that the procedures 102-112 of method 100 are shown in a particular order in FIG. 1 for ease of illustration. However, one or more of the programs 102-112 may be performed in a different order or may not be executed at all. For example, in some embodiments, block 106 is an optional program that does not need to be executed, but when it is executed, it can be executed, for example, before and/or after block 104. In some cases, the features of the IC structure shown in Figures 2A-E can be illustrated in a manner different from the nomenclature used primarily herein (which has been selected for ease of reference). For example, in some cases, top electrode 232 and bottom electrode 236 can alternatively be considered the first and second electrodes in any order. Moreover, in some cases, piezoelectric layer 234 can be considered an intermediate layer between top and bottom electrodes 232, 236, wherein the intermediate layer comprises a piezoelectric material. Still further, in some cases, the thermoformable layer 220 can also be considered as an intermediate layer between the resonator stack (or one of the layers 232, 234, 236 it includes) and the substrate 200, where The intermediate layer contains a material that reduces volume in response to an increase in temperature. Moreover, in some cases, various included features may be described in any other suitable manner, such as based on their material, characteristics, size, shape, location relative to other features in the IC structure (eg, above, below, Up, above, adjacent, between, near, close, closest, and with respect to one or more features, or any other suitable manner of description that will be apparent to the present invention. Many variations and configurations will be apparent to the invention.

 Sample system  

3 shows a computing system 1000 implemented using integrated circuit structures and/or resonator devices formed using the techniques disclosed herein, in accordance with some embodiments of the present invention. As shown, computing system 1000 houses motherboard 1002. The motherboard 1002 can include multiple components including, but not limited to, a processor 1004 and at least one communication chip 1006. The processor 1004 and the at least one communication chip 1006 can be physically and electrically coupled to the motherboard 1002 or otherwise integrated therein. As will be appreciated, the motherboard 1002 can be, for example, any printed circuit board, whether it be a motherboard, a daughter board mounted on a motherboard, or a unique board of the system 1000 or the like.

Depending on its application, computing system 1000 can include one or more other components that may or may not be physically and electrically coupled to motherboard 1002. These other components may include, but are not limited to, volatile memory (eg, DRAM), non-volatile memory (eg, ROM), graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touch Control screen display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera and mass storage device ( Such as hard disk, compact disc (CD), digital multifunction, compact disc (DVD), etc.). Any of the elements included in computing system 1000 can include one or more integrated circuit structures or devices formed using the disclosed techniques in accordance with example embodiments. In some embodiments, multiple functions may be integrated into one or more wafers (eg, for example, note that communication chip 1006 may be part of processor 1004 or otherwise integrated into processor 1004).

The communication chip 1006 can be used to transfer data to and from the computing system 1000 for wireless communication. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., which may be transmitted by non-solid-state media using modulated electromagnetic radiation. This term does not imply that the associated device does not contain any wires, although in some embodiments they may not. The communication chip 1006 can implement any number of wireless standards or protocols including, but not limited to, Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+ , HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof and any other wireless protocols designated as 3G, 4G, 5G and beyond. Computing system 1000 can include a plurality of communication chips 1006. For example, the first communication chip 1006 can be dedicated to short-range wireless communication, such as Wi-Fi and Bluetooth, and the second communication chip 1006 can be dedicated to long-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev. -DO and others.

Processor 1004 of computing system 1000 includes integrated circuit dies that are packaged within processor 1004. In some embodiments, the integrated circuit die of the processor includes an onboard circuit implemented using one or more integrated circuit structures or devices formed using various disclosed techniques as described herein. The term "processor" may refer to any device that processes, for example, electronic data from a register and/or memory to convert the electronic material into other electronic material that can be stored in a register and/or memory. Or part of the device.

The communication chip 1006 can also include integrated circuit dies that are packaged within the communication chip 1006. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the disclosed techniques as described herein in various manners. As will be appreciated by the present invention, it is noted that multi-standard wireless capabilities can be directly integrated into the processor 1004 (eg, where the functionality of any of the wafers 1006 is integrated into the processor 1004, rather than having a separate communication chip). It is further noted that the processor 1004 can be a chipset having such wireless capabilities. In summary, any number of processors 1004 and/or communication chips 1006 can be used. Likewise, any one wafer or wafer set can have multiple functions integrated therein. In some embodiments, for example, communication chip 1006 can include one or more resonator devices formed using the techniques described herein, wherein such resonator devices can be included in an RF filter, and the RF filter can be It is included in the RF front end of the communication chip.

In various implementations, computing system 1000 can be a laptop, a small notebook, a notebook, a smart phone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, Printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, digital video recorder, or processing material or one formed using various disclosed techniques as described herein Any other electronic device that integrates a circuit structure or device. Please note that reference to a computing system is intended to encompass computing devices, devices, and other structures configured to calculate or process information.

 Further example embodiments  

The following examples pertain to further embodiments in which numerous arrangements and configurations will be apparent.

Example 1 is an integrated circuit (IC) comprising: a substrate; a resonator comprising a first electrode above the substrate, a second electrode between the first electrode and the substrate, and a first intermediate layer Between the first and second electrodes, the first intermediate layer comprising a piezoelectric material; and a second intermediate layer between the second electrode and the substrate, wherein the second intermediate layer comprises An increase in temperature with a material that reduces volume by at least one of a given temperature.

Example 2 includes the subject matter of Example 1, further comprising an isolation layer between the portions of the isolation layer, wherein the isolation layer comprises a different material than the second intermediate layer.

Example 3 includes the subject matter of Example 1 or Example 2, wherein at least one of the first and second electrodes comprises one of a metal and a metal alloy.

Example 4 includes the subject matter of any one of examples 1 to 3, wherein at least one of the first and second electrodes comprises a III-V semiconductor material.

Example 5 includes the subject matter of any one of examples 1 to 4, wherein the piezoelectric material comprises at least one of a III-V semiconductor material and a II-VI semiconductor material.

Example 6 includes the subject matter of any one of examples 1 to 5, wherein the piezoelectric material comprises at least one of aluminum nitride (AlN) and zinc oxide (ZnO).

Example 7 includes the subject matter of any of Examples 1 to 6, wherein the second intermediate layer comprises at least one thermoplastic material.

Example 8 includes the subject matter of any one of Examples 1 to 6, wherein the second intermediate layer comprises at least one material having a negative coefficient of thermal expansion.

Example 9 includes the subject matter of any of Examples 1-8, wherein the given temperature is less than 500 degrees Celsius.

Example 10 includes the subject matter of any of Examples 1 to 9, further comprising an air cavity between the second intermediate layer and the second electrode.

Example 11 includes the subject matter of Example 10, wherein the air cavity has a maximum dimension of at least 5 nanometers between the second intermediate layer and the second electrode.

Example 12 includes the subject matter of any of Examples 10 to 11, wherein the air cavity is completely enclosed.

Example 13 is a radio frequency (RF) filtering device comprising the subject matter of any of Examples 1-12.

Example 14 is a computing system that includes the subject matter of any of Examples 1-13.

Example 15 is an integrated circuit (IC) comprising: a substrate; a resonator comprising a first electrode above the substrate, a second electrode between the first electrode and the substrate, and a first intermediate layer Between the first and second electrodes, the first intermediate layer comprises a piezoelectric material; a second intermediate layer between the second electrode and the substrate; and an air cavity in the second intermediate Between the layer and the second electrode, wherein the air cavity is completely enclosed.

Example 16 includes the subject matter of Example 15, wherein the second intermediate layer comprises a material that reduces volume in response to an increase in temperature and at least one of a given temperature.

Example 17 includes the subject matter of Example 15 or 16, further comprising an isolation layer between the portions of the isolation layer, wherein the isolation layer comprises a different material than the second intermediate layer.

The subject matter of any one of examples 15 to 17, wherein at least one of the first and second electrodes comprises one of a metal and a metal alloy.

The subject matter of any one of examples 15 to 18, wherein at least one of the first and second electrodes comprises a III-V semiconductor material.

Example 20 includes the subject matter of any one of Examples 15 to 19, wherein the piezoelectric material comprises at least one of a Group III-V semiconductor material and a Group II-VI semiconductor material.

The example 21 includes the subject matter of any one of examples 15 to 20, wherein the piezoelectric material comprises at least one of aluminum nitride (AlN) and zinc oxide (ZnO).

Example 22 includes the subject matter of any one of Examples 15 to 21, wherein the second intermediate layer comprises at least one thermoplastic material.

Example 23 includes the subject matter of any one of Examples 15 to 21, wherein the second intermediate layer comprises at least one material having a negative coefficient of thermal expansion.

Example 24 includes the subject matter of any one of Examples 15 to 23, wherein the second intermediate layer comprises a porous material.

Example 25 includes the subject matter of any of Examples 15 to 24, wherein the given temperature is greater than 300 degrees Celsius.

Example 26 includes the subject matter of any one of Examples 15 to 25, wherein the given temperature is less than 400 degrees Celsius.

Example 27 includes the subject matter of Example 26, wherein the air cavity has a maximum dimension of at least 5 nanometers between the second intermediate layer and the second electrode.

Example 28 is a radio frequency (RF) filtering device comprising the subject matter of any of Examples 15-27.

Example 29 is a computing system comprising the subject matter of any of Examples 15-28.

Example 30 is a method of forming an integrated circuit (IC), the method comprising: forming a resonator on a first layer, the resonator comprising an intermediate layer between two electrodes, wherein the intermediate layer comprises a piezoelectric material; Heating is applied to reduce the volume of the first layer and form an air cavity between the first layer and the resonator.

Example 31 includes the subject matter of Example 30, further comprising forming a second layer adjacent to at least one side of the first layer.

Example 32 includes the subject matter of Example 31, wherein the second layer comprises a different material than the first layer.

Example 33 includes the subject matter of any one of examples 30 to 32, wherein applying heat comprises performing an annealing procedure comprising a temperature of at least 200 degrees Celsius.

Example 34 includes the subject matter of any one of examples 30 to 33, wherein applying heat comprises performing an annealing procedure comprising a temperature of less than 500 degrees Celsius.

Example 35 includes the subject matter of any one of examples 30 to 34, wherein applying heat comprises directing the resonator using a laser annealing procedure.

Example 36 includes the subject matter of any one of Examples 30 to 35, wherein the first layer is reduced in volume by at least 10%.

Example 37 includes the subject matter of any one of Examples 30 to 36, wherein the first layer is reduced in volume by at least 20%.

Example 38 includes the subject matter of any one of Examples 30 to 37, wherein the air cavity is completely enclosed.

The example 39 includes the subject matter of any one of examples 30 to 38, further comprising forming the resonator over the first layer at a temperature of less than 20 degrees Celsius.

Example 40 includes the subject matter of any one of Examples 30 to 39, wherein the intermediate layer is formed using an atomic layer deposition (ALD) procedure.

Example 41 includes the subject matter of any one of Examples 30 to 40, wherein the first layer comprises at least one thermoplastic material.

Example 42 includes the subject matter of any one of examples 30 to 41, wherein the first layer comprises at least one material having a negative coefficient of thermal expansion.

The example 43 includes the subject matter of any one of examples 30 to 42, further comprising forming a bond on at least one side of the first layer.

The foregoing exemplary embodiments have been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in accordance with the present invention. It is intended that the scope of the invention not be limited The claims filed in the future may claim the claimed subject matter in various ways, and may generally include one or more limitations of any group as disclosed herein or otherwise indicated.

Claims (25)

 An integrated circuit (IC) comprising: a substrate; a resonator comprising a first electrode above the substrate, a second electrode between the first electrode and the substrate, and a first intermediate layer, Between the first and second electrodes, the first intermediate layer comprises a piezoelectric material; and a second intermediate layer between the second electrode and the substrate, wherein the second intermediate layer comprises an increase in temperature A material that reduces volume with at least one of a given temperature.    The IC of claim 1, further comprising an isolation layer between the portions of the isolation layer, wherein the isolation layer comprises a different material than the second intermediate layer.    The IC of claim 1, wherein at least one of the first and second electrodes comprises one of a metal and a metal alloy.    The IC of claim 1, wherein at least one of the first and second electrodes comprises a III-V semiconductor material.    The IC of claim 1, wherein the piezoelectric material comprises at least one of a III-V semiconductor material and a II-VI semiconductor material.    The IC of claim 1, wherein the piezoelectric material comprises at least one of aluminum nitride (AlN) and zinc oxide (ZnO).    The IC of claim 1, wherein the second intermediate layer comprises at least one thermoplastic material.    The IC of claim 1, wherein the second intermediate layer comprises at least one material having a negative thermal expansion coefficient.    An IC as claimed in claim 1, wherein the given temperature is less than 500 degrees Celsius.    An IC as claimed in claim 1, further comprising an air cavity between the second intermediate layer and the second electrode.    The IC of claim 10, wherein the air cavity has a maximum dimension of at least 5 nanometers between the second intermediate layer and the second electrode.    An IC as claimed in claim 10, wherein the air chamber is completely enclosed.    A radio frequency (RF) filtering device comprising the IC of any one of claims 1 to 12.    A computing system comprising the IC of any one of claims 1 to 12.    An integrated circuit (IC) comprising: a substrate; a resonator comprising a first electrode above the substrate, a second electrode between the first electrode and the substrate, and a first intermediate layer, Between the first and second electrodes, the first intermediate layer comprises a piezoelectric material; a second intermediate layer between the second electrode and the substrate; and an air cavity in the second intermediate layer and the Between the second electrodes, wherein the air chamber is completely enclosed.    The IC of claim 15 wherein the second intermediate layer comprises a material that reduces volume in response to an increase in temperature and at least one of a given temperature.    The IC of claim 15 further comprising an isolation layer between the portions of the isolation layer, wherein the isolation layer comprises a different material than the second intermediate layer.    The IC of any one of claims 15 to 17, wherein the given temperature is greater than 300 degrees Celsius.    The IC of any one of claims 15 to 17, wherein the given temperature is less than 400 degrees Celsius.    A method of forming an integrated circuit (IC), the method comprising: forming a resonator on a first layer, the resonator comprising an intermediate layer between two electrodes, wherein the intermediate layer comprises a piezoelectric material; and applying heat The volume of the first layer is reduced and an air cavity between the first layer and the resonator is formed.    The method of claim 20, further comprising forming a second layer adjacent to at least one side of the first layer.    The method of claim 21, wherein the second layer comprises a different material than the first layer.    The method of any one of claims 20 to 22, wherein applying heat comprises performing an annealing procedure comprising a temperature of at least 200 degrees Celsius.    The method of any one of claims 20 to 22, wherein applying heat comprises performing an annealing procedure comprising a temperature of less than 500 degrees Celsius.    The method of any one of claims 20 to 22, wherein the first layer is reduced in volume by at least 10%.