TW201803117A - High electron mobility transistor and method for manufacturing high electron mobility transistor - Google Patents

Abstract

HEMT (100, 500) comprising a plurality of first individual cells (201) and at least one second individual cell (214, 314, 414), wherein the second individual cell (214, 314, 414) has a first insulation layer (202, 302, 402), which is arranged perpendicular to a substrate front side and extends from the substrate front side right into a two-dimensional electron gas, such that a first individual transistor (204, 304, 404) having a first gate terminal (205, 305, 405) and a second individual transistor (206, 306, 406) having a second gate terminal (207, 307, 407) are produced, wherein the first individual transistor (204, 304, 404) and the second individual transistor (206, 306, 406)are electrically connected in parallel and have a source terminal (108, 208, 308, 408, 508) and a drain terminal (109, 209, 309, 409, 509), characterized in that a potential contact (213, 313, 413) is arranged between the drain terminal (109, 209, 309, 409, 509), and the source terminal (108, 208, 308, 408, 508) in a region of the second individual transistor (206, 306, 406),said potential contact being arranged perpendicular to the substrate front side and extending from the substrate front side right into the two-dimensional electron gas of the second individual transistor (206, 306, 406), such that a first resistance (510) is produced between the drain terminal (109, 209, 309, 409, 509) and the second gate terminal (207, 307, 407) and a second resistance (511) is produced between the second gate terminal (207, 307, 407) and the source terminal (108, 208, 308, 408, 508), wherein a means is provided which electrically connects the potential contact (213, 313, 413) and the second gate terminal(207, 307, 407).

Description

High electron mobility transistor and method for manufacturing high electron mobility transistor

The invention relates to a high electron mobility transistor HEMT and a method for manufacturing a high electron mobility transistor.

A lateral power transistor HEMT based on gallium nitride is not resistant to overvoltage because the dielectric layers (such as buffer layers and shield capacitors) of the HEMT undergo breakdown at a field strength lower than the semiconductor substrate below the HEMT. The transistor did not show burst. Here, the maximum burst energy that the HEMT can safely operate corresponds to the energy that can be stored on the output capacitor at the maximum reverse voltage.

The disadvantage here is that if this maximum reverse voltage is exceeded, irreversible dielectric breakdown occurs and the HEMT is destroyed.

In the case of IGBT-based components, the destruction of the components is also known. In this case, the Zener diode and the burst diode are interconnected to resist overvoltage. However, this approach cannot be implemented for HEMT, because Zener diodes and burst diodes cannot be integrated into HEMT technology. Furthermore, it is disadvantageous here that these diodes are not fast enough because GaN HEMTs have high switching speeds.

Document DE 10 2013 102 457 A1 describes components for overvoltage protection of synthetic semiconductor field effect transistors. The device includes an implanted region disposed in a synthetic semiconductor material. The The implanted region has spatially distributed capture states, which have the effect of making the implanted region conductive under a threshold voltage. Therefore, according to the Frenkel-Pool principle, the implanted region has a conduction mechanism. By implanting impurity atoms, the introduction of high energy states (so-called defects) makes it possible for frequency hopping conduction types. These defects form high energy states that are possible for electrons in the region of the energy band gap of the free state. With frequency hopping conduction, electrons can pass one defect to the next. This corresponds to the current. The high-energy depth of the state is determined by selecting impurity atoms. The field strength that starts with the generation of current in the field effect transistor can be adjusted by means of these states.

The disadvantage here is that a current may pass through the implanted synthetic semiconductor material, making it impossible to achieve the long-term stability of the overvoltage protection device.

The object of the present invention is to provide an over-voltage resistant HEMT with long-term stability.

The high electron mobility transistor includes a plurality of first individual cells and at least one second individual cell, wherein the second individual cell has a first insulating layer. In this case, a different unit should be understood to mean a basic unit with one HEMT having one source terminal, one gate terminal, and one drain terminal. The second insulating layer is configured to be perpendicular to a substrate front side and directly extends from the substrate front side into a two-dimensional electronic gas, so that a first individual transistor having a first gate electrode terminal and a second gate electrode are manufactured. A second individual transistor for the terminal. In this case, the term substrate front side should be understood to mean the side of the substrate on which the contacts of the HEMT are arranged, that is, the gate, the drain, and the source. The first individual transistor and the second individual transistor are electrically connected in parallel and have a source terminal and a drain terminal. In other words, the first individual transistor and the second individual transistor have a common source terminal or source contact and a common drain terminal or sink Pole contact. According to the present invention, a potential contact is disposed between the drain terminal and the source terminal in the region of the second individual transistor. The potential contact extends perpendicular to the front side of the substrate and directly extends from the front side of the substrate into the two-dimensional electron gas of the second individual transistor. This situation means that the potential contact is configured to be perpendicular to the front side of the substrate. Due to the potential contact, a first resistance is formed or generated between the drain terminal and the second gate terminal, and a second resistance is formed or generated between the second gate terminal and the source terminal. resistance. In other words, the potential contact forms a voltage divider between the source terminal and the drain terminal, wherein the voltage divider is electrically connected to the second gate terminal via the potential contact. This situation means providing a means for electrically connecting the potential contact to the second gate terminal.

The advantage here is that the resulting HEMT power transistor is resistant to overvoltage. The gate voltage of the second individual transistor can be adjusted by the voltage divider. If the gate voltage of the second individual transistor exceeds the threshold voltage of the second individual transistor, the second individual transistor is turned on and the overvoltage is conducted away. In addition, the HEMT has long-term stability and overvoltage protection can be easily integrated into the HEMT process.

In another configuration, the component is a gate field plate.

This has the advantage of preventing dynamic Rds from working by reducing the maximum field strength.

In a development, a region of the second gate terminal corresponds to a region of the potential contact. Both the region of the second gate terminal and the region of the potential contact are configured to be parallel to or on the front side of the substrate.

It is advantageous here that the potential contact can be shaped into a larger area. In this case, the potential contact does not affect the two-dimensional electron gas, nor does it affect the drift zone between the drain terminal and the second gate terminal.

In another configuration, an area of the second gate terminal is larger than an area of the potential contact. Both the region of the second gate terminal and the region of the potential contact are configured to be parallel to or on the front side of the substrate.

The advantage here is that the potential contact has a lower impact on the two-dimensional electron gas because the potential contact area is smaller.

In a development, the potential contact is disposed between the drain terminal and the second gate terminal in the region of the second individual transistor.

It is advantageous here that the required total area of the HEMT is reduced.

In another configuration, the potential contact is disposed between the source terminal and the second gate terminal in the region of the second individual transistor.

The advantage here is a reduction in the total area.

In a development, the second individual transistor has a second insulating layer that is configured to be perpendicular to the front side of the substrate and directly extends from the front side of the substrate into the two-dimensional electron gas of the second individual transistor.

It is advantageous here that the potential contact does not affect the two-dimensional electron gas, since the potential contact is electrically insulated from the second gate terminal.

In another configuration, a sustain current of one of the second individual transistors may be adjusted depending on a level of the potential contact.

The advantage here is that the gate terminal of the second individual transistor can be safely switched in an over-voltage situation.

A method for manufacturing a HEMT including one of a plurality of first individual units according to the present invention includes fabricating a first insulating layer in at least one second individual unit, wherein the The first insulating layer is configured to be perpendicular to the front side of the substrate and directly extends into a two-dimensional electronic gas, so that a first individual transistor having a first gate terminal and a second gate electrode having a second gate terminal are manufactured. The second individual transistor. A potential contact is manufactured in the region of the second individual transistor, and the potential contact is configured to be perpendicular to the front side of the substrate and directly extends from the front side of the substrate into the two-dimensional electron gas of the second individual transistor. In addition, the method includes creating an electrical connection between the potential contact and the second gate terminal.

In another configuration, a second insulating layer is manufactured, the second insulating layer is configured to be perpendicular to the front side of the substrate and directly extends into the two-dimensional electron gas of the second individual transistor.

Other advantages are apparent from the description of the following illustrative specific examples and / or from the scope of patent applications of the subsidiary patents.

100‧‧‧High Electron Mobility Transistor (HEMT)

101‧‧‧First individual unit

108‧‧‧Source terminal

109‧‧‧ drain terminal

112‧‧‧Gate terminal

200‧‧‧High Electron Mobility Transistor (HEMT)

201‧‧‧ the first individual unit

202‧‧‧First insulation layer

205‧‧‧First Gate Extreme

207‧‧‧Second Gate Extreme

208‧‧‧Source terminal

209‧‧‧ drain terminal

212‧‧‧Gate terminal

213‧‧‧potential contact

214‧‧‧Second Individual Unit

302‧‧‧First insulation layer

304‧‧‧The first individual transistor

305‧‧‧First Gate Extreme

306‧‧‧Second individual transistor

307‧‧‧Second Gate Extreme

308‧‧‧Source terminal

309‧‧‧ terminal

313‧‧‧potential contact

314‧‧‧Second Unit

402‧‧‧First insulation layer

403‧‧‧Second insulation layer

404‧‧‧The first individual transistor

405‧‧‧First Gate Extreme

406‧‧‧Second individual transistor

407‧‧‧Second Gate Extreme

408‧‧‧source terminal

409‧‧‧ drain terminal

413‧‧‧potential contact

414‧‧‧Second Individual Unit

500‧‧‧High Electron Mobility Transistor (HEMT)

504‧‧‧The first individual transistor

505‧‧‧First Gate Extreme

506‧‧‧Second individual transistor

507‧‧‧Second Gate Extreme

508‧‧‧Source terminal

509‧‧‧ drain terminal

510‧‧‧first resistor

511‧‧‧Second resistor

513‧‧‧potential contact

600‧‧‧ Method

610‧‧‧step

620‧‧‧step

630‧‧‧step

640‧‧‧step

The invention is explained below based on preferred specific examples and drawings.

In the drawings: FIG. 1 shows a plan view of a prior art HEMT, FIG. 2 shows a schematic plan view of a HEMT according to the present invention, FIG. 3 shows a plan view of a first configuration of a second individual unit, and FIG. 4 shows a second individual unit A plan view of the second configuration, FIG. 5 shows an equivalent circuit diagram of a HEMT according to the present invention, and FIG. 6 shows a method for manufacturing the HEMT according to the present invention.

Figure 1 shows a plan view of a prior art HEMT 100. The HEMT 100 includes a plurality of first individual cells 101 each forming at least one individual transistor. Therefore, the The HEMT 100 includes a series circuit formed by a plurality of individual transistors. Figure 1 also shows the source terminal 108, the drain terminal 109, and the gate terminal 112 of the HEMT 100.

FIG. 2 shows a schematic plan view of a HEMT 200 according to the present invention. The HEMT 200 includes a source terminal 208, a drain terminal 209 and a gate terminal 212, a plurality of first individual units 201, and at least one second individual unit 214 having a first insulating layer 202. A first individual transistor having a first gate terminal 205 and a second individual transistor having a second gate terminal 207 are formed by the first insulating layer 202. In this case, the first individual transistor and the second individual transistor are electrically connected in parallel. The potential contact 213 is disposed in a region of the second individual transistor. In this case, the second individual transistor functions to protect the first individual transistor from overvoltage.

FIG. 3 shows a first configuration of the second individual unit 314. The second individual unit 314 has a source terminal 308 and a drain terminal 309. In addition, the other individual units 314 have a first insulating layer 302, so that a first individual transistor 304 having a first gate terminal 305 and a second individual transistor 306 having a second gate terminal 307 are formed. In this case, the first individual transistor 304 and the second individual transistor 306 are connected in parallel. The potential contact 313 is disposed in a region of the second individual transistor 306.

FIG. 4 shows a second configuration of the second individual unit 414. In this case, the mantissas of the reference symbols that correspond to the mantissas of the reference symbols in FIG. 3 represent the same characteristics. In addition, the second individual transistor 406 has a second insulating layer 403 that electrically insulates the potential contact 413 from the second gate terminal 407. The second insulating layer 406 is configured to be at a right angle to the front side of the substrate and directly extends into the two-dimensional electronic gas of the second individual transistor 406.

Optionally, the HEMT may include a plurality of second individual units 314 and 414. Of course However, one such second individual unit 314 and 414 is sufficient to function as an overvoltage protection.

In an illustrative specific example, the HEMT includes a plurality of individual units. The individual units are connected in parallel so that they have a common sink terminal, source terminal, and gate terminal. In this case, both of the individual units are implemented separately. Two individual cells are insulated from other individual cells via an insulating layer, wherein these individual cells still have a common drain and source terminal. The first of these two individually implemented individual units contains another ohmic contact as a potential contact, which is on the drift zone of the actual base unit. The second of the two individual units is implemented so that the gate terminal is connected to the ohmic contact of the first individual unit.

FIG. 5 shows an equivalent circuit diagram of a HEMT 500 according to the present invention. The HEMT includes a first individual transistor 504 having a first gate terminal 505 and a second individual transistor 506 having a second gate terminal 507. The first individual transistor 504 and the second individual transistor 506 are electrically connected in parallel by means of a common source terminal 508 and a common drain terminal 509. The HEMT includes a heterostructure with two layers having band gaps of different magnitudes, such as an AlGaN / GaN layer or AlGaAs / GaAs, so that a two-dimensional electron gas is formed under the active component. In this case, the two-dimensional electron gas forms an ohmic resistance between the drain terminal and the source terminal. The HEMT has a potential contact 513 that extends directly from the front side of the substrate to a two-dimensional electronic gas, so that the ohmic resistance is subdivided into a first resistance 510 and a second resistance 511, that is, a voltage divider is formed. The voltage divider sets a gate voltage or a sustain current of the second individual transistor 506. For the reliable functionality of the over-voltage device, the sustain current must be higher than the on-current of the gate, so that the second individual transistor 506 is available in an over-voltage situation. This situation means that the second individual transistor 506 is normally on. In this case, the level of the potential contact 513 sets a sustain current.

For example, the material of the potential contact 513 includes a titanium / aluminum / nickel / gold contact.

FIG. 6 shows a method 600 for manufacturing a HEMT including a plurality of first individual units and at least one second individual unit. The method 600 begins with step 610, which involves fabricating a first insulating layer in a second individual cell. In this case, the first insulating layer is configured to be perpendicular to the front side of the substrate and directly extends into the two-dimensional electronic gas. Therefore, a first individual transistor having a first gate terminal and a second individual transistor having a second gate terminal are manufactured. The subsequent step 630 involves making a potential contact in the region of the second individual transistor. The potential contact is also configured to be perpendicular to the front side of the substrate and directly extends from the front side of the substrate into the two-dimensional electron gas of the second individual transistor. The subsequent step 640 involves creating an electrical connection between the potential contact and the second gate terminal.

In an illustrative specific example, step 620 is performed between step 610 and step 630. This step 620 involves manufacturing a second insulating layer that is configured to be perpendicular to the front side of the substrate and directly extends to a second individual. The two-dimensional electron gas of the transistor. Therefore, the potential contact is electrically isolated from the second gate terminal.

200‧‧‧High Electron Mobility Transistor (HEMT)

201‧‧‧ the first individual unit

202‧‧‧First insulation layer

205‧‧‧First Gate Extreme

207‧‧‧Second Gate Extreme

208‧‧‧Source terminal

209‧‧‧ drain terminal

212‧‧‧Gate terminal

213‧‧‧potential contact

214‧‧‧Second Individual Unit

Claims (10)

A high electron mobility transistor (HEMT) (100, 500), comprising a plurality of first individual units (201) and at least one second individual unit (214, 314, 414), wherein the second individual unit ( (214, 314, 414) has a first insulating layer (202, 302, 402), the first insulating layer is configured to be perpendicular to a substrate front side and directly extends from the substrate front side into a two-dimensional electronic gas, so that Fabricate a first individual transistor (204, 304, 404) with a first gate terminal (205, 305, 405) and a second individual transistor with a second gate terminal (207, 307, 407) Crystal (206, 306, 406), wherein the first individual transistor (204, 304, 404) and the second individual transistor (206, 306, 406) are electrically connected in parallel and have a source terminal (108, 208) , 308, 408, 508) and a drain terminal (109, 209, 309, 409, 509), of which: a potential contact (213, 313, 413) is arranged in the second individual transistor (206, 306, 406) and between the drain terminal (109, 209, 309, 409, 509) and the source terminal (108, 208, 308, 408, 508), the potential contact is configured as a vertical Straight to the front side of the substrate and extending directly from the front side of the substrate into the two-dimensional electron gas of the second individual transistor (206, 306, 406) so that the drain terminal (109, 209, 309, 409, 509) and the second gate terminal (207, 307, 407) generate a first resistance (510) and between the second gate terminal (207, 307, 407) and the source terminal (108, 208) , 308, 408, 508) to generate a second resistor (511), which provides a resistor for electrically connecting the potential contact (213, 313, 413) and the second gate terminal (207, 307, 407). component. For example, the high electron mobility transistor (100, 500) in the scope of patent application, where The component is a gate field plate. For example, if a high electron mobility transistor (100, 500) of the first or second patent scope is applied, one of the regions of the second gate electrode (207, 307, 407) corresponds to the potential contact (213 , 313, 413). For example, the transistor (100, 500) with high electron mobility in the first or second scope of the patent application, wherein one area of the second gate electrode (207, 307, 407) is larger than the potential contact (213, 313, 413). For example, the high electron mobility transistor (100, 500) of the first or second patent application scope, wherein the potential contact (213, 313, 413) is arranged on the second individual transistor (206, 306, 406) and between the drain terminal (209, 309, 409) and the second gate terminal (207, 307, 407). For example, the high electron mobility transistor (100, 500) of the first or second patent application scope, wherein the potential contact (213, 313, 413) is arranged on the second individual transistor (206, 306, 406) and between the source terminal (208, 308, 408) and the second gate terminal (207, 307, 407). For example, if the high electron mobility transistor (100, 500) of the first or second patent scope is applied for, the second individual transistor (206, 306, 406) has a second insulating layer (403). The second insulating layer (403) is configured to be perpendicular to the front side of the substrate and directly extends from the front side of the substrate into the two-dimensional electron gas of the second individual transistor (206, 306, 406). For example, if the high electron mobility transistor (100, 500) of the first or second patent application scope is applied, one of the second individual transistor (206, 306, 406) sustaining current may depend on the potential contact (213, 313, 413). A method (600) for manufacturing a high electron mobility transistor, the high electron mobility transistor comprising a plurality of first individual units, the method comprising the steps of: manufacturing (610 in at least one second individual unit) ) A first insulating layer, wherein the first insulating layer is configured to be perpendicular to a front side of a substrate and directly extends into a two-dimensional electronic gas, so that a first individual transistor having a first gate terminal and a first transistor are manufactured; A second individual transistor having a second gate electrode terminal is used to manufacture (630) a potential contact in a region of the second individual transistor, wherein the potential contact is configured to be perpendicular to the front side of the substrate and from the The front side of the substrate extends directly into the two-dimensional electronic gas of the second individual transistor, and an electrical connection is made (640) between the potential contact and the second gate terminal. For example, a method (600) for manufacturing a transistor having a high electron mobility in the scope of the patent application, wherein a second insulating layer is manufactured, and the second insulating layer is configured to be perpendicular to the front side of the substrate and directly extend Into the two-dimensional electron gas of the second individual transistor.