TW201803046A - Fan-out semiconductor package - Google Patents

Abstract

A fan-out type semiconductor package includes: a fan-out type semiconductor package may include: a first interconnecting member having a through hole; a semiconductor wafer disposed in the through hole of the first interconnecting member and having an active A surface and a passive surface opposite to the active surface, a connection pad is disposed on the active surface; an encapsulation body encapsulating at least some parts of the first interconnecting member and the passive surface of the semiconductor wafer At least some parts of; a second interconnecting member disposed on the first interconnecting member and the active surface of the semiconductor wafer; and a reinforcing layer disposed on the encapsulation body. The first interconnect member and the second interconnect member respectively include a redistribution layer, and the redistribution layer is electrically connected to the connection pad of the semiconductor wafer.

Description

Fan-out semiconductor package

The present invention relates to a semiconductor package, and more specifically, to a fan-out type semiconductor package in which a connection terminal can extend beyond a region in which a semiconductor wafer is disposed.

The recent significant trend in the development of technology related to semiconductor wafers is to reduce the size of semiconductor wafers. Therefore, in the case of packaging technology, with the rapid increase in demand for small-sized semiconductor wafers and the like, it has been necessary to implement a semiconductor package having a compact size while including a plurality of pins.

One packaging technology proposed to meet the above technical requirements is a fan-out package. Such a fan-out type package has a compact size by rewiring the connection terminals outside the area in which the semiconductor chip is disposed, and can achieve the implementation of multiple pins.

The aspect of the present invention can provide a fan-out type semiconductor package in which the warpage problem can be effectively solved.

According to an aspect of the present invention, there can be provided a fan-out type semiconductor package in which a reinforcing layer that can control the warpage of the fan-out type semiconductor package is attached to an encapsulant encapsulating a semiconductor wafer.

According to an aspect of the present invention, a fan-out type semiconductor package may include: a first interconnection member having a through hole; a semiconductor wafer disposed in the through hole of the first interconnection member and having An active surface and a passive surface opposite to the active surface, a connection pad is disposed on the active surface; an encapsulation body encapsulating at least some parts of the first interconnecting member and the passive of the semiconductor chip At least some portions of the surface; a second interconnecting member disposed on the first interconnecting member and the active surface of the semiconductor wafer; and a reinforcing layer disposed on the encapsulation body. The first interconnect member and the second interconnect member respectively include a redistribution layer, and the redistribution layer is electrically connected to the connection pad of the semiconductor wafer.

Hereinafter, each exemplary embodiment of the present invention will be explained with reference to the drawings. In the drawings, the shape, size, etc. of each component may be exaggerated or omitted for clarity.

The term "exemplary embodiment" as used herein does not refer to the same exemplary embodiment, but is provided to emphasize specific features or characteristics that are different from the specific features or characteristics of another exemplary embodiment. However, the exemplary embodiments provided herein are considered to be able to be implemented by combining with each other in whole or in part. For example, even if an element set forth in a specific exemplary embodiment is not set forth in another exemplary embodiment, the element can be understood as unless the contrary or contradictory description is provided herein. Description related to another exemplary embodiment.

In the description, the meaning of "connection" between one component and another component includes the indirect connection through the third component and the direct connection between the two components. In addition, "electrical connection" is meant to include the concepts of physical connection and physical disconnection. It should be understood that when elements are referred to as "first" and "second", the elements are not limited thereby. The use of "first" and "second" may only be used for the purpose of distinguishing the element from other elements, and may not limit the order or importance of the elements. In some cases, the first element may be referred to as the second element without departing from the scope of the patent application filed herein. Similarly, the second element may also be referred to as the first element.

Herein, the upper part, the lower part, the upper side, the lower side, the upper surface, the lower surface, etc. are judged in the drawings. For example, the first interconnection member is disposed at a higher level than the heavy wiring layer. However, the patent scope of this application is not limited to this. In addition, the vertical direction refers to the above upward and downward directions, and the horizontal direction refers to the direction perpendicular to the above upward and downward directions. In this case, the vertical cross section refers to a case taken along a plane in the vertical direction, and an example of the vertical cross section may be a cross-sectional view shown in the drawing. In addition, the horizontal cross section refers to a case taken along a plane in the horizontal direction, and an example of the horizontal cross section may be a plan view shown in the drawings.

The terminology used herein is merely to illustrate exemplary embodiments and not to limit the present invention. In this case, unless otherwise explained in the context, singular forms include the majority form. Electronic device

FIG. 1 is a schematic block diagram illustrating an example of an electronic device system.

Referring to FIG. 1, the electronic device 1000 may house a motherboard 1010. The motherboard 1010 may include chip-related components 1020, network-related components 1030, other components 1040, etc. that are physically connected or electrically connected to the motherboard 1010. These components can be connected to other components described below to form various signal lines 1090.

The chip-related components 1020 may include: memory chips, such as volatile memory (eg, dynamic random access memory (DRAM)), non-volatile memory (eg, read only memory) memory, ROM)), flash memory, etc.; application processor chips, such as central processing unit (eg, central processing unit (CPU)), graphics processor (eg, graphic processing unit, GPU)), digital signal processor, cryptographic processor, microprocessor, microcontroller, etc.; and logic chips, such as analog-to-digital (ADC) converters, application-specific integrated products Circuit (application-specific integrated circuit, ASIC), etc. However, the wafer-related components 1020 are not limited thereto, but may also include other types of wafer-related components. In addition, the wafer-related components 1020 may be combined with each other.

The network-related components 1030 are compatible with, for example, the following protocols: wireless fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 family, etc.), global interoperable microwave access (Worldwide interoperability for microwave access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high-speed packet access + ( High speed packet access +, HSPA+), high speed downlink packet access + (HSDPA+), high speed uplink packet access + (HSUPA+), enhanced data GSM environment (enhanced data GSM environment, EDGE, global system for mobile communications (GSM), global positioning system (GPS), general packet radio service (GPRS), CDMA multiple access (Code division multiple access, CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G agreement, 4G agreement, and 5G agreement and Any other wireless agreement and wired agreement specified after the above agreement. However, the network-related component 1030 is not limited to this, but may also include various other wireless standards or protocols or wired standards or protocols. In addition, the network-related components 1030 can be combined with the above-mentioned chip-related components 1020 together.

Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC), electromagnetic interference (electromagnetic interference) , EMI) filter, multilayer ceramic capacitor (MLCC), etc. However, the other components 1040 are not limited thereto, but may also include passive components for various other purposes and the like. In addition, other components 1040 may be combined with each other together with the above-mentioned chip-related components 1020 or network-related components 1030.

Depending on the type of the electronic device 1000, the electronic device 1000 may include other components that may be physically connected or electrically connected to the motherboard 1010 or may not be physically connected or electrically connected to the motherboard 1010. These other components may include, for example, camera module 1050, antenna 1060, display device 1070, battery 1080, audio codec (not shown), video codec (not shown), power amplifier (picture (Not shown in the figure), compass (not shown in the figure), accelerometer (not shown in the figure), gyroscope (not shown in the figure), speaker (not shown in the figure), mass storage unit (for example , Hard disk drive) (not shown), compact disk (CD) drive (not shown), digital versatile disk (DVD) drive (not shown) )Wait. However, these other components are not limited to this, but the type of the electronic device 1000 or the like may include other components used for various purposes.

The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital camera, a digital still camera, a network system, a computer, a monitor, a tablet PC, a laptop Personal computers, portable netbook PCs, TVs, video game machines, smart watches, automotive components, etc. However, the electronic device 1000 is not limited to this, but may be any other electronic device capable of processing data.

2 is a schematic perspective view illustrating an example of an electronic device.

Referring to FIG. 2, the semiconductor package may be used in various electronic devices 1000 as described above for various purposes. For example, the motherboard 1110 may be housed in the main body 1101 of the smartphone 1100, and various electronic components 1120 may be physically connected or electrically connected to the motherboard 1110. In addition, other components (eg, camera module 1130) that may be physically connected or electrically connected to the main board 1110 or may not be physically connected or electrically connected to the main board 1110 may be accommodated in the main body 1101. Some of the electronic components 1120 may be wafer-related components, and the semiconductor package 100 may be, for example, an application processor in the wafer-related components, but it is not limited thereto. The electronic device need not be limited to the smart phone 1100, but may be other electronic devices as described above. Semiconductor package

Generally speaking, many fine circuits are integrated in the semiconductor chip. However, the semiconductor wafer itself cannot be used as a finished semiconductor product, and will be damaged due to external physical impact or chemical impact. Therefore, the semiconductor wafer cannot be used alone, but can be packaged in an electronic device or the like and used in a packaged state in the electronic device or the like.

Here, in terms of electrical connection, there is a difference in circuit width between the semiconductor wafer and the main board of the electronic device, so semiconductor packaging is required. In detail, the size of the connection pads of the semiconductor chip and the intervals between the connection pads of the semiconductor chip are very fine, but the size of the component mounting pads of the motherboard used in the electronic device and the size of the component mounting pads of the motherboard The spacing between them is significantly larger than the size of the connection pads of the semiconductor wafer and the spacing between the connection pads. Therefore, it may be difficult to directly mount the semiconductor wafer on the main board, and a packaging technique for buffering the difference in circuit width between the semiconductor wafer and the main board is required.

Depending on the structure and purpose of the semiconductor package, the semiconductor package manufactured by the packaging technology can be divided into a fan-in type semiconductor package and a fan-out type semiconductor package.

The fan-in type semiconductor package and the fan-out type semiconductor package will be explained in more detail below with reference to the drawings. Fan-in semiconductor package

3A and 3B are schematic cross-sectional views illustrating the state of the fan-in semiconductor package before and after being packaged.

4 is a schematic cross-sectional view illustrating a packaging process of a fan-in semiconductor package.

Referring to the drawing, the semiconductor wafer 2220 may be, for example, an integrated circuit (IC) in a bare state. The semiconductor wafer 2220 includes a body 2221 including silicon (Si), germanium (Ge), and gallium arsenide ( GaAs) etc.; a connection pad 2222 formed on one surface of the body 2221 and containing a conductive material such as aluminum (Al); and a protective layer 2223 such as an oxide film or a nitride film formed on one surface of the body 2221 It covers and covers at least some parts of the connection pad 2222. Here, since the connection pad 2222 is very small, it is difficult to mount an integrated circuit (IC) on an intermediate printed circuit board (PCB), a motherboard of an electronic device, or the like.

Therefore, depending on the size of the semiconductor wafer 2220, an interconnection member 2240 may be formed on the semiconductor wafer 2220 to rewire the connection pad 2222. The interconnection member 2240 can be formed by the following steps: forming an insulating layer 2241 on the semiconductor wafer 2220 using an insulating material such as a photoimagable dielectric (PID) resin; forming a via hole that opens the connection pad 2222 2243h; and then a redistribution layer 2242 and a via 2243 are formed. Next, a protective layer 2250 that protects the interconnection member 2240, an opening 2251, an under bump metal layer 2260, and the like can be formed. That is, the fan-in semiconductor package 2200 including, for example, the semiconductor wafer 2220, the interconnection member 2240, the protective layer 2250, and the under-bump metal layer 2260 can be manufactured through a series of processes.

As described above, the fan-in type semiconductor package may have a package in which all connection pads of the semiconductor wafer, such as input/output (I/O) terminals, etc., are disposed in the semiconductor wafer The form can have excellent electrical properties and can be produced at low cost. Therefore, many components installed in smart phones have been manufactured in the form of fan-in semiconductor packages. In detail, many components installed in smart phones have been developed to enable fast signal transfer while having a compact size.

However, since all input/output terminals need to be placed in the semiconductor wafer in the fan-in type semiconductor package, the fan-in type semiconductor package has a large space limitation. Therefore, it is difficult to apply this structure to a semiconductor wafer having a large number of input/output terminals or a semiconductor wafer having a compact size. In addition, due to the above disadvantages, the fan-in semiconductor package cannot be directly installed and used on the motherboard of the electronic device. Here, even in the case where the size of the input/output terminals of the semiconductor wafer and the interval between the input/output terminals of the semiconductor wafer are increased by the rewiring process, the size of the input/output terminals of the semiconductor wafer and the semiconductor The spacing between the input/output terminals of the chip may still be insufficient to directly mount the fan-in semiconductor package on the motherboard of the electronic device.

5 is a schematic cross-sectional view illustrating a situation in which a fan-in type semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic device.

6 is a schematic cross-sectional view illustrating a situation in which a fan-in type semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic device.

Referring to the drawing, in the fan-in semiconductor package 2200, the connection pads 2222 (ie, input/output terminals) of the semiconductor chip 2220 can be re-routed again through the interposer 2301, and the fan-in semiconductor package 2200 can It is finally mounted on the motherboard 2500 of the electronic device in a state of being mounted on the interposer 2301. In this case, the solder balls 2270 and the like can be fixed by underfilling the resin 2280 and the like, and the outer surface of the semiconductor wafer 2220 can be covered with the molding material 2290 and the like. Alternatively, the fan-in semiconductor package 2200 may be embedded in a separate interposer substrate 2302, and the connection pad 2222 (ie, input/output terminals) of the semiconductor chip 2220 may be embedded in the fan-in semiconductor package 2200 in the interposer In the state of the substrate 2302, rewiring is performed again through the interposer substrate 2302, and the fan-in semiconductor package 2200 can be finally mounted on the motherboard 2500 of the electronic device.

As described above, it may be difficult to directly install and use a fan-in type semiconductor package on the main board of the electronic device. Therefore, the fan-in semiconductor package can be mounted on a separate interposer and then mounted on the main board of the electronic device by a packaging process, or can be electronically in a state where the fan-in semiconductor package is embedded in the interposer Installed and used on the main board of the device. Fan-out semiconductor package

7 is a schematic cross-sectional view illustrating a fan-out type semiconductor package.

Referring to the drawing, in the fan-out semiconductor package 2100, for example, the outer surface of the semiconductor chip 2120 may be protected by the encapsulation body 2130, and the connection pad 2122 of the semiconductor chip 2120 may be passed through the interconnection member 2140. Rewiring is performed outside the semiconductor wafer 2120. In this case, a protective layer 2150 may be further formed on the interconnection member 2140, and an under bump metal layer 2160 may be further formed in the opening of the protective layer 2150. Solder balls 2170 may be further formed on the under bump metal layer 2160. The semiconductor wafer 2120 may be an integrated circuit (IC) including a main body 2121, a connection pad 2122, a protective layer (not shown in the figure), and the like. The interconnection member 2140 may include an insulating layer 2141, a redistribution layer 2142 formed on the insulating layer 2141, and a via 2143 electrically connecting the connection pad 2122 and the redistribution layer 2142 to each other.

As described above, the fan-out type semiconductor package may have a form in which the input/output terminals of the semiconductor wafer are rewired and placed outside the semiconductor wafer by the interconnection member formed on the semiconductor wafer . As described above, in the fan-in type semiconductor package, all input/output terminals of the semiconductor wafer need to be placed in the semiconductor wafer. Therefore, when the size of the semiconductor wafer is reduced, the size and pitch of the balls need to be reduced, so that it may not be possible to use a standardized ball layout in the fan-in type semiconductor package. On the other hand, the fan-out type semiconductor package has a form in which the input/output terminals of the semiconductor wafer are rewired and placed outside the semiconductor wafer by the interconnection member formed on the semiconductor wafer as described above. Therefore, even in the case where the size of the semiconductor wafer is reduced, it is actually possible to use a standardized ball layout in the fan-out semiconductor package, so that the fan-out semiconductor package can be used without a separate interposer substrate It is installed on the motherboard of the electronic device under the conditions as described below.

8 is a schematic cross-sectional view illustrating a situation in which a fan-out type semiconductor package is mounted on a main board of an electronic device.

Referring to the drawings, the fan-out semiconductor package 2100 can be mounted on the motherboard 2500 of the electronic device through solder balls 2170 or the like. That is, as described above, the fan-out semiconductor package 2100 includes the interconnection member 2140 formed on the semiconductor wafer 2120 and capable of rewiring the connection pad 2122 to the fan-out area outside the area of the semiconductor wafer 2120, So that the standardized ball layout can actually be used in the fan-out semiconductor package 2100. Therefore, the fan-out semiconductor package 2100 can be mounted on the motherboard 2500 of the electronic device without using a separate interposer or the like.

As described above, since the fan-out type semiconductor package can be mounted on the main board of an electronic device without using a separate interposer substrate, the fan-out type semiconductor package can be implemented to have a more used interposer substrate The thickness of the fan-in semiconductor package is small. Therefore, the fan-out semiconductor package can be miniaturized and thinned. In addition, the fan-out semiconductor package has excellent thermal and electrical characteristics, so that the fan-out semiconductor package is particularly suitable for mobile products. Therefore, the fan-out semiconductor package can be implemented in a more compact form than a general package-on-package (POP) type semiconductor package using a printed circuit board (PCB), and can be solved Problems arising from warping.

Meanwhile, the fan-out type semiconductor package refers to a packaging technology for mounting a semiconductor chip on a motherboard of an electronic device or the like as described above and protects the semiconductor chip from external impact, and the fan-out type semiconductor package It is conceptually different from a printed circuit board (PCB) (for example, an interposer substrate, etc.) that has a different scale, purpose, etc. from that of the fan-out semiconductor package and in which the fan-in semiconductor package is embedded.

The fan-out semiconductor package in which the warpage problem can be effectively solved will be explained below with reference to the drawings.

9 is a schematic cross-sectional view illustrating an example of a fan-out type semiconductor package.

FIG. 10 is a schematic plan view taken along line I-I' of the fan-out type semiconductor package shown in FIG. 9.

11A to 11D are schematic cross-sectional views illustrating various forms of vias formed in the first interconnect member of the fan-out type semiconductor package shown in FIG. 9.

Referring to the drawings, the fan-out semiconductor package 100A according to an exemplary embodiment of the present invention may include: a first interconnect member 110 having a through hole 110H; a semiconductor wafer 120 disposed on the first interconnect member 110 The through hole 110H has an active surface and a passive surface opposite to the active surface, a connection pad 122 is disposed on the active surface; an encapsulation body 130 encapsulates at least some parts of the first interconnecting member 110 And at least some parts of the passive surface of the semiconductor wafer 120; the second interconnection member 140, disposed on the first interconnection member 110 and the active surface of the semiconductor wafer 120; the reinforcement layer 181, disposed on the encapsulation body 130; The resin layer 182 is disposed on the reinforcement layer 181; and the opening 182H penetrates through the resin layer 182, the reinforcement layer 181 and the encapsulant 130 and exposes at least some portions of the third redistribution layer 112c of the first interconnect member 110 . The fan-out semiconductor package 100A according to the exemplary embodiment may further include: a protective layer 150 disposed on the second interconnection member 140; an under bump metal layer 160 disposed in the opening 150H of the protective layer 150; And the connection terminal 170 is disposed on the under bump metal layer 160. The reinforcement layer 181 may have a larger elastic modulus than the elastic modulus of the encapsulation body 130 and may have a lower thermal expansion coefficient than the coefficient of thermal expansion (CTE) of the encapsulation body 130.

Meanwhile, as shown in FIG. 26, a thermosetting resin film that can firmly fix the first interconnect member 510, the semiconductor wafer 520, and the like can be used to form an encapsulation body 530 that encapsulates the first interconnect member 510, the semiconductor wafer 520, and the like. In detail, the encapsulation body 530 may be formed using a thermosetting resin film having a high thermal expansion coefficient, which generally has good resin fluidity, so that the space of the through hole 510H between the first interconnect member 510 and the semiconductor wafer 520 It is completely filled with resin and enhances the close adhesion between the first interconnect member 510 and the semiconductor wafer 520. However, in such a thermosetting resin film, the thermosetting shrinkage of the resin is large, which in turn may cause severe warpage W1 in the package after the resin is hardened. Therefore, it may be difficult to form a fine circuit pattern on the active surface of the semiconductor wafer 520 later.

Meanwhile, as shown in FIG. 27, to solve this problem, it may be considered to use a thermosetting resin film having a low coefficient of thermal expansion to form the encapsulation body 540. In this case, the warpage W2 can be suppressed compared to the case where a thermosetting resin film having a high coefficient of thermal expansion is used. However, as shown in FIG. 28, in order to reduce the coefficient of thermal expansion, the content of the inorganic filler in the thermosetting resin film is generally increased, so that the resin may not be able to sufficiently fill fine spaces due to the decrease in the fluidity of the resin, resulting in the formation of voids Wait. In addition, delamination or the like may occur between the first interconnect member and the semiconductor wafer due to a reduction in close adhesion between the first interconnect member and the semiconductor wafer.

On the other hand, as in the fan-out type semiconductor package 100A according to the exemplary embodiment, in the case where the reinforcement layer 181 having a relatively large elastic modulus or a relatively small coefficient of thermal expansion is introduced, the reinforcement layer 181 may The hardening shrinkage of the material (for example, thermosetting resin film) of the encapsulation body 130 is suppressed, thereby making it possible to significantly reduce the generation of warpage of the fan-out semiconductor package 100A after the material is hardened. Therefore, a material having a high coefficient of thermal expansion can be used as the material of the encapsulation body 130. As a result, problems such as voids and delamination may not occur.

Meanwhile, in the fan-out semiconductor package 100A according to the exemplary embodiment, the reinforcement layer 181 may include glass cloth, inorganic filler, and insulating resin. In this case, it may not be easy to form an opening in the reinforcement layer 181. However, in the case where the resin layer 182 is disposed on the reinforcement layer 181, this problem can be solved. For example, an insulating material (for example, including inorganic filler and insulating resin but not including a core material such as glass cloth (or glass fiber), etc. (i.e. In the case of a constitutive film (Ajinomoto Build-up Film (ABF), etc.) as the material of the resin layer 182, the opening 182H can be easily formed. The wiring exposed through the opening 182H can be used as a mark, a pad, or the like.

The respective components included in the fan-out semiconductor package 100A according to the exemplary embodiment will be explained in more detail below.

The first interconnection member 110 may include a rewiring layer 112a and a rewiring layer 112b that rewire the connection pads 122 of the semiconductor wafer 120 to thereby reduce the number of layers of the second interconnection member 140. If necessary, the first interconnecting member 110 can maintain the rigidity of the fan-out semiconductor package 100A depending on the material of the encapsulation body 130 and is used to ensure the uniformity of the thickness of the encapsulation body 130. In some cases, due to the first interconnection member 110, the fan-out type semiconductor package 100A according to an exemplary embodiment may be used as a part of a stacked package semiconductor package. The first interconnecting member 110 may have a through hole 110H. A semiconductor wafer 120 may be disposed in the through hole 110H to be spaced apart from the first interconnect member 110 by a predetermined distance. The side surface of the semiconductor wafer 120 may be surrounded by the first interconnect member 110. However, this form is only an example and various modifications can be made to the present invention to have other forms, and the fan-out semiconductor package 100A can perform another function depending on this form.

The first interconnecting member 110 may include: a first insulating layer 111a contacting the second interconnecting member 140; a first heavy wiring layer 112a contacting the second interconnecting member 140 and being embedded in the first insulating layer 111a; a second heavy The wiring layer 112b is disposed on the other surface of the first insulating layer 111a opposite to the surface of the first insulating layer 111a in which the first heavy wiring layer 112a is embedded; the second insulating layer 111b is disposed on the first insulating layer 111a The second redistribution layer 112b is covered and covered; and the third redistribution layer 112c is disposed on the second insulating layer 111b. The first redistribution layer 112a, the second redistribution layer 112b, and the third redistribution layer 112c may be electrically connected to the connection pad 122. The first interconnection member 110 may include penetrating through the first insulating layer 111a and the second insulating layer 112b and respectively connecting the first redistribution layer 112a and the second redistribution layer 112b and the second redistribution layer 112b and the third redistribution layer The layer 112c is electrically connected to the first via 113a and the second via 113b of each other. As described above, since the first redistribution layer 112a is embedded, the insulation distance of the insulation layer 141a of the second interconnection member 140 may be substantially constant. Since the first interconnecting member 110 may include a large number of redistribution layers 112a, 112b, and 112c, the second interconnection member 140 may be further simplified. Therefore, the decrease in yield due to defects occurring in the process of forming the second interconnection member 140 can be improved.

The case where the first interconnecting member 110 includes two insulating layers 111a and 111b is illustrated in the drawings, but the number of insulating layers constituting the first interconnecting member 110 may be greater than two. In this case, the number of redistribution layers disposed in the first interconnection member 110 may increase, and an additional via window connecting the redistribution layers to each other may be formed.

The material of each of the insulating layer 111a and the insulating layer 111b is not particularly limited. For example, an insulating material may be used as the material of each of the insulating layer 111a and the insulating layer 111b. In this case, the insulating material may be: a thermosetting resin, such as epoxy resin; a thermoplastic resin, such as polyimide resin; wherein the thermosetting resin or thermoplastic resin and the inorganic filler are impregnated into, for example, glass cloth (or glass Resin in core materials such as prepreg, Ajinomoto constituent film (ABF), FR-4, bismaleimide triazine (BT), etc. Alternatively, a photosensitive imaging dielectric (PID) resin may be used as the insulating material. The first insulating layer 111a and the second insulating layer 111b may include the same insulating material, and the boundary between the first insulating layer 111a and the second insulating layer 111b may not be obvious. However, the first insulating layer 111a and the second insulating layer 111b are not limited thereto.

The rewiring layer 112a, the rewiring layer 112b, and the rewiring layer 112c can be used to rewire the connection pads 122 of the semiconductor wafer 120, and the material of each of the rewiring layer 112a, the rewiring layer 112b, and the rewiring layer 112c It may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c can have various functions depending on the design of the layer corresponding thereto. For example, the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and so on. Here, the signal (S) pattern may include various signals other than a ground (GND) pattern, a power (PWR) pattern, etc., such as a data signal. In addition, the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c may include via window pads, connection terminal pads, and the like. As a non-limiting example, both of the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c may include a ground pattern. In this case, the number of ground patterns formed on the redistribution layer 142a and the redistribution layer 142b of the second interconnection member 140 can be significantly reduced, and thus the degree of freedom in wiring design can be improved.

If necessary, a surface treatment layer (not shown) may be further formed on the third rewiring layer 112c exposed from the rewiring layer 112a, the rewiring layer 112b, and the rewiring layer 112c through the opening 182H. The surface treatment layer (not shown in the figure) is not particularly limited, as long as the surface treatment layer is known in the related art, and the surface treatment layer can be formed by, for example, electrolytic gold plating or electroless plating Gold, organic solderability preservative (OSP) or electroless tin, electroless silver, electroless nickel/displacement gold plating, direct immersion gold (DIG) plating, hot air solder coating (hot air solder leveling (HASL) etc. formed.

The via 113a and the via 113b may electrically connect the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c formed on different layers to each other, thereby forming an electrical path in the first interconnecting member 110 . The material of each of the via 113a and the via 113b may be a conductive material. As shown in FIGS. 11A to 11D, each of the vias 113 may be completely filled with a conductive material, or the conductive material may also be formed along the walls of the respective via holes. In addition, each of the via window 113a and the via window 113b may have all shapes known in the related art, such as a tapered shape, a cylindrical shape, and the like. Meanwhile, as can be seen from the process to be explained below, when forming the via of the via 113a, some of the pads of the first redistribution layer 112a may serve as stoppers; and when forming the second via For the hole of 113b, some of the pads of the second redistribution layer 112b may serve as stoppers, and therefore each of the first via 113a and the second via 113b has a width of the upper surface A tapered shape with a large width on the lower surface may be advantageous in the manufacturing process. In this case, the first via 113a may be integrated with some parts of the second redistribution layer 112b, and the second via 113b may be integrated with some parts of the third redistribution layer 112c.

The semiconductor wafer 120 may be an integrated circuit (IC) configured to integrate a number of hundreds to millions of elements or more into a single wafer. For example, the integrated circuit may be an application processor chip, such as a central processor (eg, central processing unit), a graphics processor (eg, graphics processing unit), a digital signal processor, a cryptographic processor, a micro processor Processors, microcontrollers, etc., but not limited to this. The semiconductor wafer 120 may be formed based on an active wafer. In this case, the base material of the body 121 may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits can be formed on the main body 121. The connection pad 122 can electrically connect the semiconductor chip 120 to other components. The material of the connection pad 122 may be a conductive material such as aluminum (Al). A protective layer 123 exposing the connection pad 122 may be formed on the body 121, and the protective layer 123 may be an oxide film, a nitride film, or the like, or a double layer formed of an oxide layer and a nitride layer. With the protective layer 123, the lower surface of the connection pad 122 may have a stepped portion relative to the lower surface of the encapsulation body 130. As a result, a phenomenon in which the encapsulation body 130 penetrates into the lower surface of the connection pad 122 can be prevented to some extent. An insulating layer (not shown in the figure) or the like may be further arranged in other required positions.

The passive surface of the semiconductor wafer 120 may be disposed at a level lower than the upper surface of the third redistribution layer 112c of the first interconnect member 110. For example, the passive surface of the semiconductor wafer 120 may be disposed at a level lower than the upper surface of the second insulating layer 111b of the first interconnect member 110. The height difference between the passive surface of the semiconductor wafer 120 and the upper surface of the third redistribution layer 112c of the first interconnect member 110 may be 2 micrometers (μm) or more than 2 micrometers, for example, 5 micrometers or more than 5 micrometers. In this case, cracks in the corners of the passive surface of the semiconductor wafer 120 can be effectively prevented. In addition, the deviation of the insulation distance on the passive surface of the semiconductor wafer 120 can be significantly reduced in the case where the encapsulation body 130 is used.

The second redistribution layer 112b of the first interconnect member 110 may be disposed at a level between the active surface and the passive surface of the semiconductor wafer 120. The first interconnect member 110 may be formed to a thickness corresponding to the thickness of the semiconductor wafer 120. Therefore, the second redistribution layer 112b formed in the first interconnection member 110 may be disposed at a level between the active surface and the passive surface of the semiconductor wafer 120.

The encapsulation body 130 can protect the first interconnect member 110 and/or the semiconductor wafer 120. The encapsulation form of the encapsulation body 130 is not particularly limited, but may be a form in which the encapsulation body 130 surrounds at least some parts of the first interconnecting member 110 and/or at least some parts of the semiconductor wafer 120. For example, the encapsulation body 130 may cover the first interconnect member 110 and the passive surface of the semiconductor wafer 120 and fill the space between the wall of the through hole 110H and the side surface of the semiconductor wafer 120. In addition, the encapsulation body 130 may also fill at least a part of the space between the protective layer 123 of the semiconductor wafer 120 and the second interconnection member 140. At the same time, the encapsulation body 130 may fill the through hole 110H to thereby act as an adhesive depending on the material of the encapsulation body 130 and reduce buckling of the semiconductor wafer 120.

The material of the encapsulation body 130 is not particularly limited. For example, an insulating material can be used as the material of the encapsulation body 130. In this case, the insulating material may be: a thermosetting resin such as epoxy resin; a thermoplastic resin such as polyimide resin; a resin having a reinforcing material such as an inorganic filler impregnated in the thermosetting resin and thermoplastic resin, For example, Ajinomoto constitutes a film, FR-4, bismaleimide triazine, photosensitive imaging dielectric resin, and the like. In addition, conventional molding materials such as epoxy molding compound (EMC) can also be used. Alternatively, a resin in which a thermosetting resin or a thermoplastic resin is impregnated together with an inorganic filler in a core material such as glass cloth (or glass fiber) may be used as the insulating material.

The encapsulation body 130 may include multiple layers formed of multiple materials. For example, the space within the through hole 110H may be filled with the first encapsulation, and the first interconnect member 110 and the semiconductor wafer 120 may be covered with the second encapsulation. Alternatively, the first encapsulation body may cover the first interconnect member 110 and the semiconductor wafer 120 with a predetermined thickness while filling the space in the through hole 110H, and the second encapsulation body may cover the first encapsulation body with a predetermined thickness . In addition to the above forms, various forms can also be used.

If necessary, the encapsulation body 130 may contain conductive particles to block electromagnetic waves. For example, the conductive particles may be any material that can block electromagnetic waves, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), solder, etc. However, this is only an example, and the conductive particles are not limited to this.

The second interconnection member 140 may be configured to rewire the connection pad 122 of the semiconductor wafer 120. Dozens to hundreds of connection pads 122 having various functions can be re-routed through the second interconnection member 140, and can be physically connected to or electrically connected via the connection terminal 170 described below depending on the function Connect to an external source (external source). The second interconnection member 140 may include: an insulating layer 141a and an insulating layer 141b; a redistribution layer 142a and a redistribution layer 142b disposed on the insulating layer 141a and the insulating layer 141b; and an interlayer window 143a and an interlayer window 143b, through The rewiring layer 142a and the rewiring layer 142b are connected to each other through the insulating layer 141a and the insulating layer 141b. In the fan-out type semiconductor package 100A according to the exemplary embodiment, the second interconnection member 140 may include a plurality of redistribution layers 142a and redistribution layers 142b, but it is not limited thereto. That is, the second interconnection member 140 may also include a single layer. In addition, the second interconnection member 140 may also include different numbers of layers.

An insulating material may be used as the material of each of the insulating layer 141a and the insulating layer 141b. In this case, a photosensitive insulating material such as a photosensitive imaging dielectric (PID) resin may also be used as the insulating material. In this case, each of the insulating layer 141a and the insulating layer 141b can be formed to have a smaller thickness, and the precision of each of the via 143a and the via 143b can be more easily achieved Pitch. If necessary, the materials of the insulating layer 141a and the insulating layer 141b may be the same as each other or may be different from each other. The insulating layer 141a and the insulating layer 141b may be integrated with each other depending on the manufacturing process, so that the boundary between the insulating layer 141a and the insulating layer 141b may not be easily obvious.

The redistribution layer 142a and the redistribution layer 142b can be substantially used to reroute the connection pad 122. The material of each of the redistribution layer 142a and the redistribution layer 142b may be, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or its alloy and other conductive materials. The redistribution layer 142a and the redistribution layer 142b can have various functions depending on the design of the layer corresponding thereto. For example, the redistribution layer 142a and the redistribution layer 142b may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and so on. Here, the signal (S) pattern may include various signals other than a ground (GND) pattern, a power (PWR) pattern, etc., such as a data signal. In addition, the redistribution layer 142a and the redistribution layer 142b may include via window pads, connection terminal pads, and the like.

If necessary, a surface treatment layer (not shown) may be further formed on some portions of the redistribution layer 142a and the redistribution layer 142b exposed to the redistribution layer 142b. The surface treatment layer (not shown in the figure) is not particularly limited, as long as the surface treatment layer is known in the related art, and the surface treatment layer can be formed by, for example, electrolytic gold plating or electroless plating Gold, organic solderability protection or electroless tin, electroless silver, electroless nickel/displacement gold plating, direct gold plating, hot air solder coating, etc. are formed.

The via 143a and the via 143b can electrically connect the redistribution layer 142a and the redistribution layer 142b, the connection pad 122, etc. formed on different layers to each other, thereby generating electricity in the fan-out semiconductor package 100A Sexual path. The material of each of the via 143a and the via 143b may be, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or its alloy and other conductive materials. Each of the via window 143a and the via window 143b may be completely filled with the conductive material, or the conductive material may also be formed along the wall of each of the via windows. In addition, each of the via 143a and the via 143b may have all shapes conventionally known in the related art, such as a tapered shape, a cylindrical shape, and the like.

The thickness of the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c of the first interconnection member 110 may be greater than the thickness of the redistribution layer 142a and the redistribution layer 142b of the second interconnection member 140. Since the first interconnection member 110 may have a thickness equal to or greater than that of the semiconductor wafer 120, depending on the scale of the first interconnection member 110, the weight formed in the first interconnection member 110 The wiring layer 112a, the redistribution layer 112b, and the redistribution layer 112c may be formed to be large. On the other hand, the redistribution layer 142a and the redistribution layer 142b of the second interconnection member 140 may be formed to have a relatively larger size than the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c of the first interconnection member 110. Small size to achieve the thinness of the second interconnect member 140.

The reinforcement layer 181 can suppress the warpage generated in the fan-out semiconductor package 100A. For example, the reinforcement layer 181 can suppress the hardening shrinkage of the material of the encapsulation body 130, such as a thermosetting resin film, to suppress the warpage of the fan-out semiconductor package 100A. The reinforcement layer 181 may have an elastic modulus greater than that of the encapsulation body 130, and may have a thermal expansion coefficient smaller than that of the encapsulation body 130. In this case, the warpage suppression effect may be particularly excellent.

The reinforcement layer 181 may include a core material, an inorganic filler, and an insulating resin. For example, the reinforcement layer 181 may be formed of an uncovered copper clad laminate (CCL), prepreg, or the like. In the case where the reinforcing layer 181 contains a core material such as glass cloth (or glass fiber), the reinforcing layer 181 may be implemented to have a relatively large elastic modulus, and in the case where the reinforcing layer 181 contains an inorganic filler, the The reinforcing layer 181 is implemented to have a relatively small coefficient of thermal expansion by adjusting the content of the inorganic filler. The reinforcement layer 181 may be attached to the encapsulation body 130 in a hardened state (c-stage). In this case, the boundary surface between the encapsulation body 130 and the reinforcement layer 181 may have an approximately linear shape. Meanwhile, the inorganic filler may be silica, alumina, etc., and the resin may be epoxy resin, etc. However, the inorganic filler and the resin are not limited to this.

A resin layer 182 may be placed on the reinforcement layer 181. The resin layer 182 may be formed of a material that is the same as or similar to the material of the encapsulation body 130, for example, an insulating material including an inorganic filler and an insulating resin but not a core material, that is, Ajinomoto Composition Film (ABF), or the like. In the case where the reinforcing layer 181 contains a core material or the like, it is difficult to form the opening 182H in the reinforcing layer 181, but in the case where the resin layer 182 is added, the opening 182H can be easily formed. The opening 182H may penetrate the encapsulation body 130, the reinforcement layer 181, and the resin layer 182, and may expose at least some portions of the third redistribution layer 112c of the first interconnect member 110. The opening 182H may be used as an opening for marking. Alternatively, the opening 182H may be used as an opening for exposing pads in the stacked package structure. Alternatively, the opening 182H may be used as an opening for mounting surface mounted technology (SMT) components. In the case where the resin layer 182 is disposed, the warpage can be suppressed more easily.

The protective layer 150 may be additionally configured to protect the second interconnect member 140 from external physical damage or chemical damage. The protective layer 150 may have an opening 150H exposing at least some portions of one of the redistribution layer 142a and the redistribution layer 142b of the second interconnection member 140. The opening 150H may expose the entire surface of the redistribution layer 142b or only a part of the surface of the redistribution layer 142b. The material of the protective layer 150 is not particularly limited, but may be a photosensitive insulating material such as a photosensitive imaging dielectric resin. Alternatively, solder resist can also be used as the material of the protective layer 150. Alternatively, an insulating resin that does not contain a core material but contains a filler (for example, an Ajinomoto film containing an inorganic filler and an epoxy resin) can be used as the material of the protective layer 150. In the case where an insulating material containing an inorganic filler and an insulating resin but not a core material (for example, Ajinomoto constitutes a film, etc.) is used as the material of the protective layer 150, the protective layer 150 and the resin layer 182 may have symmetric effects with each other , Which can more effectively control warpage.

When an insulating material containing an inorganic filler and an insulating resin (for example, Ajinomoto constitutes a film, etc.) is used as the material of the protective layer 150, the insulating layer 141a and the insulating layer 141b of the second interconnecting member 140 may also contain the inorganic filler and the insulating Resin. In this case, the weight percentage of the inorganic filler included in the protective layer 150 may be greater than the weight percentage of the inorganic filler included in the insulating layer 141a and the insulating layer 141b of the second interconnecting member 140. In this case, the protective layer 150 may have a relatively low coefficient of thermal expansion, and similar to the reinforcement layer 181, may be used to control warpage.

If necessary, the protective layer 150 may be formed of a material satisfying Equation 1 to Equation 4. In this case, the board level reliability of the electronic component package can be improved. The modulus of elasticity is defined as the ratio between stress and deformation, and can be determined by the standard tension test specified in, for example, JIS C-6481, KS M 3001, KS M 527-3, ASTM D882, etc. ) While measuring. In addition, the thermal expansion coefficient may refer to the thermal expansion coefficient measured using a thermomechanical analyzer (TMA) or a dynamic mechanical analyzer (DMA). In addition, the thickness refers to the thickness of the protective layer 150 after hardening, and can be measured using a general thickness measuring device. In addition, the surface roughness can be formed by a conventional method such as surface treatment using cubic zirconia (CZ), and can be measured using a general-purpose roughness measurement device. In addition, the moisture absorption ratio can be measured using general-purpose measuring equipment. Equation 1: Elastic modulus ´Coefficient of thermal expansion = 230 GPa·ppm/℃ Equation 2: Thickness = 10 microns Equation 3: Surface roughness = 1 nm Equation 4: Moisture absorption rate = 1.5%

The under-bump metal layer 160 may be additionally configured to improve the connection reliability of the connection terminal 170 to improve the board-level reliability of the fan-out sensor package 100A. The under bump metal layer 160 may be disposed on the wall in the opening 150H of the protective layer 150 and on the exposed redistribution layer 142 b of the second interconnection member 140. The under bump metal layer 160 may be formed by a conventional metallization method using a conventional conductive material (eg, metal).

The connection terminal 170 may additionally be configured to physically or electrically connect the fan-out semiconductor package 100A externally. For example, the fan-out semiconductor package 100A can be mounted on the motherboard of the electronic device via the connection terminal 170. Each of the connection terminals 170 may be formed of a conductive material such as solder. However, this is only an example, and the material of each of the connection terminals 170 is not limited to this. Each of the connection terminals 170 may be a land, ball, pin, or the like. The connection terminal 170 may be formed in a multi-layer structure or a single-layer structure. When the connection terminal 170 is formed in a multilayer structure, the connection terminal 170 may include copper (Cu) pillars and solder. When the connection terminal 170 is formed in a single-layer structure, the connection terminal 170 may include tin-silver solder or copper (Cu). However, this is only an example, and the connection terminal 170 is not limited to this. The number, interval, configuration, etc. of the connection terminals 170 are not particularly limited, but can be sufficiently modified by those skilled in the art depending on the design details. For example, according to the number of connection pads 122 of the semiconductor chip 120, the connection terminals 170 may be set to a number of tens to thousands, but it is not limited to this, and may be set to tens to thousands or more The number or the number of tens to thousands or less.

At least one of the connection terminals 170 may be disposed in the fan-out area. The fan-out area is an area other than the area in which the semiconductor wafer 120 is disposed. That is, the fan-out type semiconductor package 100A according to the exemplary embodiment may be a fan-out type package. Compared with the fan-in package, the fan-out package can have excellent reliability. The fan-out package can implement multiple input/output (I/O) terminals, and can Favorable for 3D interconnection. In addition, compared to a ball grid array (BGA) package, a land grid array (LGA) package, etc., the fan-out package can be used without the need for a separate board It is installed on the electronic device. Therefore, the fan-out package can be manufactured to have a reduced thickness, and can be competitively priced.

If necessary, a plurality of semiconductor wafers (not shown in the figure) may be placed in the through holes 110H of the first interconnect member 110, and the number of the through holes 110H of the first interconnect member 110 may be multiple (in the figure (Not shown), and semiconductor wafers (not shown in the figure) may be disposed in the through holes, respectively. In addition, a separate passive component (not shown in the figure) such as a condenser (condenser), an inductor, etc. may be encapsulated in the through hole 110H together with the semiconductor wafer. In addition, surface mount technology components (not shown in the figure) may be installed on the protective layer 150.

12 to 16 are schematic diagrams illustrating an example of the manufacturing process of the fan-out semiconductor package shown in FIG. 9.

Referring to FIG. 12, the carrier film 301 can be prepared first. The carrier film 301 may have a metal layer 302 and a metal layer 303 formed on one surface or two opposite surfaces of the carrier film. A surface treatment may be performed on the bonding surface between the metal layer 302 and the metal layer 303 to facilitate separation in the subsequent separation process. Alternatively, a release layer may be provided between the metal layer 302 and the metal layer 303 to facilitate separation in subsequent processes. The carrier film 301 may be a conventional insulating substrate, and the material of the carrier film 301 is not particularly limited. The metal layer 302 and the metal layer 303 may generally be copper (Cu) foil, but it is not limited thereto. That is, the metal layer 302 and the metal layer 303 may be thin films formed of other conductive materials. Next, patterning for forming the first redistribution layer 112a may be performed using the dry film 304. The first redistribution layer 112a can be formed by a conventional photolithography method. The dry film 304 may be a conventional dry film formed of a photosensitive material. Next, a conductive material may be disposed in the patterned space of the dry film 304 to form the first redistribution layer 112a. The first redistribution layer 112a may be formed using a plating process. In this case, the metal layer 303 may serve as a seed layer. The plating process may be electroplating or electroless plating, and more specifically, may be chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, and subtractive processes , Additive process, semi-additive process (semi-additive process, SAP), modified semi-additive process (modified semi-additive process, MSAP), etc., but not limited to this. Next, the dry film 304 can be removed. The dry film 304 can be removed by a conventional method such as an etching process.

Referring to FIG. 13, next, a first insulating layer 111 a in which at least a part of the first redistribution layer 112 a is embedded may be formed on the metal layer 303. Next, a first via 113a may be formed through the first insulating layer 111a. In addition, a second redistribution layer 112b may be formed on the first insulating layer 111a. A method of laminating the precursor of the first insulating layer 111a by a conventional lamination method and then hardening the precursor, applying the precursor of the first insulating layer 111a by a conventional application method and then applying The first insulating layer 111a is formed by the method of hardening the precursor. The first via 113a and the second redistribution layer 112b can be formed by the following methods: using photolithography, mechanical drilling, laser drilling, etc. to form vias in the first insulating layer 111a; Patterning is performed on dry films and the like; and the via holes and patterned spaces are filled by a plating process or the like. Next, a second insulating layer 111b covering the second redistribution layer 112b may be formed on the first insulating layer 111a. Next, a second via 113b may be formed through the second insulating layer 111b. In addition, a third redistribution layer 112c may be formed on the second insulating layer 111b. The method of forming the second via 113b and the third redistribution layer 112c may be the same as the above method. Next, the carrier film 301 can be peeled off. In this case, the peeling may indicate that the metal layer 302 and the metal layer 303 are separated from each other. Here, a blade can be used to separate the metal layers from each other, but it is not limited to this. That is, all conventional methods can be used to separate the metal layers from each other. Meanwhile, an example in which the first interconnect member 110 is formed before peeling off the carrier film 301 is explained in a series of processes. However, the present invention is not limited to this. For example, after the carrier film 301 is peeled off, the first interconnection member 110 may be formed according to the above process. That is, the order is not necessarily limited to the above order.

Referring to FIG. 14, next, the remaining metal layer 303 may be removed by a conventional etching method or the like, and the through hole 110H may be formed in the first interconnect member 110. The through hole 110H may be formed by mechanical drilling or laser drilling. However, the through hole 110H is not limited to this, and the through hole 110H may also be formed by a sandblasting method using abrasive particles, a dry etching method using plasma, or the like. In the case where the through hole 110H is formed by mechanical drilling or laser drilling, a desmearing process such as a permanganate method may be performed to remove resin dirt in the through hole 110H. Next, the adhesive film 305 may be attached to one surface of the first interconnect member 110. Any material that can fix the first interconnecting member 110 can be used as the adhesive film 305. As a non-limiting example, conventional tape and the like can be used. Examples of the conventional adhesive tape may include: thermosetting adhesive tape whose adhesive force is weakened by heat treatment; ultraviolet-curable adhesive tape whose adhesive force is weakened by ultraviolet radiation, and the like. Next, the semiconductor wafer 120 may be placed in the through hole 110H of the first interconnect member 110. For example, the semiconductor wafer 120 may be installed by attaching the semiconductor wafer 120 to the adhesive film 305 in the through hole 110H. The semiconductor wafer 120 may be placed in a face-down form, so that the connection pad 122 is attached to the adhesive film 305.

Referring to FIG. 15, next, the semiconductor wafer 120 may be encapsulated with an encapsulation body 130. The encapsulation body 130 may cover the first interconnect member 110 and the passive surface of the semiconductor wafer 120 and may fill the space in the through hole 110H. The encapsulation body 130 can be formed by a conventional method. For example, the encapsulation body 130 may be formed by a method of laminating the resin for forming the encapsulation body 130 in a non-hardened state and then hardening the resin. Alternatively, the resin for forming the encapsulation body 130 may be applied to the adhesive film 305 in an uncured state to encapsulate the first interconnect member 110 and the semiconductor wafer 120 and then harden the resin Method to form encapsulated body 130. The semiconductor chip 120 can be fixed by hardening. As a method of laminating the resin, for example, a method of performing a hot pressing process of compressing the resin at a high temperature for a predetermined time, depressurizing the resin, and then cooling the resin to room temperature can be used. The resin is cooled in the cold-pressing process, and then the work tool and the like are separated. As the method of applying the resin, for example, the following methods can be used: a screen printing method of applying ink using a squeegee, a spray printing method of applying ink in the form of mist, and the like. Next, a reinforcement layer 181 may be formed on the encapsulation body 130. The reinforcement layer 181 may be attached to the encapsulation body 130 in a hardened state (stage c) of, for example, an uncovered copper-clad laminate or the like. Therefore, after the reinforcement layer 181 is attached to the encapsulation body 130, the boundary surface between the encapsulation body 130 and the reinforcement layer 181 may have an approximately linear form. After the reinforcement layer 181 is attached to the encapsulation body 130, the encapsulation body 130 may be hardened. In this case, the reinforcing layer 181 can control the warpage caused by the hardening and shrinkage of the encapsulation body 130. In addition, in this case, the close adhesion between the reinforcing layer 181 and the encapsulation body 130 may be excellent. Next, the adhesive film 305 can be peeled off. The method of peeling the adhesive film is not particularly limited, but may be a conventional method. For example, in the case where a thermosetting adhesive tape whose adhesive force is weakened by heat treatment, an ultraviolet curing adhesive tape whose adhesive force is weakened by ultraviolet radiation, and the like are used as the adhesive film 305, the adhesive film 305 may be weakened by heat treatment After the adhesive force of the adhesive film 305 is peeled off, the adhesive film 305 may be peeled off after weakening the adhesive force of the adhesive film 305 by irradiating the adhesive film 305 with ultraviolet light. Next, the second interconnection member 140 may be formed on the first interconnection member 110 from which the adhesive film 305 is removed and on the active surface of the semiconductor wafer 120. The insulating layer 141a and the insulating layer 141b can be sequentially formed by the above plating process and the like, and then the redistribution layer 142a and the redistribution layer 142b are formed on and in the insulating layer 141a and the layer 141b, respectively And the via 143a and the via 143b to form the second interconnection member 140. In addition, a resin layer 182 may be formed on the reinforcement layer 181. In addition, a protective layer 150 may be formed on the second interconnection member 140. It is also possible by laminating the precursor of the resin layer 182 and the precursor of the protective layer 150 and then hardening the precursor, applying a material for forming the resin layer 182 and the protective layer 150 and then hardening the material Method to form the resin layer 182 and the protective layer 150.

16, next, an opening 150H may be formed in the protective layer 150 to expose at least some portions of the redistribution layer 142b of the second interconnection member 140, and may be formed in the opening 150H by a conventional metallization method The bump metal layer 160. In addition, an opening 182H that penetrates through the encapsulation body 130, the reinforcement layer 181, and the resin layer 182 and exposes at least some portions of the third redistribution layer 112c of the first interconnect member 110 may be formed. The opening 182H can be formed by mechanical drilling, laser drilling, a sandblasting method using abrasive particles, a dry etching method using plasma, or the like. Next, the connection terminal 170 may be formed on the under bump metal layer 160. The method of forming the connection terminal 170 is not particularly limited. That is, depending on the structure or form of the connection terminal 170, the connection terminal 170 can be formed by a conventional method in the related art. The connection terminal 170 can be fixed by reflow soldering, and some parts of the connection terminal 170 can be embedded in the protective layer 150 to enhance the fixing force, and the remaining part of the connection terminal 170 can be exposed to the outside, so that the reliability can be improved .

Meanwhile, in order to facilitate mass production, a series of processes may be the following processes: preparing a carrier film 301 having a large size; manufacturing a plurality of fan-out semiconductor packages 100A; and then using a dicing process to convert the multiple The fan-out semiconductor package is singulated into a separate fan-out semiconductor package 100A. In this case, the productivity may be excellent.

17 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package.

Referring to the drawings, in the fan-out semiconductor package 100B according to another exemplary embodiment in the present invention, only the reinforcement layer 181 may be attached to the encapsulation body 130. Even in the case where a separate resin layer 182 and the like are not attached to the reinforcing layer 181 as described above, warpage can be controlled. The reinforcement layer 181 may be formed of, for example, an uncovered copper-clad laminate including a core material, an inorganic filler, and an insulating resin, a prepreg, or the like. The reinforcing layer 181 may have an elastic modulus relatively larger than that of the encapsulation body 130, and may have a thermal expansion coefficient smaller than that of the encapsulation body 130. In this case, the warpage suppression effect can be particularly good. The reinforcement layer 181 may be attached to the encapsulation body 130 in a hardened state (c-stage). In this case, the boundary surface between the encapsulation body 130 and the reinforcement layer 181 may have an approximately linear shape.

Descriptions of architectures other than the above-mentioned architectures may overlap with those provided above, and therefore will not be repeated here. In addition, the description of the process of manufacturing the fan-out type semiconductor package 100B in which the resin layer 182 is not formed may overlap with the description provided above, and therefore will not be repeated here.

18 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

Referring to the drawings, in the fan-out semiconductor package 100C according to another exemplary embodiment of the present invention, only the reinforcement layer 181 may be attached to the encapsulation body 130. In this case, an opening 181H may be formed in the reinforcement layer 181 that penetrates the encapsulation body 130 and the reinforcement layer 181 and exposes at least some portions of the third redistribution layer 112c of the first interconnect member 110. Even in the case where a separate resin layer 182 and the like are not attached to the reinforcement layer 181 as described above, the opening 181H may be formed in the reinforcement layer 181. However, in this case, due to the characteristics of the material of the reinforcement layer 181 including the core material, it may be more difficult to form the opening 181H than in the case where the resin layer 182 is present. In addition, the core material of the reinforcement layer 181 may be exposed to the wall of the opening 181H, and therefore, an additional process for removing the exposed core material may be required. The reinforcement layer 181 may be attached to the encapsulation body 130 in a hardened state (c-stage). In this case, the boundary surface between the encapsulation body 130 and the reinforcement layer 181 may have an approximately linear shape.

Descriptions of architectures other than the above-mentioned architectures may overlap with those provided above, and therefore will not be repeated here. In addition, the description of the manufacturing process of manufacturing the fan-out type semiconductor package 100C in which the resin layer 182 is not formed may overlap with the description provided above, and therefore will not be repeated here.

19 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package.

Referring to the drawings, in the fan-out semiconductor package 100D according to another exemplary embodiment of the present invention, the reinforcement layer 183 may be formed of, for example, a prepreg including a core material, an inorganic filler, and an insulating resin, and The encapsulation body 130 may be formed of, for example, a film composed of Ajinomoto that includes an inorganic filler and an insulating resin but does not include a core material. In this case, when the weight percentage of the inorganic filler contained in the encapsulation body 130 is a1 and the weight percentage of the inorganic filler contained in the reinforcing layer 183 is a2, a1 <a2. For example, 1.10 <a2/a1 <1.95. That is, the reinforcing layer 183 having a relatively high concentration of inorganic filler may have a relatively low coefficient of thermal expansion, and the encapsulant 130 having a relatively low concentration of inorganic filler may have a relatively high coefficient of thermal expansion. Therefore, the encapsulation body 130 may have excellent resin fluidity, and the reinforcement layer 183 may be advantageous in controlling warpage. In addition, when the thickness of the reinforcement layer 183 is t1, the thickness of the portion of the encapsulation body 130 covering the first interconnecting member 110 is t2 and the thickness of the portion of the encapsulation body 130 covering the passive surface of the semiconductor wafer 120 is t3, t2 <t1, and t3 <t1. For example, 0.2 <t2/t1 <0.6, and 0.2 <t3/t1 <0.6. That is, the thickness of the reinforcement layer 183 may be greater than the thickness of the portion of the encapsulation body 130 covering the first interconnect member 110 and the portion covering the passive surface of the semiconductor wafer 120, which may be more beneficial for controlling warpage.

Meanwhile, the reinforcement layer 183 may be attached to the encapsulation body 130 in a non-hardened state and then be hardened. Therefore, the material of the reinforcement layer 183 having a relatively small coefficient of thermal expansion may penetrate into the through hole 110H due to mixing with the heterogeneous materials in contact with each other or movement of the boundary surface. For example, a prepreg including a core material, an inorganic filler, and an insulating resin can be attached to the encapsulation body 130 at the b stage in a semi-hardened state, and can then be cured by a subsequent process in the c stage, So that the reinforcement layer 183 can be formed. In this case, the mixing or boundary surface between the materials may move due to the difference between the concentration of the inorganic filler of the reinforcement layer 183 and the concentration of the inorganic filler of the encapsulation body 130. As a result, the boundary surface between the encapsulation body 130 and the reinforcement layer 183 will have a nonlinear shape. For example, the boundary surface between the encapsulation body 130 and the reinforcement layer 183 may have a bent portion 183P bent toward the space between the wall of the through hole 110H of the first interconnecting member 110 and the wall of the semiconductor wafer 120. In this case, the contact area between the reinforcement layer 183 and the encapsulation body 130 can be increased, and thus the tight adhesion between the reinforcement layer 183 and the encapsulation body 130 can be further improved.

Architectural-type descriptions other than the above-mentioned architectures may overlap with the descriptions provided above, and therefore will not be repeated here. In addition, the description of the process of manufacturing the fan-out semiconductor package 100D in which the resin layer 182 is not formed and the material and hardened state of the reinforcement layer 183 different from the material and hardened state of the above-mentioned reinforcement layer 181 overlaps the description provided above, and Therefore, it will not be repeated here.

20 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package.

Referring to the drawings, in the fan-out semiconductor package 100E according to another exemplary embodiment of the present invention, the reinforcement layer 184 may be formed of, for example, an asymmetric prepreg including a core material, an inorganic filler, and an insulating resin, etc. And the weight percentage of the inorganic filler contained in the side 184a of the reinforcing layer 184 in contact with the encapsulation body 130 is different from the side 184b of the reinforcing layer 184 opposite the side 184a with respect to the core material 184c The weight percentages of the inorganic fillers are different from each other. The encapsulation body 130 may be formed of, for example, a film composed of Ajinomoto that includes an inorganic filler and an insulating resin but does not include a core material. In this case, when the weight percentage of the inorganic filler included in the encapsulation body 130 is a1, the weight percentage of the inorganic filler included in the side 184a of the reinforcement layer 184 is a2, and the When the weight percentage of the inorganic filler in one side 184a opposite to the other side 184b is a3, a1 <a2 <a3. For example, 1.10 <a3/a1 <1.95. That is, the thermal expansion coefficient of the other side 184b of the reinforcement layer 184 may be the lowest, the thermal expansion coefficient of the one side 184a of the reinforcement layer 184 may be an intermediate value, and the thermal expansion coefficient of the encapsulation body 130 may be the highest. Therefore, the encapsulation body 130 can have excellent resin fluidity, one side 184a of the reinforcement layer 184 can ensure excellent tight adhesion with the encapsulation body 130, and the other side 184b of the reinforcement layer 184 can effectively control warpage. In addition, when the thickness of the reinforcement layer 184 is t1, the thickness of the portion of the encapsulation body 130 covering the first interconnecting member 110 is t2 and the thickness of the portion of the encapsulation body 130 covering the passive surface of the semiconductor wafer 120 is t3, t2 <t1, and t3 <t1. For example, 0.2 <t2/t1 <0.6, and 0.2 <t3/t1 <0.6. In this case, the warpage can be controlled more easily.

Meanwhile, the reinforcing layer 184 may be attached to the encapsulation body 130 in a semi-hardened state in a non-hardened state and then be hardened. Therefore, the material of the reinforcement layer 184 having a relatively small coefficient of thermal expansion may penetrate into the through hole 110H due to mixing with the heterogeneous materials in contact with each other or movement of the boundary surface. That is, for example, an asymmetric prepreg including a core material, an inorganic filler, and an insulating resin can be attached to the encapsulation body 130 in the b-stage, and can then be processed by a subsequent process in the c-stage Hardening, thereby making it possible to form the reinforcement layer 184. In this case, the mixing or boundary surface between the materials may move due to the difference between the weight percentage of the inorganic filler on one side 184a of the reinforcement layer 184 and the weight percentage of the inorganic filler of the encapsulation body 130. As a result, the boundary surface between the encapsulation body 130 and the reinforcement layer 184 will have a nonlinear shape. For example, some portions of one side 184a of the reinforcement layer 184 may face the encapsulant 130 filling the space between the first interconnect member 110 and the semiconductor wafer 120 within the through hole 110H of the first interconnect member 110 Recessed, thereby making it possible to form the bent portion 184P. In this case, the contact area between the reinforcement layer 184 and the encapsulation body 130 can be increased, and thus the tight adhesion between the reinforcement layer 184 and the encapsulation body 130 can be further improved.

Descriptions of architectures other than the above-mentioned architectures may overlap with those provided above, and therefore will not be repeated here. In addition, the description of the process of manufacturing the fan-out semiconductor package 100E in which the resin layer 182 is not formed and the material and curing state of the reinforcement layer 184 different from those of the above-mentioned reinforcement layer 181 and the cured state overlaps the description provided above, and Therefore, it will not be repeated here.

21 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package.

Referring to the drawings, in the fan-out semiconductor package 100F according to another exemplary embodiment in the present invention, only the reinforcement layer 185 may be attached to the encapsulation body 130. In this case, the reinforcement layer 185 may be formed of, for example, an Ajinomoto film that contains an inorganic filler and an insulating resin but does not contain a core material. In addition, the encapsulation body 130 may be formed of, for example, a film composed of Ajinomoto that includes an inorganic filler and an insulating resin but does not include a core material. However, the reinforcing layer 185 may have an elastic modulus larger than that of the encapsulation body 130 or a thermal expansion coefficient smaller than that of the encapsulation body 130 to suppress warpage. The reinforcement layer 185 may be attached to the encapsulation body 130 in a hardened state (stage c). In this case, the boundary surface between the encapsulation body 130 and the reinforcement layer 185 may have an approximately linear shape.

The description of the frame type other than the above-mentioned architecture may overlap with the description provided above, and therefore will not be repeated here. In addition, the description of the process of manufacturing the fan-out semiconductor package 100F in which the resin layer 182 is not formed and the material and curing state of the reinforcement layer 185 different from those of the above-mentioned reinforcement layer 181 and the cured state overlaps the description provided above, and Therefore, it will not be repeated here.

22 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package.

Referring to the drawings, in the fan-out semiconductor package 100G according to another exemplary embodiment in the present invention, only the reinforcement layer 185 may be attached to the encapsulation body 130. In this case, an opening 185H that penetrates through the reinforcement layer 185 and exposes at least some portions of the third redistribution layer 112c of the first interconnect member 110 may be formed in the reinforcement layer 185. In the case where the reinforcing layer 185 does not contain the core material, the opening 185H can be easily formed. The reinforcement layer 185 may be attached to the encapsulation body 130 in a hardened state (c-stage), and the boundary surface between the encapsulation body 130 and the reinforcement layer 185 may thus have an approximately linear shape.

Descriptions of architectures other than the above-mentioned architectures may overlap with those provided above, and therefore will not be repeated here. In addition, the description of the process of manufacturing the fan-out semiconductor package 100G in which the resin layer 182 is not formed and the material and hardened state of the reinforcement layer 185 different from the above-mentioned material and hardened state of the reinforcement layer 181 overlaps with the description provided above, and Therefore, it will not be repeated here.

23 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package.

Referring to the drawings, in the fan-out semiconductor package 100H according to another exemplary embodiment of the present invention, the reinforcement layer 186 may be formed of a film of Ajinomoto, which includes an inorganic filler and an insulating resin but does not include a core material, for example The encapsulation body 130 may also be formed by, for example, a film composed of Ajinomoto that includes an inorganic filler and an insulating resin but does not include a core material. In this case, when the weight percentage of the inorganic filler contained in the encapsulation body 130 is a1 and the weight percentage of the inorganic filler contained in the reinforcing layer 186 is a2, a1 <a2. For example, 1.10 <a2/a1 <1.95. That is, the reinforcing layer 186 having a relatively high concentration of inorganic filler may have a relatively low coefficient of thermal expansion, and the encapsulant 130 having a relatively low concentration of inorganic filler may have a relatively high coefficient of thermal expansion. Therefore, the encapsulation body 130 may have excellent resin fluidity, and the reinforcing layer 186 may be advantageous in controlling warpage. In addition, when the thickness of the reinforcement layer 186 is t1, the thickness of the portion of the encapsulation body 130 covering the first interconnecting member 110 is t2 and the thickness of the portion of the encapsulation body 130 covering the passive surface of the semiconductor wafer 120 is t3, t2 <t1, and t3 <t1. For example, 0.2 <t2/t1 <0.6, and 0.2 <t3/t1 <0.6. That is, the thickness of the reinforcing layer 186 may be greater than the thickness of the encapsulation body 130 covering the first interconnecting member 110 and the passive surface covering the semiconductor wafer 120, which may be more beneficial for controlling warpage.

Meanwhile, the reinforcement layer 186 may be attached to the encapsulation body 130 in a semi-hardened state in a non-hardened state and then be hardened. Therefore, the material of the reinforcement layer 186 having a relatively small coefficient of thermal expansion may penetrate into the through hole 110H due to mixing with the heterogeneous materials in contact with each other or movement of the boundary surface. That is, for example, an Ajinomoto composition film including an inorganic filler and an insulating resin but not a glass cloth can be attached to the encapsulation body 130 in the b stage, and then hardened by a subsequent process in the c stage , Which in turn makes it possible to form the reinforcement layer 186. In this case, the mixing or boundary surface between the materials may move due to the difference between the weight percentage of the inorganic filler of the reinforcement layer 186 and the weight percentage of the inorganic filler of the encapsulation body 130. As a result, the boundary surface between the encapsulation 130 and the reinforcement layer 186 will have an approximately nonlinear shape. For example, some portions of the reinforcement layer 186 may be recessed toward the encapsulation body 130 filling the space between the first interconnect member 110 and the semiconductor wafer 120 located in the through hole 110H of the first interconnect member 110, and then This makes it possible to form the bent portion 186P. In this case, the contact area between the reinforcement layer 186 and the encapsulation body 130 can be increased, and thus the tight adhesion between the reinforcement layer 186 and the encapsulation body 130 can be further improved.

Descriptions of architectures other than the above-mentioned architectures may overlap with those provided above, and therefore will not be repeated here. In addition, the description of the process of manufacturing the fan-out semiconductor package 100H in which the resin layer 182 is not formed and the material and curing state of the reinforcement layer 186 different from those of the above-mentioned reinforcement layer 181 and the cured state overlaps the description provided above, and Therefore, it will not be repeated here.

24 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package.

Referring to the drawings, in the fan-out semiconductor package 100I according to another exemplary embodiment of the present invention, the first redistribution layer 112a may be recessed in the first insulating layer 111a, thereby making the first insulating layer The lower surface of 111a may have a stepped portion with respect to the lower surface of the first redistribution layer 112a. As a result, when the encapsulation body 130 is formed, a phenomenon in which the material of the encapsulation body 130 seeps out to contaminate the first redistribution layer 112a can be prevented. Meanwhile, since the first redistribution layer 112a is recessed in the first insulating layer 111a as described above, the first interconnection member 110 can be placed at a level higher than the lower surface of the connection pad 122 of the semiconductor wafer 120 The lower surface of the heavy wiring layer 112a. In addition, the distance between the redistribution layer 142a of the second interconnection member 140 and the first redistribution layer 112a of the first interconnection member 110 may be greater than the connection of the redistribution layer 142a of the second interconnection member 140 and the semiconductor wafer 120 The distance between the pads 122.

Descriptions of architectures other than the above-mentioned architectures may overlap with those provided above, and therefore will not be repeated here. In addition, the description of the process of manufacturing the fan-out type semiconductor package 100I in which the stepped portion is formed by partially removing the first redistribution layer 112a when the metal layer 303 is removed may overlap the description provided above, and therefore not Repeat them again. Meanwhile, the features of the fan-out semiconductor package 100B to the fan-out semiconductor package 100H can also be applied to the fan-out semiconductor package 100I.

25 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package.

Referring to the drawings, in a fan-out semiconductor package 100J according to another exemplary embodiment of the present invention, the first interconnection member 110 may include: a first insulating layer 111a; a first redistribution layer 112a and The second redistribution layer 112b is respectively disposed on two opposite surfaces of the first insulating layer 111a; the second insulating layer 111b is disposed on the first insulating layer 111a and covers the first redistribution layer 112a; the third redistribution Layer 112c is disposed on the second insulating layer 111b; third insulating layer 111c is disposed on the first insulating layer 111a and covers the second redistribution layer 112b; and fourth redistribution layer 112d is disposed on the third insulating layer 111c on. The first redistribution layer 112a, the second redistribution layer 112b, the third redistribution layer 112c, and the fourth redistribution layer 112d may be electrically connected to the connection pad 122 of the semiconductor wafer 120. Since the first interconnection member 110 may include a larger number of redistribution layers 112a, 112b, redistribution layers 112c, and 112d, the second interconnection member 140 may be further simplified. Therefore, it is possible to improve the decrease in yield due to defects occurring in the process of forming the second interconnection member 140. Meanwhile, although not shown in the drawings, the first redistribution layer 112a, the second redistribution layer 112b, the third redistribution layer 112c, and the fourth redistribution layer 112d can penetrate the first insulating layer 111a, The first to third vias of the second insulating layer 111b and the third insulating layer 111c are electrically connected to each other.

The first insulating layer 111a may have a thickness greater than that of the second insulating layer 111b and the third insulating layer 111c. The first insulating layer 111a may be relatively thick to maintain rigidity, and the second insulating layer 111b and the third insulating layer 111c may be introduced to form a larger number of redistribution layers 112c and redistribution layers 112d. The first insulating layer 111a may include an insulating material different from that of the second insulating layer 111b and the third insulating layer 111c. For example, the first insulating layer 111a may be, for example, a prepreg including a core material, inorganic filler, and insulating resin, and the second insulating layer 111b and the third insulating layer 111c may be Ajinomoto including inorganic filler and insulating resin Constitute a film or photosensitive insulating film. However, the materials of the first insulating layer 111a and the materials of the second insulating layer 111b and the third insulating layer 111c are not limited thereto.

The lower surface of the third redistribution layer 112c of the first interconnect member 110 may be disposed at a lower level than the lower surface of the connection pad 122 of the semiconductor wafer 120. In addition, the distance between the redistribution layer 142 of the second interconnection member 140 and the third redistribution layer 112c of the first interconnection member 110 may be smaller than the connection of the redistribution layer 142 of the second interconnection member 140 and the semiconductor wafer 120 The distance between the pads 122. Here, the third redistribution layer 112c may be disposed on the second insulating layer 111b in a protruding manner so as to contact the second interconnection member 140. The first redistribution layer 112a and the second redistribution layer 112b of the first interconnect member 110 may be disposed at a level between the active surface and the passive surface of the semiconductor wafer 120. The first interconnect member 110 may be formed to a thickness corresponding to the thickness of the semiconductor wafer 120. Therefore, the first redistribution layer 112a and the second redistribution layer 112b formed in the first interconnection member 110 may be disposed at a level between the active surface and the passive surface of the semiconductor wafer 120.

The thickness of the redistribution layer 112a, the redistribution layer 112b, the redistribution layer 112c, and the redistribution layer 112d of the first interconnection member 110 may be greater than the thickness of the redistribution layer 142 of the second interconnection member 140. Since the first interconnection member 110 may have a thickness equal to or greater than the thickness of the semiconductor wafer 120, the redistribution layer 112a, the redistribution layer 112b, the redistribution layer 112c, and the redistribution layer 112d may also be Formed into large. On the other hand, the redistribution layer 142 of the second interconnection member 140 may be formed to have a relatively small size to achieve thinness.

Descriptions of architectures other than the above-mentioned architectures may overlap with those provided above, and therefore will not be repeated here. In addition, in addition to the architecture of the first interconnect member 110, the description of the manufacturing process of the fan-out semiconductor package 100J may overlap with the description provided above, and therefore will not be repeated here. Meanwhile, the features of the fan-out semiconductor package 100B to the fan-out semiconductor package 100H can also be applied to the fan-out semiconductor package 100J.

FIG. 26 is a schematic diagram illustrating a situation in which warpage is generated in the fan-out type semiconductor package.

Referring to the drawings, a thermosetting resin film that can firmly fix the first interconnect member 510 and the semiconductor wafer 520 can be used as a material for encapsulating the first interconnect member 510 and the encapsulation body 530 of the semiconductor wafer 520, the first mutual The connecting member 510 includes an insulating layer 511, a redistribution layer 512a and a redistribution layer 512b, a via window 513, and the like. The semiconductor wafer 520 includes a main body 521, an electrode pad 522, and the like. In detail, the encapsulation body 530 may be formed using a thermosetting resin film having a high thermal expansion coefficient, which generally has good resin fluidity, so that the space of the through hole 510H between the first interconnect member 510 and the semiconductor wafer 520 It is completely filled with resin and enhances the close adhesion between the first interconnect member 510 and the semiconductor wafer 520. However, it can be understood that in such a thermosetting resin film, the thermosetting shrinkage of the resin is large, which in turn causes severe warpage W1 in the package after the resin is hardened. Therefore, it may be difficult to form a fine circuit pattern later.

FIG. 27 is a schematic diagram illustrating a situation in which the warpage of the fan-out semiconductor package is suppressed.

FIG. 28 is a schematic diagram illustrating other problems that occur in FIG. 27. FIG.

Referring to the drawings, it may be considered to use a thermosetting resin film having a low coefficient of thermal expansion as the material for encapsulating the first interconnect member 510 and the encapsulating body 540 of the semiconductor wafer 510, the first interconnect member 510 includes an insulating layer 511, The rewiring layer 512a and the rewiring layer 512b, the via 513, etc., the semiconductor wafer 510 includes a main body 521, electrode pads 522, etc. It can be understood that in the case of using a thermosetting resin film having a low coefficient of thermal expansion as the material of the encapsulation body 540, the warpage W2 is suppressed compared to the case of using a thermosetting resin film having a high coefficient of thermal expansion. However, in order to reduce the coefficient of thermal expansion, the content of the inorganic filler in the thermosetting resin film is generally increased, so that the resin cannot sufficiently fill fine spaces due to the decrease in the fluidity of the resin, which may cause voids and the like. In addition, delamination between the first interconnect member and the semiconductor wafer may occur due to a reduction in the close adhesion between the first interconnect member and the semiconductor wafer.

FIG. 29 is a graph for comparing the effect of suppressing warpage between the fan-out semiconductor packages.

Referring to the drawings, Comparative Example 1 refers to a case where a thermosetting resin film having a high coefficient of thermal expansion having good resin fluidity is used as the material of the encapsulation body as shown in FIG. 26. It is understandable that in Comparative Example 1, severe warpage occurs due to the high heat-hardening shrinkage of the encapsulated body. Comparative Example 2 refers to a case where a thermosetting resin having a low coefficient of thermal expansion is used as the material of the encapsulation body as shown in FIG. 27 to suppress warpage. In Comparative Example 2, the warpage may be suppressed due to the low thermosetting shrinkage of the encapsulated body, but the above-mentioned problems such as voids and delamination also occur. The example of the present invention refers to a material in which a thermosetting resin film having a high coefficient of thermal expansion with good resin flowability is used as the material of the encapsulation as in the present invention, and the elasticity of the encapsulation is introduced on the encapsulation In the case of a reinforced layer having a large modulus of elasticity and having a coefficient of thermal expansion smaller than that of the encapsulation. In the examples of the present invention, warpage can be suppressed at a level similar to that of Comparative Example 2 without causing problems such as voids and delamination.

As described above, according to the exemplary embodiments in the present invention, it is possible to provide a fan-out type semiconductor package in which the warpage problem can be effectively solved.

Although the exemplary embodiments have been shown and described above, it will be obvious to those skilled in the art that modifications and modifications can be made without departing from the scope of the invention defined by the scope of the accompanying patent application transform.

100‧‧‧Semiconductor package
100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, 100J, 2100 ‧‧‧‧Fan-out semiconductor package
110、510‧‧‧The first interconnecting member
110H, 510H‧‧‧Through hole
111a‧‧‧First insulation layer
111b‧‧‧Second insulation layer
111c‧‧‧The third insulating layer
112a‧‧‧First wiring layer
112b‧‧‧Second redistribution layer
112c‧‧‧ Third wiring layer
112d‧‧‧ Fourth wiring layer
113a‧‧‧First interlayer window
113b‧‧‧Second via
120, 520, 2120, 2220 ‧‧‧ semiconductor chip
121, 521, 1101, 2121, 2221
122, 2122, 2222 ‧‧‧ connection pad
123, 150, 2150, 2223, 2250‧‧‧protection layer
130, 530, 540, 2130
140‧‧‧Second interconnecting member
141a, 141b, 511, 2141, 2241‧‧‧Insulation
142, 142a, 142b, 512a, 512b, 2142 ‧‧‧ redistribution layer
143a, 143b, 513, 2143, 2243
150H, 181H, 182H, 185H, 2251‧‧‧ opening
160, 2160, 2260 ‧‧‧ under bump metal layer
170‧‧‧Connecting terminal
181, 183, 184, 185, 186
182‧‧‧Resin layer
183P, 184P, 186P‧‧‧Bent part
184a‧‧‧One side of the reinforcement layer 184
184b‧‧‧The other side of the reinforcement layer 184
184c‧‧‧Core material
301‧‧‧Carrier film
302, 303‧‧‧ metal layer
304‧‧‧Dry film
305‧‧‧ Adhesive film
522‧‧‧electrode pad
1000‧‧‧Electronic device
1010, 1110, 2500‧‧‧ Motherboard
1020‧‧‧chip related components
1030‧‧‧Network-related components
1040‧‧‧Other components
1050, 1130‧‧‧ camera module
1060‧‧‧ Antenna
1070‧‧‧Display device
1080‧‧‧Battery
1090‧‧‧Signal line
1100‧‧‧Smartphone
1120‧‧‧Electronic components
2140, 2240
2170, 2270‧‧‧ solder balls
2200‧‧‧Fan-in semiconductor package
2242‧‧‧Rewiring layer
2243h‧‧‧Interlayer window
2280‧‧‧Bottom filling resin
2290‧‧‧Molding material
2301, 2302‧‧‧Intermediate substrate
t1, t2, t3 ‧‧‧ thickness
W1, W2‧‧‧‧Warpage
I-I'‧‧‧ line

The above and other aspects, features, and advantages of the present invention will be more clearly understood by reading the following detailed description in conjunction with the drawings. In the drawings: FIG. 1 is a schematic block diagram illustrating an example of an electronic device system. 2 is a schematic perspective view illustrating an example of an electronic device. 3A and 3B are schematic cross-sectional views illustrating the state of the fan-in semiconductor package before and after being packaged. 4 is a schematic cross-sectional view illustrating a packaging process of a fan-in semiconductor package. 5 is a schematic cross-sectional view illustrating a situation in which a fan-in type semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic device. 6 is a schematic cross-sectional view illustrating a situation in which a fan-in type semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic device. 7 is a schematic cross-sectional view illustrating a fan-out type semiconductor package. 8 is a schematic cross-sectional view illustrating a situation in which a fan-out type semiconductor package is mounted on a main board of an electronic device. 9 is a schematic cross-sectional view illustrating an example of a fan-out type semiconductor package. FIG. 10 is a schematic plan view taken along line I-I' of the fan-out type semiconductor package shown in FIG. 9. 11A to 11D are schematic cross-sectional views illustrating various forms of vias formed in the first interconnect member of the fan-out type semiconductor package shown in FIG. 9. 12 to 16 are schematic diagrams illustrating an example of the manufacturing process of the fan-out semiconductor package shown in FIG. 9. 17 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package. 18 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package. 19 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package. 20 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package. 21 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package. 22 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package. 23 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package. 24 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package. 25 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package. FIG. 26 is a schematic diagram illustrating a situation in which warpage is generated in the fan-out type semiconductor package. FIG. 27 is a schematic diagram illustrating a situation in which the warpage of the fan-out semiconductor package is suppressed. FIG. 28 is a schematic diagram illustrating other problems that occur in FIG. 27. FIG. FIG. 29 is a graph for comparing the effect of suppressing warpage between the fan-out semiconductor packages.

2100‧‧‧Fan-out semiconductor package

2120‧‧‧Semiconductor chip

2121‧‧‧Main

2122‧‧‧ connection pad

2130‧‧‧Encapsulated body

2140‧‧‧Interconnecting components

2141‧‧‧Insulation

2142‧‧‧Rewiring layer

2143‧‧‧Interlayer window

2150‧‧‧Protection layer

2160‧‧‧ under bump metal layer

2170‧‧‧ solder ball

Claims (30)

A fan-out type semiconductor package includes: a first interconnect member having a through hole; a semiconductor wafer disposed in the through hole of the first interconnect member and having an active surface and an opposite surface to the active surface A passive surface on which a connection pad is placed; an encapsulation body that encapsulates at least some parts of the first interconnect member and at least some parts of the passive surface of the semiconductor wafer; a second mutual A connecting member disposed on the first interconnect member and the active surface of the semiconductor wafer; and a reinforcing layer disposed on the encapsulation body, wherein the first interconnect member and the first The two interconnecting members respectively include a redistribution layer that is electrically connected to the connection pad of the semiconductor wafer. The fan-out semiconductor package as described in item 1 of the patent application range, wherein the reinforcing layer has an elastic modulus greater than that of the encapsulation body. The fan-out semiconductor package as described in item 1 of the patent application range, wherein the reinforcing layer has a thermal expansion coefficient lower than that of the encapsulation body. The fan-out semiconductor package as described in item 1 of the patent application range, wherein the reinforcement layer includes a core material, an inorganic filler, and an insulating resin. The fan-out semiconductor package as described in item 4 of the patent application scope further includes a resin layer disposed on the reinforcement layer, wherein the resin layer includes an inorganic filler and an insulating resin. The fan-out semiconductor package according to item 5 of the patent application scope further includes an opening that penetrates through the resin layer, the reinforcement layer, and the encapsulation body, and exposes the first mutual At least some parts of the rewiring layer of the connecting member. The fan-out semiconductor package as described in item 5 of the scope of the patent application further includes a protective layer disposed on the second interconnecting member, wherein the protective layer includes an inorganic filler and an insulating resin. The fan-out type semiconductor package as described in item 7 of the patent application range, wherein the composition of the resin layer and the composition of the protective layer are the same as each other. The fan-out type semiconductor package as described in item 4 of the patent application range, wherein the encapsulation body includes an inorganic filler and an insulating resin, and the weight percentage of the inorganic filler contained in the reinforcement layer is greater than that contained in the The weight percentage of the inorganic filler in the encapsulation. The fan-out type semiconductor package as described in item 9 of the patent application range, wherein the weight percentage of the inorganic filler contained in the side of the reinforcement layer in contact with the encapsulation body and that contained in the reinforcement The weight percentages of the inorganic filler in the other side of the layer opposite to the one side with respect to the core material are different from each other. The fan-out semiconductor package as described in item 10 of the patent application scope, wherein a1 <a2 <a3, where a1 is the weight percentage of the inorganic filler contained in the encapsulation body, and a2 is contained in the reinforcing layer The weight percentage of the inorganic filler in the one side in contact with the encapsulated body, and a3 is the inorganic contained in the other side of the reinforcing layer opposite to the one side Weight percentage of filler. The fan-out semiconductor package as described in item 1 of the patent application range, wherein the reinforcing layer includes an inorganic filler and an insulating resin but does not include a core material. The fan-out semiconductor package as described in item 12 of the patent application range, wherein the encapsulation body contains an inorganic filler and an insulating resin, and the weight percentage of the inorganic filler contained in the reinforcement layer is greater than that contained in the The weight percentage of the inorganic filler in the encapsulation. The fan-out semiconductor package as described in item 1 of the patent application scope further includes a protective layer disposed on the second interconnecting member, wherein the protective layer includes an inorganic filler and an insulating resin. The fan-out type semiconductor package as described in item 14 of the patent application range, wherein the second interconnecting member includes an insulating layer including an inorganic filler and an insulating resin, and the inorganic filler contained in the protective layer The weight percentage is greater than the weight percentage of the inorganic filler contained in the insulating layer of the second interconnecting member. The fan-out type semiconductor package as described in item 1 of the patent application range, wherein the boundary surface between the reinforcing layer and the encapsulation body has a surface between the inner wall of the through hole and the semiconductor wafer The curved part of space bending. The fan-out semiconductor package as described in item 1 of the patent application range, wherein the reinforcement layer has a thickness that is greater than that of the first portion of the encapsulation body covering the first interconnecting member and the encapsulation body The thickness of the second portion covering the passive surface of the semiconductor wafer is large. The fan-out type semiconductor package as described in item 1 of the patent application range, wherein the first interconnect member includes a first insulating layer, a first rewiring layer, and a second rewiring layer, the first rewiring layer In contact with the second interconnecting member and embedded in the first insulating layer, the second redistribution layer is disposed between the first insulating layer and the first insulating layer in which the first A surface of a redistribution layer is opposite to the other surface, and the first redistribution layer and the second redistribution layer are electrically connected to the connection pad. The fan-out semiconductor package as described in item 18 of the patent application range, wherein the first interconnecting member further includes a second insulating layer and a third redistribution layer, and the second insulating layer is disposed on the first The second rewiring layer is covered on the insulating layer, the third rewiring layer is disposed on the second insulating layer, and the third rewiring layer is electrically connected to the connection pad. The fan-out semiconductor package as described in item 19 of the patent application range, wherein the second redistribution layer is disposed at a level between the active surface and the passive surface of the semiconductor wafer. The fan-out type semiconductor package according to item 18 of the patent application range, wherein the distance between the redistribution layer of the second interconnection member and the first redistribution layer is greater than that of the second interconnection The distance between the redistribution layer of the component and the connection pad. The fan-out type semiconductor package of claim 18, wherein the first redistribution layer has a thickness greater than that of the redistribution layer of the second interconnection member. The fan-out semiconductor package as described in item 18 of the patent application range, wherein the lower surface of the first redistribution layer is disposed at a level higher than the lower surface of the connection pad. The fan-out type semiconductor package as described in item 1 of the patent application scope, wherein: the first interconnecting member includes a first insulating layer, and the first insulating layer is respectively disposed on two opposite surfaces of the first insulating layer A heavy wiring layer and a second heavy wiring layer, a second insulating layer disposed on the first insulating layer and covering the first heavy wiring layer, and a third heavy wiring layer disposed on the second insulating layer And the first rewiring layer to the third rewiring layer are electrically connected to the connection pad. The fan-out semiconductor package as described in item 24 of the patent application range, wherein the first interconnecting member further includes a third insulating layer disposed on the first insulating layer and covering the second redistribution layer And a fourth redistribution layer disposed on the third insulating layer, and the fourth redistribution layer is electrically connected to the connection pad. The fan-out type semiconductor package as described in item 24 of the patent application range, wherein the first insulating layer has a thickness greater than that of the second insulating layer. The fan-out type semiconductor package as described in item 24 of the patent application range, wherein the third redistribution layer has a thickness greater than that of the redistribution layer of the second interconnection member. The fan-out semiconductor package as described in item 24 of the patent application range, wherein the first redistribution layer is disposed at a level between the active surface and the passive surface of the semiconductor wafer. The fan-out type semiconductor package as described in item 24 of the patent application range, wherein the lower surface of the third redistribution layer is disposed at a level lower than the lower surface of the connection pad. The fan-out semiconductor package as described in item 1 of the patent application range, wherein the boundary surface between the encapsulation body and the reinforcement layer has an approximately linear shape.