TW201701400A - A manufacturing method of a dual damascene - Google Patents

Abstract

The present invention provides a manufacturing method of a dual damascene, which comprises the following steps. Step (S1) is to provide a substrate having a side; step (S2) is to form a patterned dielectric interlayer on the side of the substrate, wherein a first trench is formed in the patterned dielectric interlayer; step (S3) is to form a dielectric layer on the patterned dielectric interlayer and in the first trench, wherein a plurality of voids is formed in an vertical area of the dielectric layer covered by the first trench; step (S4) is to form a patterned hard mask on the dielectric layer, wherein an opening is formed on the patterned hard mask covering and bigger than the first trench; step (S5) is to perform an etching process using the patterned hard mask as a mask to remove a portion of the dielectric layer in order to expose a portion of the substrate and form a second trench; and step (S6) is to form a conductor line layer in the second trench.

Description

Double damascene process

The present invention relates to a dual damascene process, and more particularly to a dual damascene process having an effect of easier control of the etch back process and less residue.

As the semiconductor industry develops ultra-large-scale integrated circuit (ULSI) components, shrinking components to sub-half micron sizes increases circuit density, resulting in RC delay and copper reactive ion etching (RIE). In a process of forming a bit line pattern for a reduced size component, the pattern may be bridged or collapsed.

In order to avoid bridging and/or collapse of the pattern, and in order to improve the layout of the components, a dual damascene process has been developed. The dual damascene method is applied when the metal material is not likely to be patterned by conventional etching techniques due to the reduction in the size of the element, or when the dielectric material is filled in a deep contact etching process to form a conventional metal wire. The interconnection between the layers of copper includes vertically connected vias and horizontally connected metal wires. In a dual damascene process, a plug material is used to fill the via and then etch back the material.

However, due to the shrinking of the size, in the prior art, the control of the etch back process is not easy, and at the same time, the etching residue is easily caused, resulting in a product yield that is not as expected, resulting in waste of cost and man-hours. Therefore, the present invention provides A method of forming a dual damascene structure to modify the problems of the prior art.

The present invention provides a dual damascene process, the steps comprising: (S1) providing a substrate having one side; (S2) forming a patterned interposer on the side of the substrate, wherein the patterned interposer is formed with a first trench; (S3) forming a dielectric layer on the patterned interposer and filling the first trench, wherein a plurality of holes are formed in a portion of the dielectric layer in a direction perpendicular to the first trench cover area; (S4) Forming a patterned mask layer on the dielectric layer, the patterned mask layer is formed with an opening, wherein the opening covers and is larger than the first trench; (S5) performing an etching process to pattern the mask layer as a mask, removing a portion of the dielectric layer to expose a portion of the substrate and form a second trench; and (S6) to form a wire layer in the second trench.

In a preferred embodiment of the invention, the substrate may be an integrated circuit.

In a preferred embodiment of the present invention, the substrate includes: an element layer; a substrate etch stop layer formed on the side of the element layer adjacent to the patterned interposer; and a contact region formed in the element layer Adjacent to the substrate etch stop layer, corresponding to the bottom surface of the second trench.

In a preferred embodiment of the invention, the second etch in step (S5) described above is stopped at the substrate etch stop layer.

In a preferred embodiment of the present invention, the step (S5) includes: (51) performing a first etching process to pattern the mask layer as a mask, removing a portion of the dielectric layer exposed by the opening, and exposing a portion of the substrate Etching the termination layer to form an intermediate trench; and (52) performing a second etching process to pattern the interposer as a mask to remove a portion of the substrate etch stop layer exposed by the intermediate trench.

In a preferred embodiment of the present invention, in the above step (S3), the dielectric layer is formed by a chemical vapor deposition method using at least two precursors.

In a preferred embodiment of the invention, the dielectric layer of the dielectric layer is often The number (k) is less than 3.5.

In a preferred embodiment of the invention, the patterned interposer includes: an etch stop layer; and a dielectric layer between the intervening etch stop layer and the substrate.

Therefore, according to the double damascene process provided by the present invention, the residue of the etch back process can be reduced, thereby achieving the effect of improving the yield of the product. At the same time, due to the generation of holes, the efficiency of the etchback process is improved, so that the cost of the process can be saved. .

11, 21‧‧‧ substrate

12, 22‧‧‧ patterned intermediary

13, 23‧‧‧Intermediary

14, 24‧‧‧ wire layer

111, 211‧‧‧ component layer

112, 212‧‧‧ substrate etching stop layer

113, 213‧‧ ‧ contact area

121, 221‧‧‧ dielectric layer

122, 222‧‧ ‧ etch stop layer

131‧‧‧Oxide layer

132, 232‧‧ ‧ protective layer

231‧‧‧Low dielectric constant layer

G1‧‧‧ gap

O1, O2‧‧‧ openings

S1, S2‧‧‧ one side of the substrate

T11, T12, T13, T21, T22, T23‧‧‧ trench

V1‧‧‧ hole

The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the invention. A cross-sectional view of a process step structure drawn in an embodiment; and FIGS. 6-10 are cross-sectional views of a process step structure drawn in accordance with another embodiment of the present invention.

The invention provides a double damascene process, which utilizes the adjustment of the interposer holes backfilled in the trenches, improves the effect and accuracy of the subsequent etchback process, and reduces the residue of the etchback process, thereby improving the product quality. The effect of the rate. At the same time, due to the generation of holes, the efficiency of the etchback process is improved, so that the cost of the process can be saved. The above and other objects, features, and advantages of the present invention will become more apparent and understood.

1 to FIG. 5 are schematic cross-sectional views showing different steps in a process step of a dual damascene process according to an embodiment of the invention. As shown in FIG. 1, a substrate 11 is provided. The substrate 11 can be a semiconductor substrate, and is applied to an integrated circuit, a ceramic substrate, and a photoelectric device. Any substrate required in microelectronic fabrications such as (optoelectronic). The substrate 11 has a first side S1 and includes an element layer 111, a substrate etch stop layer 112 on the first side S1 of the element layer 111, and a contact region 113 in the element layer 111 adjacent to the substrate etch stop layer 112. . Next, as shown in FIG. 2, a patterned interposer 12 is formed on the first side S1 of the substrate 11, and the patterned interposer 12 is formed with a trench T11. The patterned interposer 12 can include a dielectric layer 121 and an etch stop layer 122 on the first side S1 of the dielectric layer 121. The method of forming the trench T11 may be an etching process, and the etching method and/or the etching liquid may be selected according to the material of the patterned interposer 12, which will not be described herein. Next, as shown in FIG. 3, an interposer 13 is formed, which comprises a hafnium oxide layer 131 and a protective layer 132 on the first side S1 of the oxide layer 131. In this embodiment, an undoped silicon oxide is used. (USG)) As the yttrium oxide layer 131, and utilizing the poor deposition characteristics of the USG gap, the USG is rapidly deposited in the trench T11 to cause the void G1 to be generated in the trench T11. Then, as shown in FIG. 4, a patterned mask layer PR1 is formed on the first side S1 of the interposer 13, wherein the patterned mask layer PR1 is formed with an opening O1 corresponding to and larger than the trench T11. Then, the etchback process is performed by using the patterned mask layer PR1 as a mask, and a portion of the interposer 13 and the partially patterned interposer 12 corresponding to the opening O1 are removed to form the trench T12 in the interposer 13 and the patterned interposer 12. , under the opening O1.

Finally, as shown in FIG. 5, the patterned mask layer PR1 is removed, and a portion of the substrate etch stop layer 112 corresponding to the bottom of the trench T12 is removed to expose the contact region 113 and form the trench T13, and then fill in the wiring layer. 14 is in the trench T13. The planarization process is selectively performed such that the upper surface of the filled wiring layer 14 is coplanar with the upper surface of the interposer 13. The order of removing the portion of the substrate etch stop layer 112 at the bottom of the patterned mask layer PR1 and the trench T12 may be adjusted according to a process. The material of the wire layer 14 may be copper or other suitable metal or conductive material to be electrically The contact area 113 is connected. In addition, due to the relationship between material selection and process condition setting, a portion of the substrate etch stop layer 112 and/or the etch stop layer 122 may be removed simultaneously during the etch back step. In addition to the portion of the substrate etch stop layer 112 at the bottom of the second trench T12, it is also possible to simultaneously remove portions or etch stop layers 122 and/or thinned protective layers 132 (not shown).

Since the portion of the trench is less easily removed during the etching process, the method according to the present invention provides a void in the trench, and an etching rate of a portion of the oxide layer in the trench is increased, thereby improving etching accuracy and improving In the conventional process, the control of the etchback process is not easy, and the product yield is improved. Although the above embodiment can improve the accuracy of the etch back process in the conventional process, the inventors have further found that, according to the method of the above embodiment, there is still some problem of residue after the etch back process. After many tests and experiments, it is considered that the voids generated in the USG used in the yttrium oxide layer 131 are difficult to control the void size due to deposition, and often only a single void is generated, so that it is difficult to control the distribution, resulting in subsequent Possible residual problems in the etching process. Accordingly, after the inventors have adjusted the experimental conditions several times, another embodiment is provided to illustrate the following, in order to have better control of the etchback process, solve the problem of residue after the etch back process, and at the same time achieve the improvement of the product yield. The effect.

6-10 are schematic cross-sectional views showing different steps in a process step of a dual damascene process according to another embodiment of the present invention. As shown in FIG. 6, a substrate 21 is provided, and the substrate 21 may be a semiconductor substrate. 6 to FIG. 10 are schematic cross-sectional views showing different steps in a process step of a dual damascene process according to another embodiment of the present invention. As shown in FIG. 6, a substrate 21 is provided. The substrate 21 can be a semiconductor substrate and is used in a microelectronic fabrication process such as an integrated circuit, a ceramic substrate, or an optoelectronic. The substrate. The substrate 21 has a second side S2 and includes an element layer 211, a substrate etch stop layer 212 on the second side S2 of the element layer 211, and a contact region 213 in the element layer 211 adjacent to the substrate etch stop layer 212. . Next, as shown in FIG. 7, a patterned interposer 22 is formed on the second side S2 of the substrate 21, and is patterned. The via 22 is formed with a trench T21. The patterned interposer 22 can include a dielectric layer 221 and an etch stop layer 222 on the second side S2 of the dielectric layer 221. The method of forming the trench T21 may be an etching process, and the etching method and/or the etching solution may be adjusted according to the material of the patterned interposer 22, and details are not described herein. Next, as shown in FIG. 8, an interposer 23 is formed which includes a low dielectric constant (low-k) layer 231 and a protective layer 232 on the second side S2 of the low dielectric constant layer 231. The dielectric constant (k) of the low dielectric constant layer 231 is less than 3.5, and in the forming step, the UV curing is used to adjust the hole size and distribution, thereby forming a plurality of holes V1 in the portion corresponding to the groove T21. In the low dielectric constant layer 231. The hole V1 may be distributed only in the trench T21 or partially formed in the trench T21 and partially formed in the portion of the low dielectric constant layer 231 on the trench T21. In this embodiment, the hole V1 is only distributed in the trench V1. In the groove T21. Then, as shown in FIG. 9, a patterned mask layer PR2 is formed on the second side S2 of the interposer 23, wherein the patterned mask layer PR2 is formed with an opening O2 corresponding to and larger than the trench T21. Then, the masking layer PR2 is used as a mask to perform an etch back process, and a portion of the interposer 23 and the partially patterned interposer 22 corresponding to the opening O2 are removed to form the trench T22 in the interposer 23 and the patterned interposer 22. , under the opening O2.

Finally, as shown in FIG. 10, the patterned mask layer PR2 is removed, and a portion of the substrate etch stop layer 212 corresponding to the bottom of the trench T22 is removed to expose the contact region 213 and form the trench T23, and then fill in the wiring layer. 24 is in the trench T23. The planarization process is selectively performed such that the upper surface of the filled wiring layer 24 is coplanar with the upper surface of the interposer 23. The order of removing the portion of the substrate etch stop layer 212 at the bottom of the patterned mask layer PR2 and the trench T22 may be adjusted according to a process. The material of the wire layer 24 may be copper or other suitable metal or conductive material to be electrically The contact area 213 is connected. In addition, due to the relationship between material selection and process condition setting, a portion of the substrate etch stop layer 212 and/or the etch stop layer 222 may be removed simultaneously in the etch back step, and a portion of the substrate etch stop layer 212 at the bottom of the trench T22 is removed. In the step, it is also possible to remove portions or etch stop layer 222 and/or thinned protective layer 232 (not shown).

In this embodiment, the substrate etch stop layer 212 has a thickness of about 600 angstroms (Å) and contains non-diamond carbon; the material of the dielectric layer 221 is ethyl orthosilicate (TEOS). And having a thickness of about 6000 angstroms; the material of the etch stop layer 222 is selected from cerium oxynitride (SiON) and has a thickness of about 1350 angstroms; and the low dielectric constant layer 231 is formed by chemical vapor deposition using a single precursor, and The thickness of the portion on the etch stop layer 222 is about 9000 angstroms; the width of the opening O2 is about 360 nanometers (nm).

The thickness of each layer and the selected materials can be adjusted according to requirements. In other embodiments, the substrate etch stop layer 212 has a thickness of 500-700 Å (Å), and may or may not contain non-diamond crystal carbon (non- The material of the dielectric layer 221 is bismuth oxynitride or lanthanum oxide, and the thickness thereof is between 5000 and 7000 angstroms; the material of the etch stop layer 222 is yttrium oxynitride (SiON) or tantalum nitride, and the thickness is selected. Between 1000-2000 angstroms. The etch stop layer 222 can also be a multi-layer structure. As in another embodiment of the present invention, the etch stop layer 222 includes a tantalum nitride layer having a thickness between 1500 and 1900 angstroms, and a layer on the tantalum nitride layer. Partial oxidation of methane (MEPOX), which is depicted in the drawings, has a thickness between 20 and 100 angstroms. This section can be adjusted according to different applications, so do not repeat them. The low dielectric constant layer 231 can also be formed using two or more precursors, for example, two or more kinds of low dielectric constant materials, or low dielectric constant materials and cerium oxide. In another embodiment of the invention, the low dielectric constant layer 231 has a dielectric constant (k) of less than 3.

According to another embodiment of the present invention, after forming the patterned interposer 22, before forming the low dielectric constant layer 231, an oxide layer may be selectively formed on the patterned interposer 22 and the trench T21 (not drawn Shown), and the portion of the oxide layer corresponding to the bottom of the trench T21 is removed in the post process. The etching selectivity can be adjusted according to the materials used. The partial oxide layer can be removed simultaneously with the removal of a portion of the low dielectric constant layer 231, or with the removal of a portion of the dielectric layer 221, or more An additional etching step removes the partial oxide layer.

Therefore, the double damascene process provided by the present invention can adjust the holes generated in the trench by the low dielectric constant layer according to different applications and processes, so that the part of the etch back step in the trench can be more precise, and the conventional process is improved. In the process of controlling the etch back process, it is easy to cause problems such as etching residues, thereby improving product yield, avoiding cost and waste of working hours.

Although the present invention has been disclosed above by way of example, it is not intended to limit the invention. Anyone having ordinary knowledge in the field can make some changes and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

21‧‧‧Substrate

22‧‧‧ patterned intermediary

23‧‧‧Intermediary

24‧‧‧ wire layer

211‧‧‧ component layer

212‧‧‧Substrate Etch Stop Layer

213‧‧‧Contact area

221‧‧‧ dielectric layer

222‧‧‧etch stop layer

232‧‧‧Protective layer

231‧‧‧Low dielectric constant layer

O2‧‧‧ openings

One side of the S2‧‧‧ substrate

T21, T22, T23‧‧‧ trench

V1‧‧‧ hole

Claims (11)

A dual damascene process, the method comprising: (S1) providing a substrate having one side; (S2) forming a patterned interposer on the side of the substrate, wherein the patterned interposer is formed with a first trench; (S3) forming a dielectric layer on the patterned interposer and filling the first trench, wherein a plurality of holes are formed in a portion of the dielectric layer in a direction perpendicular to the first trench cover area (S4) forming a patterned mask layer on the dielectric layer, the patterned mask layer is formed with an opening, wherein the opening covers and is larger than the first trench; (S5) performing an etching process to The patterned mask layer is a mask, a portion of the dielectric layer is removed to expose a portion of the substrate and a second trench is formed; and (S6) a wire layer is formed in the second trench. The dual damascene process of claim 1, wherein the substrate can be an integrated circuit. The dual damascene process of claim 1, wherein the substrate comprises: an element layer; a substrate etch stop layer formed on the side of the element layer adjacent to the patterned interposer; A contact region is formed in the element layer adjacent to the substrate etch stop layer and corresponds to a bottom surface of the second trench. The dual damascene process of claim 3, wherein the etching in the step (S5) is stopped at the substrate etch stop layer. The double damascene process of claim 3, wherein the step (S5) comprises: (51) performing a first etching process, using the patterned mask layer as a mask, and removing the opening to expose Part of the dielectric layer, and exposing a portion of the substrate etch stop layer to form an intermediate trench; and (52) performing a second etching process to mask the interposer as a mask to remove the intermediate trench A portion of the substrate etches the stop layer. The double damascene process of claim 1, wherein in the step (S3), the method of forming the dielectric layer is a chemical vapor deposition method using at least two precursors. The dual damascene process of claim 1, wherein the step (S2) and the step (S3) further comprise: (S21) conforming to form an oxide layer on the first trench and the On the patterned interposer; and wherein in the step (S5), the etching process simultaneously removes the oxide layer corresponding to the opening. The dual damascene process of claim 1, wherein the dielectric layer has a dielectric constant (k) of less than 3.5. The dual damascene process of claim 1, wherein the dielectric layer is a low dielectric constant layer. The dual damascene process of claim 1, wherein the patterned interposer comprises: an etch stop layer; and a dielectric layer between the intervening etch stop layer and the substrate. The dual damascene process of claim 10, wherein the etching in the step (S5) is stopped at the etch stop layer.