Ϊ295083 九、發明說明： 【發明領域】 本發明係提供一種雙鑲嵌導線製程，由指一種結合低介電常數 材料與銅的雙鑲嵌導線製程。 【背景說明】 銅雙鑲嵌(dual damascene)技術搭配低介電常數材料所構成的 金屬間介電層(inter metal dielectric，IMD)是目前最被廣泛應用的 金屬内連線製程組合，尤其針對高積集度、高速(high-speed)邏輯 積體電路晶片製造以及〇· 18微米以下的深次微米(deep sub-micrc)) 半導體製程。這是由於銅具有低電阻值(比鋁低30%)以及抗電致遷 (electromigrationresistance)的特性，而低介電常數材料則可幫助降 低金屬導線之間的RC延遲(RC delay)效應。因此，銅金屬雙鑲嵌内 連線技術在積體電路製程中顯得日益重要，而且勢必將成為下一 世代半導體製程的標準内連線技術。 請參閱圖一，圖一為一典型之雙鑲嵌結構n的剖面示意圖。 如圖一所示，雙鑲嵌結構U係形成於一半導體晶片1〇上之介電層 20中’其包括有一下部接觸窗(via)結構22以及一上部溝渠結構 23。半導體晶片1〇另包含有一下層導線14形成於一介電層12中， 以及一上層銅導線24填入於上部溝渠結構23中，而上層銅導線24 以及下層導線14係藉由一接觸插塞(via piUg)22a穿過介電層12以 及介電層20之間保護層18互相連結。 1295083 為了防止填人雙驗結構財_金屬擴散 :，因娜梅於讎結_絲崎—轉(bamer) 一般而言，阻障層25至少需具備有下列條件：⑴良好的擴 散阻絕特性；（2)對於銅金屬以及介電層有良好的_力；⑶電 阻^不能過高(<聊W_em);(4)良好__能力。所以 目則常用的阻障層材料包括有鈦、氮化鈦()、氮化峰N)、以 及氮化鶴(WN)等等。 然而，習知的雙鑲嵌銅製程往往會觀察到有接觸窗開口(via (轉)現象發生。接_則現象主要是由_金屬經由阻障層25 中的裂縫流失擴散至介電層2〇中，進而導致上層銅導線％以及下 層導線14之間無法導通，構成元件或電路失效。這種現象在當介 電層20採用熱膨脹係數(thermal expansion coefficient)較高的低介 電常數材料或多孔結構介電層時，更顯得特別嚴重。例如以 SiLKTM作為介電層2〇以及氮化鈕(TaN)作為阻障層25的銅金屬雙 鑲嵌銅製程為例，由於SiLKTM、銅金屬錢氮化鈕(遍)的熱膨 脹係數分別為6〇ppm/°C、17ppm/°C以及3ppm/t：，因此當完成金屬 化的半導體晶片1〇再次經歷熱製程之後，siLKTM介電層2〇所產生 的熱應力會導致熱膨脹係數較低的氮化组阻障層25破裂 (cracking)，進而造成接觸窗開口。 【發明概述】 因此，本發明之主要目的在於提供一種雙鑲嵌製程方法，以解Ϊ295083 IX. INSTRUCTIONS: FIELD OF THE INVENTION The present invention provides a dual damascene wire process, which is a dual damascene wire process that combines a low dielectric constant material with copper. [Background] The inter-metal dielectric (IMD) composed of dual damascene technology and low dielectric constant material is currently the most widely used metal interconnect process combination, especially for high Accumulation, high-speed logic integrated circuit chip fabrication, and deep sub-micrc semiconductor processes below 18 microns. This is due to the fact that copper has low resistance values (30% lower than aluminum) and resistance to electromigration resistance, while low dielectric constant materials help reduce the RC delay between metal wires. Therefore, copper-metal dual damascene interconnect technology is becoming increasingly important in integrated circuit fabrication and is bound to become the standard interconnect technology for next-generation semiconductor processes. Please refer to FIG. 1. FIG. 1 is a schematic cross-sectional view of a typical dual damascene structure n. As shown in FIG. 1, the dual damascene structure U is formed in a dielectric layer 20 on a semiconductor wafer 1 which includes a lower via structure 22 and an upper trench structure 23. The semiconductor wafer 1 further includes a lower layer conductor 14 formed in a dielectric layer 12, and an upper copper conductor 24 filled in the upper trench structure 23, and the upper copper conductor 24 and the lower conductor 14 are connected by a contact plug. (via piUg) 22a is connected to each other through the protective layer 18 between the dielectric layer 12 and the dielectric layer 20. 1295083 In order to prevent the filling of the double-check structure of the structure _ metal diffusion: Ina Mei in the knot _ silk-sale - bamer Generally speaking, the barrier layer 25 must have at least the following conditions: (1) good diffusion resistance characteristics; (2) Good _ force for copper metal and dielectric layer; (3) resistance ^ can not be too high (<Talk W_em); (4) Good __ ability. Therefore, commonly used barrier materials include titanium, titanium nitride (), nitride peak N), and nitrided crane (WN). However, the conventional double damascene copper process often observes a contact opening (via) occurs. The phenomenon is mainly caused by the _metal diffusion through the crack in the barrier layer 25 to the dielectric layer 2〇 In this case, the upper copper wire % and the lower wire 14 are not conductive, and the component or the circuit fails. This phenomenon is when the dielectric layer 20 is made of a low dielectric constant material or a porous material having a high thermal expansion coefficient. The structure of the dielectric layer is particularly serious. For example, a copper metal dual damascene copper process using SiLKTM as the dielectric layer 2 and a nitride button (TaN) as the barrier layer 25 is exemplified by SiLKTM and copper metal nitriding. The thermal expansion coefficients of the button (pass) are 6〇ppm/°C, 17ppm/°C, and 3ppm/t: respectively, so when the finished metallized semiconductor wafer 1 undergoes a thermal process again, the siLKTM dielectric layer 2 The thermal stress causes cracking of the nitrided barrier layer 25 having a low coefficient of thermal expansion, thereby causing contact opening. [In summary] Accordingly, it is a primary object of the present invention to provide a dual damascene process. Solution
I 1295083 決上述問題。 在本發明之最佳實施例中，該雙鑲嵌(dualdamascene)導線製 私疋先提供一包含有一基底(substrate)以及一導電層設於該基底上 之半導體晶片，然後於該半導體晶片表面依序形成一第一保護 層 弟；|電層、一第二保護層。接著進行一第一黃光 (lithography)暨蝕刻製程，於該第二保護層以及該第一介電層中形 成至少-接觸洞，隨後於該半導體晶片表面依序形成—第二介電 層以及一第三保護層，且該第二介電層係填滿該接觸洞，然後進 行一第二黃光暨蝕刻製程，以於該第三保護層以及該第二介電層 中形成至少一溝槽，且該溝槽與該接觸洞係形成一雙鑲嵌結構。 最後於該半導體晶片表面依序形成一障礙層(barrier layer)以及一 金屬層’且該金屬層係填滿該雙鑲嵌結構，並進行一化學機械研 磨(chemical mechanical polishing，CMP)製程，完成該雙鑲嵌導線製 程。 由於本發明是利用一較為堅硬之介電材料以形成雙鑲嵌結構 中之下層接觸洞，同時利用一低介電常數(1〇w_K)材料形成雙鑲嵌 結構中之上層接觸窗，因此可以使該雙鑲嵌結構具有足夠之抗壓 性避免結構變形(structure deformation)以及發生接觸窗開口的問 題，而又兼具降低RC延遲(RCdelay)效應的良好表現。 【發明之詳細說明】 1295083 睛參考圖二至圖九，圖二至圖九為本發明製作一雙鑲嵌導線製 程的方法示意圖。如圖二所示，該製程先提供一半導體晶片4〇， 且半導體晶片40包含有一基底(substrate)42以及一由銅導線構成之 導電層44設於基底42上。然後於半導體晶片40表面依序形成一第 一保護層46、一第一介電層48、一第二保護層50以及一第一抗反 射層52，並覆蓋於導電層44之上。其中，第一46及第二5〇保護層 係由氮化石夕(silicon nitride)、氮氧化石夕(siiicon-oxy_nitride滅 (siliconcarbon)所構成，而第一抗反射層52係由氮氧化石夕所構成。 接著進行-第-黃光(lithography)製程，於第一抗反射層52表面形 成一第一光阻(photoresist)層54，用來定義該雙鑲嵌結構之一下層 接觸洞(via hole)55的圖案。 如圖三所示，進行-第i刻(eteh)製程，沿著第—光阻層54 之圖案去除未被第-光阻層54覆蓋之第—抗反射層52、第二保^ 層50以及第-介電層48 ’直至第—保護層46表面’以於第二保護 層50以及第-介電層48中形成至少―接觸洞分。隨後去除第二光 P且層54以及第-抗反射層52 ’並於半導體晶⑽表面依序形成一 第二介電層56、-第三保護層58以及—第二抗反射層6()，且第二 介電層56係填滿接觸洞55，如圖四所示。 隨後如圖五所示，進行—第二黃光製程，於第二抗反射層60 表面形成-第二光阻層62，以定義該雙鑲嵌結構之—上層 的圖案。接著如圖六所示，進行一第二餘刻製程，沿著第二^阻 1295083 層㈤之隨去除未被第二絲層62覆蓋之第二抗反射層6〇、第三 保善層取及第二介電層％，直至第—保護層*表面以於第三 保縣取及第二介電層56巾形成至少-賴63，且溝槽63與接 觸洞55係形成_雙鑲嵌結構。 —f圖七所示’去除第二光阻層伽及第二抗反射層6〇，並進 行第了餘刻製程，去除未被第二介電層％以及第一介電層招所 覆蓋之第二保護層5G以及第-保護層46。隨後如圖續示，於半 導體aa片4〇表面依序形成—障礙層1&网64以及一金屬層 66，且金屬層66係填滿該雙鑲嵌結構。 最後如圖九卿，進行—第四蝴製程以去除該雙舰結構底 部表面之障礙層64，並利用第三保護層58當作停止層(st〇player) 來進行一化學機械研磨(chemicai mechanical p〇lishing，CMp)製 程以去除邛伤之金屬層％以及障礙層64，完成該雙鑲嵌導線製 程0 在上述本發明製作之雙鑲欲結構的實施例中，第一介電層係 由一氟石夕玻璃(fluorinated silicate glass，FSG)或一無摻雜石夕玻璃 (Undoped silicate glass，USG)所構成，其材質較為堅硬，因此具有 較佳之抗壓性。第二介電層係由一低介電常數(1〇w_K)材料，包含 有FLARETM、SiLKTM、亞芳香基峻類聚合物(p〇iy(aryieneether) polymer)、parylene類化合物、聚醯亞胺(p〇iyimide)系高分子、氟化 1295083 聚醯亞胺(£111〇111^6(10〇如111丨〇16)、118(^、氟梦玻璃(？8〇)、二氧化 矽、多孔矽玻璃(nanoporoussilica)或鐵氟龍所構成，故可幫助降低 金屬導線之間的RC延遲(RC delay)效應。 相較於習知製作雙鑲嵌結構製程，本發明製作之雙鑲嵌結構 由混合介電層材料(hybrid dielectric material)所構成，因此可以使該 雙鑲嵌結構具有足夠之抗壓性避免結構變形以及發生接觸窗開口 的問題，並且又兼具降低RC延遲(RCdelay)效應的良好表現。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 園所做之均等變化與修飾，皆應屬本發明專利之涵蓋範圍。 【圖式之簡單說明】 圖。 程的方法示意圖。 圖一為習知雙鑲嵌内連線結構之剖面示意 圖二至圖九為本發明製作一雙鑲嵌導線製 【圖示之符號說明】 10半導體晶片 12介電層 18保護層 22接觸窗結構 23導線溝渠結構 25阻障層 11雙鑲嵌結構 導電層 2〇介電層 22a接觸插塞 24上層銅導線 40半導體晶片 1295083 42基底 46第一保護層 50第二保護層 54第一光阻層 56第二介電層 60第二抗反射層 63溝槽 66金屬層 44 導電層 48第一介電層 52第一抗反射層 55接觸洞 58第三保護層 62第二光阻層 64障礙層I 1295083 to resolve the above issues. In a preferred embodiment of the present invention, the dual damascene wire is provided with a semiconductor wafer including a substrate and a conductive layer disposed on the substrate, and then sequentially on the surface of the semiconductor wafer. Forming a first protective layer; an electrical layer, a second protective layer. Then performing a first lithography and etching process to form at least a contact hole in the second protective layer and the first dielectric layer, and then sequentially forming a second dielectric layer on the surface of the semiconductor wafer and a third protective layer, and the second dielectric layer fills the contact hole, and then performing a second yellow light etch process to form at least one trench in the third protective layer and the second dielectric layer a groove, and the groove and the contact hole form a double damascene structure. Finally, a barrier layer and a metal layer are sequentially formed on the surface of the semiconductor wafer, and the metal layer fills the dual damascene structure, and a chemical mechanical polishing (CMP) process is performed to complete the process. Dual inlaid wire process. Since the present invention utilizes a relatively hard dielectric material to form a lower contact hole in the dual damascene structure while using a low dielectric constant (1 〇 w_K) material to form an upper contact window in the dual damascene structure, the The dual damascene structure has sufficient pressure resistance to avoid structural deformation and the occurrence of contact window openings, and has a good performance in reducing the RC delay (RCdelay) effect. DETAILED DESCRIPTION OF THE INVENTION 1295083 Eyes Referring to Figures 2 to 9, FIG. 2 to FIG. 9 are schematic views of a method for fabricating a dual inlaid wire process according to the present invention. As shown in FIG. 2, the process first provides a semiconductor wafer 4, and the semiconductor wafer 40 includes a substrate 42 and a conductive layer 44 of copper wires disposed on the substrate 42. A first protective layer 46, a first dielectric layer 48, a second protective layer 50, and a first anti-reflective layer 52 are sequentially formed on the surface of the semiconductor wafer 40 and overlying the conductive layer 44. Wherein, the first 46 and the second 5 〇 protective layer are composed of silicon nitride, siiicon-oxy_nit annihilation (silicon carbon), and the first anti-reflective layer 52 is composed of arsenic oxide Next, a lithography process is performed to form a first photoresist layer 54 on the surface of the first anti-reflective layer 52 for defining a via hole of the dual damascene structure. a pattern of 55. As shown in FIG. 3, an eteh process is performed, and the first anti-reflective layer 52 not covered by the first photoresist layer 54 is removed along the pattern of the first photoresist layer 54. The second layer 50 and the first dielectric layer 48' up to the surface of the first protective layer 46 form at least a contact hole in the second protective layer 50 and the first dielectric layer 48. The second light P is then removed and The layer 54 and the anti-reflective layer 52' and a second dielectric layer 56, a third protective layer 58 and a second anti-reflective layer 6 are sequentially formed on the surface of the semiconductor crystal (10), and the second dielectric layer The 56 series fills the contact hole 55, as shown in Fig. 4. Subsequently, as shown in Fig. 5, a second yellow light process is performed on the second anti-reflection layer 60. Forming a second photoresist layer 62 to define a pattern of the upper layer of the dual damascene structure. Then, as shown in FIG. 6, a second engraving process is performed, along which the second layer 1295083 layer (f) is removed. The second anti-reflective layer 6〇, the third good layer and the second dielectric layer are covered by the second layer 62 until the first protective layer* surface is used for the third Baoxian and the second dielectric layer 56. The towel forms at least a lap 63, and the groove 63 and the contact hole 55 form a _ double damascene structure. -f FIG. 7 shows the removal of the second photoresist layer and the second anti-reflection layer 6 〇, and performs the first The engraving process removes the second protective layer 5G and the first protective layer 46 which are not covered by the second dielectric layer % and the first dielectric layer. Subsequently, as shown in the continuation, the surface of the semiconductor aa 4 is sequentially formed. a barrier layer 1 & net 64 and a metal layer 66, and a metal layer 66 is filled with the dual damascene structure. Finally, as shown in Fig. 9, a fourth butterfly process is performed to remove the barrier layer 64 of the bottom surface of the double ship structure. And using a third protective layer 58 as a stop layer to perform a chemical mechanical polishing (chemicai mechanical p〇l The ishing, CMp) process for removing the scratched metal layer % and the barrier layer 64 to complete the dual damascene wire process 0. In the embodiment of the double-embedded structure of the present invention described above, the first dielectric layer is made of fluorspar It is composed of fluorinated silicate glass (FSG) or undoped silicate glass (USG), which is relatively hard and therefore has good pressure resistance. The second dielectric layer is composed of a low dielectric constant (1〇w_K) material, including FLARETM, SiLKTM, p〇iy (aryieneether) polymer, parylene compound, polyimine (p〇iyimide) is a polymer, fluorinated 1129083 polypyridinium (£111〇111^6 (10〇111丨〇16), 118(^, fluorine dream glass (?8〇), cerium oxide, The porous bismuth glass (nanoporoussilica) or Teflon can help reduce the RC delay effect between the metal wires. Compared with the conventional dual damascene structure process, the dual damascene structure produced by the present invention is mixed. The dielectric material is composed of a dielectric material, so that the dual damascene structure has sufficient pressure resistance to avoid structural deformation and contact window openings, and has good performance in reducing RC delay (RCdelay) effect. The above description is only the preferred embodiment of the present invention, and all the equivalent changes and modifications made by the patent application scope of the present invention should be covered by the patent of the present invention. [Simplified description of the drawing] Schematic diagram of the method. Cross-sectional view of the dual damascene interconnect structure 2 to 9 is a dual damascene wire made in the present invention. [Illustration of the symbol] 10 semiconductor wafer 12 dielectric layer 18 protective layer 22 contact window structure 23 wire trench structure 25 barrier Layer 11 dual damascene structure conductive layer 2 〇 dielectric layer 22a contact plug 24 upper layer copper wire 40 semiconductor wafer 1295083 42 substrate 46 first protective layer 50 second protective layer 54 first photoresist layer 56 second dielectric layer 60 Second anti-reflection layer 63 trench 66 metal layer 44 conductive layer 48 first dielectric layer 52 first anti-reflective layer 55 contact hole 58 third protective layer 62 second photoresist layer 64 barrier layer
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