TW201709507A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

It is a method of manufacturing a semiconductor device and a semiconductor device that can reduce the on-resistance while suppressing a decrease in withstand voltage. The element active portion (10a) is provided with a first parallel pn layer (5) in which the first n-type region (3) and the first p-type region (4) are alternately repeatedly bonded. The planar layout of the first parallel pn layer (5) is long. The pressure-resistant structure portion (10c) is provided with a second parallel pn layer (15) in which the second n-type region (13) and the second p-type region (14) are alternately repeatedly joined. The planar layout of the second parallel pn layer (15) is elongated in the same direction as the strip of the first parallel pn layer (5). Between the first and second parallel pn layers (5, 15), there is provided an intermediate region (6) having a third parallel pn layer having a lower impurity mass than the first parallel pn layer (5) and The fourth parallel pn layer. The intermediate region (6) is formed by diffusing the impurity-implanted regions between the respective impurity-implanted regions of the first and second parallel pn layers (5, 15) formed to be separated from each other.

Description

Semiconductor device and method of manufacturing the same

This invention relates to a semiconductor device and a method of manufacturing the semiconductor device.

Conventionally, a semiconductor device having a super junction (SJ) structure (hereinafter referred to as a super junction semiconductor device) which is formed by alternately shifting an n-type region and a p-type region in which impurity concentration is increased is known. A parallel pn layer disposed in a direction (lateral direction) parallel to the major faces of the wafer. In the super-junction semiconductor device, current flows in the n-type region of the parallel pn layer in the on state, and also in the off state, the depletion layer extends from the pn junction between the n-type region and the p-type region of the parallel pn layer. The n-type region and the p-type region are depleted and are subjected to withstand voltage. Further, in the super-junction semiconductor device, the impurity concentration of the drift layer can be increased, so that the on-resistance can be reduced at a high withstand voltage.

In such a super-junction semiconductor device, it has been proposed to arrange the n-type region and the p-type region to extend from the element active portion to the withstand voltage structure. A device for forming a parallel pn layer in a plan view having a rectangular shape extending in the same width (for example, the following Patent Document 1 (paragraph 0020, paragraphs 1 and 2)). In the following Patent Document 1, the impurity concentration of the parallel pn layer in the withstand voltage structure portion is lower than the impurity concentration of the parallel pn layer in the element active portion, and the withstand voltage of the withstand voltage structure portion is higher than the withstand voltage of the element active portion. high. The element active portion is a region where current flows in an on state. The peripheral portion of the element surrounds the periphery of the active portion of the element. The pressure-resistant structure portion is disposed on the peripheral portion of the element to alleviate the electric field on the front side of the wafer and the region where the withstand voltage is maintained.

Further, in the case of the other super-junction semiconductor device, a device in which the repetitive pitch of the n-type region and the p-type region of the parallel pn layer is narrowed in the breakdown structure portion is proposed (for example, Patent Document 2 below) Paragraph 0023, Fig. 6) and Patent Document 3 below (paragraph 0032, paragraphs 1 and 2). In the following Patent Document 2, the element active portion and the withstand voltage structure portion collectively have a planar layout in which the parallel pn layers in which the n-type region and the p-type region are arranged are formed in a strip shape. In the following Patent Document 3, a planar layout in which a parallel pn layer in which an n-type region and a p-type region are arranged is formed in a strip shape is formed in the element active portion, and a p-type region is arranged in a matrix in the n-type region in the withstand voltage structure portion. A parallel pn layer of a planar layout.

Further, in another super-junction semiconductor device, an apparatus has been proposed in which an n-type region and a p-type region of a parallel pn layer are arranged in a stripe-like planar layout, and an n-type region of the parallel pn layer in the withstand voltage structure portion and The lateral width (hereinafter, simply referred to as the width) of the p-type region orthogonal to the strip is locally changed (for example, refer to Patent Document 4 below). In addition, in other super-junction semiconductor devices, the following devices have been proposed: The n-type region and the p-type region of the parallel pn layer are arranged in a stripe-like planar layout, and the width of the p-type region of the parallel pn layer in the element active portion is directed toward the outer side in the vicinity of the boundary with the withstand voltage structure portion. It is gradually narrowed (for example, the following Patent Document 5 (paragraph 0051, paragraphs 18 and 19)).

In the following Patent Documents 2 to 5, in the element active portion and the withstand voltage structure portion, the repeating pitch of the n-type region and the p-type region of the parallel pn layer, the width of the p-type region of the parallel pn layer, and the like are changed so as to be resistant. The impurity concentration of the parallel pn layer of the piezoelectric structure portion is lower than the impurity concentration of the parallel pn layer of the element active portion. Therefore, as in the following Patent Document 1, the withstand voltage of the pressure-resistant structure portion is higher than the withstand voltage of the element active portion.

In the method of forming a parallel pn layer, a method has been proposed in which an undoped layer is laminated each time by epitaxial growth, an n-type impurity is ion-implanted on the entire surface, and a p-type impurity is selectively used by a resist mask. After the ion implantation, the impurities are diffused by heat treatment (for example, Patent Document 6 (paragraph 0025, paragraphs 1 to 4)). In the following Patent Document 6, the thermal diffusion process after consideration is made, and the degree of opening of the resist mask for ion implantation of the p-type impurity is about 1/4 of the width, thereby injecting the p-type impurity. The amount is approximately four times the amount of implantation of the n-type impurity, so that the total impurity amount of the n-type region and the p-type region of the parallel pn layer is equal.

In terms of other formation methods of the parallel pn layer, a method has been proposed in which an n-type high-resistance layer is laminated each time by epitaxial growth, and n-type impurities and p-type impurities are selectively ion-implanted by using different resist masks, respectively. After that, the impurities are diffused by heat treatment (for example, Patent Document 7 below) Paragraph 0032~0035, Figure 4) Reference). In the following Patent Document 7, the n-type impurity implantation region which is an n-type region of the parallel pn layer and the p-type impurity implantation region which is a p-type region are selectively formed to be thermally diffused so as to face each other in the lateral direction. For this reason, both the n-type region and the p-type region can have a high impurity concentration, and it is possible to suppress the unevenness of the impurity concentration in the vicinity of the pn junction between the regions adjacent in the lateral direction.

[Previous Technical Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Publication No. 2008-294214

[Patent Document 2] Japanese Patent Publication No. 2002-280555

[Patent Document 3] International Publication No. 2013/008543

[Patent Document 4] Japanese Patent Publication No. 2010-056154

[Patent Document 5] Japanese Patent Publication No. 2012-160752

[Patent Document 6] Japanese Patent Laid-Open Publication No. 2011-192824

[Patent Document 7] Japanese Patent Publication No. 2000-040822

However, as a result of the inventors' intensive research, the inventors have found that the n-type impurity and the p-type impurity are selectively ion-implanted to form a parallel pn layer in the element active portion and the withstand voltage structure portion, respectively. The following problems have arisen. 27 and 28 are plan views showing the planar layout of the parallel pn layer of the conventional super junction semiconductor device. 27(a) and 28(a) show the planar layout at the time of completion of the parallel pn layer. 27(a) and 28(a) show a portion of the conventional 1/4 of the super-bonded semiconductor device. FIGS. 27(b) and 28(b) show a state in the middle of the formation of the parallel pn layer in the boundary region 100b between the element active portion 100a and the pressure-resistant structure portion 100c. The element peripheral portion 100d is configured by a boundary region 100b and a pressure resistant structure portion 100c. In Figs. 27 and 28, the lateral direction of the extension of the parallel pn layer is y, and the lateral direction orthogonal to the long strip is x. Reference numeral 101 is an n ^- type semiconductor layer which is epitaxially grown in order to form a parallel pn layer.

As shown in FIGS. 27(a) and 28(a), in the conventional super-junction semiconductor device, the parallel pn layer (hereinafter referred to as a first parallel pn layer) 104 and the withstand voltage structure portion 100c of the element active portion 100a are juxtaposed. The pn layer (hereinafter referred to as a second parallel pn layer) 114 is connected to each other in a boundary region 100b between the element active portion 100a and the withstand voltage structure portion 100c. As shown in FIGS. 27(b) and 28(b), when the first and second parallel pn layers 104 and 114 are formed, the n-type impurity implantation region 121 of the first n-type region 102 of the first parallel pn layer 104 is formed. The p-type impurity implantation region 122 to be the first p-type region 103 is formed as a first region 100e extending to the inner side (on the element active portion 100a side) of the boundary region 100b. The n-type impurity implantation regions 131 and 141 which are the second n-type regions 112 and 115 of the second parallel pn layer 114, and the p-type impurity implantation regions 132 and 142 which are the second p-type regions 113 and 116 are formed to extend to The second region 100f on the outer side (on the side of the pressure-resistant structure portion 100c) of the boundary region 100b. Each of the impurity implantation regions extends to the first region The boundary between the domain 100e and the second region 100f (vertical dashed line).

As shown in FIG. 27, when the first n-type region 102, the first p-type region 103, the second n-type region 112, and the second p-type region 113 have the same repetition pitch P11 and P12 (P11=P12), the boundary region 100b is formed. The same conductivity type regions of the first and second parallel pn layers 104 and 114 are in a state of being in contact with each other. In other words, the n-type impurity implantation regions 121 and 131 which are the first and second n-type regions 102 and 112 and the p-type impurity implantation regions 122 and 132 which are the first and second p-type regions 103 and 113 are arranged to each other. The element active portion 100a is arranged in a continuous planar shape extending over the pressure-resistant structure portion 100c. Therefore, the charge balance of the first and second parallel pn layers 104 and 114 in the boundary region 100b does not collapse, but the first and second parallel pn layers 104 and 114 have the same average impurity concentration, so that the element activity is not The portion 100a and the pressure-resistant structure portion 100c generate a pressure difference. Therefore, the electric field is likely to be locally concentrated in the pressure-resistant structure portion 100c, and there is a problem that the withstand voltage of the entire pressure-resistant structure portion 100c determines the withstand voltage of the entire element.

On the other hand, as shown in FIG. 28, when the repetition pitch P12 of the second n-type region 115 and the second p-type region 116 is narrower than the repetition pitch P11 of the first n-type region 102 and the first p-type region 103 (P11) P12), the periods in which the same-conductivity-type regions of the first and second parallel pn layers 104 and 114 are in contact with each other are determined by the repetition ratios P11 and P12 of each other. In other words, in the boundary region 100b, the n-type impurity implantation regions 121 and 141 which are the first and second n-type regions 102 and 115 and the p-type impurity implantation regions 122 and 142 which are the first and second p-type regions 103 and 116 are mutually in each other. Become There are states where the junctions are not connected. For this reason, the n-type impurity concentration and the p-type impurity concentration locally become higher in the boundary region 100b. For example, in the vicinity of the continuous portion 143 where the p-type impurity implantation regions 122 and 142 are in contact with each other, the distance to the adjacent n-type impurity implantation regions 121 and 141 is different, so that the p-type impurity concentration is changed to the n-type impurity concentration. high. Therefore, it is difficult to ensure the charge balance at the boundary between the first parallel pn layer 104 and the second parallel pn layer 114, and there is a problem that the withstand voltage of the boundary region 100b is locally lowered. This problem is achieved by lowering the average impurity concentration of the first and second parallel pn layers 104 and 114 to suppress a partial decrease in withstand voltage, but the breakdown voltage of the entire element is lowered.

This invention is directed to providing a semiconductor device and a method of manufacturing a semiconductor device in order to eliminate the problems caused by the prior art described above, thereby reducing on-resistance and suppressing breakdown voltage.

In order to solve the above problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features. A surface element structure is provided on the first main surface side. A low resistance layer is provided on the second main surface side. A first parallel pn layer is provided between the surface element structure and the low resistance layer, and a second parallel pn layer is provided so as to surround the periphery of the first parallel pn layer. The first parallel pn layer is formed by alternately arranging the first first conductivity type region and the first second conductivity type region. In the second parallel pn layer, the second first conductive is alternately arranged at a pitch narrower than a repetition pitch of the first first conductive type region and the first second conductive type region. The type region and the second second conductivity type region are formed. An intermediate region is provided between the first parallel pn layer and the second parallel pn layer so as to be connected to the first parallel pn layer and the second parallel pn layer. The intermediate portion includes a third second conductivity type region and a fourth second conductivity type region. The third second conductivity type region is connected to the first second conductivity type region of the first parallel pn layer, and has an average impurity concentration lower than that of the first second conductivity type region. The fourth second conductivity type region is connected to the second second conductivity type region of the second parallel pn layer, and has an average impurity concentration lower than that of the second second conductivity type region.

Further, in the semiconductor device according to the invention, the intermediate region includes the third first conductivity type region and the fourth first conductivity type region. The third first conductivity type region is connected to the first first conductivity type region of the first parallel pn layer, and has an average impurity concentration lower than that of the first first conductivity type region. The fourth first conductivity type region is connected to the second first conductivity type region of the second parallel pn layer, and has an average impurity concentration lower than that of the second first conductivity type region.

Further, in the semiconductor device according to the invention described above, in the intermediate region, the third parallel pn in which the third first conductivity type region and the third second conductivity type region are alternately arranged is disposed. Floor.

Further, in the semiconductor device according to the invention described above, in the intermediate region, the fourth portion is arranged alternately. The fourth parallel type pn layer of the first conductive type region and the fourth second conductive type region.

Further, the semiconductor device according to the invention is the above-described invention and further has the following features. The first first conductivity type region and the first second conductivity type region are arranged in a stripe planar layout. The second first conductivity type region and the second second conductivity type region are arranged in a stripe plane that is oriented in the same direction as the first first conductivity type region and the first second conductivity type region. layout. The third second conductivity type region and the fourth second conductivity type region are arranged in a stripe plane that is oriented in the same direction as the first second conductivity type region and the second second conductivity type region. layout.

Further, in the semiconductor device according to the invention described above, at least one of the third and second conductivity type regions that are opposed to each other is in contact with at least one of the fourth and second conductivity type regions.

Further, the semiconductor device according to the invention is the above-described invention and further has the following features. The first first conductivity type region and the first second conductivity type region are arranged in a stripe planar layout. The second first conductivity type region and the second second conductivity type region are arranged in a strip shape in a direction orthogonal to the first first conductivity type region and the first second conductivity type region. The layout of the plane. The third second conductivity type region is arranged in a stripe plan layout in the same direction as the first second conductivity type region. The fourth second conductivity type region is arranged in a stripe plan layout in the same direction as the second second conductivity type region.

Further, the semiconductor device according to the invention is the above-described invention and further has the following features. The surface element structure and the first parallel pn layer are arranged in an element active portion through which an electric current flows in an on state. The second parallel pn layer is disposed on a peripheral portion of the element surrounding the element active portion. A terminal region is provided between the first main surface and the low resistance layer on the side opposite to the element active portion side of the peripheral portion of the element. A fifth first conductivity type region having an average impurity concentration lower than that of the second first conductivity type region is provided between the second parallel pn layer and the terminal region. The conductive layer is electrically connected to the terminal region.

Further, in order to solve the above-described problems and achieve the object of the present invention, a method of manufacturing a semiconductor device according to the present invention has the following features. First, the formation procedure of the first and second programs is repeated. In the first procedure described above, the first conductive semiconductor layer is deposited. In the second step, the first first conductivity type impurity implantation region, the first second conductivity type impurity implantation region, and the second first conductivity type impurity are formed on the surface layer of the first conductivity type semiconductor layer. The implantation region and the second second conductivity type impurity implantation region. The first first conductivity type impurity implantation region and the first second conductivity type impurity implantation region are alternately arranged. The second first conductivity type impurity implantation region and the second second conductivity type impurity implantation region are oriented toward the first first conductivity type impurity implantation region and the first second conductivity type impurity implantation region. The outside is separated by a given width. The second first conductivity type impurity implantation region and the second second conductivity type impurity implantation region are different from the first first conductivity type impurity region. The material injection region and the first second conductivity type impurity implantation region have a narrow pitch at which the repetition pitch is alternately arranged. Next, a heat treatment process is performed. In the heat treatment process, the first first conductivity type impurity implantation region and the first second conductivity type impurity implantation region are diffused to form a first first conductivity type region and a first second portion. The first parallel pn layer of the conductive region. The second first conductivity type impurity implantation region and the second second conductivity type impurity implantation region are diffused to form the second first conductivity type region and the second second conductivity type region alternately arranged. Parallel pn layer. In the heat treatment process, the first first conductivity type impurity implantation region and the first second conductivity type impurity implantation region are formed between the first parallel pn layer and the second parallel pn layer. The second first conductivity type impurity implantation region and the second second conductivity type impurity implantation region are diffused to form a third first conductive material having an average impurity concentration lower than that of the first first conductive type region. a third region of the third conductivity type having a lower impurity concentration than the first second conductivity type region, and a fourth first conductivity type region having an average impurity concentration lower than that of the second first conductivity type region and The intermediate portion of the fourth second conductivity type region having a lower average impurity concentration than the second second conductivity type region.

Further, in the method of manufacturing a semiconductor device according to the invention described above, in the heat treatment process, the third first conductivity type region and the third second conductivity type region are alternately arranged. In the third parallel pn layer, the intermediate regions of the fourth parallel pn layer of the fourth first conductivity type region and the fourth second conductivity type region are alternately arranged.

Further, in the second aspect of the invention, the first first conductivity type impurity implantation region and the first second conductivity type impurity implantation region are used in the second aspect of the invention. The second first conductivity type impurity implantation region and the second second conductivity type impurity implantation region are formed in the same manner as the first first conductivity type impurity implantation region and the first A strip-shaped planar layout in which the second conductivity type impurity implantation regions of 1 are oriented in the same direction.

Further, in the second aspect of the invention, the first first conductivity type impurity implantation region and the first second conductivity type impurity implantation region are used in the second aspect of the invention. The second first conductivity type impurity implantation region and the second second conductivity type impurity implantation region are formed in the same manner as the first first conductivity type impurity implantation region and the first A strip-shaped planar layout in which the second conductivity type impurity implantation regions of 1 are orthogonal to each other.

Further, in order to solve the above-described problems and achieve the object of the present invention, a method of manufacturing a semiconductor device according to the present invention has the following features. First, the formation procedure of the first and second programs is repeated. In the first procedure described above, the first conductive semiconductor layer is deposited. In the second step, the first second conductivity type impurity implantation region is formed alternately on the surface layer of the first conductivity type semiconductor layer, and the second conductivity type impurity implantation is performed in comparison with the first second conductivity type impurity implantation region. The region is separated from the outside by a predetermined width, and is larger than the first second conductivity type impurity implantation region of the first The second second conductivity type impurity implantation region is formed at a pitch having a narrow pitch. Then, a heat treatment process is performed in which the first second conductivity type impurity implantation region is diffused to form a first parallel pn in which the first second conductivity type region is alternately arranged with the first conductivity type semiconductor layer. In the layer, the second second conductivity type impurity implantation region is diffused to form a second parallel pn layer in which the second second conductivity type region is alternately arranged with the first conductive semiconductor layer. In the heat treatment process, the first second conductivity type impurity implantation region and the second second conductivity type impurity implantation region are diffused between the first parallel pn layer and the second parallel pn layer. a third second conductivity type region having a lower average impurity concentration than the first second conductivity type region and a fourth second conductivity type region having an average impurity concentration lower than the second second conductivity type region The middle area.

Further, in the above-described second aspect of the invention, in the second aspect of the invention, the first second conductivity type impurity implantation region is formed in a stripe planar layout, and the first The second conductivity type impurity implantation region of 2 is formed in a stripe planar layout in the same direction as the first second conductivity type impurity implantation region.

Further, in the above-described second aspect of the invention, in the second aspect of the invention, the first second conductivity type impurity implantation region is formed in a stripe planar layout, and the first The second conductivity type impurity implantation region of 2 is formed in a stripe planar layout in a direction orthogonal to the first second conductivity type impurity implantation region.

In the above-described invention, the method of manufacturing the semiconductor device according to the invention is characterized in that the predetermined width is 1/2 or less of the thickness of the first conductive semiconductor layer deposited by the first program of the first time.

Further, in the method of manufacturing a semiconductor device according to the invention, the first parallel pn layer and the second parallel pn layer are formed on a low resistance layer having a lower electric resistance than the first conductive semiconductor layer. After the heat treatment process, a surface element structure is formed on the side opposite to the low resistance layer side of the first parallel pn layer.

Further, in the method of manufacturing a semiconductor device according to the invention, the first parallel pn layer is formed in an element active portion through which an electric current flows in an on state, and the second parallel pn layer is formed in The peripheral portion of the element surrounding the active portion of the element.

According to the above invention, a region in which an impurity is implanted into the impurity region of the first parallel pn layer and the impurity implant region which is the second parallel pn layer is formed, and the impurity implantation region is thermally diffused in the region. The intermediate region of the fourth parallel pn layer having a lower average impurity concentration than the first parallel pn layer and having a lower average impurity concentration than the second parallel pn layer can be formed between the first and second parallel pn layers. . Further, since the amount of impurities in the intermediate portion is lower than that of the first parallel pn layer, the pn layer is more likely to be depleted than the first pn layer, and the electric field is not concentrated. For this reason, even in the pressure-resistant structure portion (the terminal side portion of the element peripheral portion), the second parallel pn layer in which the repeating pitch of the n-type region and the p-type region is narrower than the element active portion is disposed, and the withstand voltage of the withstand voltage structure portion is formed. Specific pressure of the active part of the component When the boundary area between the active portion of the element and the pressure-resistant structure portion is high, the withstand voltage is not lowered. Therefore, since the charge balance of the first and second parallel pn layers can be adjusted, the withstand voltage of the peripheral portion (the pressure-resistant structure portion and the boundary region) of the element is higher than the withstand voltage of the element active portion, and the high withstand voltage of the entire device is changed. easily. Further, even if the average impurity concentration of the first parallel pn layer is increased and the low on-resistance is obtained, the withstand voltage difference between the peripheral portion of the element and the element active portion can be maintained.

According to the semiconductor device and the method of manufacturing a semiconductor device according to the present invention, it is possible to reduce the on-resistance and suppress the breakdown voltage.

1‧‧‧n ⁺ type bungee layer

2‧‧‧n type buffer layer

3, 83‧‧‧1n type area

4, 84‧‧‧1p type area

5, 85‧‧‧1 juxtaposed pn layer

6‧‧‧1 and 2 juxtaposed intermediate areas between pn layers

7‧‧‧p-type base region

8‧‧‧Source electrode

9‧‧‧汲electrode

10a‧‧‧Component Active Unit

10b‧‧‧ border area

10c‧‧‧Pressure structure

10d‧‧‧Parts of the component

10e‧‧‧1st area

10f‧‧‧2nd area

10g‧‧‧3rd area

12‧‧‧n ^- type area

13‧‧‧2n-type area

14‧‧‧2p-type area

15‧‧‧2nd parallel pn layer

16‧‧‧n type channel blocking area

17‧‧‧p-type outermost area

18‧‧‧channel blocking electrode

19‧‧‧Interlayer insulating film

21a~21f‧‧‧n ^- type semiconductor layer

22a~22e, 42a‧‧‧p type impurity implantation area

23a~23e, 43a‧‧‧n type impurity implantation area

24‧‧‧ epitaxial layer

31, 33‧‧‧Resistance mask

32, 34‧‧‧ ion implantation

41‧‧‧3n-type area

42‧‧‧3p-type area

43‧‧‧3rd parallel pn layer

44‧‧‧4n-type area

45‧‧‧4p type area

46‧‧‧4th parallel pn layer

47‧‧‧Migration area

51, 61‧‧‧n ⁺ source region

52, 62‧‧‧p ⁺ type contact area

53, 64‧‧‧ gate insulating film

54, 65‧‧‧ gate electrode

63‧‧‧ Ditch

70‧‧‧n type area

71a~71f‧‧‧n type semiconductor layer

P1‧‧‧1st parallel pn layer repeat spacing

P2‧‧‧2nd parallel pn layer repeat spacing

Y‧‧‧interval between the positions of the center of the first p-type region and the second p-type region

A1, b1‧‧‧ the area of the first parallel pn layer sandwiched between the positions of the first p-type region and the second p-type region

A2, b2‧‧‧ the middle area of the interval between the positions of the center of the first p-type region and the second p-type region

A3, b3‧‧‧ The area of the second parallel pn layer sandwiched between the positions of the first p-type region and the second p-type region

A1', a2', a3', b1', b2', b3'‧‧‧ midpoint

D1‧‧‧ Interval between the n-type impurity implantation region and the p-type impurity implantation region formed in the active portion of the device

D2‧‧‧ The interval between the n-type impurity implantation region and the p-type impurity implantation region formed in the withstand voltage structure portion

Width of w1‧‧‧n ^- type area

W2‧‧‧Width of pressure-resistant structure

W3‧‧‧ Width of the portion of the second pn layer disposed in the pressure-resistant structure portion

W4‧‧‧ Width of the middle area between the 1st and 2nd pn layers

Thickness of t‧‧‧n ^- type semiconductor layer

X‧‧‧ transverse to the strip of the parallel pn layer (2nd direction)

y ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧

Z‧‧‧depth direction

Fig. 1 is a plan view showing a plan layout of a semiconductor device according to a first embodiment.

Fig. 2 is a plan view showing an enlarged portion X1 of Fig. 1;

Fig. 3 is a cross-sectional view showing a cross-sectional structure taken along a cutting line A-A' of Fig. 1.

Fig. 4 is a cross-sectional view showing a cross-sectional structure taken along a cutting line B-B' of Fig. 1.

Fig. 5 is a cross-sectional view showing a cross-sectional structure taken along a cutting line C-C' of Fig. 1 .

Fig. 6 is a cross-sectional view showing a state in the middle of the manufacture of the semiconductor device according to the first embodiment.

FIG. 7 is a cross-sectional view showing a state in the middle of the manufacture of the semiconductor device according to the first embodiment.

FIG. 8 is a cross-sectional view showing a state in the middle of the manufacture of the semiconductor device according to the first embodiment.

FIG. 9 is a cross-sectional view showing a state in the middle of the manufacture of the semiconductor device according to the first embodiment.

FIG. 10 is a cross-sectional view showing a state in the middle of the manufacture of the semiconductor device according to the first embodiment.

FIG. 11 is a cross-sectional view showing a state in the middle of the manufacture of the semiconductor device according to the first embodiment.

FIG. 12 is a plan view showing a state in the middle of the manufacture of the semiconductor device according to the first embodiment.

Fig. 13 is a plan view showing a state in the middle of the manufacture of the semiconductor device according to the first embodiment.

FIG. 14 is a cross-sectional view showing an example of an element active portion of the semiconductor device according to the first embodiment.

FIG. 15 is a cross-sectional view showing another example of the element active portion of the semiconductor device according to the first embodiment.

Fig. 16 is a plan view showing an enlarged portion X1 of Fig. 1;

Fig. 17 is a cross-sectional view showing a cross-sectional structure taken along a cutting line A-A' of Fig. 1 .

Fig. 18 is a cross-sectional view of the cutting line B-B' of Fig. 1 The cross-sectional view shown.

Fig. 19 is a cross-sectional view showing a cross-sectional structure taken along a cutting line C-C' of Fig. 1 .

Fig. 20 is a cross-sectional view showing a state in the middle of the manufacture of the semiconductor device according to the second embodiment.

FIG. 21 is a cross-sectional view showing a state in the middle of the manufacture of the semiconductor device according to the second embodiment.

FIG. 22 is a cross-sectional view showing a state in the middle of the manufacture of the semiconductor device according to the second embodiment.

FIG. 23 is a cross-sectional view showing a state in the middle of the manufacture of the semiconductor device according to the second embodiment.

Fig. 24 is a cross-sectional view showing a state in the middle of the manufacture of the semiconductor device according to the second embodiment.

Fig. 25 is a plan view showing a state in the middle of the manufacture of the semiconductor device according to the second embodiment.

Fig. 26 is a plan view showing a state in the middle of the manufacture of the semiconductor device according to the second embodiment.

FIG. 27 is a plan view showing a planar layout of a parallel pn layer of a conventional super junction semiconductor device. FIG.

FIG. 28 is a plan view showing a planar layout of a parallel pn layer of a conventional super junction semiconductor device. FIG.

Fig. 29 is a plan view showing a planar layout of a semiconductor device according to a third embodiment.

FIG. 30 is a plan view showing an enlarged portion taken along line X2 of FIG. 29.

FIG. 31 is a plan view showing an enlarged portion of the X3 portion of FIG. 29. FIG.

Fig. 32 is a cross-sectional view showing a cross-sectional structure taken along a cutting line D-D' of Fig. 29.

Fig. 33 is a cross-sectional view showing a cross-sectional structure taken along a cutting line E-E' of Fig. 29.

Hereinafter, a preferred embodiment of the semiconductor device and the method of manufacturing the semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the drawings, the layers or regions in which n or p are marked are referred to as electrons or holes as a plurality of carriers, respectively. Further, + and - added to n, p, and the like respectively indicate higher impurity concentrations and lower impurity concentrations than layers, regions, and the like which are not added. In the following description of the embodiments and the drawings, the same reference numerals are given to the same components, and the description thereof will not be repeated.

(Embodiment 1)

An n-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a super-junction structure will be described as an example of the structure of the semiconductor device according to the first embodiment. Fig. 1 is a plan view showing the planar layout of a semiconductor device according to the first embodiment. Fig. 2 is a plan view showing an enlarged portion X1 of Fig. 1. Fig. 3 is a cross-sectional view showing the cross-sectional structure taken along the cutting line A-A' of Fig. 1. Figure 4 is a cut for Figure 1. A cross-sectional view of the cross-sectional structure under the broken line B-B' is shown. Fig. 5 is a cross-sectional view showing a cross-sectional structure taken along a cutting line C-C' of Fig. 1.

FIG. 1 shows a shape in a plane transverse to the first and second parallel pn layers 5 and 15 of the element active portion 10a and the element peripheral portion 10d. For example, the first parallel pn layer 5 of the element active portion 10a is shown. The shape of the plane under the depth of 1/2. The element active portion 10a is a region where current flows in an on state. The element peripheral portion 10d surrounds the periphery of the element active portion 10a. In addition, in FIG. 1, in order to clarify the repeating pitch P1 and the second n-type region of the first n-type region (first first conductive type region) 3 and the first p-type region (first second conductive type region) 4 The difference in the repetition pitch P2 between the (second first conductivity type region) 13 and the second p type region (second second conductivity type region) 14 is shown to be smaller than that of FIG.

As shown in FIGS. 1 to 5, the semiconductor device according to the first embodiment includes an element active portion 10a and an element peripheral portion 10d surrounding the element active portion 10a. On the first main surface (wafer front surface) side of the element active portion 10a, a front surface structure of the element is provided, and a MOS gate (an insulating gate formed of a metal-oxide film-semiconductor) which is omitted is provided. An n ⁺ -type drain layer (low-resistance layer) 1 is provided on the second main surface side of the element active portion 10a, and is provided at a position deeper than the n ⁺ -type drain layer 1 from the second main surface (wafer back surface) N-type buffer layer 2. A drain electrode 9 connected to the n ⁺ -type drain layer 1 is provided on the second main surface of the element active portion 10a. The n-type buffer layer 2, the n ⁺ -type drain layer 1 and the drain electrode 9 are provided from the element active portion 10a over the element peripheral portion 10d.

In the element active portion 10a, a first parallel pn layer 5 is provided between the MOS gate structure and the n-type buffer layer 2. The first parallel pn layer 5 is formed by alternately repeating joining of the first n-type region 3 and the first p-type region 4 in a direction (lateral direction) parallel to the first main surface. The planar layout of the first n-type region 3 and the first p-type region 4 is elongated. The outermost (wafer end side) of the first n-type region 3 and the first p-type region 4 of the first parallel pn layer 5 is, for example, the first n-type region 3, and the outermost first n-type region 3 is For example, the second p-type region 14 facing the second parallel pn layer 15 is sandwiched between the intermediate regions 6 to be described later in the direction in which the strips of the parallel pn layers 5 are orthogonal. The first parallel pn layer 5 is formed between the element active portion 10a and the withstand voltage structure portion 10c from the element active portion 10a in the direction in which the strip of the first parallel pn layer 5 extends and in the direction orthogonal to the strip. The boundary area 10b is provided.

The element peripheral portion 10d is constituted by the boundary region 10b and the pressure-resistant structure portion 10c. The element peripheral portion 10d is a region that is located outside the outer end portion of the gate electrode of the MOS gate structure that is disposed at the outermost side, or where the n ⁺ -type source region is disposed outside the gate electrode. The lower portion is a region outside the outer end portion of the n ⁺ -type source region. The pressure-resistant structure portion 10c surrounds the periphery of the element active portion 10a with the boundary region 10b interposed therebetween, and moderates the electric field on the front side of the wafer and maintains the withstand voltage. The pressure-resistant structure portion 10c is a region outside the outer end portion of the p-type base region 7 disposed at the outermost side. In the withstand voltage structure portion 10c, a second parallel pn layer 15 is provided on the n-type buffer layer 2. The second parallel pn layer 15 is formed by alternately repeating the second n-type region 13 and the second p-type region 14 in the lateral direction.

The planar layout of the second n-type region 13 and the second p-type region 14 is elongated. The orientation of the strip of the second parallel pn layer 15 is the same as the orientation of the strip of the first parallel pn layer 5. Hereinafter, the lateral direction in which the strips of the first and second parallel pn layers 5 and 15 are extended is the first direction y, and the lateral direction orthogonal to the strip (that is, the lateral direction orthogonal to the first direction y) is the second. Direction x. The repetition pitch P2 of the second n-type region 13 and the second p-type region 14 is narrower than the repetition pitch P1 of the first n-type region 3 and the first p-type region 4. Thereby, the average impurity concentration of the second n-type region 13 and the second p-type region 14 is lower than the average impurity concentration of the first n-type region 3 and the first p-type region 4, respectively. Since the second n-type region 13 and the second p-type region 14 are formed simultaneously with the first n-type region 3 and the first p-type region 4, the pitch is narrowed so that the average impurity concentration is lowered, and the vacant layer is formed in the second parallel pn layer 15. It is easy to extend in the outer peripheral direction, and the high withstand voltage of the initial withstand voltage becomes easy. The second p-type region 14 performs the same function as the guard ring until it is depleted. As a result, the electric field of the second n-type region 13 is alleviated, so that the high withstand voltage of the pressure-resistant structure portion 10c is facilitated.

The second parallel pn layer 15 is provided over the boundary region 10b from the withstand voltage structure portion 10c in the extending direction of the strip of the second parallel pn layer 15 and in the direction orthogonal to the strip. Further, the second parallel pn layer 15 surrounds the periphery of the first parallel pn layer 5 with the intermediate portion 6 interposed therebetween, and is connected to the first parallel pn layer 5 via the intermediate portion 6. In other words, the first parallel pn layer 5 and the second parallel pn layer 15 are connected to the intermediate portion 6 in common, and are continuous regions interposed between the intermediate regions 6. 2nd parallel pn layer 15 The portion disposed in the pressure-resistant structure portion 10c can be provided so as not to reach the thickness of the first main surface from the n-type buffer layer 2. In other words, in the ion implantation and heat treatment to be described later for forming the second parallel pn layer 15, impurities implanted into the epitaxial substrate may not diffuse to the first main surface. In this case, between the second parallel pn layer 15 and the first main surface, the n-type semiconductor layer which is epitaxially grown when the second parallel pn layer 15 is formed is formed in the breakdown structure portion 10c.

In the intermediate region 6 between the first and second parallel pn layers 5 and 15, a third parallel pn layer 43 and a fourth parallel pn layer 46 are disposed, and the third parallel pn layer 43 and the fourth parallel pn layer 46 are connected to each other. The region (the third region to be described later) in which the impurities between the impurity injection regions of the first and second parallel pn layers 5 and 15 are formed by ion implantation without being implanted by the first and second ions described later is used. Each impurity implantation region is diffused. Specifically, the inner side (wafer center side) portion of the intermediate portion 6 includes a third parallel pn layer 43 having a repeating pitch from the first n-type region 3 and the first p-type region 4 The third impurity region (the third first conductivity type region) 41 and the third p-type region (the third second conductivity type region) 42 which are alternately arranged with the P1 having a substantially equal repeating pitch are gradually lowered toward the outside. . The outer portion of the intermediate portion 6 is provided with a fourth parallel pn layer 46 which is alternately arranged with a repeating pitch substantially equal to the repeating pitch P2 of the second n-type region 13 and the second p-type region 14 The impurity concentration is in the fourth n-type region (fourth first conductivity type region) 44 and the fourth p-type region (fourth second conductivity type region) 45 which are gradually lowered toward the inside. That is, the middle area 6 is averaged The third n-type region 41 having a lower concentration than the first n-type region 3 and the fourth n-type region 44 having a lower average impurity concentration than the second n-type region 13 and the third p-type region 42 having an average impurity concentration lower than that of the first p-type region 4 The fourth p-type region 45 having an average impurity concentration lower than that of the second p-type region 14 is formed.

Further, the region a1 and the second parallel pn layer 15 of the first parallel pn layer 5 having the same width w4 as the intermediate portion a2 in the interval Y between the positions of the first p-type region 4 and the second p-type region 14 The p-type impurity and the n-type impurity in the region a3 satisfy Ca2<(Ca1+Ca3)/2 with respect to the intermediate region a2 of the region Y, respectively. Ca1~Ca3 are the impurity masses of the regions a1~a3, respectively. The first p-type region 4 and the center of the second p-type region 14 are opposed to each other, and the center of the second direction x of the first p-type region 4 and the center of the second direction x of the second p-type region 14 are located in the first direction y. On the same line. For this reason, the intermediate region 6 is a region that is more depleted than the first parallel pn layer 5 in the off state. Further, in the position where the first p-type region 4 and the second p-type region 14 oppose each other, the impurity concentration at the midpoint a2' of the intermediate region a2 of the segment Y is higher than the midpoint of the region a1 of the first parallel pn layer The impurity concentration of a1' and the impurity concentration of the midpoint a3' of the region a3 of the second parallel pn layer are low.

The third parallel pn layer 43 disposed in the intermediate region 6 is opposed to the fourth parallel pn layer 46. Between the third parallel pn layer 43 and the fourth parallel pn layer 46, there are transition regions 47 in which impurities of the respective impurity implantation regions of the first and second parallel pn layers 5 and 15 having different repeating pitches are diffused. Further, the third parallel pn layer 43 and the fourth parallel pn layer 46 can be connected between the impurity implantation regions as the first and second parallel pn layers 5 and 15. The impurities overlap and diffuse.

In the withstand voltage structure portion 10c, an n ^- type region (the fifth first conductivity type region) 12 is provided on the n-type buffer layer 2 outside the second parallel pn layer 15. n ^- -type region 12, the thickness of the lines to reach the first main surface of the n-type buffer layer 2 is provided. The n ⁻ -type region 12 surrounds the periphery of the second parallel pn layer 15 and has a function of suppressing the extension of the depletion layer diffused outward by the second parallel pn layer 15 in the off state. The average impurity concentration of the n ⁻ -type region 12 is lower than the average impurity concentration of the second n ^- type region 13 . The width w1 of the n ^- type region 12 is preferably, for example, 1/20 or more and 1/3 or less of the width w2 of the pressure-resistant structure portion 10c. The reason for this is that the width w3 of the portion of the second parallel pn layer 15 disposed in the pressure-resistant structure portion 10c is 2/3 or more of the width w2 of the withstand voltage structure portion 10c, so that the second parallel pn layer 15 is depleted. It is easier to change, so it is easy to ensure a predetermined withstand voltage.

In the termination region of the withstand voltage structure portion 10c, an n-type channel blocking region 16 is provided on the n-type buffer layer 2. The n-type channel blocking region 16 is provided to have a thickness from the n-type buffer layer 2 to the first main surface. Instead of the n-type channel blocking region 16, a p-type channel blocking region may be provided. A p-type outermost peripheral region 17 is provided on the first main surface side of the n-type channel blocking region 16. The channel blocking electrode 18 is connected to the p-type outermost peripheral region 17, and is electrically insulated from the source electrode 8 of the MOS gate structure by the interlayer insulating film 19 covering the first main surface on the element peripheral portion 10d. Further, the channel blocking electrode 18 extends over the interlayer insulating film 19 and protrudes inward from the p-type outermost peripheral region 17. Channel blocking electrode 18, can also be no more than n The type channel blocking region 16 protrudes inward.

In the case where the semiconductor device of the first embodiment is a vertical MOSFET and the withstand voltage is 600 V, the size and impurity concentration of each portion take the following values. The thickness of the drift region (thickness of the first parallel pn layer 5) is 35 μm, and the width of the first n-type region 3 and the first p-type region 4 is 6.0 μm (repeat pitch P1 is 12.0 μm). The peak in the width direction of the first n-type region 3 and the first p-type region 4 on the surface of the n ⁻ -type semiconductor layer 21 c corresponding to a depth of 1/2 in the drift region (refer to the epitaxial layer 24 (see FIG. 10 ) to be described later) The impurity concentration was 4.0 × 10 ¹⁵ /cm ³ . The width of the second n-type region 13 and the second p-type region 14 is 4.0 μm (repeat pitch P2 is 8.0 μm). The peak impurity concentration in the width direction of the second n ^- type region 13 and the second p-type region 14 on the surface of the n ^- type semiconductor layer 21c corresponding to a depth of 1/2 in the drift region (the epitaxial layer 24 to be described later) is 2.0 × 10 ¹⁵ /cm ³ . The width w4 of the intermediate portion 6 is 2 μm. The peak impurity concentration in the width direction of the n ⁻ -type region 12 disposed on the surface of the n ⁻ -type semiconductor layer 21 c corresponding to a depth of 1/2 in the drift region (the epitaxial layer 24 to be described later) is 1.0×10 ¹⁵ /cm ³ or less. It is preferred. n ^- -type region width w1 of 8μm 12 lines. The width w2 of the pressure-resistant structure portion 10c is 150 μm. 3 to 5 (the same applies to FIGS. 17 to 19, 32, and 33), the portion of the second parallel pn layer 15 disposed in the withstand voltage structure portion 10c is simplified, and the second parallel pn layer 15 is shown. The width w3 of the portion of the pressure-resistant structure portion 10c is 110 μm. Further, when the withstand voltage is 300 V, the peak impurity concentration in the width direction of the n ⁻ -type region 12 is preferably 1.0×10 ¹⁶ /cm ³ or less.

Further, in the first embodiment, the element active portion 10a is provided with the first parallel pn layer 5 between the MOS gate structure and the n-type buffer layer 2, and the pressure resistant structure portion 10c is n-type. The second parallel pn layer 15 is provided on the buffer layer 2; the first parallel pn layer 5 is provided between the MOS gate structure and the n ⁺ type drain layer 1, and the second parallel column is provided on the n ⁺ type drain layer 1. The pn layer 15 can also be used.

Next, a method of manufacturing the semiconductor device according to the first embodiment will be described. 6 to 11 are cross-sectional views showing a state in the middle of the manufacture of the semiconductor device according to the first embodiment. 12 and 13 are plan views showing a state in the middle of the manufacture of the semiconductor device according to the first embodiment. FIG. 12 shows a state in the middle of formation of the first and second parallel pn layers 5 and 15. Specifically, FIG. 12 shows a plan layout of an impurity implantation region after the first and second ion implantations 32 and 34 for forming the first and second parallel pn layers 5 and 15 and before the heat treatment. In Fig. 13, the state of the intermediate portion 6 after the heat treatment is shown. In the state in the middle of the production of the first parallel pn layer 5 of the element active portion 10a, the state in the middle of the manufacture of the second parallel pn layer 15 of the withstand voltage structure portion 10c is omitted. The parallel pn layer 15 is formed simultaneously with the first parallel pn layer 5 by the same method as the first parallel pn layer 5. That is, in FIGS. 6 to 11, the state in which the repetition pitch P2 is narrowed is a state in the middle of the manufacture of the second parallel pn layer 15.

First, as shown in Fig. 6, on the front surface of the n ⁺ -type starting substrate which becomes the n ⁺ -type drain layer 1, the n-type buffer layer 2 is formed by epitaxial growth. Next, as shown in FIG. 7, on the n-type buffer layer 2, the n ^- type semiconductor layer 21a of the first order is deposited (formed) by epitaxial growth at a predetermined thickness t. Next, as shown in FIG. 8, a resist mask 31 is formed on the n ^- -type semiconductor layer 21a, and the resist mask 31 is tied to the first p-type region 4 and the second side corresponding to the first parallel pn layer 5. The portion of the formation region of the second p-type region 14 of the pn layer 15 has an opening. The width of the opening portion of the resist mask 31 in the second direction x is narrower than the width of the element active portion 10a in the second direction x of the first p-type region 4, and the pressure-resistant structure portion 10c is larger than the second p-type region 14 The width of the second direction x is narrow. Further, the width of the opening portion of the resist mask 31 in the second direction x is narrower than the element active portion 10a in the pressure-resistant structure portion 10c. Next, the p-type impurity is used as the first ion implantation 32 by using the resist mask 31 as a mask. By the first ion implantation 32, the p-type impurity implantation region 22a is selectively formed in the element active portion 10a in the surface layer of the n ^- -type semiconductor layer 21a, and the p-type impurity implantation region 42a is selectively formed in the breakdown voltage structure portion 10c ( Figure 12 refers to). The depth of the p-type impurity implantation regions 22a, 42a is shallower than, for example, the thickness t of the n ^- -type semiconductor layer 21a.

Next, as shown in FIG. 9, after the resist mask 31 is removed, a resist mask 33 is formed on the n ^- -type semiconductor layer 21a, and the resist mask 33 is associated with the first parallel pn layer 5. Portions of the formation regions of the first n-type region 3 and the second n-type region 13 of the second parallel pn layer 15 have openings. The width of the opening portion of the resist mask 33 in the second direction x is narrower than the width of the element active portion 10a in the second direction x of the first n-type region 3, and the pressure-resistant structure portion 10c is larger than the second n-type region 13 The width of the second direction x is narrow. Further, the width of the opening portion of the resist mask 33 in the second direction x is narrower than the element active portion 10a in the pressure-resistant structure portion 10c. Next, the n-type impurity is used as the second ion implantation 34 by using the resist mask 33 as a mask. 34 whereby the second ion implantation, the n ^- type semiconductor layer, a surface layer 21a, the active element portion 10a for selectively forming an n-type impurity regions 23a, 10c in the breakdown voltage structure of the n ^- type semiconductor layer 21a of the surface layer of The n-type impurity implantation region 43a is selectively formed (refer to FIG. 12). The depth of the n-type impurity implantation regions 23a and 43a is shallower than, for example, the thickness t of the n ⁻ -type semiconductor layer 21a. The formation procedure of the n-type impurity implantation regions 23a and 43a and the formation procedure of the p-type impurity implantation regions 22a and 42a can be changed.

The first and second ion implantations 32 and 34 are arranged in the element active portion 10a so that the element-type active portion 10a separates the n-type impurity implantation region 23a from the p-type impurity implantation region 22a at a predetermined interval d1. In the withstand voltage structure portion 10c, the n-type impurity implantation region 43a and the p-type impurity implantation region 42a are separated by a predetermined interval d2. Further, each of the impurity-injecting regions 22a, 23a, 42a, and 43a of the element active portion 10a and the pressure-resistant structure portion 10c is disposed so as to extend to the boundary region 10b between the element active portion 10a and the pressure-resistant structure portion 10c. Specifically, in the first direction y, the n-type impurity implantation region 23a and the p-type impurity implantation region 22a of the element active portion 10a are arranged so as to extend to the first region inside the boundary region 10b (on the side of the element active portion 10a). 10e. The n-type impurity implantation region 43a and the p-type impurity implantation region 42a of the pressure-resistant structure portion 10c are disposed so as to extend to the second region 10f on the outer side (the pressure-resistant structure portion 10c side) of the boundary region 10b. In addition, the third region 10g between the first region 10e and the second region 10f is covered with the resist masks 31 and 33, and impurities are not implanted into the third region 10g, thereby removing impurities of the element active portion 10a. The injection regions 22a and 23a are disposed apart from the respective impurity injection regions 42a and 43a of the pressure-resistant structure portion 10c in the first direction y. The third region 10g is a portion which becomes the intermediate portion 6 between the first and second parallel pn layers 5 and 15 by heat treatment described later. The width w4 of the third region 10g (intermediate region 6) in the first direction y is preferably 1/2 or less of the thickness t of the n ^- -type semiconductor layer 21a (w4 ≦ t/2). The reason for this is that the difference in the repetition pitch of the n-type region and the p-type region is less likely to be adversely affected by the first and second parallel pn layers 5 and 15, and the withstand voltage is less likely to occur in the boundary region 10b. . Specifically, when the thickness t of the n ⁻ -type semiconductor layer 21 a is about 7 μm, the width w4 of the first region y of the intermediate portion 6 can be, for example, about 2 μm.

Next, as shown in FIG. 10, after the resist mask 33 is removed, a plurality of n ^- -type semiconductor layers 21b to 21f are further deposited on the n ^- -type semiconductor layer 21a by epitaxial growth, thereby forming a plurality of For example, the epitaxial layer 24 of a predetermined thickness formed by the n ^- type semiconductor layers 21a to 21f is formed. In this case, the n ^- type semiconductor layers 21b to 21e are stacked, and the first and second ion implantations 32 and 34 are performed in the same manner as the first-order n ^- type semiconductor layer 21a, and the element active portion 10a and the withstand voltage structure portion are formed. 10c forms a p-type impurity implantation region and an n-type impurity implantation region, respectively. The planar layout of the p-type impurity implantation region and the n-type impurity implantation region formed in each of the element active portion 10a and the withstand voltage structure portion 10c is a p-type impurity implantation region formed in the n ^- type semiconductor layer 21a of the first step and The planar layout of the n-type impurity implantation region is the same. In FIG. 10, in the element active portion 10a, p-type impurity implantation regions 22b to 22e are formed in the n ^- -type semiconductor layers 21b to 21f, respectively, and n-type impurity implantation regions 23b to 23e are formed, respectively. Epitaxial layer 24 is an n ^- type semiconductor layer in 21a ~ 21f, in the uppermost order n ^- -type semiconductor layer 21f may be based first and second ion implantation 32,34. The epitaxial substrate in which the n-type buffer layer 2 and the epitaxial layer 24 are sequentially formed on the front surface of the n ⁺ -type start substrate which becomes the n ⁺ -type drain layer 1 is formed by the conventional procedure.

Next, as shown in Fig. 11, each n-type impurity implantation region and each p-type impurity implantation region in the n ^- -type semiconductor layers 21a to 21e are diffused by heat treatment. Each of the n-type impurity implantation regions and each of the p-type impurity implantation regions is formed in a linear shape extending in the first direction y, and is diffused into a substantially columnar shape having the ion implantation center as a central axis. In the element active portion 10a, the n-type impurity implantation regions 23a to 23e in the depth direction z overlap each other to form the first n-type region 3, and the p-type impurity implantation in the depth direction z is simultaneously performed. The regions 22a to 22e are connected to each other to form the first p-type region 4 so as to overlap each other. Further, the first n-type region 3 and the first p-type region 4 are connected to each other to form a first parallel pn layer 5. In the same manner, in the pressure-resistant structure portion 10c, the n-type impurity implantation regions (not shown) in the depth direction z overlap each other to form the second n-type region 13 while facing the p-type in the depth direction z. The impurity implantation regions (not shown) are superposed on each other so as to overlap each other to form the second p-type region 14. Further, the second n-type region 13 and the second p-type region 14 are connected to each other to form the second parallel pn layer 15. At this time, in the third region 10g of the boundary region 10b, the n-type impurity and the p-type impurity are diffused from the n-type impurity implantation region and the p-type impurity implantation region of the element active portion 10a and the withstand voltage structure portion 10c, respectively, to form an intermediate region. 6.

In the case where the semiconductor device according to the first embodiment is a vertical MOSFET, the withstand voltage is 600 V, and the width w4 of the first region y of the intermediate portion 6 is about 2 μm, the first and second ion implantations are 32. The conditions of the heat treatment for the diffusion of impurities 34 and 34 are as follows. The first ion implantation 32 is such that the amount of the first p-type region 4 and the second p-type region 14 is about 0.2 × 10 ¹³ /cm ² or more and 2.0 × 10 ¹³ /cm ² or less. In the second ion implantation 34, the amount of the first n-type region 3 and the second n-type region 13 is about 0.2 × 10 ¹³ /cm ² or more and 2.0 × 10 ¹³ /cm ² or less. The heat treatment temperature is about 1000 ° C or more and 1200 ° C or less.

The state of the intermediate portion 6 after the heat treatment is shown in Fig. 13 . In the third region 10g which does not ion-implant the impurity between the respective impurity implantation regions of the first and second parallel pn layers 5 and 15 which are formed by separating the first and second ion implantations 32 and 34, the intermediate region 10g is formed in the middle. In the region 6, the intermediate region 6 includes a third parallel pn layer 43 and a fourth parallel pn layer 46 which are diffused into the respective impurity implantation regions. Specifically, in the inner side (wafer center side) of the intermediate portion 6 of the third region 10g, the third parallel pn layer 43 is formed, and the third parallel pn layer 43 has the first n-type region 3 and the first p The impurity concentration alternately arranged in the repeating pitch P1 of the pattern region 4 is substantially equal to the third n-type region 41 and the third p-type region 42 which are gradually lowered toward the outside. In the outer portion of the intermediate portion 6, a fourth parallel pn layer 46 is formed, and the fourth parallel pn layer 46 has a repetition substantially equal to the repetition pitch P2 of the second n-type region 13 and the second p-type region 14. The impurity concentration which is alternately arranged at intervals is the fourth n-type region 44 and the fourth p-type region 45 which are gradually lowered toward the inner side. In other words, the intermediate region 6 is formed with a third n-type region 41 having an average impurity concentration lower than that of the first n-type region 3, a fourth n-type region 44 having an average impurity concentration lower than that of the second n-type region 13, and an average impurity concentration ratio 1p. The third p-type region 42 having a low pattern region 4 and the fourth p-type region 45 having a lower average impurity concentration than the second p-type region 14 are more likely to be depleted than the first parallel pn layer 5 and the second parallel pn layer 15 in the off state. Area.

The third parallel pn layer 43 disposed in the intermediate region 6 is opposed to the fourth parallel pn layer 46. Between the third parallel pn layer 43 and the fourth parallel pn layer 46, there are diffusion regions 47 in which impurities of the impurity regions of the first and second parallel pn layers 5 and 15 having different repeating pitches are diffused. In addition, the third parallel pn layer 43 and the fourth parallel pn layer 46 are formed so as to be diffused and diffused as impurities between the impurity implantation regions of the first and second parallel pn layers 5 and 15.

The planar layout of the second n-type region 13 and the second p-type region 14 is preferably a growth strip shape. The reason for this is that it is easy to adjust the average impurity concentration of each of the plurality of second n-type regions 13 and the plurality of second p-type regions 14 to be substantially the same, and it is easy to ensure the charge balance of the second parallel pn layer 15. It is assumed that the second p-type regions 14 are arranged in a matrix-like planar layout, and the second n-type regions 13 are formed in a lattice-like planar layout surrounding the second p-type regions 14. In this case, the second n-type region 13 has a lattice-like planar shape having a surface area three times larger than that of the second p-type region 14 with respect to the planar shape of the second p-type region 14 which is substantially rectangular. for Therefore, it is difficult to review the planar layout of the n-type impurity implantation region to be the second n-type region 13 in order to uniformly diffuse the n-type impurity as a whole in the second n-type region 13 and to improve the processing accuracy of the resist mask. There is unevenness in the limit plasma implantation, and the average impurity concentration of each of the plurality of second n-type regions 13 is uneven. The adverse effect due to the unevenness of the ion implantation is particularly remarkable in the pressure-resistant structure portion 10c in which the repetition pitch P2 of the second n-type region 13 and the second p-type region 14 is narrow. On the other hand, when the planar layout of the second n-type region 13 and the second p-type region 14 is elongated, the second n-type region 13 and the second p-type region 14 simultaneously have a linear planar shape having substantially the same surface area. . Therefore, the widths of the n-type impurity implantation region and the p-type impurity implantation region in the second direction x are made equal, so that the average impurity concentration of each of the plurality of second n-type regions 13 and the plurality of second p-type regions 14 can be easily adjusted. It is roughly the same.

The n-type channel blocking region 16 can be formed by, for example, the formation of the first and second p-type regions 4, 14 by the first ion implantation 32, and can also selectively select the p-type impurity at a different timing from the first ion implantation 32. It is formed by ion implantation. The n ⁻ -type region 12 can be formed by covering the formation regions of the n ⁻ -type region 12 with the resist masks 31 and 33 at the first and second ion implantations 32 and 34, and further adding the n-type impurity selectivity. A procedure for ion implantation is formed. Next, the remaining procedures for forming the MOS gate structure, the p-type outermost peripheral region 17, the interlayer insulating film 19, the source electrode 8, the channel blocking electrode 18, and the drain electrode 9 are sequentially performed by a general method. Thereafter, the epitaxial substrate is cut (cut) into a wafer shape, thereby completing the super junction semiconductor device shown in FIGS. 1 to 5.

Further, in the method of manufacturing a semiconductor device according to the first embodiment, the n-type buffer layer 2 is formed on the front surface of the n ⁺ -type start substrate which is the n ⁺ -type drain layer 1, but the n-type buffer may not be formed. Layer 2, and an epitaxial layer 24 is formed on the front surface of the n ⁺ -type starting substrate which becomes the n ⁺ -type drain layer 1.

Next, an example of the element active portion 10a of the semiconductor device according to the first embodiment will be described. FIG. 14 is a cross-sectional view showing an example of an element active portion of the semiconductor device according to the first embodiment. Fig. 15 is a cross-sectional view showing another example of the element active portion of the semiconductor device according to the first embodiment. As shown in FIG. 14, the element active portion 10a is provided with a p-type base region 7, an n ⁺ -type source region 51, a p ⁺ -type contact region 52, and a gate insulating film 53 on the first main surface side. The MOS gate structure of the general planar gate structure formed by the gate electrode 54. Further, as shown in Fig. 15, the element active portion 10a may be provided with a p-type base region 7, an n ⁺ -type source region 61, a p ⁺ -type contact region 62, a trench 63, and a gate on the first main surface side. The MOS gate structure of the general trench gate structure formed by the pole insulating film 64 and the gate electrode 65. In the MOS gate structure, the p-type base region 7 can be disposed so as to be connected to the first p-type region 4 of the first parallel pn layer 5 in the depth direction z. The broken line in the first parallel pn layer 5 is a boundary between a plurality of n ^- type semiconductor layers which are stacked by epitaxial growth when the first parallel pn layer 5 is formed.

(Embodiment 2)

The structure of the semiconductor device according to the second embodiment is provided with super An n-channel MOSFET having a bonded structure is exemplified. The plan view of the planar layout of the semiconductor device according to the second embodiment is the same as the plan view of the semiconductor device according to the first embodiment. Fig. 16 is a plan view showing an enlarged portion X1 of Fig. 1. Fig. 17 is a cross-sectional view showing the cross-sectional structure taken along the cutting line A-A' of Fig. 1. Fig. 18 is a cross-sectional view showing the cross-sectional structure taken along the cutting line B-B' of Fig. 1. Fig. 19 is a cross-sectional view showing the cross-sectional structure taken along the cutting line C-C' of Fig. 1.

The semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment in that the first n-type region 3, the second n-type region 13, the third n-type region 41, and the fourth n-type region 44 have the same average impurity concentration. It is formed without ion implantation of an n-type impurity. Ion implantation for forming the n-type impurity for the first n-type region 3 and the second n-type region 13 is not performed, and the n-type impurity concentration of the epitaxial substrate (n-type semiconductor layers 71a to 71f to be described later) is not changed to form a parallel pn. In the case of the n-type region of the layer, the same effect as in the first embodiment can be obtained by providing the intermediate region 6.

The intermediate region 6 between the first and second parallel pn layers 5 and 15 is disposed between the impurity implantation regions which are formed by separating the first and second parallel pn layers 5 and 15 without being implanted by the first ions. The impurity is a region (the third region) where the ion implantation is performed, and the third parallel pn layer 43 and the fourth parallel pn layer 46 are formed by diffusing the respective impurity implantation regions. Specifically, the inner side (wafer center side) portion of the intermediate portion 6 includes a third parallel pn layer 43 having the first n-type region 3 and The impurity concentration alternately arranged in the repeating pitch P1 of the first p-type region 4 is substantially equal to the third p-type region 42 which is gradually lowered toward the outside. The outer portion of the intermediate portion 6 is provided with a fourth parallel pn layer 46 which is alternately arranged with a repeating pitch substantially equal to the repeating pitch P2 of the second n-type region 13 and the second p-type region 14 The impurity concentration is in the 4th p-type region 45 which is gradually lowered toward the inside. In other words, the intermediate region 6 is the third n-type region 41 and the fourth n-type region 44 having the same average impurity concentration as the first n-type region 3, and the third p-type region 42 having an average impurity concentration lower than that of the first p-type region 4 and an average value. The fourth p-type region 45 having a lower impurity concentration than the second p-type region 14 is formed.

Further, the region b1 and the second parallel pn layer 15 of the first parallel pn layer 5 having the same width w4 as the intermediate region b2 in the interval Y between the positions of the first p-type region 4 and the second p-type region 14 The p-type impurity amount of the region b3 is equal to the intermediate region b2 of the interval Y, and satisfies Cb2 < (Cb1 + Cb3)/2. Cb1~Cb3 are the p-type impurity masses of the regions b1 to b3, respectively. For this reason, the intermediate region 6 is a region that is more depleted than the first parallel pn layer 5 in the off state. Further, in the position where the first p-type region 4 and the second p-type region 14 oppose each other, the impurity concentration at the midpoint b2' of the intermediate region b2 of the segment Y is higher than the region b1 of the first parallel pn layer 5 The impurity concentration of the point b1' and the impurity concentration of the midpoint b3' of the region b3 of the second parallel pn layer 15. The third parallel pn layer 43 disposed in the intermediate region 6 is opposed to the fourth parallel pn layer 46. Further, the third parallel pn layer 43 and the fourth parallel pn layer 46 can be connected to each other as impurities in the impurity implantation regions of the first and second parallel pn layers 5 and 15 to be diffused and heavy. Stack.

The semiconductor device of the second embodiment is, for example, a vertical MOSFET, and when the withstand voltage is 600 V, the size and impurity concentration of each portion are as follows. The thickness of the drift region (thickness of the first parallel pn layer 5) is 35 μm, and the width of the first n-type region 3 and the first p-type region 4 is 6.0 μm (repeat pitch P1 is 12.0 μm). The peak impurity concentration in the width direction of the first n-type region 3 (n-type semiconductor layers 71a to 71f) on the surface of the n-type semiconductor layer 71c corresponding to a depth of 1/2 in the drift region (the epitaxial layer 24 to be described later) 4.0 × 10 ¹⁵ /cm ³ . The peak impurity concentration in the width direction of the first p-type region 4 disposed on the surface of the n-type semiconductor layer 71c corresponding to a depth of 1/2 in the drift region (the epitaxial layer 24 to be described later) is 4.0 × 10 ¹⁵ /cm ³ . The width of the second n-type region 13 and the second p-type region 14 is 4.0 μm (repeat pitch P2 is 8.0 μm). The peak impurity concentration in the width direction of the second p-type region 14 disposed on the surface of the n-type semiconductor layer 71c having a depth of 1/2 in the drift region (the epitaxial layer 24 to be described later) is 2.0 × 10 ¹⁵ /cm ³ . The width w4 of the intermediate portion 6 is 2 μm. The width w2 of the pressure-resistant structure portion 10c is 150 μm, and the width w3 of the portion of the second parallel pn layer 15 disposed on the pressure-resistant structure portion 10c is 110 μm.

In the withstand voltage structure portion 10c, an n-type region 70 is provided on the n-type buffer layer 2 outside the second parallel pn layer 15.

Further, in the second embodiment, the element active portion 10a is provided with the first parallel pn layer 5 between the MOS gate structure and the n-type buffer layer 2, and the withstand voltage structure portion 10c is n. The second parallel pn layer 15 is provided on the buffer layer 2; however, a first parallel pn layer 5 may be provided between the MOS gate structure and the n ⁺ type drain layer 1, and is disposed on the n ⁺ type drain layer 1 The second parallel pn layer 15.

Next, a method of manufacturing the semiconductor device according to the second embodiment will be described. 20 to 24 are cross-sectional views showing a state in the middle of the manufacture of the semiconductor device according to the second embodiment. 25 and 26 are plan views showing a state in the middle of the manufacture of the semiconductor device according to the second embodiment. FIG. 25 shows a plan layout of an impurity implantation region after the first ion implantation 32 for forming the first and second parallel pn layers 5 and 15 and before the heat treatment. In Fig. 26, the state of the intermediate portion 6 after the heat treatment is shown. The manufacturing method of the semiconductor device according to the second embodiment differs from the method of manufacturing the semiconductor device according to the first embodiment in that the second ion implantation 34 for ion implantation of the n-type impurity is not performed.

Specifically, first, as shown in FIG. 20, the n-type buffer layer 2 is formed by epitaxial growth on the front surface of the n ⁺ -type start substrate which becomes the n ⁺ -type drain layer 1. Next, as shown in FIG. 21, on the n-type buffer layer 2, the n-type semiconductor layer 71a of the first order is deposited (formed) by a predetermined thickness t by epitaxial growth. Next, as shown in FIG. 22, a resist mask 31 is formed on the n-type semiconductor layer 71a, and the resist mask 31 is connected to the first p-type region 4 and the second parallel pn corresponding to the first parallel pn layer 5. The portion of the formation region of the second p-type region 14 of the layer 15 has an opening. The width of the opening portion of the resist mask 31 in the second direction x is narrower than the width of the element active portion 10a in the second direction x of the first p-type region 4, and the pressure-resistant structure portion 10c is larger than the second p-type region 14 The width of the second direction x is narrow. Further, the width of the opening portion of the resist mask 31 in the second direction x is narrower than the element active portion 10a in the pressure-resistant structure portion 10c. Next, the p-type impurity is used as the first ion implantation 32 by using the resist mask 31 as a mask. By the first ion implantation 32, the p-type impurity implantation region 22a is selectively formed in the element active portion 10a in the surface layer of the n-type semiconductor layer 71a, and the p-type impurity implantation region 42a is selectively formed in the withstand voltage structure portion 10c (Fig. 25 reference). The depth of the p-type impurity implantation regions 22a, 42a is shallower than, for example, the thickness t of the n-type semiconductor layer 71a.

In the above-described first ion implantation 32, as shown in FIG. 25, the p-type impurity implantation regions 22a and 42a of the element active portion 10a and the withstand voltage structure portion 10c are arranged to extend to the element active portion 10a and the withstand voltage structure portion. A boundary area 10b between 10c. Specifically, in the first direction y, the p-type impurity implantation region 22a of the element active portion 10a is disposed so as to extend to the first region 10e inside the boundary region 10b (on the side of the element active portion 10a). The p-type impurity implantation region 42a of the pressure-resistant structure portion 10c is disposed so as to extend to the second region 10f on the outer side (the pressure-resistant structure portion 10c side) of the boundary region 10b. In addition, the third region 10g between the first region 10e and the second region 10f is covered with the resist mask 31, and impurity ions are not implanted into the third region 10g, thereby p-type impurities of the element active portion 10a. The injection region 22a and the p-type impurity implantation region 42a of the withstand voltage structure portion 10c are separated from each other in the first direction y. The third region 10g is a portion which becomes the intermediate portion 6 between the first and second parallel pn layers 5 and 15 by heat treatment described later. The width w4 of the first direction y of the third region 10g (intermediate region 6) is preferably 1/2 or less of the thickness t of the n-type semiconductor layer 71a (w4 ≦ t/2). The reason for this is that the difference in the repetition pitch of the n-type region and the p-type region is less likely to be adversely affected by the first and second parallel pn layers 5 and 15, and the withstand voltage is less likely to occur in the boundary region 10b. . Specifically, when the thickness t of the n ⁻ -type semiconductor layer 21 a is about 7 μm, the width w4 of the first region y of the intermediate portion 6 can be, for example, about 2 μm.

Next, as shown in FIG. 23, after the resist mask 31 is removed, a plurality of n-type semiconductor layers 71b to 71f are further deposited on the n-type semiconductor layer 71a by epitaxial growth, thereby forming a plurality of (for example, 6). The epitaxial layer 24 of a predetermined thickness formed by the n-type semiconductor layers 71a to 71f. In this case, the n-type semiconductor layers 71b to 71e are stacked, and the first ion implantation 32 is performed in the same manner as the n-type semiconductor layer 71a of the first-order semiconductor layer 71a, and p-type impurities are formed in the element active portion 10a and the breakdown voltage structure portion 10c, respectively. Inject area. The planar layout of the p-type impurity implantation region formed in each of the element active portion 10a and the withstand voltage structure portion 10c is the same as the planar layout of the p-type impurity implantation region formed in the n-type semiconductor layer 71a of the first step. In FIG. 23, in the element active portion 10a, p-type impurity implantation regions 22b to 22e are formed in the n-type semiconductor layers 71b to 71f, respectively. Among the n-type semiconductor layers 71a to 71f to be the epitaxial layer 24, the first ion implantation 32 may not be performed in the uppermost n-type semiconductor layer 71f. The epitaxial substrate in which the n-type buffer layer 2 and the epitaxial layer 24 are sequentially formed on the front surface of the n ⁺ -type start substrate which becomes the n ⁺ -type drain layer 1 is formed by the conventional procedure.

Next, as shown in Fig. 24, each p-type impurity implantation region in the n-type semiconductor layers 71a to 71e is diffused by heat treatment. Each of the p-type impurity implantation regions is formed as a straight line extending in the first direction y Therefore, they are respectively diffused into a substantially cylindrical shape with the ion implantation as a central axis. In the element active portion 10a, the p-type impurity implantation regions 22a to 22e in the depth direction z are connected to each other to form the first p-type region 4 so as to overlap each other. In the same manner, in the pressure-resistant structure portion 10c, the p-type impurity implantation regions (not shown) in the depth direction z are superposed on each other so as to overlap each other to form the second p-type region 14. At this time, in the third region 10g of the boundary region 10b, the p-type impurity is diffused from each of the p-type impurity implantation regions of the element active portion 10a and the withstand voltage structure portion 10c to form the intermediate portion 6.

In the case where the semiconductor device according to the second embodiment is a vertical MOSFET, the withstand voltage is 600 V, and the width w4 of the first region y of the intermediate portion 6 is about 2 μm, the first ion implantation 32 and the supply are provided. The conditions of the heat treatment for the subsequent impurity diffusion are as follows. The first ion implantation 32 is such that the amount of the first p-type region 4 and the second p-type region 14 is about 0.2 × 10 ¹³ /cm ² or more and 2.0 × 10 ¹³ /cm ² or less. The heat treatment temperature is about 1000 ° C or more and 1200 ° C or less.

The state of the intermediate portion 6 after the heat treatment is shown in Fig. 26, respectively. In the third region 10g which does not ion-implant the impurity between the p-type impurity implantation regions of the first and second parallel pn layers 5 and 15 which are formed by the first ion implantation 324 and are separated from each other, the intermediate region 6 is formed. The intermediate region 6 includes a third parallel pn layer 43 and a fourth parallel pn layer 46 that are diffused into the impurity implantation region. Specifically, in the inner side (wafer center side) of the intermediate portion 6 of the third region 10g, the third parallel pn layer 43 is formed, and the third parallel pn layer 43 has the first n-type region 3 and the first p The repeating pitch P1 of the type region 4 is approximately equal to the repeating pitch The impurity concentration alternately arranged is along the third p-type region 42 which is gradually lowered toward the outside. In the outer portion of the intermediate portion 6, a fourth parallel pn layer 46 is formed, and the fourth parallel pn layer 46 is alternately arranged at a repeating pitch substantially equal to the repeating pitch P2 of the second n-type region 13 and the second p-type region 14. The impurity concentration is in the 4th p-type region 45 which is gradually lowered toward the inside. In other words, in the intermediate region 6, the third n-type region 41 and the fourth n-type region 44 having the same average impurity concentration as the first n-type region 3, and the third p-type region 42 having an average impurity concentration lower than that of the first p-type region 4 are formed. The fourth p-type region 45 is a region that is more depleted than the first parallel pn layer 5 in the off state.

The third parallel pn layer 43 disposed in the intermediate region 6 is opposed to the fourth parallel pn layer 46. In addition, the third parallel pn layer 43 and the fourth parallel pn layer 46 are formed so as to be diffused and diffused as impurities between the impurity implantation regions of the first and second parallel pn layers 5 and 15. In addition, in the second embodiment, the element active portion 10a of the semiconductor device according to the second embodiment is different from the first embodiment in that the first n-type region 3 and the second n-type region 13 are not subjected to the second ion implantation 34. The element active portion 10a of the semiconductor device according to the first embodiment has the same configuration.

(Embodiment 3)

An n-channel MOSFET having a super junction structure will be described as an example of the structure of the semiconductor device according to the third embodiment. Fig. 29 is a plan view showing the planar layout of the semiconductor device according to the third embodiment. Fig. 30 is a plan view showing the X2 portion of Fig. 29 in an enlarged manner. Figure 31 is a plan view showing an enlarged view of the X3 portion of Fig. 29 . Figure 32 is a cross-sectional view showing the cross-sectional structure taken along the cutting line D-D' of Figure 29 . Figure 33 is a cross-sectional view showing the cross-sectional structure taken along the cutting line E-E' of Figure 29 . FIG. 29 shows a planar shape in which the first and second parallel pn layers 85 and 15 of the element active portion 10a and the element peripheral portion 10d are transversely cut, and for example, the first parallel pn layer 85 of the element active portion 10a is shown. The shape under the plane at a depth of 1/2. In FIG. 29, in order to clarify the difference between the repetition pitch P1 of the first n-type region 83 and the first p-type region 84 and the repetition pitch P2 of the second n-type region 13 and the second p-type region 14, the regions are shown as such regions. The number is less than Figure 30~34.

The semiconductor device according to the third embodiment differs from the semiconductor device according to the first embodiment in that the first parallel pn layer 85 is arranged to extend in a direction orthogonal to the direction in which the strips of the second parallel pn layer 15 extend. Long strip layout (Figures 29~33). In the third embodiment, the lateral direction of the extension of the strip of the first parallel pn layer 85 is the second direction x, and the lateral direction of the extension of the strip of the second parallel pn layer 15 is the first direction y. The configuration other than the planar layout of the first parallel pn layer 85 of the element active portion 10a is as in the first embodiment. The configuration of the element peripheral portion 10d is as in the first embodiment. The second parallel pn layer 15 is connected to the first parallel pn layer 85 via the intermediate portion 6 as in the first embodiment, and surrounds the periphery of the first parallel pn layer 85 with the intermediate portion 6 interposed therebetween.

In other words, a straight line portion (hereinafter referred to as a first straight line portion) 6b parallel to the first direction y and a straight line portion parallel to the second direction x in the intermediate portion 6 of the planar layout arranged in a substantially rectangular frame shape ( Take Hereinafter, the arrangement of the third and fourth parallel pn layers 43 and 46 is different in terms of the second straight line portion 6a. The third and fourth parallel pn layers 43 and 46 are in the region (the third region described above) which is not implanted as impurity ions between the respective impurity implantation regions of the first and second parallel pn layers 85 and 15 as in the first embodiment. The impurity injecting regions are diffused. The conditions of the repetition pitch P1 of the first n-type region 83 and the first p-type region 84 and the repetition pitch P2 of the second n-type region 13 and the second p-type region 14 are as in the first embodiment.

Specifically, as shown in FIG. 30, for example, the first n-type region 83 of the first parallel pn layer 85 and the first outermost region of the first p-type region 84 are, for example, the first n-type region 83, and the first parallel pn layer 85. In the direction orthogonal to the strip (the first direction y), the strips of the second n-type region 13 and the second p-type region 14 of the second parallel pn layer 15 are opposed to each other with the second straight portion 6a of the intermediate region 6 interposed therebetween. Ends. In other words, in the inner portion of the second straight portion 6a of the intermediate portion 6, only the third n-type region 41 of the third parallel pn layer 43 is disposed, and the fourth n-type region 44 is disposed on the outer portion with the transition region 47 interposed therebetween. The fourth parallel pn layer 46 in which the 4p-type region 45 is alternately repeated in the second direction x.

The transition region 47 of the second straight portion 6a of the intermediate portion 6 is, for example, the first n-type region 83 of the first parallel pn layer 85, the second n-type region 13 of the second parallel pn layer 15, and the second p-type region 14 A region in which impurities in the impurity implantation regions are diffused. The n-type impurity amount of the region a11 of the first parallel pn layer 85 and the region a13 of the second parallel pn layer 15 having the same width w4 as the second straight portion 6a of the intermediate region 6 is relative to the middle The second straight line portion 6a of the intermediate region 6 satisfies Ca12 < (Ca11 + Ca13)/2. Ca11 to Ca13 are the n-type impurity amounts of the region a11, the second straight portion 6a, and the region a13, respectively. The p-type impurity amount of the second straight portion 6a of the intermediate portion 6 decreases from the outer side toward the inner side.

On the other hand, as shown in FIG. 31, for example, the second n-type region 13 of the second parallel region pn layer 15 and the second innermost region of the second p-type region 14 are, for example, the second n-type region 13 and the second parallel pn layer 85. In the direction orthogonal to the strip (the second direction x), the first n-type region 83 and the first p-type region 84 of the first parallel pn layer 85 are opposed to each other with the first straight portion 6b of the intermediate portion 6 interposed therebetween. Ends. In other words, in the inner portion of the first straight portion 6b of the intermediate portion 6, a third parallel pn layer 43 in which the third n-type region 41 and the third p-type region 42 are alternately repeated in the first direction y is disposed, sandwiching The migration region 47 is provided with only the fourth n-type region 44 of the fourth parallel pn layer 46 in the outer portion.

The transition region 47 of the first straight portion 6b of the intermediate portion 6 is, for example, the first n-type region 83 and the first p-type region 84 of the first parallel pn layer 85, and the second n-type region 13 of the second parallel pn layer 15, for example. A region in which impurities in the impurity implantation regions are diffused. The n-type impurity amount of the region a21 of the first parallel pn layer 85 and the region a23 of the second parallel pn layer 15 having the same width w4 as the first straight portion 6b of the intermediate portion 6 is the first straight portion with respect to the intermediate portion 6. 6b, satisfying Ca22<(Ca21+Ca23)/2. Ca21 to Ca23 are the n-type impurity amounts of the region a21, the second straight portion 6b, and the region a23, respectively. The p-type impurity amount of the first straight portion 6b of the intermediate portion 6 decreases from the inside toward the outside.

The method of manufacturing a semiconductor device according to the third embodiment is a method for manufacturing a semiconductor device according to the first embodiment, and is used for the first and second ion implantations 32 for forming the first and second parallel pn layers 85 and 15, The planar layout of the resist masks 31 and 33 (refer to FIGS. 8 to 10) of 34 may be used. Specifically, the resist mask 31 used in the first ion implantation 32 is a portion corresponding to a formation region of the first p-type region 84 of the first parallel pn layer 85 and a portion corresponding to the second parallel pn layer 15 The partially planar layout of the formation region of the second p-type region 14 has an opening. The resist mask 33 used in the second ion implantation 34 is a portion corresponding to the formation region of the first n-type region 83 of the first parallel pn layer 85 and a second n-type region corresponding to the second parallel pn layer 15. The partially orthogonal planar layout of the formation regions of 13 has openings.

In the third embodiment, when the withstand voltage is at a level of 600 V, the impurity concentration of the intermediate portion 6 (the first and second straight portions 6b and 6a) is preferably, for example, 1.0 × 10 ¹⁴ /cm ³ or less. Further, when the withstand voltage is at a level of 300 V, the impurity concentration of the intermediate portion 6 is preferably, for example, 1.0 × 10 ¹⁵ /cm ³ or less.

The third embodiment can also be applied to the semiconductor device according to the second embodiment.

As described above, in the above-described respective embodiments, the third region in which the impurity is implanted into the impurity region of the first parallel pn layer and the impurity implant region which is the second parallel pn layer is formed. The third region thermally diffuses each of the impurity implantation regions so that the first and second parallel pn layers can be formed to have an average impurity concentration ratio of the first The third parallel pn layer having a low pn layer and the intermediate region of the fourth parallel pn layer having an average impurity concentration lower than that of the second parallel pn layer. Further, since the amount of impurities in the intermediate portion is lower than that of the first parallel pn layer, the pn layer is more likely to be depleted than the first pn layer, and the electric field is not concentrated. For this reason, even if the second parallel pn layer in which the repeating pitch of the n-type region and the p-type region is narrower than the element active portion is disposed in the pressure-resistant structure portion, the withstand voltage of the withstand voltage structure portion is higher than the withstand voltage of the element active portion. The charge balance change in the boundary region between the element active portion and the withstand voltage structure portion does not adversely affect each other. For this reason, the pressure drop resistance does not occur in the boundary region between the element active portion and the pressure resistant structure portion. Therefore, since the charge balance of the first and second parallel pn layers can be adjusted, the withstand voltage of the peripheral portion (the pressure-resistant structure portion and the boundary region) of the element is higher than the withstand voltage of the element active portion, and the high withstand voltage of the entire device is changed. easily. For this reason, reliability can be improved. Further, even if the average impurity concentration of the first parallel pn layer is increased and the low on-resistance is obtained, the withstand voltage difference between the peripheral portion of the element and the element active portion can be maintained. Therefore, the on-resistance can be reduced while suppressing the breakdown voltage. Further, the withstand voltage of the peripheral portion of the element is made higher than the withstand voltage of the element active portion, so that the element active portion can be collapsed (falling) faster than the peripheral portion of the element, so that the amount of anti-avalanche, the amount of anti-backup, and the like can be improved.

Further, in the conventional configuration (for example, FIG. 8 of Patent Document 1), in the configuration in which the guard ring is provided on the peripheral portion of the element, a plurality of guard rings are separated from each other and arranged so as to surround the concentric shape around the active portion of the element, so that the element The width of the peripheral portion will become longer. On the other hand, according to each of the above embodiments, the second p-type region of the second parallel pn layer provided on the peripheral portion of the element functions as a guard ring. For this reason, the second parallel pn layer is provided on the peripheral portion of the element, so that it is easy to reduce the peripheral portion of the element at the time of turning off, and it is not necessary to provide a guard ring at the peripheral portion of the element, and it is possible to prevent the width of the pressure-resistant structure from becoming long. Further, in the above-described respective embodiments, the n ⁻ -type region is provided outside the second parallel pn layer, and when the off state is reached, the second parallel pn layer can be rapidly depleted, and the second parallel column can be suppressed. The extension of the depleted layer of the pn layer diffused to the outside. Thereby, the depletion layer is less likely to reach the n-type channel blocking region, and local electric field concentration is less likely to occur in the vicinity of the n-type channel blocking region, so that the withstand voltage can be suppressed from being lowered. Further, the n ^- type region disposed outside the second parallel pn layer and the extension of the depletion layer by the n-type region are suppressed, so that the width of the withstand voltage structure portion can be shortened. Further, in the case of the third embodiment, when the plane in which the strips of the first parallel pn layer are extended and the direction in which the strips of the second parallel pn layer extend are orthogonal to each other, the first one can be adjusted. 2, the charge balance of the parallel pn layer. For this reason, the degree of freedom of design is high.

The present invention is not limited to the embodiments described above, and various modifications can be made without departing from the spirit and scope of the invention. For example, the size, the impurity concentration, and the like described in each of the above embodiments are examples, and the present invention is not limited to the equivalent. Further, in each of the above embodiments, the first conductivity type is n-type and the second conductivity type is p-type. However, in the present invention, the first conductivity type is p-type, and the second conductivity type is n-type. Established. Further, the present invention is not limited to a MOSFET, and can also be applied to an IGBT (Insulated Gate Bipolar Transistor), a bipolar transistor, a FWD (Free Wheeling Diode), or a Schottky. Diode and so on.

[Industrial availability]

As described above, the semiconductor device and the semiconductor device manufacturing method according to the present invention are large power semiconductor devices including a breakdown voltage structure portion around the element surrounding portion of the element active portion, and particularly for aligning the drift layers. A high-voltage semiconductor device such as a pn layer MOSFET, IGBT, bipolar transistor, FWD or Schottky diode.

3‧‧‧1n-type area

4‧‧‧1p-type area

5‧‧‧1st pn layer

6‧‧‧1 and 2 juxtaposed intermediate areas between pn layers

10a‧‧‧Component Active Unit

10b‧‧‧ border area

10c‧‧‧Pressure structure

10d‧‧‧Parts of the component

12‧‧‧n ^- type area

13‧‧‧2n-type area

14‧‧‧2p-type area

15‧‧‧2nd parallel pn layer

16‧‧‧n type channel blocking area

P1‧‧‧1st parallel pn layer repeat spacing

P2‧‧‧2nd parallel pn layer repeat spacing

Claims (18)

A semiconductor device comprising: a surface element structure provided on a first main surface side; a low resistance layer provided on a second main surface side; and an alternate arrangement between the surface element structure and the low resistance layer a first parallel pn layer of the first first conductivity type region and the first second conductivity type region; and the first first conductivity type region is provided to surround the first parallel pn layer And the second parallel type pn layer of the second first conductive type region and the second second conductive type region are alternately arranged at a pitch at which the repeating pitch of the first second conductive type region is narrow; and the first parallel pn is An intermediate region provided between the layer and the second parallel pn layer so as to be connected to the first parallel pn layer and the second parallel pn layer; and the intermediate region is connected to the first parallel pn layer a first second conductivity type region in which the average impurity concentration is lower than the first second conductivity type region, and a second second region connected to the second parallel pn layer The second conductivity type region and the fourth impurity having a lower average impurity concentration than the second second conductivity type region The second conductivity type region. The semiconductor device of claim 1, wherein in the intermediate region, there is: a first first conductivity type region in the first first conductivity type region of the first parallel pn layer and having a lower average impurity concentration than the first first conductivity type region; and a second conductivity type region The second first conductivity type region of the second pn layer of the pn layer and the fourth first conductivity type region having a lower average impurity concentration than the second first conductivity type region. The semiconductor device according to claim 2, wherein the third parallel pn layer in which the third first conductivity type region and the third second conductivity type region are alternately arranged is disposed in the intermediate portion. The semiconductor device according to claim 2, wherein the fourth parallel pn layer in which the fourth first conductive type region and the fourth second conductive type region are alternately arranged is disposed in the intermediate portion. . The semiconductor device according to any one of claims 1 to 4, wherein the first first conductivity type region and the first second conductivity type region are arranged in a stripe planar layout, and the first The first conductive type region of the second conductive type region and the second second conductive type region are arranged in a stripe plane layout in the same direction as the first first conductive type region and the first second conductive type region. The third second conductivity type region and the fourth second conductivity type region are arranged in a stripe plane that is oriented in the same direction as the first second conductivity type region and the second second conductivity type region. layout. Such as the semiconductor package of any one of the patent scopes 1 to 5 Further, at least one of the third and second conductivity type regions that are opposed to each other is in contact with at least one of the fourth and second conductivity type regions. The semiconductor device according to any one of claims 1 to 4, wherein the first first conductivity type region and the first second conductivity type region are arranged in a stripe planar layout, and the first The stripe-shaped plane in which the first conductive type region and the second second conductive type region are arranged in a direction orthogonal to the first first conductive type region and the first second conductive type region In the layout, the third second conductivity type region is arranged in a stripe plan layout in the same direction as the first second conductivity type region, and the fourth second conductivity type region is arranged in the same manner as described above. A strip-shaped planar layout in which the second conductive type regions of 2 are oriented in the same direction. The semiconductor device according to any one of claims 1 to 7, further comprising: a surface active element in which the surface element structure and the first parallel pn layer are disposed, and an electric current flows in an on state; and the second portion is disposed a peripheral portion of the element surrounding the element active portion of the parallel pn layer; and a terminal region provided between the first main surface and the low resistance layer on a side opposite to the element active portion side of the element peripheral portion; a fifth first conductivity type region in which an average impurity concentration between the second parallel pn layer and the termination region is lower than the second first conductivity type region; Electrically connected to the conductive layer of the aforementioned termination region. A method of manufacturing a semiconductor device, comprising: a forming process and a heat treatment process, wherein the forming process repeats: a first process of depositing a first conductive semiconductor layer; and a surface layer of the first conductive semiconductor layer The first first conductivity type impurity implantation region and the first second conductivity type impurity implantation region are formed alternately, and the first first conductivity type impurity implantation region and the first one are formed. The position where the conductive impurity-implanted region is separated from the outside by a predetermined width, and is alternately arranged at a pitch narrower than the pitch of the first first conductivity type impurity implantation region and the first second conductivity type impurity implantation region. A second procedure of forming the second first conductivity type impurity implantation region and the second second conductivity type impurity implantation region, wherein the first first conductivity type impurity implantation region and the aforementioned The first second conductivity type impurity implantation region is diffused to form a first parallel pn layer in which the first first conductivity type region and the first second conductivity type region are alternately arranged, and the aforementioned The second first conductivity type impurity implantation region and the second second conductivity type impurity implantation region are diffused to form a second parallel pn in which the second first conductivity type region and the second second conductivity type region are alternately arranged. In the heat treatment process, the first first conductivity type impurity implantation region and the first second conductivity type impurity implantation region are formed between the first parallel pn layer and the second parallel pn layer. The aforementioned second The first conductivity type impurity implantation region and the second second conductivity type impurity implantation region are diffused to form a third first conductivity type region and an average impurity having an average impurity concentration lower than that of the first first conductivity type region. a third second conductivity type region having a lower concentration than the first second conductivity type region, and a fourth first conductivity type region having an average impurity concentration lower than the second first conductivity type region and an average impurity concentration ratio The intermediate portion of the fourth second conductivity type region in which the second second conductivity type region is low. The method of manufacturing a semiconductor device according to claim 9, wherein the heat treatment process is performed by forming a third parallel arrangement in which the third first conductivity type region and the third second conductivity type region are alternately arranged. In the pn layer, the intermediate regions of the fourth parallel pn layer of the fourth first conductivity type region and the fourth second conductivity type region are alternately arranged. The method of manufacturing a semiconductor device according to the ninth or tenth aspect, wherein the first first conductivity type impurity implantation region and the first second conductivity type impurity implantation region are formed in the second program In the strip-shaped planar layout, the second first conductivity type impurity implantation region and the second second conductivity type impurity implantation region are formed in the same manner as the first first conductivity type impurity implantation region and the first The second conductivity type impurity implantation region has a stripe planar layout in the same direction. The method of manufacturing a semiconductor device according to the ninth or tenth aspect, wherein the first first conductivity type impurity implantation region and the first second conductivity type impurity implantation region are formed in the second program a strip-shaped planar layout, and the second first conductivity type The material injection region and the second second conductivity type impurity implantation region are formed in a stripe plane that is orthogonal to the first first conductivity type impurity implantation region and the first second conductivity type impurity implantation region. layout. A method of manufacturing a semiconductor device, comprising: a forming process and a heat treatment process, wherein the forming process is repeated: a first process of depositing a first conductive semiconductor layer; and a surface layer of the first conductive semiconductor layer The first second conductivity type impurity implantation region is formed alternately, and a predetermined width is separated from the first second conductivity type impurity implantation region toward the outside, and is larger than the first second conductivity type. a second process of forming a second second conductivity type impurity implantation region at a pitch of a narrow pitch of the impurity implantation region; the heat treatment process is performed by heat treatment to diffuse the first second conductivity type impurity implantation region to form a first The second parallel type pn layer which is disposed alternately with the first conductive semiconductor layer, and the second second conductive type impurity implantation region are diffused to form the second second conductive type region. The second parallel pn layer in which the first conductive semiconductor layers are alternately arranged is formed between the first parallel pn layer and the second parallel pn layer in the heat treatment process. The first second conductivity type impurity implantation region and the second second conductivity type impurity implantation region are diffused to form a third second conductivity type region having an average impurity concentration lower than that of the first second conductivity type region. And the average impurity concentration is higher than the second guide of the second The intermediate portion of the fourth second conductivity type region in which the electric pattern region is low. The method of manufacturing a semiconductor device according to claim 13, wherein in the second program, the first second conductivity type impurity implantation region is formed into a stripe planar layout, and the second portion is The second conductivity type impurity implantation region is formed in a stripe planar layout in the same direction as the first second conductivity type impurity implantation region. The method of manufacturing a semiconductor device according to claim 13, wherein in the second program, the first second conductivity type impurity implantation region is formed into a stripe planar layout, and the second portion is The second conductivity type impurity implantation region is formed in a stripe planar layout in a direction orthogonal to the first second conductivity type impurity implantation region. The method of manufacturing a semiconductor device according to any one of the first aspect of the present invention, wherein the predetermined width is 1/1 of a thickness of the first conductive semiconductor layer deposited by the first program of the first time. 2 or less. The method of manufacturing a semiconductor device according to any one of claims 9 to 16, wherein the first parallel pn layer and the second parallel are formed on a low resistance layer having a lower electric resistance than the first conductive semiconductor layer In the pn layer, after the heat treatment process, a surface element structure is formed on the side opposite to the low resistance layer side of the first parallel pn layer. The method of manufacturing a semiconductor device according to any one of claims 9 to 17, wherein the first parallel pn layer is formed in a current state in a conducting state In the element active portion, the second parallel pn layer is formed on the peripheral portion of the element surrounding the element active portion.