CN106057866A - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Abstract

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. In the element active portion 10a, a first parallel pn layer 5 in which the first n-type regions 3 and the first p-type regions 4 are alternately and repeatedly joined is provided. The planar layout of the first parallel pn layer 5 is striped. The second parallel pn layer 15 in which the second n-type regions 13 and the second p-type regions 14 are alternately and repeatedly joined is provided in the voltage-resistant structure portion 10c. The planar layout of the second parallel pn layer 15 is a stripe shape with the same orientation as that of the first parallel pn layer 5 . Between the first parallel pn layer 5 and the second parallel pn layer 15, an intermediate region 6 having a third parallel pn layer and a fourth parallel pn layer is provided. The intermediate region 6 is formed by diffusing the impurity-implanted regions to be the first parallel pn layer 5 and the second parallel pn layer 15 formed separately from each other into regions where impurity ion implantation is not performed between the impurity-implanted regions. .

Description

Semiconductor device and method for manufacturing semiconductor device

technical field

The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.

Background technique

Conventionally, there is known a semiconductor device having a super junction (SJ: Super Junction) structure (hereinafter referred to as a super junction semiconductor device) in which drift layers are provided alternately in a direction (lateral direction) parallel to the principal surface of a chip. The n-type region and the p-type region of which the impurity concentration is increased are arranged in parallel pn layers. In the super junction semiconductor device, the current flows through the n-type region of the parallel pn layer in the on state, and the depletion layer also extends from the pn junction between the n-type region and the p-type region of the parallel pn layer in the off state to make the n-type region as well as the p-type region are depleted, and the load withstands voltage. In addition, in the super junction semiconductor device, since the impurity concentration of the drift layer can be increased, the on-resistance can be reduced while maintaining a high breakdown voltage.

As such a super-junction semiconductor device, a parallel pn layer having a stripe-like planar layout in which n-type regions and p-type regions are arranged to extend in the same width from the device active part to the withstand voltage structure part has been proposed. (for example, refer to the following patent document 1 (paragraph 0020, FIG. 1, FIG. 2)). In the following Patent Document 1, the withstand voltage of the withstand voltage structure is lower than that of the active part of the device by making the impurity concentration of the parallel pn layers in the withstand voltage structure lower than the impurity concentration of the parallel pn layers in the active part of the device. High pressure. The active part of the element is the area where current flows in the on state. The element peripheral portion surrounds the periphery of the active portion of the element. The withstand voltage structure part is arranged on the peripheral part of the element, and is a region that relaxes the electric field on the front side of the chip and maintains the withstand voltage.

In addition, as another super junction semiconductor device, a device in which the repetition pitch of n-type regions and p-type regions of juxtaposed pn layers is set narrower in the withstand voltage structure than in the active part of the device has been proposed (for example, refer to the following The aforementioned Patent Document 2 (paragraph 0023, FIG. 6) and the following Patent Document 3 (paragraph 0032, FIG. 1, FIG. 2)). In Patent Document 2 below, a side-by-side pn layer in which n-type regions and p-type regions are arranged in a stripe-like planar layout is provided in both the element active part and the withstand voltage structure part. In the following patent document 3, a side-by-side pn layer in which n-type regions and p-type regions are arranged in a striped planar layout is provided in the active part of the element, and a p-type region is arranged in a matrix-like planar layout in the withstand voltage structure part. A parallel pn layer formed in an n-type region.

In addition, as another super junction semiconductor device, a planar layout in which the n-type region and the p-type region of the pn layer are arranged in stripes is proposed, and the n-type region and the p-type region of the pn layer in the withstand voltage structure are arranged A device obtained by partially changing the width (hereinafter, simply referred to as width) of the horizontal direction perpendicular to the stripes (for example, refer to the following Patent Document 4). In addition, as another super junction semiconductor device, a planar layout in which the n-type region and the p-type region of the pn layer are arranged in a stripe shape has been proposed, and in the vicinity of the boundary with the withstand voltage structure part, the parallel region in the active part of the element is proposed. A device in which the width of the p-type region of the pn layer gradually becomes narrower toward the outside (for example, refer to the following Patent Document 5 (paragraph 0051, FIGS. 18 and 19 )).

In the following patent documents 2 to 5, by changing the repetition pitch of the n-type region and the p-type region of the parallel pn layer and/or the width of the p-type region of the parallel pn layer in the active part of the element and the withstand voltage structure part, thereby The impurity concentration of the parallel pn layers in the withstand voltage structure portion is made lower than the impurity concentration of the parallel pn layers in the element active portion. Therefore, similarly to Patent Document 1 below, the withstand voltage of the withstand voltage structure portion is higher than the withstand voltage of the active portion of the element.

As a method for forming the parallel pn layer, there is proposed a method in which n-type impurity ion implantation is performed on the entire surface every time an undoped layer is stacked by epitaxial growth, and is selectively performed using a resist mask. After the ion implantation of the p-type impurity, the impurity is diffused by heat treatment (for example, refer to the following Patent Document 6 (paragraph 0025, FIGS. 1 to 4 )). In Patent Document 6 below, the opening width of the resist mask for ion implantation of p-type impurities is about 1/4 of the remaining width in consideration of the subsequent thermal diffusion step, and correspondingly, the p-type impurities are The implantation amount is set to about four times the implantation amount of the n-type impurity so that the total impurity amounts of the n-type region and the p-type region in which the pn layer is juxtaposed are equal.

As another method of forming the parallel pn layer, the following proposal is proposed: Each time the n-type high resistance layer is stacked by epitaxial growth, the n-type impurity and the p-type impurity are selectively removed by using different resist masks. After the ion implantation of impurities, the impurities are diffused by heat treatment (for example, refer to the following Patent Document 7 (paragraphs 0032 to 0035, FIG. 4 )). In Patent Document 7 below, an n-type impurity-implanted region serving as an n-type region of the juxtaposed pn layer and a p-type impurity-implanted region serving as a p-type region are selectively formed so as to face each other laterally and thermally diffused. Therefore, both the n-type region and the p-type region can be increased in impurity concentration, and variations in impurity concentration near the pn junction between laterally adjacent regions can be suppressed.

prior art literature

patent documents

Patent Document 1: Japanese Patent Laid-Open No. 2008-294214

Patent Document 2: Japanese Patent Laid-Open No. 2002-280555

Patent Document 3: Japanese International Publication No. 2013/008543

Patent Document 4: Japanese Patent Laid-Open No. 2010-056154

Patent Document 5: Japanese Patent Laid-Open No. 2012-160752

Patent Document 6: Japanese Patent Laid-Open No. 2011-192824

Patent Document 7: Japanese Patent Laid-Open No. 2000-040822

Contents of the invention

technical problem

However, as a result of intensive research, the inventors of the present invention have newly found that, as in the above-mentioned Patent Document 7, by selectively performing ion implantation of n-type impurities and p-type impurities, the active part of the device and the withstand voltage structure part When forming parallel pn layers, the following problems arise. 27 and 28 are plan views showing the planar layout of parallel pn layers of a conventional super junction semiconductor device. FIG. 27( a ) and FIG. 28( a ) show the completed planar layout of the parallel pn layers. 27(a) and 28(a) show a quarter of a conventional super junction semiconductor device. 27(b) and 28(b) show states during the formation of the parallel pn layers in the boundary region 100b between the element active portion 100a and the voltage-resistant structure portion 100c. The element peripheral portion 100d is composed of a boundary region 100b and a pressure-resistant structure portion 100c. In FIGS. 27 and 28 , the horizontal direction in which the stripes of the parallel pn layers extend is y, and the horizontal direction perpendicular to the stripes is represented by x. Reference numeral 101 is an n ^- type semiconductor layer grown epitaxially to form a side-by-side pn layer.

As shown in FIG. 27(a) and FIG. 28(a), in a conventional superjunction semiconductor device, the parallel pn layer (hereinafter referred to as the first parallel pn layer) 104 of the device active part 100a and the withstand voltage structure part 100c The parallel pn layers (hereinafter referred to as second parallel pn layers) 114 all extend to the boundary region 100b between the device active part 100a and the voltage-resistant structure part 100c to be adjacent to each other. As shown in FIG. 27(b) and FIG. 28(b), when the first parallel pn layer 104 and the second parallel pn layer 114 are formed, the n-type region 102 of the first parallel pn layer 104 becomes the first n-type region 102. The impurity-implanted region 121 and the p-type impurity-implanted region 122 serving as the first p-type region 103 are each formed to extend to the first region 100e inside the boundary region 100b (on the side of the element active portion 100a ). The n-type impurity implanted regions 131, 141 which become the second n-type regions 112, 115 of the second parallel pn layer 114, and the p-type impurity implanted regions 132, 142 which become the second p-type regions 113, 116 respectively extend to the boundary The second region 100f outside the region 100b (on the side of the pressure-resistant structure 100c ) is formed. Each of these impurity-implanted regions extends to the boundary (vertical dotted line) between the first region 100e and the second region 100f, respectively.

As shown in FIG. 27, when the repetition pitch P11 of the first n-type region 102 and the first p-type region 103 and the repetition pitch P12 of the second n-type region 112 and the second p-type region 113 are set to be the same ( P11=P12), in the boundary region 100b, the regions of the same conductivity type of the first parallel pn layer 104 and the second parallel pn layer 114 are in a state of complete contact with each other. That is, the n-type impurity-implanted regions 121 and 131 forming the first n-type region 102 and the second n-type region 112 and the p-type impurity-implanted regions 122 and 132 forming the first p-type region 103 and the second p-type region 113 They are respectively arranged in a continuous stripe-like planar layout extending from the element active part 100a to the voltage-resistant structure part 100c. Therefore, in the boundary region 100b, the charge balance of the first parallel pn layer 104 and the second parallel pn layer 114 is not destroyed, and the average impurity concentrations of the first parallel pn layer 104 and the second parallel pn layer 114 are the same, as shown by There is no withstand voltage difference between the element active part 100a and the withstand voltage structure part 100c. Therefore, there is a problem that the electric field tends to be locally concentrated in the voltage-resistant structure portion 100c, and the withstand voltage of the entire element is determined by the withstand voltage of the voltage-resistant structure portion 100c.

On the other hand, as shown in FIG. 28 , when the repetition pitch P12 of the second n-type region 115 and the second p-type region 116 is set to be higher than the repetition pitch of the first n-type region 102 and the first p-type region 103 When P11 is narrow (P11>P12), the period at which regions of the same conductivity type of first parallel pn layer 104 and second parallel pn layer 114 are in contact with each other is determined based on the ratio of mutual repetition pitches P11 and P12. That is, in the boundary region 100b, the n-type impurity-implanted regions 121 and 141 forming the first n-type region 102 and the second n-type region 115, and the p-implantation regions forming the first p-type region 103 and the second p-type region 116 Type impurity-implanted regions 122 and 142 are in a state where they are in contact with each other and where they are not. Therefore, the n-type impurity concentration and the p-type impurity concentration partially become high in the boundary region 100b. For example, the p-type impurity concentration is higher than the n-type impurity concentration near the position 143 where the p-type impurity implanted regions 122 and 142 contact each other continuously, and the distance between the adjacent n-type impurity implanted regions 121 and 141 is different. Therefore, there is a problem that it is difficult to ensure charge balance at the boundary between first parallel pn layer 104 and second parallel pn layer 114 , and the withstand voltage of boundary region 100 b is partially lowered. With regard to this problem, by relatively reducing the average impurity concentration of the first parallel pn layer 104 and the second parallel pn layer 114 , partial reduction in breakdown voltage can be suppressed, but the breakdown voltage of the entire element is also reduced.

In order to solve the above-mentioned problems of the prior art, an object of the present invention is to provide a semiconductor device and a semiconductor device manufacturing method capable of reducing on-resistance and suppressing a drop in withstand voltage.

Technical solutions

In order to solve the above problems and achieve the object of the present invention, the semiconductor device of the present invention has the following features. A surface element structure is arranged on the first main surface side. A low-resistance layer is provided on the second main surface side. A first parallel pn layer is provided between the surface element structure and the low resistance layer, and a second parallel pn layer is provided so as to surround the first parallel pn layer. The first parallel pn layer is formed by alternately disposing the first regions of the first conductivity type and the first regions of the second conductivity type. The above-mentioned second parallel pn layer is the second first conductivity type region and the second second second conductivity type region at a repetition pitch than the first first first conductivity type region and the first second conductivity type region The narrow pitches are arranged alternately. An intermediate region is provided between the first parallel pn layer and the second parallel pn layer so as to be in contact with the first parallel pn layer and the second parallel pn layer. In the middle region, there is a third region of the second conductivity type and a fourth region of the second conductivity type. The third region of the second conductivity type is in contact with the first region of the second conductivity type of the first juxtaposed pn layer, and has an average impurity concentration lower than that of the first region of the second conductivity type. The fourth second conductivity type region is in contact with the second second conductivity type region of the second juxtaposed pn layer, and has a lower average impurity concentration than the second second conductivity type region.

In addition, the semiconductor device of the present invention is characterized in that, in the above invention, the intermediate region has a third first conductivity type region and a fourth first conductivity type region. The third region of the first conductivity type is in contact with the first region of the first conductivity type of the first parallel pn layer, and has an average impurity concentration lower than that of the first region of the first conductivity type. The fourth first conductivity type region is in contact with the second first conductivity type region of the second juxtaposed pn layer, and has a lower average impurity concentration than the second first conductivity type region.

In addition, the semiconductor device of the present invention is characterized in that in the above-mentioned invention, the third region in which the third first-conductivity-type regions and the third second-conductivity-type regions are alternately arranged is arranged in the middle region. Parallel pn layers.

In addition, the semiconductor device of the present invention is characterized in that in the above-mentioned invention, the fourth region in which the fourth first-conductivity-type regions and the fourth second-conductivity-type regions are alternately arranged is arranged in the middle region. Parallel pn layers.

In addition, the semiconductor device of the present invention further has the following features in the above-mentioned invention. The first region of the first conductivity type and the region of the first second conductivity type are arranged in a striped planar layout. The second first conductivity type region and the second second conductivity type region are configured to face the same stripe-shaped planar layout as the first first first conductivity type region and the first second conductivity type region. The third second conductivity type region and the fourth second conductivity type region are configured to face the same stripe-shaped planar layout as the first second conductivity type region and the second second conductivity type region.

In addition, the semiconductor device of the present invention is characterized in that, in the above invention, the third second conductivity type region and the fourth second conductivity type region facing each other at the center are adjacent to each other with a drift region interposed therebetween.

In addition, the semiconductor device of the present invention further has the following features in the above-mentioned invention. The first region of the first conductivity type and the region of the first second conductivity type are arranged in a striped planar layout. The second first conductivity type region and the second second conductivity type region are arranged in a stripe-like planar layout that is perpendicular to the first first conductivity type region and the first second conductivity type region . The third region of the second conductivity type is arranged in a stripe-like planar layout facing the same as the first region of the second conductivity type. The fourth region of the second conductivity type is arranged in a stripe-shaped planar layout facing the same as the region of the second second conductivity type.

In addition, the semiconductor device of the present invention further has the following features in the above-mentioned invention. The above-mentioned surface element structure and the above-mentioned first parallel pn layer are arranged in an element active part through which current flows when they are in an on state. The second parallel pn layer is disposed on a peripheral portion of the element surrounding the active portion of the element. A termination region is provided between the first principal surface and the low-resistance layer on a side opposite to the element active portion side of the element peripheral portion. A fifth first conductivity type region having an average impurity concentration lower than that of the second first conductivity type region is provided between the second parallel pn layer and the termination region. The conductive layer is electrically connected to the above-mentioned terminal area.

In addition, in order to solve the above-mentioned problems and achieve the object of the present invention, the method of manufacturing a semiconductor device according to the present invention has the following features. First, a forming step of repeating the first step and the second step is performed. In the first step described above, the first conductivity type semiconductor layer is deposited. In the above-mentioned second step, the first first conductive type impurity implanted region, the first second conductive type impurity implanted region, and the second first conductive type impurity implanted region are formed on the surface layer of the first conductive type semiconductor layer. an implantation region and a second second conductivity type impurity implantation region. The first impurity implantation regions of the first conductivity type and the first impurity implantation regions of the second conductivity type are arranged alternately. The second impurity implantation region of the first conductivity type and the second impurity implantation region of the second conductivity type are closer to the first impurity implantation region of the first conductivity type and the first impurity implantation region of the second conductivity type. The outer position is separated by a predetermined width from the first impurity-implanted region of the first conductivity type and the impurity-implanted region of the first second conductivity type. The second impurity-implanted region of the first conductivity type and the impurity-implanted region of the second second-conductivity type are repeated more than the first impurity-implanted region of the first conductivity type and the first impurity-implanted region of the second conductivity type. The narrow pitches are arranged alternately. Next, a heat treatment step is performed. In the heat treatment step, the first first conductivity type impurity implanted region and the first second conductivity type impurity implanted region are diffused to form the first first conductivity type region and the first second conductivity type region Alternately arranged first parallel pn layers. Diffusion of the second first conductivity type impurity implantation region and the second second conductivity type impurity implantation region to form the second first conductivity type region and the second second conductivity type region alternately arranged The second parallel pn layer. In addition, in the heat treatment step, between the first parallel pn layer and the second parallel pn layer, the first first conductivity type impurity implantation region, the first second conductivity type impurity implantation region, The second impurity-implanted region of the first conductivity type and the second impurity-implanted region of the second conductivity type are diffused to form a third region of the first conductivity type with an average impurity concentration lower than that of the first region of the first conductivity type , the third second conductivity type region with an average impurity concentration lower than the above first second conductivity type region, the fourth first conductivity type region with an average impurity concentration lower than the above second first conductivity type region, and the upper An intermediate region of the fourth second conductivity type region having an average impurity concentration lower than that of the second second conductivity type region.

In addition, the method of manufacturing a semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, in the heat treatment step, the third region of the first conductivity type and the third region of the second conductivity type are formed alternately. The middle region of the arranged third parallel pn layer and the fourth parallel pn layer formed by alternately disposing the fourth first conductivity type region and the fourth second conductivity type region.

In addition, the method of manufacturing a semiconductor device according to the present invention is characterized in that in the above-mentioned invention, in the second step, the first impurity implantation region of the first conductivity type and the first impurity implantation of the second conductivity type are implanted into The region is formed in a stripe-like planar layout, and the second impurity implantation region of the first conductivity type and the second impurity implantation region of the second conductivity type are formed to be the same as the first impurity implantation region of the first conductivity type and the first impurity implantation region of the first conductivity type. A stripe-like planar layout with the same orientation as the first impurity implantation region of the second conductivity type.

In addition, the method of manufacturing a semiconductor device according to the present invention is characterized in that in the above-mentioned invention, in the second step, the first impurity-implanted region of the first conductivity type and the first impurity-implanted region of the second conductivity type It is formed into a stripe-like planar layout, and the second impurity implantation region of the first conductivity type and the second impurity implantation region of the second conductivity type are formed to face the first impurity implantation region of the first conductivity type and the first impurity implantation region of the first conductivity type. The first second conductive type impurity implantation region is orthogonal to the striped planar layout.

In addition, in order to solve the above-mentioned problems and achieve the object of the present invention, the method of manufacturing a semiconductor device according to the present invention has the following features. First, a forming step of repeating the first step and the second step is performed. In the first step described above, the first conductivity type semiconductor layer is deposited. In the above-mentioned second step, the first second-conductivity-type impurity-implanted regions are alternately arranged on the surface layer of the above-mentioned first-conductivity-type semiconductor layer, and the impurity-implanted regions of the first second-conductivity type Where the regions are further outside separated by a predetermined width, a second second conductivity type impurity implantation region is formed at a pitch narrower than that of the first second conductivity type impurity implantation region described above. Next, the following heat treatment process is carried out. Through the heat treatment, the first second conductivity type impurity implanted region is diffused to form the first second conductivity type region and the first conductivity type semiconductor layer alternately arranged. A pn layer is arranged in parallel, and the second second conductivity type impurity implanted region is diffused to form a second parallel pn layer in which the second second conductivity type region and the first conductivity type semiconductor layer are alternately arranged. In the heat treatment step, between the first parallel pn layer and the second parallel pn layer, the first second conductivity type impurity implantation region and the second second conductivity type impurity implantation region are diffused to form having a third second conductivity type region with an average impurity concentration lower than that of the first second conductivity type region and a fourth second conductivity type region with an average impurity concentration lower than that of the second second conductivity type region middle area.

In addition, the method of manufacturing a semiconductor device according to the present invention is characterized in that in the above-mentioned invention, in the second step, the first second-conductivity-type impurity-implanted region is formed in a stripe-like planar layout, and the above-mentioned The second impurity-implanted region of the second conductivity type is formed in a stripe-like planar layout facing the same direction as the first impurity-implanted region of the second conductivity type.

In addition, the method of manufacturing a semiconductor device according to the present invention is characterized in that in the above-mentioned invention, in the second step, the first second-conductivity-type impurity-implanted region is formed in a stripe-like planar layout, and the above-mentioned The second impurity implantation region of the second conductivity type is formed in a stripe-like planar layout facing perpendicular to the first impurity implantation region of the second conductivity type.

In addition, in the method of manufacturing a semiconductor device according to the present invention, in the above invention, the predetermined width is 1/2 or less of the thickness of the first conductivity type semiconductor layer deposited in one of the first steps.

In addition, the method of manufacturing a semiconductor device according to the present invention is characterized in that, in the above invention, the first parallel pn layer and the second parallel pn layer are formed on a low-resistance layer having a resistance lower than that of the first conductivity type semiconductor layer. . After the heat treatment step, a surface element structure is formed on the side of the first parallel pn layer opposite to the side of the low resistance layer.

In addition, the method of manufacturing a semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the first parallel pn layer is formed in an element active portion through which current flows when in an on state, and the second parallel pn layer is formed in A peripheral portion of the element surrounding the active portion of the element.

According to the above invention, by forming a region where no impurity is ion-implanted between the impurity-implanted region to be the first parallel pn layer and the impurity-implanted region to be the second parallel pn layer, each impurity-implanted region is thermally diffused into the region, A third parallel pn layer having an average impurity concentration lower than that of the first parallel pn layer and a fourth parallel pn layer having an average impurity concentration lower than that of the second parallel pn layer can be formed between the first parallel pn layer and the second parallel pn layer. middle area of the layer. In addition, since the impurity amount in the middle region is lower than that of the first parallel pn layer, it is easier to deplete and the electric field is less likely to concentrate than the first parallel pn layer. Therefore, the second parallel pn layer in which the repeated pitch of the n-type region and the p-type region is narrower than that of the element active part is arranged in the voltage-resistant structure part (the terminal side part of the element peripheral part), even if the voltage-resistant structure part The withstand voltage is set higher than the withstand voltage of the element active portion, and no drop in withstand voltage occurs in the boundary region between the element active portion and the withstand voltage structure portion. Therefore, the charge balance of the first parallel pn layer and the second parallel pn layer can be adjusted separately, so that the withstand voltage of the peripheral part of the device (the withstand voltage structure part and the boundary region) is set higher than the withstand voltage of the active part of the device, so that the device Overall, it is easy to increase the withstand voltage. In addition, even if the average impurity concentration of the first parallel pn layer is increased to achieve low on-resistance, the withstand voltage difference between the peripheral portion of the element and the active portion of the element can be maintained.

Invention effect

According to the semiconductor device and the manufacturing method of the semiconductor device of the present invention, it is possible to reduce the on-resistance and suppress a decrease in withstand voltage.

Description of drawings

FIG. 1 is a plan view showing a planar layout of a semiconductor device according to Embodiment 1. As shown in FIG.

FIG. 2 is an enlarged plan view showing a portion X1 in FIG. 1 .

FIG. 3 is a cross-sectional view showing a cross-sectional structure along cutting line AA' in FIG. 1 .

Fig. 4 is a cross-sectional view showing a cross-sectional structure along a cutting line BB' in Fig. 1 .

Fig. 5 is a cross-sectional view showing a cross-sectional structure along a cutting line CC' in Fig. 1 .

6 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the first embodiment.

7 is a cross-sectional view showing a state during the manufacturing process of the semiconductor device according to the first embodiment.

8 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the first embodiment.

9 is a cross-sectional view showing a state during the manufacturing process of the semiconductor device according to the first embodiment.

FIG. 10 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to Embodiment 1. FIG.

11 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the first embodiment.

12 is a plan view showing a state during the manufacturing process of the semiconductor device according to the first embodiment.

FIG. 13 is a plan view showing a state during the manufacturing process of the semiconductor device according to Embodiment 1. FIG.

14 is a cross-sectional view showing an example of an element active portion of the semiconductor device according to the first embodiment.

15 is a cross-sectional view showing another example of the element active portion of the semiconductor device according to the first embodiment.

FIG. 16 is an enlarged plan view showing a portion X1 in FIG. 1 .

Fig. 17 is a cross-sectional view showing a cross-sectional structure along a cut line AA' in Fig. 1 .

Fig. 18 is a cross-sectional view showing a cross-sectional structure along a cutting line BB' in Fig. 1 .

Fig. 19 is a cross-sectional view showing a cross-sectional structure along a cutting line CC' in Fig. 1 .

FIG. 20 is a cross-sectional view showing a state in the process of manufacturing the semiconductor device according to Embodiment 2. FIG.

FIG. 21 is a cross-sectional view showing a state during the manufacturing process of the semiconductor device according to Embodiment 2. FIG.

22 is a cross-sectional view showing a state during the manufacturing process of the semiconductor device according to the second embodiment.

23 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the second embodiment.

FIG. 24 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to Embodiment 2. FIG.

FIG. 25 is a plan view showing a state during the manufacturing process of the semiconductor device according to Embodiment 2. FIG.

FIG. 26 is a plan view showing a state in the process of manufacturing the semiconductor device according to Embodiment 2. FIG.

27 is a plan view showing a planar layout of parallel pn layers of a conventional super junction semiconductor device.

28 is a plan view showing a planar layout of parallel pn layers of a conventional super junction semiconductor device.

FIG. 29 is a plan view showing a planar layout of a semiconductor device according to Embodiment 3. FIG.

FIG. 30 is an enlarged plan view showing a portion X2 in FIG. 29 .

FIG. 31 is an enlarged plan view showing a portion X3 in FIG. 29 .

Fig. 32 is a cross-sectional view showing a cross-sectional structure along a cutting line DD' in Fig. 29 .

Fig. 33 is a cross-sectional view showing a cross-sectional structure along a cutting line EE' in Fig. 29 .

Symbol Description

1 n ⁺ type drain layer

2 n-type buffer layer

3. 83 The first n-type region

4.84 The first p-type region

5.85 The first parallel pn layer

6 The middle area between the first parallel pn layer and the second parallel pn layer

7p base region

8 Source electrode

9 drain electrode

10a Component active part

10b Boundary area

10c Pressure-resistant structure department

10d Component Periphery

10e First area

10f Second area

10g Third zone

12 n ^-type domain

13 Second n-type region

14 Second p-type region

15 The second parallel pn layer

16 n-type channel stop region

17p-type outermost region

18 channel stop electrodes

19 Interlayer insulating film

21a～21f n ^- type semiconductor layer

22a～22e, 42a p-type impurity implantation region

23a～23e, 43a n-type impurity implanted regions

24 epitaxial layers

31, 33 Resist mask

32, 34 Ion implantation

41 The third n-type region

42 The third p-type region

43 The third parallel pn layer

44 The fourth n-type region

45 Fourth p-type region

46 The fourth parallel pn layer

47 Transition zone

51, 61 n ⁺ type source region

52, 62p ⁺ -type contact area

53, 64 Gate insulating film

54, 65 Gate electrode

63 Groove

70 n-type region

71a～71f n-type semiconductor layer

P1 Repeat pitch of the first parallel pn layer

P2 Repeat pitch of the second parallel pn layer

Y is the interval sandwiched between the center of the first p-type region and the center of the second p-type region

a1, b1 The region of the first parallel pn layer sandwiched between the positions where the centers of the first p-type region and the second p-type region are opposite to each other

a2, b2 middle region of the interval sandwiched between the positions where the centers of the first p-type region and the center of the second p-type region are opposed

a3, b3 The region of the second parallel pn layer sandwiched between the positions where the centers of the first p-type region and the second p-type region face each other

a1', a2', a3', b1', b2', b3' Midpoint

d1 The distance between the n-type impurity implanted region and the p-type impurity implanted region formed in the active part of the element

d2 The distance between the n-type impurity implanted region and the p-type impurity implanted region formed in the withstand voltage structure

w1 n ^- Width of the type region

w2 Width of pressure-resistant structure

w3 The width of the portion of the second parallel pn layer disposed in the voltage-resistant structure

w4 The width of the middle area between the first parallel pn layer and the second parallel pn layer

The thickness of the tn ^-type semiconductor layer

x is the transverse direction (second direction) orthogonal to the stripes of the juxtaposed pn layer

The lateral direction (first direction) of the extension of the stripes of y juxtaposed pn layers

z depth direction

detailed description

Hereinafter, preferred embodiments of the semiconductor device and the method for manufacturing the semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In this specification and the drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. In addition, + and - marked on n and p indicate that the impurity concentration is higher and the impurity concentration is lower than that of unmarked layers and regions, respectively. In addition, in the following description of embodiment and drawing, the same code|symbol is attached|subjected to the same structure, and redundant description is abbreviate|omitted.

(Embodiment 1)

The structure of the semiconductor device according to Embodiment 1 will be described taking an n-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor: insulated gate field effect transistor) having a superjunction structure as an example. FIG. 1 is a plan view showing a planar layout of a semiconductor device according to Embodiment 1. As shown in FIG. FIG. 2 is an enlarged plan view showing a portion X1 in FIG. 1 . FIG. 3 is a cross-sectional view showing a cross-sectional structure along cutting line AA' in FIG. 1 . Fig. 4 is a cross-sectional view showing a cross-sectional structure along a cutting line BB' in Fig. 1 . Fig. 5 is a cross-sectional view showing a cross-sectional structure along a cutting line CC' in Fig. 1 .

1 shows a plane that crosses the first parallel pn layer 5 and the second parallel pn layer 15 of the element active portion 10a and the element peripheral portion 10d, for example, the depth of the first parallel pn layer 5 located in the element active portion 10a. The shape of the plane at 1/2. The element active portion 10a is a region where current flows in the on state. The element peripheral portion 10d surrounds the periphery of the element active portion 10a. In addition, in order to clarify the repetition pitch P1 of the first n-type region (the first first conductivity type region) 3 and the first p-type region (the first second conductivity type region) 4 and the second n-type region (the first second conductivity type region) The repetition pitch P2 of the two first conductivity type regions) 13 and the second p-type region (second second conductivity type region) 14 is different, so that the number of these regions shown in FIG. 1 is less than that in FIG. 3 .

As shown in FIGS. 1 to 5 , the semiconductor device according to Embodiment 1 includes an element active portion 10 a and an element peripheral portion 10 d surrounding the periphery of the element active portion 10 a. On the first main surface (chip front) side of the element active portion 10a, a MOS gate (insulated gate made of metal-oxide film-semiconductor) structure (not shown) is provided as the front structure of the element. An n ⁺ -type drain layer (low resistance layer) 1 is provided on the second main surface side of the device active portion 10a at a position deeper than the n ⁺ -type drain layer 1 from the second main surface (chip back surface) There is an n-type buffer layer 2 . Drain electrode 9 in contact with n ⁺ -type drain layer 1 is provided on the second main surface of element active portion 10 a. The n-type buffer layer 2, the n ⁺ -type drain layer 1, and the drain electrode 9 are provided to extend from the element active portion 10a to the element peripheral portion 10d.

In the element active portion 10 a, a first parallel pn layer 5 is provided between the MOS gate structure and the n-type buffer layer 2 . The first parallel pn layer 5 is formed by alternately joining the first n-type regions 3 and the first p-type regions 4 in a direction (lateral direction) parallel to the first main surface. The planar layout of the first n-type region 3 and the first p-type region 4 is striped. The outermost (on the side of the chip end) of the overlapping portion of the first n-type region 3 and the first p-type region 4 of the first parallel pn layer 5 is, for example, the first n-type region 3, and the outermost first n-type region 3 The region 3 faces, for example, the second p-type region 14 of the second parallel pn layer 15 via an intermediate region 6 described later in a direction perpendicular to the stripes of the first parallel pn layer 5 . The first parallel pn layer 5 is arranged to extend from the element active part 10a to the boundary region between the element active part 10a and the voltage-resistant structure part 10c in the direction in which the stripes of the first parallel pn layer 5 extend and in the direction perpendicular to the stripes. 10b.

The element peripheral portion 10d is constituted by the boundary region 10b and the pressure-resistant structure portion 10c. The element peripheral portion 10d is, for example, a region outside the outer end of the gate electrode of the MOS gate structure disposed on the outermost side, or a region that is closer than the n ⁺ type source region when the n ⁺ type source region is disposed outside the gate electrode. The outer end of the type source region is more outside. The withstand voltage structure part 10c surrounds the periphery of the element active part 10a via the boundary region 10b, and is a region that relaxes the electric field on the front side of the chip and maintains a withstand voltage. The withstand voltage structure portion 10 c is, for example, a region located outside the outer end portion of the p-type base region 7 arranged on the outermost side. In the withstand voltage structure part 10c, the second parallel pn layer 15 is provided on the n-type buffer layer 2 . The second parallel pn layer 15 is formed by alternately bonding the second n-type regions 13 and the second p-type regions 14 in the lateral direction.

The planar layout of the second n-type region 13 and the second p-type region 14 is striped. The direction of the stripes of the second parallel pn layer 15 is the same as the direction of the stripes of the first parallel pn layer 5 . Hereinafter, let the horizontal direction in which the stripes of the first parallel pn layer 5 and the second parallel pn layer 15 extend be the first direction y, and let the horizontal direction perpendicular to the stripes (that is, the horizontal direction perpendicular to the first direction y) be the first direction y. Two directions x. The repetition pitch P2 of the second n-type region 13 and the second p-type region 14 is narrower than the repetition pitch P1 of the first n-type region 3 and the first p-type region 4 . Accordingly, the average impurity concentrations of the second n-type region 13 and the second p-type region 14 are lower than the average impurity concentrations of the first n-type region 3 and the first p-type region 4 , respectively. Since the second n-type region 13 and the second p-type region 14 are formed simultaneously with the first n-type region 3 and the first p-type region 4 respectively, the average impurity concentration becomes lower by making the pitch narrower, and the second parallel The depletion layer of the pn layer 15 is easy to extend in the outer peripheral direction, and it is easy to increase the withstand voltage of the initial withstand voltage. The second p-type region 14 plays the same role as a guard ring until depleted. Thereby, the electric field of the second n-type region 13 is relaxed, and thus it is easy to increase the withstand voltage of the withstand voltage structure portion 10c.

The second parallel pn layer 15 is provided so as to extend from the voltage-resistant structure part 10c to the boundary region 10b in the direction in which the stripes of the second parallel pn layer 15 extend and in the direction perpendicular to the stripes. In addition, the second parallel pn layer 15 surrounds the first parallel pn layer 5 via the intermediate region 6 , and is adjacent to the first parallel pn layer 5 through the intermediate region 6 . That is, the first parallel pn layer 5 and the second parallel pn layer 15 are in common contact with the intermediate region 6 and are continuous regions via the intermediate region 6 . The portion of the second parallel pn layer 15 disposed on the voltage-resistant structure portion 10 c may be provided so as to be thick enough not to reach the first main surface from the n-type buffer layer 2 . That is, in ion implantation and heat treatment described later for forming second parallel pn layer 15 , impurities ion-implanted into the epitaxial body need not diffuse to the first main surface. In this case, in the withstand voltage structure portion 10c, the space between the second parallel pn layer 15 and the first main surface becomes an n ⁻ -type semiconductor layer grown epitaxially when the second parallel pn layer 15 is formed.

In the intermediate region 6 between the first parallel pn layer 5 and the second parallel pn layer 15, a third parallel pn layer 43 and a fourth parallel pn layer 46 are arranged, and the third parallel pn layer 43 and the fourth parallel pn layer 46 The impurity-implanted regions forming the first parallel pn layer 5 and the second parallel pn layer 15 formed by separating the first ion implantation and the second ion implantation described later are diffused between the impurity implantation regions. The region (the third region to be described later) where impurities are ion-implanted is formed. Specifically, the inner side (chip center side) of the middle region 6 is provided with a third parallel pn layer 43 having a repeating structure with the first n-type region 3 and the first p-type region 4. The third n-type region (the third first conductivity type region) 41 and the third p-type region (the third second conductivity type region) 41 and the third p-type region (the third second conductivity type region) which are arranged alternately at a repetition pitch approximately equal to P1 and whose impurity concentration becomes lower toward the outside. type area)42. The outer portion of the middle region 6 is provided with fourth parallel pn layers 46 having alternating layers at a repetition pitch approximately equal to the repetition pitch P2 of the second n-type region 13 and the second p-type region 14. The fourth n-type region (the fourth first conductivity type region) 44 and the fourth p-type region (the fourth second conductivity type region) 45 having the lower impurity concentration toward the inner side are disposed on the ground. That is, the intermediate region 6 is composed of a third n-type region 41 having an average impurity concentration lower than that of the first n-type region 3, a fourth n-type region 44 having an average impurity concentration lower than that of the second n-type region 13, and a fourth n-type region 44 having an average impurity concentration lower than that of the first n-type region 3. The third p-type region 42 having a lower p-type region 4 and the fourth p-type region 45 having an average impurity concentration lower than that of the second p-type region 14 are configured.

In addition, the region a1 of the first parallel pn layer 5 having the same width as the width w4 of the middle region a2 of the section Y sandwiched between the positions facing the centers of the first p-type region 4 and the second p-type region 14 and the second The p-type impurity amount and n-type impurity amount in the region a3 of the parallel pn layer 15 satisfies Ca2<(Ca1+Ca3)/2 with respect to the middle region a2 of the section Y. Ca1 to Ca3 are the impurity amounts in the regions a1 to a3, respectively. The opposite center of the first p-type region 4 and the second p-type region 14 means that the center of the first p-type region 4 in the second direction x and the center of the second p-type region 14 in the second direction x are in the first direction y lie on the same line. Therefore, the intermediate region 6 is a region that is more easily depleted than the first parallel pn layer 5 in the off state. In addition, at the position where the centers of the first p-type region 4 and the second p-type region 14 face each other, the impurity concentration at the middle point a2' of the middle region a2 in the section Y is higher than that at the middle point a1 of the region a1 of the first parallel pn layer. ' and the impurity concentration of the middle point a3' of the region a3 of the second juxtaposed pn layer are low.

The third parallel pn layer 43 and the fourth parallel pn layer 46 disposed in the intermediate region 6 face each other. Between the third parallel pn layer 43 and the fourth parallel pn layer 46, the transition obtained by diffusing impurities in the impurity-implanted regions of the first parallel pn layer 5 and the second parallel pn layer 15 having different repetition pitches District 47. It should be noted that the third parallel pn layer 43 and the fourth parallel pn layer 46 may be in contact with each other by impurity diffusion between impurity implanted regions to be the first parallel pn layer 5 and the second parallel pn layer 15 .

In the withstand voltage structure portion 10c, an n ⁻ -type region (fifth first conductivity type region) 12 is provided on the n-type buffer layer 2 at a position outside the second parallel pn layer 15 . The n ⁻ -type region 12 is provided from the n-type buffer layer 2 to the thickness of the first main surface. The n ⁻ -type region 12 surrounds the second parallel pn layer 15 and has a function of suppressing the extension of the depletion layer extending outward beyond the second parallel pn layer 15 in the off state. The average impurity concentration of n ^- -type region 12 is lower than the average impurity concentration of second n -type region 13 . The width w1 of the n ^- -type region 12 is preferably, for example, about 1/20 or more and 1/3 or less of the width w2 of the voltage-resistant structure portion 10c. The reason for this is that by setting the width w3 of the portion of the second parallel pn layer 15 disposed on the voltage-resistant structure portion 10c to 2/3 or more of the width w2 of the voltage-resistant structure portion 10c, the second parallel pn layer 15 is depleted. It becomes relatively easy, so it is easy to secure a predetermined withstand voltage.

An n-type channel stop region 16 is provided on the n-type buffer layer 2 in the termination region of the voltage-resistant structure portion 10c. The n-type channel stop region 16 is provided with a thickness extending from the n-type buffer layer 2 to the first main surface. Instead of the n-type channel stopper region 16, a p-type channel stopper region may also be provided. On the first main surface side of n-type channel stopper region 16, p-type outermost peripheral region 17 is provided. The channel stopper electrode 18 is connected to the p-type outermost peripheral region 17, and is electrically insulated from the source electrode 8 of the MOS gate structure by the interlayer insulating film 19 covering the first main surface at the element peripheral portion 10d. In addition, channel stopper electrode 18 extends on interlayer insulating film 19 and protrudes inward from p-type outermost region 17 . Channel stopper electrode 18 does not need to protrude further inward than n-type channel stopper region 16 .

Although not particularly limited, for example, when the semiconductor device according to Embodiment 1 is a vertical MOSFET with a breakdown voltage of about 600V, the dimensions and impurity concentrations of each part are set to the following values. The thickness of the drift region (thickness of the first parallel pn layer 5 ) is 35 μm, and the widths of the first n-type region 3 and the first p-type region 4 are 6.0 μm (the repetition pitch P1 is 12.0 μm). The width direction of the first n-type region 3 and the first p-type region 4 arranged on the surface of the n ^- type semiconductor layer 21c corresponding to the depth of 1/2 of the drift region (the epitaxial layer 24 (see FIG. 10 ) described later) The peak impurity concentration was 4.0×10 ¹⁵ /cm ³ . The width of the second n-type region 13 and the second p-type region 14 is 4.0 μm (repetition pitch P2 is 8.0 μm). The peak impurity concentration in the width direction of the second n-type region 13 and the second p-type region 14 arranged on the surface of the n ^- type semiconductor layer 21c at a depth corresponding to 1/2 of the drift region (the epitaxial layer 24 described later) is 2.0×10 ¹⁵ /cm ³ . The width w4 of the middle region 6 is 2 μm. The peak impurity concentration in the width direction of the n ^- -type region 12 disposed on the surface of the n ^- -type semiconductor layer 21c at a depth corresponding to 1/2 of the drift region (epitaxial layer 24 described later) is preferably 1.0×10 ¹⁵ /cm ³ the following. The width w1 of the n ^- type region 12 is 8 µm. The width w2 of the pressure-resistant structure portion 10c is 150 μm. 3 to 5 (the same is true in FIGS. 17 to 19, 32, and 33), although the portion of the second parallel pn layer 15 arranged in the voltage-resistant structure portion 10c is simplified and illustrated, the second parallel pn layer 15 The width w3 of the portion disposed on the pressure-resistant structure portion 10c is 110 μm. In addition, when the withstand voltage is at the level of 300 V, the peak impurity concentration in the width direction of n ^- -type region 12 is preferably 1.0×10 ¹⁶ /cm ³ or less.

It should be noted that, in Embodiment 1, the first parallel pn layer 5 is provided between the MOS gate structure and the n-type buffer layer 2 in the device active part 10a, and the n-type buffer layer 5 is provided in the voltage-resistant structure part 10c. The second parallel pn layer 15 is provided on the buffer layer 2, but the first parallel pn layer 5 may also be provided between the MOS gate structure and the n ⁺ type drain layer 1, and the second parallel pn layer 5 may be provided on the n ⁺ type drain layer 1 Two pn layers 15 are arranged in parallel.

Next, a method of manufacturing the semiconductor device according to Embodiment 1 will be described. 6 to 11 are cross-sectional views showing states during the manufacturing process of the semiconductor device according to the first embodiment. 12 and 13 are plan views showing states during the manufacturing process of the semiconductor device according to the first embodiment. FIG. 12 shows the state during the formation of the first parallel pn layer 5 and the second parallel pn layer 15 . Specifically, FIG. 12 shows the planar layout of the impurity implantation region after the first ion implantation 32 and the second ion implantation 34 for forming the first parallel pn layer 5 and the second parallel pn layer 15 and before heat treatment. The state of the intermediate region 6 after heat treatment is shown in FIG. 13 . 6 to 11 show the state during the manufacturing process of the first parallel pn layer 5 of the element active part 10a, although the state during the manufacturing process of the second parallel pn layer 15 of the voltage-resistant structure part 10c is omitted from the illustration, However, the second parallel pn layer 15 is formed simultaneously with the first parallel pn layer 5 by the same method as the first parallel pn layer 5 . That is, in FIGS. 6 to 11 , the state in which the repetition pitch P2 is narrowed is the state in the process of manufacturing the second parallel pn layer 15 .

First, as shown in FIG. 6 , an n-type buffer layer 2 is formed by epitaxial growth on the front surface of an n ⁺ -type initial substrate as an n ⁺ -type drain layer 1 . Next, as shown in FIG. 7, on the n-type buffer layer 2, a first-stage n ^- type semiconductor layer 21a is deposited (formed) with a predetermined thickness t by epitaxial growth. Next, as shown in FIG. 8, on the n ^- type semiconductor layer 21a, a formation region corresponding to the first p-type region 4 of the first parallel pn layer 5 and the second p-type region 14 of the second parallel pn layer 15 is formed. The corresponding partially opened resist mask 31 . The width of the opening of the resist mask 31 in the second direction x is narrower than the width of the first p-type region 4 in the second direction x in the element active part 10a, and narrower than the width of the second p-type region 4 in the withstand voltage structure part 10c. 14 has a narrow width in the second direction x. In addition, the width of the opening portion of the resist mask 31 in the second direction x is narrower in the voltage-resistant structure portion 10c than in the element active portion 10a. Next, the first ion implantation 32 is performed on the p-type impurity using the resist mask 31 as a mask. By the first ion implantation 32, the p-type impurity implanted region 22a is selectively formed in the element active part 10a on the surface layer of the n ^- type semiconductor layer 21a, and the p-type impurity is selectively formed in the withstand voltage structure part 10c. Implantation region 42a (refer to FIG. 12 ). The depth of the p-type impurity-implanted regions 22a and 42a is, for example, shallower than the thickness t of the n ^- type semiconductor layer 21a.

Next, as shown in FIG. 9, after removing the resist mask 31, on the n ^- type semiconductor layer 21a, the first n-type region 3 with the first parallel pn layer 5 and the second parallel pn layer 15 are formed. The resist mask 33 obtained by opening the part corresponding to the formation area of the second n-type region 13 . The width of the opening of the resist mask 33 in the second direction x is narrower than the width of the first n-type region 3 in the second direction x in the element active part 10a, and narrower than the width of the second n-type region 3 in the voltage-resistant structure part 10c. 13 has a narrow width in the second direction x. In addition, the width of the opening portion of the resist mask 33 in the second direction x is narrower in the voltage-resistant structure portion 10c than in the element active portion 10a. Next, second ion implantation 34 is performed on the n-type impurity using the resist mask 33 as a mask. By this second ion implantation 34, an n-type impurity implanted region 23a is selectively formed in the element active part 10a on the surface layer of the n ^- type semiconductor layer 21a, and an n-type impurity implanted region 23a is selectively formed in the n ^- type semiconductor layer 21a in the withstand voltage structure part 10c. An n-type impurity implantation region 43a is selectively formed on the surface layer (see FIG. 12 ). The depth of the n-type impurity-implanted regions 23a and 43a is, for example, shallower than the thickness t of the n ^- type semiconductor layer 21a. The formation process of the n-type impurity-implanted regions 23a, 43a and the formation process of the p-type impurity-implanted regions 22a, 42a may be reversed.

In the first ion implantation 32 and the second ion implantation 34 described above, as shown in FIG. 12 , the n-type impurity implantation region 23 a and the p-type impurity implantation region 22 a are separately arranged at a predetermined interval d1 in the element active portion 10 a. In the withstand voltage structure part 10c, the n-type impurity implantation region 43a and the p-type impurity implantation region 42a are separately arranged at a predetermined interval d2. In addition, the impurity implanted regions 22a, 23a, 42a, 43a of the device active part 10a and the voltage-resistant structure part 10c are arranged to extend to the boundary region 10b between the device active part 10a and the voltage-resistant structure part 10c. Specifically, in the first direction y, the n-type impurity-implanted region 23a and the p-type impurity-implanted region 22a of the element active portion 10a are arranged to extend in the first region 10e inside the boundary region 10b (on the element active portion 10a side). . The n-type impurity-implanted region 43a and the p-type impurity-implanted region 42a of the voltage-resistant structure portion 10c are arranged to extend outside the boundary region 10b (on the side of the voltage-resistant structure portion 10c ) in the second region 10f. Furthermore, by covering the third region 10g between the first region 10e and the second region 10f with the resist masks 31 and 33, the third region 10g is not ion-implanted with impurities, so that the impurities in the element active portion 10a are The implanted regions 22a, 23a and the respective impurity implanted regions 42a, 43a of the withstand voltage structure portion 10c are arranged separately in the first direction y. The third region 10g is a portion that becomes the intermediate region 6 between the first parallel pn layer 5 and the second parallel pn layer 15 through heat treatment described later. The width w4 in the first direction y of the third region 10g (intermediate region 6) may be 1/2 or less of the thickness t of the n ^- type semiconductor layer 21a (w4≤t/2). The reason for this is that it is less susceptible to mutual adverse effects between the first parallel pn layer 5 and the second parallel pn layer 15 due to the difference in the repetition pitch of the n-type region and the p-type region, and it is less likely to cause a drop in withstand voltage in the boundary region 10b. . Specifically, when the thickness t of the n ⁻ -type semiconductor layer 21 a is about 7 μm, the width w4 of the intermediate region 6 in the first direction y may be, for example, about 2 μm.

Next, as shown in FIG. 10, after the resist mask 33 is removed, on the n ^- type semiconductor layer 21a, a plurality of n ^- type semiconductor layers 21b to 21f are further deposited by epitaxial growth, and these multi-segment (for example, 6-segment ) epitaxial layer 24 having a predetermined thickness composed of n ^- type semiconductor layers 21a to 21f. At this time, every time the n ^- type semiconductor layers 21b to 21e are deposited, the first ion implantation 32 and the second ion implantation 34 are performed in the same manner as the first n ^- type semiconductor layer 21a. The portion 10c forms a p-type impurity-implanted region and an n-type impurity-implanted region, respectively. The planar layout of the p-type impurity implantation region and the n-type impurity implantation region respectively formed in the element active part 10a and the withstand voltage structure part 10c is different from the p-type impurity implantation region and n-type impurity implantation region formed in the first n ^- type semiconductor layer 21a. The planar layout of the impurity implantation regions is the same. FIG. 10 shows a state where p-type impurity implanted regions 22b to 22e are respectively formed in n ^- -type semiconductor layers 21b to 21f in element active portion 10a, and n-type impurity implanted regions 23b to 23e are respectively formed. The first ion implantation 32 and the second ion implantation 34 may not be performed on the uppermost n ⁻ type semiconductor layer 21 f among the n ⁻ type semiconductor layers 21 a to 21 f to be the epitaxial layer 24 . Through the steps up to this point, an epitaxial substrate in which the n-type buffer layer 2 and the epitaxial layer 24 are sequentially stacked is formed on the front surface of the n ⁺ -type initial substrate as the n ⁺ -type drain layer 1 .

Next, as shown in FIG. 11, the respective n-type impurity implanted regions and the respective p-type impurity implanted regions in the n ^- -type semiconductor layers 21a to 21e are diffused by heat treatment. Each of the n-type impurity implanted regions and each of the p-type impurity implanted regions is formed in a linear shape extending in the first direction y, and therefore expands in a substantially columnar shape with the ion implantation position as a central axis. Thus, in the element active portion 10a, the n-type impurity implanted regions 23a to 23e facing each other in the depth direction z are connected to overlap each other to form the first n-type region 3, and the p The p-type impurity-implanted regions 22 a to 22 e are connected to overlap each other to form the first p-type region 4 . Furthermore, the first n-type region 3 and the first p-type region 4 are overlapped and connected to form the first parallel pn layer 5 . Similarly, in the withstand voltage structure portion 10c, the n-type impurity implanted regions (not shown) facing in the depth direction z are overlapped and connected to each other to form the second n-type region 13, and the opposing n-type impurity regions (not shown) in the depth direction z The p-type impurity-implanted regions (not shown) are overlapped and connected to form the second p-type region 14 . Furthermore, the second n-type region 13 and the second p-type region 14 are overlapped and connected to form the second parallel pn layer 15 . At this time, in the third region 10g of the boundary region 10b, n-type impurities and p-type impurities are respectively diffused from the n-type impurity implanted region and each p-type impurity implanted region of the element active portion 10a and the withstand voltage structure portion 10c to form an intermediate region. 6.

Although not particularly limited, for example, when the semiconductor device according to Embodiment 1 is a vertical MOSFET with a withstand voltage of 600 V and a width w4 of the intermediate region 6 in the first direction y of about 2 μm, the first ion implantation 32, the second The conditions of the secondary ion implantation 34 and the subsequent heat treatment for impurity diffusion are as follows. In the first ion implantation 32 , the doses of the first p-type region 4 and the second p-type region 14 are set to about 0.2×10 ¹³ /cm ² to 2.0×10 ¹³ /cm ² . In the second ion implantation 34 , the doses of the first n-type region 3 and the second n-type region 13 are about 0.2×10 ¹³ /cm ² to 2.0×10 ¹³ /cm ² . The heat treatment temperature is about 1000°C to 1200°C.

The state of the intermediate region 6 after the heat treatment is shown in FIG. 13 . The third region 10g where impurity ion implantation is not performed between the impurity implanted regions to become the first parallel pn layer 5 and the second parallel pn layer 15 formed by separating the first ion implantation 32 and the second ion implantation 34 from each other , an intermediate region 6 is formed, and the intermediate region 6 includes a third parallel pn layer 43 and a fourth parallel pn layer 46 obtained by diffusing the respective impurity-implanted regions. Specifically, a third parallel pn layer 43 is formed on the inner side (chip center side) of the intermediate region 6 as the third region 10g, and the third parallel pn layer 43 has The third n-type region 41 and the third p-type region 42 are arranged alternately at a repetition pitch P1 almost equal to the repetition pitch of the region 4 , and the impurity concentration becomes lower toward the outside. The outer portion of the middle region 6 is formed with fourth juxtaposed pn layers 46 having a repeating pitch approximately equal to the repeating pitch P2 of the second n-type region 13 and the second p-type region 14 alternately. A fourth n-type region 44 and a fourth p-type region 45 with lower impurity concentration are arranged inwardly. That is, the intermediate region 6 is formed with a third n-type region 41 having an average impurity concentration lower than that of the first n-type region 3, a fourth n-type region 44 having an average impurity concentration lower than that of the second n-type region 13, and a fourth n-type region 44 having an average impurity concentration lower than that of the first n-type region 3. The third p-type region 42 lower than the p-type region 4 and the fourth p-type region 45 whose average impurity concentration is lower than that of the second p-type region 14 are lower than the first parallel pn layer 5 and the second parallel pn layer when they are in the off state. 15 more prone to depletion areas.

The third parallel pn layer 43 and the fourth parallel pn layer 46 disposed in the intermediate region 6 face each other. Between the third parallel pn layer 43 and the fourth parallel pn layer 46, there is a transition obtained by diffusing impurities in the impurity implanted regions of the first parallel pn layer 5 and the second parallel pn layer 15 having different repetition pitches. District 47. It should be noted that the third parallel pn layer 43 and the fourth parallel pn layer 46 may be in contact so as to be overlapped by impurity diffusion between impurity implanted regions to be the first parallel pn layer 5 and the second parallel pn layer 15 .

The planar layout of the second n-type region 13 and the second p-type region 14 is preferably striped. The reason is that it is easy to adjust the respective average impurity concentrations of the plurality of second n-type regions 13 and the plurality of second p-type regions 14 to be substantially the same, and it is easy to ensure the charge balance of the second parallel pn layer 15 . Assume that second p-type regions 14 are arranged in a matrix-like planar layout, and second n-type regions 13 are formed in a grid-like planar layout surrounding second p-type regions 14 . In this case, second p-type region 14 has a substantially rectangular planar shape, whereas second n-type region 13 has a grid-like planar shape having three times the surface area of second p-type region 14 . Therefore, there is a concern that, in order to uniformly diffuse the n-type impurity throughout the second n-type region 13, it is difficult to study the planar layout of the n-type impurity implanted region as the second n-type region 13, and/or the resist mask The average impurity concentration of each of the plurality of second n-type regions 13 varies due to differences in ion implantation such as limitations in processing accuracy of the mold. The adverse effect caused by the difference in ion implantation is particularly noticeable in the voltage-resistant structure portion 10c in which the repetition pitch P2 of the second n-type region 13 and the second p-type region 14 is narrow. On the other hand, when the planar layout of the second n-type region 13 and the second p-type region 14 is made into stripes, both the second n-type region 13 and the second p-type region 14 are straight lines with substantially equal surface areas. flat shape. Therefore, by making the widths of the n-type impurity-implanted region and the p-type impurity-implanted region equal in the second direction x, the respective average impurity concentrations of the plurality of second n-type regions 13 and the plurality of second p-type regions 14 can be adjusted to Easily adjusted to approximately the same.

The n-type channel stop region 16 can be formed by the first ion implantation 32 at the same time as the formation of the first p-type region 4 and the second p-type region 14, or can be selectively performed at a timing different from that of the first ion implantation 32. Formed by ion implantation of p-type impurities. The n ^- type region 12 can be formed by covering the formation area of the n ^- type region 12 with resist masks 31, 33 during the first ion implantation 32 and the second ion implantation 34, and it is also possible to further increase the selective ion implantation of the n-type region. Formed by the process of impurities. Next, the remaining steps such as the step of forming the MOS gate structure and/or the p-type outermost region 17 , the interlayer insulating film 19 , the source electrode 8 , the channel stopper electrode 18 , and the drain electrode 9 are sequentially performed by a usual method. Thereafter, by dicing (cutting) the epitaxial substrate into chips, the super junction semiconductor device shown in FIGS. 1 to 5 is completed.

It should be noted that in the semiconductor device manufacturing method of Embodiment 1, although the n-type buffer layer 2 is formed on the front surface of the n ⁺ -type initial substrate to be the n ⁺ -type drain layer 1, the n-type buffer layer 2 may not be formed. layer 2, and an epitaxial layer 24 is formed on the front surface of the n ⁺ -type initial substrate to become the n ⁺ -type drain layer 1 .

Next, an example of the element active portion 10 a of the semiconductor device according to Embodiment 1 will be described. 14 is a cross-sectional view showing an example of an element active portion of the semiconductor device according to the first embodiment. 15 is a cross-sectional view showing another example of the element active portion of the semiconductor device according to the first embodiment. As shown in FIG. 14, on the first main surface side of the element active portion 10a, there is provided a p-type base region 7, an n ⁺ type source region 51, a p ⁺ type contact region 52, a gate insulating film 53, and a gate electrode 54. The usual planar gate structure of the MOS gate structure. In addition, as shown in FIG. 15, on the first main surface side of the element active portion 10a, a p-type base region 7, an n ⁺ type source region 61, a p ⁺ type contact region 62, a trench 63, and a gate insulating film may be provided. 64 and the gate electrode 65 constitute the MOS gate structure of the common trench gate structure. In these MOS gate structures, the p-type base region 7 may be arranged so as to be in contact with the first p-type region 4 of the first parallel pn layer 5 in the depth direction z. Dotted lines in the first parallel pn layer 5 are boundaries between n ^- -type semiconductor layers stacked by epitaxial growth when the first parallel pn layer 5 is formed.

(Embodiment 2)

The structure of the semiconductor device according to Embodiment 2 will be described by taking an n-channel MOSFET having a superjunction structure as an example. The plan view showing the planar layout of the semiconductor device according to the second embodiment is the same as the plan view showing the planar layout of the semiconductor device according to the first embodiment. FIG. 16 is an enlarged plan view showing a portion X1 in FIG. 1 . Fig. 17 is a cross-sectional view showing a cross-sectional structure along a cut line AA' in Fig. 1 . Fig. 18 is a cross-sectional view showing a cross-sectional structure along a cutting line BB' in Fig. 1 . Fig. 19 is a cross-sectional view showing a cross-sectional structure along a cutting line CC' in Fig. 1 .

The difference between the semiconductor device of Embodiment 2 and the semiconductor device of Embodiment 1 is that the first n-type region 3, the second n-type region 13, the third n-type region 41, and the fourth n-type region 44 have the same average impurity concentration, and is not formed by ion implantation of n-type impurities. Even without ion implantation of n-type impurities for forming the first n-type region 3 and the second n-type region 13, the concentration of n-type impurities in the epitaxial substrate (n-type semiconductor layers 71a to 71f described later) is not changed. Also in the case of forming n-type regions juxtaposed with pn layers, the same effect as that of the first embodiment can be obtained by providing the intermediate region 6 .

The middle region 6 between the first parallel pn layer 5 and the second parallel pn layer 15 is configured with a third parallel pn layer 43 and a fourth parallel pn layer 46, and the third parallel pn layer 43 and the fourth parallel pn layer 46 are passed through The impurity-implanted regions forming the first parallel pn layer 5 and the second parallel pn layer 15 formed separately by the first ion implantation are diffused into regions between the impurity-implanted regions where no impurity ion-implantation is performed (the third region). ) made. Specifically, the inner side (chip central side) of the middle region 6 is provided with a third parallel pn layer 43, and the third parallel pn layer 43 is approximately equal to the overlapping pitch P1 of the first n-type region 3 and the first p-type region 4. They are arranged alternately at equal repetition pitches, and have third p-type regions 42 whose impurity concentration decreases toward the outside. The outer portion of the intermediate region 6 is provided with fourth parallel pn layers 46, and the fourth parallel pn layers 46 are alternately arranged at a repetition pitch substantially equal to the repetition pitch P2 of the second n-type regions 13 and the second p-type regions 14. formed, and has a fourth p-type region 45 with a lower impurity concentration toward the inner side. That is, the intermediate region 6 is composed of a third n-type region 41 and a fourth n-type region 44 having the same average impurity concentration as that of the first n-type region 3 and a third p-type region having an average impurity concentration lower than that of the first p-type region 4. 42 and a fourth p-type region 45 having an average impurity concentration lower than that of the second p-type region 14 .

In addition, the region b1 of the first parallel pn layer 5 having the same width as the width w4 of the intermediate region b2 of the section Y sandwiched between the positions facing the centers of the first p-type region 4 and the second p-type region 14 and the second The p-type impurity amount in the region b3 of the juxtaposed pn layer 15 satisfies Cb2<(Cb1+Cb3)/2 with respect to the middle region b2 of the section Y. Cb1 to Cb3 are the p-type impurity amounts in regions b1 to b3, respectively. Therefore, the intermediate region 6 is a region that is more likely to be depleted than the first parallel pn layer 5 in the off state. In addition, at the position where the centers of the first p-type region 4 and the second p-type region 14 face each other, the impurity concentration at the middle point b2' of the middle region b2 of the section Y is higher than that at the middle point of the region b1 of the first parallel pn layer 5. The impurity concentration of b1' and the impurity concentration of the middle point b3' of the region b3 of the second parallel pn layer 15 are low. The third parallel pn layer 43 and the fourth parallel pn layer 46 disposed in the intermediate region 6 face each other. In addition, the third parallel pn layer 43 and the fourth parallel pn layer 46 may be in contact with each other by impurity diffusion between impurity-implanted regions to become the first parallel pn layer 5 and the second parallel pn layer 15 .

Although not particularly limited, for example, when the semiconductor device according to Embodiment 2 is a vertical MOSFET with a breakdown voltage of about 600V, the dimensions and impurity concentrations of each part are the following values. The thickness of the drift region (thickness of the first parallel pn layer 5 ) is 35 μm, and the widths of the first n-type region 3 and the first p-type region 4 are 6.0 μm (the repetition pitch P1 is 12.0 μm). Peak impurity concentration in the width direction of the first n-type region 3 (n-type semiconductor layers 71a to 71f) disposed on the surface of the n-type semiconductor layer 71c at a depth corresponding to 1/2 of the drift region (epitaxial layer 24 described later) It is 4.0×10 ¹⁵ /cm ³ . The peak impurity concentration in the width direction of the first p-type region 4 disposed on the surface of the n-type semiconductor layer 71c at a depth corresponding to 1/2 of the drift region (epitaxial layer 24 described later) is 4.0×10 ¹⁵ /cm ³ . The width of the second n-type region 13 and the second p-type region 14 is 4.0 μm (repetition pitch P2 is 8.0 μm). The peak impurity concentration in the width direction of the second p-type region 14 disposed on the surface of the n-type semiconductor layer 71c at a depth corresponding to 1/2 of the drift region (epitaxial layer 24 described later) is 2.0×10 ¹⁵ /cm ³ . The width w4 of the middle region 6 is 2 μm. The width w2 of the voltage-resistant structure portion 10c is 150 μm, and the width w3 of the portion of the second parallel pn layer 15 disposed on the voltage-resistant structure portion 10 c is 110 μm.

In the withstand voltage structure portion 10 c , an n-type region 70 is provided on the n-type buffer layer 2 at a position outside the second parallel pn layer 15 .

It should be noted that in the second embodiment, the first parallel pn layer 5 is provided between the MOS gate structure and the n-type buffer layer 2 in the element active part 10a, and the n The second parallel pn layer 15 is provided on the buffer layer 2, but the first parallel pn layer 5 may also be provided between the MOS gate structure and the n ⁺ type drain layer 1, and the second parallel pn layer 5 may be provided on the n ⁺ type drain layer 1. Two pn layers 15 are arranged in parallel.

Next, a method of manufacturing the semiconductor device according to Embodiment 2 will be described. 20 to 24 are cross-sectional views showing states during the manufacturing process of the semiconductor device according to the second embodiment. 25 and 26 are plan views showing states during the manufacturing process of the semiconductor device according to the second embodiment. FIG. 25 shows the planar layout of the impurity implantation region after the first ion implantation 32 for forming the first parallel pn layer 5 and the second parallel pn layer 15 and before heat treatment. FIG. 26 shows the state of the intermediate region 6 after heat treatment. The manufacturing method of the semiconductor device according to the second embodiment differs from the manufacturing method of the semiconductor device according to the first embodiment in that the second ion implantation 34 for ion-implanting n-type impurities is not performed.

Specifically, first, as shown in FIG. 20 , an n-type buffer layer 2 is formed by epitaxial growth on the front surface of an n ⁺ -type initial substrate as an n ⁺ -type drain layer 1 . Next, as shown in FIG. 21, on the n-type buffer layer 2, a first-stage n-type semiconductor layer 71a is deposited (formed) with a predetermined thickness t by epitaxial growth. Next, as shown in FIG. 22 , on the n-type semiconductor layer 71a, a region corresponding to the formation region of the first p-type region 4 of the first parallel pn layer 5 and the second p-type region 14 of the second parallel pn layer 15 is formed. The partially opened resist mask 31. The width of the opening of the resist mask 31 in the second direction x is narrower than the width of the first p-type region 4 in the second direction x in the element active part 10a, and narrower than the width of the second p-type region 4 in the withstand voltage structure part 10c. 14 has a narrow width in the second direction x. In addition, the width of the opening portion of the resist mask 31 in the second direction x is narrower in the voltage-resistant structure portion 10c than in the element active portion 10a. Next, the first ion implantation 32 is performed on the p-type impurity using the resist mask 31 as a mask. By this first ion implantation 32, the p-type impurity implantation region 22a is selectively formed in the element active portion 10a on the surface layer of the n-type semiconductor layer 71a, and the p-type impurity implantation region 22a is selectively formed in the withstand voltage structure portion 10c. area 42a (see FIG. 25). The depth of the p-type impurity implanted regions 22a and 42a is, for example, shallower than the thickness t of the n-type semiconductor layer 71a.

In the above-mentioned first ion implantation 32, as shown in FIG. 25, the p-type impurity implanted regions 22a and 42a of the element active portion 10a and the voltage-resistant structure portion 10c are arranged to extend to the element active portion 10a and the voltage-resistant structure portion 10c. The border area 10b between. Specifically, in the first direction y, the p-type impurity implanted region 22a of the element active portion 10a is arranged to extend to the first region 10e inside the boundary region 10b (on the side of the element active portion 10a ). The p-type impurity implanted region 42a of the voltage-resistant structure portion 10c is arranged to extend to the second region 10f outside the boundary region 10b (on the side of the voltage-resistant structure portion 10c). Furthermore, by covering the third region 10g between the first region 10e and the second region 10f with the resist mask 31, the third region 10g is not implanted with impurity ions, and the p-type impurity in the element active portion 10a is removed. The implanted region 22 a and the p-type impurity implanted region 42 a of the withstand voltage structure portion 10 c are arranged separately in the first direction y. The third region 10g is a portion that serves as the intermediate region 6 between the first parallel pn layer 5 and the second parallel pn layer 15 through heat treatment described later. The width w4 in the first direction y of the third region 10g (intermediate region 6 ) may be 1/2 or less of the thickness t of the n-type semiconductor layer 71a (w4≦t/2). The reason for this is that it is less susceptible to mutual adverse effects between the first parallel pn layer 5 and the second parallel pn layer 15 due to the difference in the repeating pitch of the n-type region and the p-type region, and it is less likely to generate a breakdown voltage in the boundary region 10b. reduce. Specifically, when the thickness t of the n ⁻ -type semiconductor layer 21 a is about 7 μm, the width w4 of the intermediate region 6 in the first direction y may be, for example, about 2 μm.

Next, as shown in FIG. 23, after the resist mask 31 is removed, on the n-type semiconductor layer 71a, a plurality of n-type semiconductor layers 71b to 71f are further deposited by epitaxial growth to form a multi-segment (for example, 6-segment) An epitaxial layer 24 having a predetermined thickness composed of n-type semiconductor layers 71a to 71f. At this time, every time the n-type semiconductor layers 71b to 71e are deposited, the first ion implantation 32 is performed in the same manner as the first n-type semiconductor layer 71a, and p-type impurity implants are formed in the element active part 10a and the withstand voltage structure part 10c respectively. area. The planar layout of the p-type impurity implanted regions formed in the element active part 10a and the withstand voltage structure part 10c is the same as that of the p-type impurity implanted regions formed in the first n-type semiconductor layer 71a. FIG. 23 shows a state where p-type impurity implanted regions 22b to 22e are respectively formed in the n-type semiconductor layers 71b to 71f of the element active portion 10a. The first ion implantation 32 may not be performed on the uppermost n-type semiconductor layer 71f among the n-type semiconductor layers 71a to 71f serving as the epitaxial layer 24 . Through the steps up to this point, an epitaxial substrate in which the n-type buffer layer 2 and the epitaxial layer 24 are sequentially stacked is formed on the front surface of the n ⁺ -type initial substrate as the n ⁺ -type drain layer 1 .

Next, as shown in FIG. 24, the respective p-type impurity implanted regions in the n-type semiconductor layers 71a to 71e are diffused by heat treatment. Each p-type impurity implantation region is formed in a linear shape extending in the first direction y, and therefore expands in a substantially columnar shape with the ion implantation position as a central axis. Thus, in the element active portion 10a, the p-type impurity implanted regions 22a to 22e facing each other in the depth direction z are connected so as to overlap each other, and the first p-type region 4 is formed. Similarly, in the withstand voltage structure portion 10c, p-type impurity-implanted regions (not shown) facing each other along the depth direction z are connected so as to overlap each other to form the second p-type region 14 . At this time, in the third region 10g of the boundary region 10b, p-type impurities are diffused from the respective p-type impurity implanted regions of the element active portion 10a and the withstand voltage structure portion 10c to form the intermediate region 6 .

Although not particularly limited, for example, when the semiconductor device according to Embodiment 2 is a vertical MOSFET with a withstand voltage of 600 V and a width w4 of the intermediate region 6 in the first direction y of about 2 μm, the first ion implantation 32 and its The conditions of the subsequent heat treatment for impurity diffusion are as follows. In the first ion implantation 32 , the doses of the first p-type region 4 and the second p-type region 14 are set to about 0.2×10 ¹³ /cm ² to 2.0×10 ¹³ /cm ² . The heat treatment temperature is about 1000°C to 1200°C.

The states of the intermediate regions 6 after the heat treatment are shown in FIG. 26 . Between the p-type impurity-implanted regions of the first parallel pn layer 5 and the second parallel pn layer 15 formed by separating each other by the first ion implantation 32, a third region 10g where impurity ion implantation is not performed is formed, and an intermediate region 10g is formed. The region 6 and the intermediate region 6 include a third parallel pn layer 43 and a fourth parallel pn layer 46 diffused from the impurity-implanted region. Specifically, a third parallel pn layer 43 is formed on the inner side (chip center side) of the intermediate region 6 as the third region 10g, and the third parallel pn layer 43 is formed so as to be compatible with the first n-type region 3 and the first p-type region. The repeating pitch P1 of 4 is alternately arranged at substantially the same repeating pitch, and has the third p-type region 42 whose impurity concentration becomes lower toward the outer side. Fourth parallel pn layers 46 are formed on the outer portion of the middle region 6, and the fourth parallel pn layers 46 are alternately arranged at a repetition pitch substantially equal to the repetition pitch P2 of the second n-type regions 13 and the second p-type regions 14. As a result, the fourth p-type region 45 has a lower impurity concentration toward the inner side. That is, in the middle region 6, a third n-type region 41 and a fourth n-type region 44 having the same average impurity concentration as that of the first n-type region 3 and a third p-type region 44 having an average impurity concentration lower than that of the first p-type region 4 are formed. Type region 42 and fourth p-type region 45 are regions that are more likely to be depleted than first parallel pn layer 5 in the off state.

The third parallel pn layer 43 and the fourth parallel pn layer 46 disposed in the intermediate region 6 face each other. It should be noted that third parallel pn layer 43 and fourth parallel pn layer 46 may be in contact with each other by impurity diffusion between impurity implanted regions to become first parallel pn layer 5 and second parallel pn layer 15 . It should be noted that the difference between Embodiment 2 and Embodiment 1 is that the second ion implantation 34 is not performed on the first n-type region 3 and the second n-type region 13, but the element active portion 10a of the semiconductor device in Embodiment 2 is the same as The element active portion 10 a of the semiconductor device according to Embodiment 1 has the same configuration.

(Embodiment 3)

The structure of the semiconductor device according to Embodiment 3 will be described by taking an n-channel MOSFET having a superjunction structure as an example. FIG. 29 is a plan view showing a planar layout of a semiconductor device according to Embodiment 3. FIG. Fig. 30 is an enlarged plan view showing a portion X2 in Fig. 29 . Fig. 31 is an enlarged plan view showing a portion X3 in Fig. 29 . Fig. 32 is a cross-sectional view showing a cross-sectional structure along a cutting line DD' in Fig. 29 . Fig. 33 is a cross-sectional view showing a cross-sectional structure along a cutting line EE' in Fig. 29 . 29 shows a plane that crosses the first parallel pn layer 85 and the second parallel pn layer 15 of the element active part 10a and the element peripheral part 10d, for example, the depth is 1 of the first parallel pn layer 85 of the element active part 10a. /2 the shape of the plane. In order to clarify the difference between the repetition pitch P1 of the first n-type region 83 and the first p-type region 84 and the repetition pitch P2 of the second n-type region 13 and the second p-type region 14, these shown in FIG. 29 The number of regions is smaller than that in FIGS. 30 to 34 .

The semiconductor device of Embodiment 3 differs from the semiconductor device of Embodiment 1 in that the first parallel pn layer 85 is arranged in a stripe-like planar layout extending in a direction perpendicular to the direction in which the stripes of the second parallel pn layer 15 extend ( Figures 29 to 33). In Embodiment 3, the lateral direction in which the stripes of the first parallel pn layer 85 extend is referred to as the second direction x, and the lateral direction in which the stripes of the second parallel pn layer 15 extend is referred to as the first direction y. The configuration of the element active portion 10 a is the same as that of the first embodiment except for the planar layout of the first parallel pn layer 85 . The configuration of the element peripheral portion 10d is the same as that of the first embodiment. Like Embodiment 1, second parallel pn layer 15 surrounds first parallel pn layer 85 via intermediate region 6 , and is adjacent to first parallel pn layer 85 via intermediate region 6 .

That is, between the linear portion (hereinafter referred to as the first linear portion) 6b parallel to the first direction y (hereinafter referred to as the first linear portion) and the linear portion (hereinafter referred to as the first linear portion) parallel to the second direction x of the intermediate region 6 arranged in a substantially rectangular frame-like planar layout (hereinafter referred to as , referred to as the second straight line portion) 6a, the configurations of the third parallel pn layer 43 and the fourth parallel pn layer 46 are different. The third parallel pn layer 43 and the fourth parallel pn layer 46 are similar to the first embodiment, and the impurity implanted regions to be the first parallel pn layer 85 and the second parallel pn layer 15 are respectively diffused into the respective impurity implanted regions. The intervening region (the above-mentioned third region) in which ions of impurities are not implanted is formed. The conditions of the repetition pitch P1 of the first n-type region 83 and the first p-type region 84 and the repetition pitch P2 of the second n-type region 13 and the second p-type region 14 are the same as those of the first embodiment.

Specifically, as shown in FIG. 30 , for example, the first n-type region 83 on the outermost side of the overlapping portion of the first n-type region 83 and the first p-type region 84 of the first juxtaposed pn layer 85 is parallel to the first The direction (first direction y) perpendicular to the stripes of the pn layer 85 separates the second straight portion 6a of the intermediate region 6 from the stripe ends of the second n-type region 13 and the second p-type region 14 of the second parallel pn layer 15 opposite. That is, only the third n-type region 41 of the third parallel pn layer 43 is arranged in the inner part of the second linear part 6a of the intermediate region 6, and the fourth n-type region 44 and the fourth n-type region 44 are arranged in the outer part through the transition region 47. The fourth parallel pn layer 46 formed by alternating the fourth p-type regions 45 in the second direction x.

The transition region 47 in the second linear portion 6a of the intermediate region 6 is, for example, the first n-type region 83 that becomes the first parallel pn layer 85, the second n-type region 13 of the second parallel pn layer 15, and the second p-type region. 14 is a region formed by diffusion of impurities in each impurity-implanted region. The amount of n-type impurities in the region a11 of the first parallel pn layer 85 and the region a13 of the second parallel pn layer 15 having the same width as the width w4 of the second straight line portion 6a of the middle region 6 relative to the second straight line portion of the middle region 6 6a, satisfying Ca12<(Ca11+Ca13)/2. Ca11 to Ca13 are the amounts of n-type impurities in the region a11 , the second linear portion 6 a , and the region a13 , respectively. The p-type impurity amount of the second linear portion 6 a of the intermediate region 6 decreases from the outer side to the inner side.

On the other hand, as shown in FIG. 31 , the innermost, for example, second n-type region 13 of the overlapping portion of the second n-type region 13 and the second p-type region 14 of the second juxtaposed pn layer 15 The direction (second direction x) perpendicular to the stripes of the pn layer 15 is separated from the first n-type region 83 and the first p-type region 84 of the first juxtaposed pn layer 85 via the first straight portion 6b of the intermediate region 6. The ends of the stripes are opposite. That is, the third parallel pn layer 43 in which the third n-type region 41 and the third p-type region 42 are alternately repeated along the first direction y is disposed on the inner portion of the first linear portion 6b of the intermediate region 6, Only the fourth n-type region 44 of the fourth juxtaposed pn layer 46 is disposed on the outer portion with the transition region 47 interposed therebetween.

The transition region 47 in the first linear portion 6b of the intermediate region 6 is the first n-type region 83 and the first p-type region 84 of the first parallel pn layer 85, and the second n-type region 84 of the second parallel pn layer 15, for example, Impurities in the impurity-implanted regions of the impurity-type region 13 are diffused. The amount of n-type impurities in the region a21 of the first parallel pn layer 85 and the region a23 of the second parallel pn layer 15 having the same width as the width w4 of the first straight line portion 6b of the middle region 6 is relative to the first straight line portion 6 of the middle region 6. The line portion 6b satisfies Ca22<(Ca21+Ca23)/2. Ca21 to Ca23 are the n-type impurity amounts in the region a21 , the second linear portion 6 b , and the region a23 , respectively. The p-type impurity amount of the first linear portion 6b of the intermediate region 6 decreases from the inner side to the outer side.

In the manufacturing method of the semiconductor device of Embodiment 3, in the manufacturing method of the semiconductor device of Embodiment 1, the first ion implantation 32 and the second ion implantation for forming the first parallel pn layer 85 and the second parallel pn layer 15 are changed. The planar layout of the resist masks 31 and 33 (see FIGS. 8 to 10 ) used in 34 is sufficient. Specifically, the resist mask 31 used in the first ion implantation 32 has a part corresponding to the formation region of the first p-type region 84 of the first parallel pn layer 85 and the second p-type region of the second parallel pn layer 15 . Openings are made in a partially orthogonal planar layout corresponding to the formation region of the type region 14 . The resist mask 33 used in the second ion implantation 34 has a part corresponding to the formation region of the first n-type region 83 of the first parallel pn layer 85 and a part corresponding to the formation region of the second n-type region 13 of the second parallel pn layer 15 . Openings are formed by forming a partially orthogonal plane layout corresponding to the area.

In Embodiment 3, when the withstand voltage is at the level of 600V, the impurity concentration in the intermediate region 6 (first linear portion 6b, second linear portion 6a) is preferably, for example, about 1.0×10 ¹⁴ /cm ³ or less. In addition, when the breakdown voltage is at the level of 300 V, the impurity concentration of the intermediate region 6 is preferably, for example, about 1.0×10 ¹⁵ /cm ³ or less.

Embodiment Mode 3 can be applied to the semiconductor device of Embodiment Mode 2.

As described above, according to each of the above-described embodiments, by forming the third region where impurity ion implantation is not performed between the impurity implanted region to be the first parallel pn layer and the impurity implanted region to be the second parallel pn layer, Each impurity implantation region is thermally diffused in the third region, and a third parallel pn layer having an average impurity concentration lower than that of the first parallel pn layer and an average impurity concentration ratio can be formed between the first parallel pn layer and the second parallel pn layer. The middle region of the fourth parallel pn layer lower than the second parallel pn layer. In addition, the impurity amount in the middle region is lower than that of the first parallel pn layer, so it is easier to deplete and less likely to concentrate the electric field than the first parallel pn layer. Therefore, even if the second parallel pn layer in which the repetition pitch of the n-type region and the p-type region is narrower than that of the element active portion is arranged in the voltage-resistant structure portion, the withstand voltage of the voltage-resistant structure portion is higher than that of the element active portion, and the Changes in the charge balance in the boundary region between the active part of the element and the voltage-resistant structure part will not adversely affect each other. Therefore, no drop in withstand voltage occurs in the boundary region between the element active portion and the withstand voltage structure portion. Therefore, since the charge balance of the first parallel pn layer and the second parallel pn layer can be adjusted separately, the withstand voltage of the peripheral part of the element (the withstand voltage structure part and the boundary region) is higher than the withstand voltage of the active part of the element, and the entire element is stable. High withstand voltage becomes easy. Therefore, reliability can be improved. Also, even if the on-resistance is lowered by increasing the average impurity concentration of the first parallel pn layer, the difference in withstand voltage between the peripheral portion of the element and the active portion of the element can be maintained. Therefore, on-resistance can be reduced, and a drop in withstand voltage can be suppressed. In addition, by making the withstand voltage of the peripheral part of the device higher than that of the active part of the device, breakdown (breakdown) can occur faster in the active part of the device than in the peripheral part of the device, so that the avalanche resistance and reverse recovery resistance can be improved.

In addition, in the configuration in which a guard ring is provided on the peripheral portion of the element as in the past (for example, FIG. 8 of the above-mentioned Patent Document 1), since a plurality of guard rings are arranged concentrically apart from each other to surround the active portion of the element, Therefore, the width of the peripheral portion of the element becomes longer. On the other hand, according to each of the above-described embodiments, the second p-type region of the second parallel pn layer provided on the peripheral portion of the element functions similarly to the guard ring. Therefore, by providing the second parallel pn layer on the peripheral portion of the element, the peripheral portion of the element can be easily depleted during turn-off, and it is not necessary to provide a guard ring on the peripheral portion of the element, thereby preventing the width of the voltage-resistant structure from becoming long. In addition, according to each of the above-mentioned embodiments, by providing the n ^- -type region outside the second parallel pn layer, in the off state, the second parallel pn layer can be quickly depleted and suppressed by the second parallel pn layer. An extension of the depletion layer in which the parallel pn layer extends further outward. As a result, the depletion layer is less likely to reach the n-type channel stop region, and local electric field concentration is less likely to occur in the vicinity of the n-type channel stop region, so that a drop in withstand voltage can be suppressed. In addition, by arranging the n ^- -type region and the n-type region outside the second parallel pn layer, the extension of the depletion layer can be suppressed, so that the width of the withstand voltage structure can be shortened. In addition, according to Embodiment 3, even in the case of a planar layout in which the direction in which the stripes of the first parallel pn layer extend is perpendicular to the direction in which the stripes of the second parallel pn layer extend, the first parallel pn layer can be individually adjusted. , Charge balance of the second juxtaposed pn layer. Therefore, the degree of freedom of design is high.

As mentioned above, the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the present invention. For example, the dimensions, impurity concentrations, and the like described in the above-mentioned embodiments are examples, and the present invention is not limited to these values. In addition, in each of the above-mentioned embodiments, although the first conductivity type is set as n-type, and the second conductivity type is set as p-type, but in the present invention, the first conductivity type is set as p-type, and the second conductivity type is set as p-type. The same holds true for n-type. In addition, the present invention is not limited to MOSFETs, and may be applied to IGBTs (Insulated Gate Bipolar Transistors), bipolar transistors, FWDs (Free Wheeling Diodes), Schottky diodes, and the like.

Industrial availability

As described above, the semiconductor device and the manufacturing method of the semiconductor device according to the present invention are applied to a high-power semiconductor device provided with a voltage-resistant structure part in the peripheral part of the device surrounding the active part of the device, and are particularly applicable to a device using a drift layer as a parallel pn layer. High-voltage semiconductor devices such as MOSFETs, IGBTs, bipolar transistors, FWDs, or Schottky diodes.

Claims (18)

1. A semiconductor device, characterized in that: a surface element structure arranged on the side of the first main surface; a low-resistance layer disposed on the second main surface side; a first parallel pn layer, which is disposed between the surface element structure and the low-resistance layer, and the first regions of the first conductivity type and the first regions of the second conductivity type are arranged alternately; The second parallel pn layer is arranged to surround the first parallel pn layer, and the second first conductivity type region and the second second conductivity type region are arranged alternately so as to be smaller than the first first conductivity type region. a narrow pitch of repeating pitches of regions of one conductivity type and said first region of second conductivity type; and an intermediate region disposed between the first parallel pn layer and the second parallel pn layer and in contact with the first parallel pn layer and the second parallel pn layer, wherein, In the middle area, with: a third second conductivity type region which is in contact with the first second conductivity type region of the first juxtaposed pn layer and has an average impurity concentration lower than that of the first second conductivity type region, A fourth region of the second conductivity type, which is in contact with the second region of the second conductivity type of the second juxtaposed pn layer, and has a lower average impurity concentration than the second region of the second conductivity type. 2. The semiconductor device according to claim 1, wherein: In the middle area, with: a third region of the first conductivity type, which is in contact with the first region of the first conductivity type of the first juxtaposed pn layer, and has an average impurity concentration lower than that of the first region of the first conductivity type; A fourth region of the first conductivity type is in contact with the second region of the first conductivity type of the second juxtaposed pn layer, and has an average impurity concentration lower than that of the second region of the first conductivity type. 3. The semiconductor device according to claim 2, wherein: Configured in the middle area are: The third parallel pn layer is formed by alternately disposing the third regions of the first conductivity type and the regions of the third second conductivity type. 4. The semiconductor device according to claim 2 or 3, wherein Configured in the middle area are: The fourth parallel pn layer is formed by alternately disposing the fourth regions of the first conductivity type and the fourth regions of the second conductivity type. 5. The semiconductor device according to any one of claims 1 to 3, wherein: The first region of the first conductivity type and the first region of the second conductivity type are arranged in a striped planar layout, The second region of the first conductivity type and the second region of the second conductivity type are configured to face the same stripe shape as the first region of the first conductivity type and the first region of the second conductivity type the floor plan, The third region of the second conductivity type and the fourth region of the second conductivity type are configured to face the same stripe shape as the first region of the second conductivity type and the second region of the second conductivity type flat layout. 6. The semiconductor device according to claim 1, wherein: The third region of the second conductivity type and the fourth region of the second conductivity type opposite to each other are adjacent to each other across a drift region. 7. The semiconductor device according to claim 1 , wherein: The first region of the first conductivity type and the first region of the second conductivity type are arranged in a striped planar layout, The second region of the first conductivity type and the second region of the second conductivity type are configured to face a stripe perpendicular to the first region of the first conductivity type and the first region of the second conductivity type shape layout, The third region of the second conductivity type is configured to face the same stripe-shaped planar layout as the first region of the second conductivity type, The fourth region of the second conductivity type is arranged in a stripe-like planar layout facing the same direction as the second region of the second conductivity type. 8. The semiconductor device according to any one of claims 1 to 3, further comprising: An element active part, which is configured with the surface element structure and the first parallel pn layer, and has a current flow in the on state; an element peripheral portion configured with the second parallel pn layer and surrounding the element active portion; a terminal region disposed between the first main surface and the low-resistance layer on the opposite side of the element peripheral portion to the element active portion side; a fifth first conductivity type region, which is disposed between the second juxtaposed pn layer and the terminal region, and has an average impurity concentration lower than that of the second first conductivity type region; and A conductive layer electrically connected to the termination area. 9. A method of manufacturing a semiconductor device, comprising the following steps: Forming a process, repeating the first process and the second process, wherein, The first step is to deposit a first conductivity type semiconductor layer, In the second step, the first conductive type impurity implanted regions and the first second conductive type impurity implanted regions are alternately arranged on the surface layer of the first conductive type semiconductor layer, and the A position separated by a predetermined width on the outer side than the first impurity-implanted region of the first conductivity type and the first impurity-implanted region of the second conductivity type, so as to be wider than the first impurity-implanted region of the first conductivity type and forming a second impurity implantation region of the first conductivity type and a second impurity implantation region of the second conductivity type in such a manner that the repeating pitch of the first impurity implantation region of the second conductivity type is alternately arranged; and The heat treatment process, through heat treatment, diffuse the first impurity implanted region of the first conductivity type and the first impurity implanted region of the second conductivity type to form the first region of the first conductivity type and the first region of the second conductivity type type regions are arranged alternately in the first parallel pn layer, and the second first conductivity type impurity implantation region and the second second conductivity type impurity implantation region are diffused to form a second first conductivity type impurity implantation region type regions and second second conductivity type regions alternately arranged in the second parallel pn layer, In the heat treatment step, between the first parallel pn layer and the second parallel pn layer, the first impurity implantation region of the first conductivity type, the first impurity of the second conductivity type The implanted region, the second first conductive type impurity implanted region and the second second conductive type impurity implanted region are diffused to form a third region having an average impurity concentration lower than that of the first first conductive type region. a region of the first conductivity type, a third region of the second conductivity type having an average impurity concentration lower than that of the first region of the second conductivity type, a fourth region of the second conductivity type having an average impurity concentration lower than that of the second region of the first conductivity type a region of the first conductivity type and a middle region of a fourth region of the second conductivity type whose average impurity concentration is lower than that of the second region of the second conductivity type. 10. The method of manufacturing a semiconductor device according to claim 9, wherein: In the heat treatment step, a third parallel pn layer in which the third first conductivity type region and the third second conductivity type region are alternately arranged and the fourth second conductivity type region are formed. The first conductivity type region and the fourth second conductivity type region are alternately arranged to form the middle region of the fourth parallel pn layer. 11. The method of manufacturing a semiconductor device according to claim 9 or 10, wherein: In the second step, the first impurity-implanted region of the first conductivity type and the first impurity-implanted region of the second conductivity type are formed into a stripe-shaped planar layout, and the second The impurity implantation region of the first conductivity type and the second impurity implantation region of the second conductivity type are formed to face the same direction as the first impurity implantation region of the first conductivity type and the impurity implantation region of the first second conductivity type. Striped flat layout. 12. The method of manufacturing a semiconductor device according to claim 9 or 10, wherein: In the second step, the first impurity-implanted region of the first conductivity type and the first impurity-implanted region of the second conductivity type are formed into a stripe-shaped planar layout, and the second The impurity implantation region of a conductivity type and the second impurity implantation region of the second conductivity type are formed to be perpendicular to the first impurity implantation region of the first conductivity type and the first impurity implantation region of the second conductivity type striped flat layout. 13. A method of manufacturing a semiconductor device, comprising the following steps: Forming a process, repeating the first process and the second process, wherein, The first step is to deposit a first conductivity type semiconductor layer, In the second step, on the surface layer of the first conductivity type semiconductor layer, the first second conductivity type impurity implanted regions are alternately arranged, and the impurity implantation regions of the first second conductivity type a position where the implanted regions are more outside separated by a predetermined width, a second second conductive type impurity implanted region is formed at a pitch narrower than that of the first second conductive type impurity implanted region; and The heat treatment step is to diffuse the first impurity-implanted region of the second conductivity type through heat treatment to form a first parallel pn layer in which the first second conductivity type region and the first conductivity type semiconductor layer are alternately arranged , and diffuse the second impurity-implanted region of the second conductivity type to form a second parallel pn layer in which the second region of the second conductivity type and the semiconductor layer of the first conductivity type are alternately arranged, In the heat treatment step, between the first parallel pn layer and the second parallel pn layer, the first impurity of the second conductivity type and the second impurity of the second conductivity type The implanted region is diffused to form a third second conductivity type region having an average impurity concentration lower than that of the first second conductivity type region, and a fourth second conductivity type region having an average impurity concentration lower than that of the second second conductivity type region. The middle region of the second conductivity type region. 14. The method of manufacturing a semiconductor device according to claim 13, wherein: In the second step, the first impurity-implanted region of the second conductivity type is formed in a stripe-like planar layout, and the second impurity-implanted region of the second conductivity type is formed to face A second conductivity type impurity implantation region has the same stripe-like planar layout. 15. The method of manufacturing a semiconductor device according to claim 13, wherein: In the second step, the first impurity-implanted region of the second conductivity type is formed in a stripe-like planar layout, and the second impurity-implanted region of the second conductivity type is formed to face A second conductive type impurity implanted region is orthogonal to the striped planar layout. 16. The method of manufacturing a semiconductor device according to any one of claims 9 and 13, wherein: The predetermined width is not more than 1/2 of the thickness of the first conductive type semiconductor layer deposited in one first step. 17. The method of manufacturing a semiconductor device according to any one of claims 9 and 13, wherein: forming the first parallel pn layer and the second parallel pn layer on a low resistance layer having a resistance lower than that of the first conductivity type semiconductor layer, After the heat treatment step, a surface element structure is formed on a side of the first parallel pn layer opposite to the side of the low resistance layer. 18. The method of manufacturing a semiconductor device according to any one of claims 9 and 13, wherein: forming an active part of the element through which current flows when the first parallel pn layer is in the on state, The second parallel pn layer is formed on the peripheral portion of the element surrounding the active portion of the element.