TW201539816A - Resistance random access memory device and method for forming resistance random access memory stack - Google Patents

Abstract

The present disclosure relates to a resistance random access memory (RRAM) device architecture where a Ti metal capping layer is deposited before the deposition of the HK HfO resistance switching layer. Here, the capping layer is below the HK HfO layer, and hence no damage will occur during the top RRAM electrode etching. The outer sidewalls of the capping layer are substantially aligned with the sidewalls of the HfO layer and hence any damage that may occur during future etching steps will happen at the outer side walls of the capping layer that are positioned away from the oxygen vacancy filament (conductive filament) in the HK HfO layer. Thus the architecture in the present disclosure, improves data retention.

Description

Improving the memory capacity of resistive memory by depositing titanium cap before yttrium oxide [Interactive Reference]

The disclosure claims US Provisional Patent Application No. 61/924,504 (Application Date: 2014/01/07; Title: "Improvement of RRAM retention by depositing Ti capping layer" Prior to HK HfO)"), the contents of which are incorporated herein by reference.

Non-volatile memory is commonly used in a variety of commercial or military electronic components and equipment. Resistance random access memory (RRAM) is a promising candidate for next generation non-volatile memory because of its simple structure and process compatible with CMOS logic. Each of the resistive random access memory cells includes a metal oxide material sandwiched between the upper electrode and the lower electrode. The metal oxide material has a variable resistance whose resistance level corresponds to a state of data stored in the resistive random access memory.

According to the following detailed description and complete with the drawings dew. It should be noted that the illustrations are not necessarily drawn to scale in accordance with the general operation of the industry. In fact, it is possible to arbitrarily enlarge or reduce the size of the component for a clear explanation.

1 shows a cross-sectional view of a resistive random access memory stack in accordance with some embodiments of the present disclosure.

2 is a flow chart showing a method of fabricating a resistive random access memory stack in accordance with some embodiments of the present disclosure, wherein the resistive random access memory includes a titanium cap layer formed on a high dielectric constant tantalum oxide dielectric layer prior to.

3 is a flow chart showing a step-by-step method of forming a resistive random access memory stack in accordance with some embodiments of the present disclosure.

4-7, 8A-8B, 9-10 are cross-sectional views showing the formation of a resistive random access memory stack in accordance with some embodiments of the present disclosure, wherein the resistive random access memory includes a titanium cap layer formed at a high The dielectric constant is oxidized under the dielectric layer.

11 is a cross-sectional view showing a resistive random access memory device according to some embodiments of the present disclosure, wherein the resistive random access memory device has a resistive random access memory stack and resistive random access memory The bulk stack has a titanium cap layer underlying the high dielectric constant tantalum oxide dielectric layer.

The various features of the present disclosure are disclosed in the following, and various embodiments of the present invention are described. The embodiments are for illustrative purposes only and are not intended to limit the scope of the disclosure. For example, it is mentioned in the specification that the first feature is formed on the second feature, including an embodiment in which the first feature is in direct contact with the second feature, and additionally includes another feature between the first feature and the second feature. Characteristic embodiment, also That is, the first feature is not in direct contact with the second feature. In addition, repeated reference numerals or signs may be used in the various embodiments, which are merely for the purpose of simplicity and clarity of the disclosure, and do not represent a particular relationship between the various embodiments and/or structures discussed.

A conventional resistive random access memory (RRAM) includes an upper electrode (anode) and a lower electrode (cathode) and has a variable resistance dielectric layer disposed between the electrodes . The upper electrode is composed of a bipolar switching layer and a metal cap layer, and both share an upper electrode width, which is obtained by measuring the outer sidewall of the upper electrode. The variable resistance dielectric layer and the lower electrode have a lower electrode width, and the lower electrode width is smaller than the upper electrode width. When the read/write operation of the resistive random access memory is performed, a set voltage is applied across the upper and lower electrodes to change the variable resistance dielectric layer from the first resistance to the second resistance. Similarly, a reset voltage is applied across the electrodes to return the variable resistance dielectric layer from the second resistor to the first resistor. Therefore, in this case, the first resistance and the second resistance state respectively correspond to the state of logic "1" and logic "0" (or vice versa), and the set voltage and the reset voltage can be used to store the digital data in the resistor. In random access memory.

It is believed that the mechanism by which the resistance switching occurs is due to the selective conductive filaments arranged in the variable resistance dielectric layer. These selective conductive filaments are initially formed at the end of the resistive random access memory process when applied to form a voltage across the anode and cathode. This formation voltage creates a high electric field that knocks oxygen atoms out of the crystal lattice of the varistor dielectric layer, thus forming localized oxygen vacancies. These local oxygen depletion tends to form "filaments" which are relatively long lasting and extend between the upper and lower electrodes. reading During the writing operation, the resistance of the filament can be changed by filling oxygen atoms into the filament or stripping oxygen atoms from the filament. For example, when a first voltage (eg, a set voltage) is applied, oxygen atoms are depleted from the metal cap layer and injected into the filament to provide a first resistance; when a second voltage is applied (eg, reset voltage) Oxygen atoms are stripped from the filaments and injected into the metal cap layer to provide a second resistance. Regardless of the true mechanism, it is believed that the movement of oxygen atoms between the metal cap layer and the filament dominates the "set" resistance and "reset" resistance of the resistive random access memory, with the metal cap layer acting as Oxygen storage tank.

Unfortunately, in conventional resistive random access memory fabrication processes, the use of etching to form a relatively narrow upper electrode structure at least partially oxidizes the outer sidewalls of the metal cap layer. During subsequent heat treatment steps (e.g., baking or annealing), oxygen may undesirably diffuse from the partially oxidized metal cap layer described above and combine with oxygen depletion in the filaments. For resistive random access memory, this phenomenon effectively "pins" some filaments into one of two resistance states, so that these resistive random access memory cells (RRAM) Cell) may create issues of data retention.

Accordingly, the present disclosure provides a novel structure of a resistive random access memory cell (RRAM cell) in which an anode structure (including a metal cap layer) is disposed under the variable resistance dielectric layer and becomes one of relatively wide electrodes. Part. As a result, the metal cap layer will be formed under the variable resistance dielectric layer (ie, the anode is now formed under the variable resistance dielectric layer), and when the upper electrode is etched, the metal cap layer is thus not Will be oxidized. Furthermore, since the metal cap layer is now part of a relatively wide lower electrode, sidewall oxidation of the metal cap layer occurs at a safe distance from the filament region in the varistor dielectric layer. Therefore, it is good The effective change of the resistance between the "set" and "reset" resistors is defined to make the high resistance state and the low resistance state easier to distinguish.

1 shows a cross-sectional view of a resistive random access memory stack (RRAM stack) 100 in accordance with some embodiments of the present disclosure. The resistive random access memory stack 100 includes an upper (cathode) electrode 114 and a lower (anode) electrode 105 with a variable resistance dielectric layer 110 interposed therebetween. The variable resistance dielectric layer 110 includes a filament region 107 having filaments formed therein. The variable resistance dielectric layer 110 includes a high dielectric constant hafnium oxide.

The resistive random access memory stack 100 is located above the semiconductor operating component 103, which includes a conductive metal region 101 and an extremely low-k dielectric region 102 on either side. Directly above the semiconductor working component 103 is a dielectric cap layer 104 having an open region over the metal region 101 with the sidewalls of the dielectric cap layer 104 terminating over the metal region 101. Above the dielectric cap layer 104 is an anode 106 that passes through an opening in the dielectric cap layer 104 to abut the conductive metal region 101. In some embodiments, the anode 104 includes a transition metal nitride layer. Above the anode 106, a metal cap layer 108 is provided. In some embodiments, the metal cap layer 108 comprises titanium (Ti), tantalum (Ta) or hafnium (Hf) and acts as an oxygen storage tank. The variable resistance dielectric layer 110 abuts the entire upper surface of the metal cap layer 108. The variable resistance dielectric layer 110, the metal cap layer 108, and the anode 106 have vertical sidewalls that are aligned with each other. The cathode 114 is located over the variable resistance dielectric layer 110 and is located in a predetermined central region of the variable resistance dielectric layer. The cathode 114 has a first width w1 obtained by measuring its outer sidewall, and the variable resistance dielectric layer 110 and the metal cap layer 108 have a second width w2 obtained by measuring the opposite outer sidewalls thereof. In some embodiments, the second width w2 is greater than the first a width. In an embodiment, the cathode 114 includes a first transition metal nitride layer 112 and a second transition metal nitride layer 113 over the top of the first transition metal nitride layer 112. A pair of sidewall spacers 118a and 118b are disposed on both sides of the cathode 114. The sidewall spacers 118a and 118b are also located at both end positions of the variable resistance dielectric layer 110. The cathode 114 has an outer sidewall that directly abuts the inner sidewall of the corresponding sidewall spacers 118a and 118b. Anti-reflective layer 116 and cathode 114 have vertical sidewalls that are aligned with one another.

As will be discussed in more detail below, in some embodiments, unlike conventional methods, the metal cap layer 108 can include titanium deposited prior to the variable resistance dielectric layer 110. In addition, anode 106 and cathode 114 are flipped relative to conventional methods, and metal cap layer 108 now becomes part of lower electrode 105. When the varistor dielectric layer 110 and the outer sidewalls of the metal cap layer 108 are substantially aligned with each other, this structure causes the outer sidewall of the easily oxidized metal cap layer 108 to be located away from the filament region of the varistor dielectric layer 110. 107. Therefore, oxidation that may occur on the outer sidewalls of the metal cap layer 108 will not damage the filaments of the variable resistance dielectric layer 110, and thus improve data retention.

2 is a flow chart 200 of a method of fabricating a resistive random access memory stack in accordance with some embodiments of the present disclosure, wherein the resistive random access memory includes a titanium cap layer formed on a high dielectric constant tantalum oxide dielectric. Before the layer. The method 200 is disclosed and described below as a series of acts or events, it being understood that the order of such acts or events should not be construed as limiting. The actions may occur in different orders and/or with other acts or events in addition to those shown and/or described herein. In addition, not all illustrated acts may be required to be implemented in one or more aspects or embodiments described herein. again One or more of the acts described herein can be implemented in one or more separate acts and/or stages.

At step 202, a semiconductor base surface is provided, the semiconductor base surface including a metal interconnect structure disposed in the very low dielectric constant dielectric layer. In some embodiments, the metal interconnect structure comprises copper.

At step 204, a dielectric protective layer having an open region is formed over the surface of the semiconductor base. In some embodiments, the dielectric protective layer comprises tantalum carbide.

At step 206, an anode layer is formed over the dielectric cap layer. In some embodiments, the anode comprises tantalum nitride (TaN).

At step 208, a metal cap layer is formed over the anode. In some embodiments, the metal cap layer comprises titanium (Ti).

At step 210, a variable resistance dielectric layer is formed over the metal cap layer. In some embodiments, the variable resistance dielectric layer comprises hafnium oxide (HfO).

At step 212, a cathode layer is formed over the variable resistance dielectric layer. In some embodiments, the cathode includes a first transition metal nitride layer having a second transition metal nitride layer disposed thereon. In some embodiments, the transition metal nitride layer comprises tantalum nitride (TaN) and titanium nitride (TiN). For example, the first transition metal nitride layer may be tantalum nitride (TaN), and the second transition metal nitride layer may be titanium nitride (TiN).

3 is a flow chart showing a step-by-step method 300 of forming a resistive random access memory stack in accordance with some embodiments of the present disclosure. The method 300 is disclosed and described below as a series of acts or events, it being understood that the order of such acts or events should not be construed as limiting. The actions may occur in different orders and/or accompanied by the display and/or description herein. Other actions or events. In addition, not all illustrated acts may be required to be implemented in one or more aspects or embodiments described herein. Furthermore, one or more of the acts described herein can be implemented in one or more separate acts and/or stages.

At step 302, a horizontal stack of base material is formed over a semiconductor base region having a dielectric cap layer thereon, the horizontal stack of base material comprising an anode, a metal cap layer, a variable resistance dielectric layer, and a cathode.

At step 304, a mask is formed over the cathode layer. The mask covers portions of the cathode layer and exposes other portions of the cathode.

At step 306, a first etch is performed to remove the exposed portions of the cathode layer and form a cathode structure. In some embodiments, the first etch includes dry etch, and the dry etch includes a chlorine-based etchant, such as chlorine/BCl ₂ (Cl ₂ /BCl ₂ ) or a fluorine-based etchant, such as fluoromethane. /Trifluoromethane / CH ₂ / sulfur hexafluoride (CF ₄ /CHF ₃ /CH ₂ /SF ₆ ).

At step 308, sidewall spacers are formed around the outer sidewalls of the cathode. The sidewall spacers and cathode structures cover portions of the varistor dielectric layer and expose other portions of the varistor dielectric layer. In some embodiments, the cathode comprises tantalum nitride (TaN) over titanium nitride (TiN) and the sidewall spacer material comprises tantalum nitride (SiN).

At step 310, a second etch is performed to remove the exposed portions of the variable resistance dielectric layer. The sidewall spacers are placed in position with the cathode structure and a second etch is performed to remove exposed portions of the varistor dielectric layer and to remove the metal cap layer and anode underneath. The second etch will stop at the dielectric protection layer. In some embodiments, the anode comprises tantalum nitride (TaN). In some embodiments, the first etch includes dry etch, and the dry etch includes a chlorine-based etchant, such as chlorine/BCl ₂ (Cl ₂ /BCl ₂ ) or a fluorine-based etchant, such as fluoromethane. /Trifluoromethane / CH ₂ / sulfur hexafluoride (CF ₄ /CHF ₃ /CH ₂ /SF ₆ ).

At step 312, a metal contact is formed over the cathode structure, wherein when set, the cathode structure is further connected to the source line, and when resetting, the cathode structure is further connected to Bit line.

4-10 are cross-sectional views showing the formation of a resistive random access memory stack in accordance with some embodiments of the present disclosure, wherein the resistive random access memory includes a titanium cap layer formed on a high dielectric constant tantalum oxide dielectric layer under.

4 shows a cross-sectional image view 400 of a semiconductor body having a dielectric cap layer 404 overlying semiconductor operating component 403. The semiconductor working component 403 includes a metal interconnect structure 401 disposed in the very low dielectric constant dielectric region 402. In some embodiments, the metal interconnect structure 401 comprises copper, and the very low dielectric constant dielectric region 402 comprises porous silicon dioxide, fluorinated silica glass, polyimine. (polyimides), polynorbornenes, benzocyclobutene, or polytetrafluoroethylene (PTFE). The dielectric cap layer 404 has an opening toward the center that is formed by using a mask lithography step. This opening exposes a portion of the metal interconnect structure 401. In some embodiments, the dielectric cap layer 404 includes tantalum carbide.

FIG. 5 shows a cross-sectional image view 500 of the semiconductor body at a subsequent stage of processing, wherein the anode 502 is disposed on the structure of the image map 400. Through the opening of the dielectric cap layer 404, the anode 502 contacts the metal interconnect structure 401 so that the resistive random access memory can be subsequently coupled to other portions of the device.

Figure 6 shows a cross-sectional image view 600 of the semiconductor body at a subsequent stage of processing with a horizontal stack of base materials. The stack of materials includes an anode 502, a metal cap layer 602, a variable resistance dielectric layer 604, a cathode 608, and an anti-reflective layer 610 formed over the semiconductor base region 403. In some embodiments, the anode 502 includes tantalum nitride, the metal cap layer 602 includes titanium, the variable resistance dielectric layer 604 includes tantalum oxide, and the cathode 608 includes a first transition metal nitride layer 606 and a second transition metal nitride layer. 607 is located thereon, wherein the first transition metal nitride layer 606 includes titanium nitride, the second transition metal nitride layer 607 includes tantalum nitride, and the anti-reflection layer 610 includes hafnium oxynitride.

Figure 7 shows a cross-sectional image view 700 of the semiconductor body at a subsequent stage of processing, wherein a cathode mask (not shown) is formed over the horizontal stack 600 and a first etch is performed. After the first etch, the cathode structure including the cathode 608 and the anti-reflective layer 610 is formed at the center of the variable resistance dielectric layer 604, leaving the exposed portions of the variable resistance dielectric layer 604 on both sides.

Figure 8a shows a cross-sectional image view 800a of the semiconductor body at a subsequent stage of processing, after spacers 802a and 802b are formed on both sides of the cathode structure. In some embodiments, the gap material comprises tantalum nitride. In general, spacers 802a and 802b are formed by removing the cathode mask and then depositing a compliant layer of gap material over the working component. The deposited layer is then etched to remove the gap uniform material of vertical uniform depth from above the working component, thus leaving spacers 802a and 802b in place.

Fig. 8b shows a cross-sectional image view 800b after the second etching of the semiconductor body in Fig. 8a. The spacers 802a and 802b are placed in position with the cathode structure, and a second etch is performed to remove the variable resistance dielectric layer 604. The exposed portion is removed with a portion of the anode 502 and cap layer 602 underneath to form an anode structure. The second etch stops at the variable resistance dielectric layer 404 such that the anode structure covers portions of the varistor dielectric layer 404 and exposes other portions of the varistor dielectric layer 404. It is observed that the oxidized region 804 is located around the outer sidewall of the metal cap layer 602.

Figure 9 shows a cross-sectional image 900 of the deposited dielectric cap layer 902 and insulating layer 904 over the entire resistive random access memory. In some embodiments, the insulating layer 904 includes bismuth oxynitride (SiON). These materials isolate and protect each resistive random access memory cell from current leakage and charge diffusion. Furthermore, an interlayer dielectric layer 906 is formed and surrounds the insulating layer 904. An etched region 908 extending to the cathode is formed for a subsequent top electrode contact via (TEVA).

Figure 10 shows a cross-sectional image view 1000 after the formation of the upper electrode contact plug (TEVA) 908 and the upper electrode contact 1002. In some embodiments, the cathode layer has a thickness of about 220 angstroms (Å), the metal cap layer has a thickness of about 100 angstroms (Å), and the variable resistance dielectric layer has a thickness of about 50 angstroms (Å). The thickness of the titanium layer is about 100 angstroms (Å) and the thickness of the anodized tantalum nitride layer is about 250 angstroms (Å).

11 is a cross-sectional view 1100 of a resistive random access memory device in accordance with some embodiments of the present disclosure. The RRAM device has a resistive random access memory stack (RRAM stack). There is a titanium cap layer under the high dielectric constant yttrium oxide dielectric layer. A plurality of such resistive random access memory devices form a memory array for storing data. Figure 11 includes a conventional flat metal oxide semiconductor A field effect transistor (MOSFET) selects a transistor 1101 for suppressing sneak-path leakage (ie, avoiding currents intended for a particular memory from passing through adjacent memory cells). Provide sufficient drive current for memory unit operation. The select transistor 1101 includes a source region 1104 and a drain region 1106 located in the semiconductor body 1102, both of which are horizontally separated by the channel region 1105. Gate electrode 1108 is located on semiconductor body 1102 and above the location of channel region 1105. In some embodiments, the gate electrode 1108 includes a polysilicon, but may also be a metal. The gate electrode 1108 is separated from the source 1104 and the drain 1106 by a gate oxide layer or gate dielectric layer 1107, wherein the gate dielectric layer 1107 extends horizontally over the surface of the semiconductor body 1102. The drain 1106 is coupled to the data storage element or resistive random access memory stack 1120 by a first metal interconnect 1112a. The source 1104 is connected by a first metal contact 1112b. The gate electrode is connected to the word line 1114a, the source is connected to the bit line 1114b through the first metal contact 1112b, and the resistive random access memory stack 1120 is further connected to the upper metallization layer by the second metal contact 1112g. Source line 1114c in (upper metallization layer). The desired resistive random access memory can be selectively accessed using word lines and bit lines for read, write, and erase operations. There may be one or more metal contacts (including 1112c, 1112d, 1112e, 1112f) and metal contact vias between the drain 1106 and the second metal contact 1112g, and between the source 1104 and the first metal contact 1112b ( Including 1110a, 1110b, 1110c, 1110d, 1110e, 1110f, etc.), to help connect the resistive random access memory to external circuits. In some embodiments, the metal contact comprises copper (Cu).

The resistive random access memory stack 1120 includes a variable resistor dielectric The electric layer 1121 is interposed between the cathode 1122 and the anode 1123. A metal cap layer (not shown) is disposed between the variable resistance dielectric layer 1121 and the anode 1123. The upper electrode contact plug (TEVA) 1124 is connected to the cathode 1122 of the memory unit 1120 to the second metal contact 1112g, and the bottom electrode via (BEVA) 1125 is connected to the anode 1123 of the memory unit 1120 to the first metal. Interconnect line 1112a.

It is to be understood that the structures and their forming methods (such as the structures shown in the drawings and the above-described forming methods) used in the entire specification are not limited to the corresponding structures. The methods and structures should be considered independent of each other and both can exist separately. The methods and structures are not necessarily implemented in a particular manner in the drawings. Additionally, the layers herein may be formed by any suitable method, such as spin coating, sputtering, growth, and/or deposition.

In addition, equivalent substitutions and/or improvements may be made by those skilled in the art after reading and/or understanding the specification and drawings. The invention includes, but is not limited to, such substitutions and modifications. For example, although specific doping species are mentioned in the figures and content, those of ordinary skill in the art can replace them with other doping species.

In addition, the specific structures or embodiments disclosed in one or more embodiments may be combined with one or more other structures and/or embodiments in other embodiments as needed. In addition, the terms "including", "having", "including" and/or variations thereof are extended to include the meaning of the meaning, such as "including". In addition, an "instance" is merely an instance rather than a best instance. It is to be understood that the above-described structures, layers and/or elements are in a particular size and/or orientation of the other, and are merely used to simplify the description and facilitate understanding, and the actual size and/or orientation may differ from the above.

The present disclosure relates to a resistive random access memory device having a metal cap layer in which a metal cap layer is deposited prior to deposition of a variable resistance dielectric layer. The structure has a metal cap outer sidewall substantially aligned with the outer sidewall of the variable resistance dielectric layer, so that the metal cap can be avoided during the process of etching the cathode or the electrode layer on the variable resistance dielectric layer The sidewalls of the layer are damaged or partially oxidized. Therefore, regardless of any damage occurring on the sidewall of the metal cap layer that is susceptible to oxidation, these damages can be moved away from the filament region of the variable resistance dielectric layer, so data retention is not affected.

In some embodiments, the present disclosure relates to a resistive random access memory device including: a variable resistance dielectric layer having an upper surface and a lower surface; and a cathode disposed over the variable resistance dielectric layer adjacent to the upper surface a surface; a metal cap layer disposed under the variable resistance dielectric layer and adjacent to the lower surface; and the anode disposed under the metal cap layer.

In other embodiments, the present disclosure relates to a resistive random access memory stack of a resistive random access memory device, including: a lower electrode including tantalum nitride; a titanium metal cap layer arranged on a lower electrode; A dielectric constant yttria varistor dielectric layer is disposed over the titanium metal cap layer; and the upper electrode includes a tantalum nitride layer over the titanium nitride layer.

In still another embodiment, the present disclosure is directed to a method of forming a resistive random access memory stack, comprising: providing a semiconductor base surface including a metal interconnect structure disposed in a very low dielectric constant dielectric layer; Forming a dielectric protective layer having an open region over the surface of the semiconductor base, wherein sidewalls of the open region terminate above the metal interconnect structure; depositing a resistive random access memory upper electrode layer over the dielectric protective layer, Deposition resistive random access memory The upper electrode layer contacts the metal interconnect structure through the opening in the dielectric protective layer; the metal cap layer is deposited on the upper surface of the resistive random access memory; and the variable resistive dielectric layer is deposited on the metal cap layer And depositing a resistive random access memory lower electrode layer over the variable resistance dielectric layer.

The present disclosure has been disclosed in the above-described preferred embodiments, and is not intended to limit the disclosure. Any one of ordinary skill in the art can make any changes without departing from the spirit and scope of the disclosure. And the scope of protection of this disclosure is subject to the definition of the scope of the patent application.

Claims (20)

A resistive random access memory device comprising: a varistor dielectric layer having an upper surface and a lower surface; a cathode disposed over the varistor dielectric layer and adjacent to the upper surface; a metal cap layer disposed under the variable resistance dielectric layer and adjacent to the lower surface; and an anode disposed under the metal cap layer. The resistive random access memory device of claim 1, further comprising: a pair of sidewall spacers laterally arranged around the outer sidewall of the cathode, wherein the cathode has a first width, and the cathode The first width is obtained by measuring an outer sidewall of the cathode; wherein the variable resistance dielectric layer and the metal cap layer each have a second width, and the second width is measured by measuring the variable resistance dielectric And a respective sidewall of the metal cap layer, wherein the second width is greater than the first width. The resistive random access memory device of claim 2, wherein the sidewall spacer comprises tantalum nitride. The resistive random access memory device of claim 2, wherein the outer sidewall of the metal cap layer is away from a conductive filament region, wherein the conductive filament region is arranged under the cathode and located at the cathode Among the variable resistance dielectric layers. The resistive random access memory device of claim 2, further comprising: a plurality of oxidized regions adjacent to the outer sidewall of the metal cap layer. The resistive random access memory device of claim 2, wherein the cathode has a plurality of outer sidewalls, wherein the outer sidewalls directly adjoin the inner sidewall of the corresponding sidewall spacer, and no oxidized region is interposed The cathode and the sidewall spacer are disposed, and wherein the outer sidewalls of the cathode are disposed adjacent to a central region of the variable resistance dielectric layer. The resistive random access memory device of claim 2, wherein the outer sidewall of the variable resistance dielectric layer, the outer sidewall of the metal cap layer, and the outer sidewall of the anode are substantially aligned with each other. The resistive random access memory device of claim 1, wherein the cathode comprises a tantalum nitride layer on a titanium nitride layer; the anode comprises a tantalum nitride layer; resistive dielectric layer comprises hafnium oxide (HfO _x); and metal capping layer comprises tantalum or titanium, or hafnium. The resistive random access memory device of claim 8, wherein: the anode has a thickness of about 200 angstroms (Å); and the metal cap layer has a thickness of about 100 angstroms (Å); The thickness of the resistive dielectric layer is about 50 angstroms (Å); the thickness of the titanium nitride layer of the cathode is about 100 angstroms (Å); and the thickness of the tantalum nitride layer of the cathode is about 250 angstroms (Å) . The resistive random access memory device of claim 1, further comprising: a semiconductor base region, wherein the semiconductor base region comprises a gold The inner interconnect structure is disposed in a very low dielectric constant dielectric layer; a dielectric protective layer has an open region over the metal, wherein a sidewall of the open region of the dielectric protective layer terminates in the metal on. A resistive random access memory device comprising: a resistive random access memory stack comprising: a lower electrode comprising tantalum nitride; a titanium metal cap layer arranged over the lower electrode; a high dielectric constant A yttria varistor dielectric layer is disposed over the titanium metal cap layer; and an upper electrode including a tantalum nitride layer over the titanium nitride layer. The resistive random access memory device of claim 11, further comprising: a pair of sidewall spacers laterally arranged around the outer sidewall of the cathode, wherein the cathode has a first width, and the cathode The first width is obtained by measuring an outer sidewall of the cathode; wherein the high dielectric constant yttria varistor dielectric layer and the titanium metal cap layer each have a second width, and the second width is Measuring the high dielectric constant yttria varistor dielectric layer and the outer sidewall of each of the titanium metal cap layers, wherein the second width is greater than the first width. The resistive random access memory device of claim 11, further comprising: a semiconductor body having a source region and a drain region horizontally separated by a channel region; a gate structure coupled To the channel area; a first contact and a second contact are respectively disposed on the source region and the drain region; a first metal interconnect is disposed above the drain region, under the second contact and electrically Sexually coupled to the second contact; and the resistive random access memory stack is formed over the first metal interconnect. The resistive random access memory device of claim 11, wherein the gate structure comprises a polysilicon gate structure formed on a gate dielectric layer, wherein the gate dielectric layer is electrically The gate structure and the channel region are isolated. The resistive random access memory device of claim 14, wherein one or more metal contacts and one or more metal contact vias are present between the source region and the first contact, and Present between the drain region and the second contact. The resistive random access memory device of claim 15, wherein the source region is coupled to a one-bit line, the drain region is coupled to a source line, and the gate is coupled to a memory One word line of the body unit. A method of forming a resistive random access memory stack includes: providing a semiconductor base surface, wherein the semiconductor base surface comprises a metal interconnect structure disposed in a low dielectric constant dielectric layer; forming a dielectric protection The layer has an open region over the surface of the semiconductor base, wherein a sidewall of the open region terminates over the metal interconnect structure; an anode layer is deposited over the dielectric protective layer, and the anode layer is transparent to the dielectric layer The open region in the electrical protection layer contacts the metal interconnect structure; a metal cap layer is deposited over the anode layer; a varistor dielectric layer is deposited over the metal cap layer; and a cathode layer is deposited The variable resistance dielectric layer is over. The method for forming a resistive random access memory stack according to claim 17, further comprising: forming a mask over the cathode layer, wherein the mask covers portions of the cathode layer, and Exposing other regions of the cathode layer; performing a first etch to remove the exposed regions of the cathode layer, and thereby forming a cathode structure; and forming a plurality of sidewall spacers adjacent to the outer sidewalls of the cathode structure, The sidewall spacers and the cathode structure cover portions of the varistor dielectric layer to expose other portions of the varistor dielectric layer. The method for forming a resistive random access memory stack according to claim 18, further comprising: placing the sidewall spacers and the cathode structure in an appropriate position, and performing a second etching to remove Excluding the other portion of the varistor dielectric layer, and removing the portion of the anode and the metal cap layer under the other portion of the varistor dielectric layer, thereby forming an anode structure; Wherein the second etch stops at the dielectric protective layer. The method for forming a resistive random access memory stack according to claim 19, further comprising: forming a dielectric protective layer and an insulating layer covering the resistive random access memory stack; Forming a plurality of contact vias to couple the cathode; and forming a plurality of metal contacts to couple the resistive random access memory stack to a source line.