TW201539408A - Data transmission system and operating method of display - Google Patents

Abstract

A data transmission system of a display includes a transmission portion and a receiving portion. The transmission portion is configured to receive a first clock signal and provide a display data stream according to the first clock signal. The receiving portion includes an error detection module and a clock data recovery circuit. The error detection module is configured to determine whether the display data stream has an error according to the second clock signal. The error detection module is further configured to provide an error signal to the transmission portion according to the result of the determination, so as to make the transmission portion transmit a clock training data via the display data stream. The clock data recovery circuit is configured to update the second clock signal according to the clock training data.

Description

Data transmission system and operation method applied to display

This case is about an electronic system. In particular, it relates to a data transmission system and an operation method applied to a display.

With the rapid development of electronic technology, displays have been widely used in people's lives, such as mobile phones or notebook computers.

In general, the display can include a timing controller as well as a source driver. The timing controller can provide image data to the source driver through the data transmission interface, so that the source driver can provide an appropriate data voltage to the pixels in the display. The pixels update their display state (such as color and grayscale) based on the data voltage. This allows the display to display images.

In the conventional method, the timing controller transmits clock signals and image data to the source drivers through different transmission channels. However, in this way, the clock signal and the image data are easily misaligned with each other due to the transmission delay, so that the source driver cannot correctly receive the image data, which causes the display to be unstable.

Therefore, how to solve this problem is an important research method in the field. to.

One aspect of the present invention is to provide a data transmission system for use in a display. According to an embodiment of the invention, a data transmission system includes a transmitting end and a receiving end. The transmitting end is configured to generate a first clock signal, and is configured to provide a display data stream according to the first clock signal. The receiving end is configured to receive the display data stream. The receiving end includes a debugging module and a clock data recovery circuit. The debugging module is configured to determine, according to the second clock signal, whether the display data stream received by the receiving end has an error, and is configured to provide an error signal to the transmitting end according to the judgment result, so that the transmitting end transmits the clock calibration through the display data stream. Signal. The clock data recovery circuit is configured to update the second clock signal according to the clock calibration signal.

Another aspect of the present invention is to provide an operational method applied to a display. According to an embodiment of the present disclosure, a display includes a transmitting end and a receiving end. The operation method comprises: providing a display data stream according to the first clock signal through the transmitting end; receiving the display data stream through the receiving end, determining whether the data stream has an error according to the second clock signal, and providing an error signal according to the judgment result Transmitting, by the transmitting end, transmitting a clock calibration data by displaying the data stream according to the error signal; and updating the second clock signal according to the clock calibration data through the receiving end.

By applying the above embodiment, the clock calibration signal is transmitted in the display data stream to prevent the clock signal and the image data from being misaligned with each other due to the transmission delay, so as to improve the stability of the display. In addition, using the debug module pair The data stream is displayed for error detection, and the transmitting end can be notified when an error occurs in the displayed data stream, so that the transmitting end can perform corresponding error control accordingly. In this way, the stability of the display can be further improved.

10‧‧‧ display

20‧‧‧Sequence Controller

30‧‧‧Source Driver

40‧‧‧gate driver

100‧‧‧ data transmission system

104‧‧‧ pixel array

106‧‧‧ pixels

110‧‧‧Transport

111‧‧‧ phase-locked loop

112‧‧‧Encoder

113‧‧‧ Processor

114‧‧‧ converter

115‧‧‧transmitter

120‧‧‧ receiving end

121‧‧‧ Receiver

122‧‧‧clock data recovery circuit

123‧‧‧ converter

124‧‧‧Detection Module

125‧‧‧Decoder

G(1)-G(N)‧‧‧ scan signal

D(1)-D(M)‧‧‧Information Signal

DS-S‧‧‧Show data stream

DS-P‧‧‧Show data stream

LK‧‧‧ error signal

CLK1‧‧‧ first clock signal

CLK2‧‧‧ second clock signal

CONF‧‧‧Setting Information

DT‧‧·Image data

DT-E‧‧‧ encoded image data

FM‧‧‧ frame data

L(1)-L(N)‧‧‧Information frame

CN‧‧‧Information frame

VB‧‧‧Information frame

H-BK‧‧‧ horizontal obscuration code

V-BK‧‧‧Vertical blanking code

BAC‧‧‧bit sync code

CTRL‧‧‧ control code

EOL‧‧‧End Code

126‧‧‧Control Module

TAJ‧‧‧ clock calibration signal

S1-S13‧‧‧ steps

T0-t11‧‧‧ time point

The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; FIG. 3A is a schematic diagram of a transmitting end according to an embodiment of the present disclosure; FIG. 3B is a schematic diagram of a receiving end according to an embodiment of the present disclosure; 4 is a schematic diagram of a display data flow according to an embodiment of the present invention; FIG. 5 is a flowchart of an operation method according to an embodiment of the present invention; and FIG. 6 is a diagram of an operation example according to the present disclosure. A schematic diagram showing the flow of data.

The spirit of the present disclosure will be clearly described in the following drawings and detailed description, and those of ordinary skill in the art will understand the disclosure. The preferred embodiment of the present invention may be modified and modified by the teachings of the present disclosure without departing from the spirit and scope of the disclosure.

About the "first", "second", ..., etc. used in this article, and The meaning of non-specific reference order or order is not intended to limit the present invention, but merely distinguishes between elements or operations described in the same technical terms.

As used herein, "electrical connection" may mean two or more The components are directly in physical or electrical contact with each other, or indirectly in physical or electrical contact with each other, and "electrical connection" may also mean that two or more component components operate or interact with each other.

About "including", "including", "having", "Contains" and the like are all open words, meaning they are included but not limited.

"and/or" as used herein, includes the things described Any or all combinations.

The terms "roughly", "about", etc. used in this article are Used to modify the number or error of any slight change, but such slight changes or errors do not change its nature. In general, the slight variations or errors in such terms are 20%, in some preferred embodiments 10%, and in some preferred embodiments 5%.

For the terms used in this article, unless otherwise specified In addition, there is usually a general meaning in each of the terms used in the field, the content disclosed herein, and the special content. Certain terms used to describe the disclosure are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in the description of the disclosure.

One aspect of the present invention is to provide a data transmission system. In In the following embodiment, an intra-panel interface of a display panel will be described as an example. However, the present invention is not limited thereto.

FIG. 1 is a diagram of a display 10 according to an embodiment of the present disclosure. intention. Display 10 can include timing controller 20, source driver 30, gate driver 40, and pixel array 104. The timing controller 20 is electrically connected to the source driver 30 and the gate driver 40, respectively. The source driver 30 and the gate driver 40 are electrically connected to the pixel array. The pixel array 104 can include a plurality of pixels 106 arranged in a matrix. The timing controller 20 can provide a control signal to the gate driver 40 to cause the gate driver 40 to sequentially provide a plurality of scan signals G(1), . . . , G(N) to the pixels 106 in the pixel array 104. To open the pixel 106 column by column/row by line, where N is a natural number. In addition, the timing controller 20 can provide display data to the source driver 30 to enable the source driver 30 to provide the data signals D(1), . . . , D(M) to the turned-on pixels 106 for enabling The pixels 106 update their display state (eg, color and grayscale), where M is a natural number. In this way, the image can be displayed on the display 10.

In some approaches, the timing controller 20 provides separate clock signals. Number and image data to source driver 30. However, in this way, the clock signal and the image data are easily misaligned with each other due to the transmission delay, so that the source driver 30 cannot correctly receive the image data, resulting in instability of the display 10. Therefore, in an embodiment of the present invention, a new data transmission system 100 can be provided between the timing controller 20 and the source driver 30 to improve the stability of the display 10.

Figure 2 is a data transmission system according to an embodiment of the present invention Schematic diagram of 100. In this embodiment, the data transmission system 100 includes a transmitting end 110 and a plurality of receiving ends 120. The transmitting end 110 is located in the timing controller 20, and the receiving end 120 is respectively located in different source drivers 30, and electrically connected respectively. The transmitting end 110. In some embodiments, the source drivers 30 are configured to output data signals to different columns of pixels 106, respectively. In addition, it is noted that in the present embodiment, the six source drivers 30 and the receiving end 120 are taken as an example. However, the number of the source driver 30 and the receiving end 120 is not limited thereto. In various embodiments, the number of source drivers 30 and receivers 120 can vary depending on actual needs.

In this embodiment, the timing controller 20 is a data transmission system. The system 100 and the source driver 30 communicate with each other. For example, the timing controller 20 can transmit the display data stream DS-S to the source driver 30 through the data transmission system 100. On the other hand, when the source driver 30 finds an error (for example, finding its own error or displaying an error of the data stream DS-S), the source driver 30 can transmit the error signal LK to the timing controller 20 through the data transmission system 100. To indicate that the source driver 30 itself is in an error state, so that the timing controller 20 can perform relevant control for eliminating errors.

In this embodiment, the transmission channel for transmitting the error signal LK The track can be a single-line transmission channel. That is, each source driver 30 provides an error signal LK to the timing controller 20 through the same transmission channel. When any one of the source drivers 30 is in an error state, the source driver 30 provides an error signal LK (for example, a signal of a low voltage level) to the transmission channel to cause the timing controller 20 to perform an error. Related controls. By doing so, the area occupied by the transmission channel can be reduced.

It should be noted that in various embodiments, the source driver 30 can also The error signal LK is transmitted by using multiple transmission channels, and the present invention is not limited to the above embodiment.

FIG. 3A is a transmission end 110 according to an embodiment of the present disclosure. Schematic diagram. In the present embodiment, the transmitting end 110 includes a phase locked loop 111, an encoder 112, a processor 113, a converter 114, and a transmitter 115. The phase locked loop 111 is electrically connected to the encoder 112, the processor 113, and the converter 114. The encoder 112 is electrically connected to the processor 113. The processor 113 is electrically connected to the converter 114. The converter 114 is electrically connected to the transmitter 115. In the present embodiment, the phase-locked loop 111, the encoder 112, the processor 113, the converter 114, and the transmitter 115 can all be implemented by a specific circuit.

Those skilled in the art can clearly understand that the above-mentioned phase-locked loop 111, edited The implementation of the decoder 112, the processor 113, the converter 114, and the transmitter 115 is not limited to the above embodiments, and the connection relationship is not limited to the above embodiment, and is sufficient for the transmitting end 110 to implement the following. The connection and implementation of the technical content can be applied to the present invention.

In this embodiment, the phase locked loop 111 is configured to receive and generate the first The clock signal CLK1 is coupled to the encoder 112, the processor 113, and the converter 114 to cause the encoder 112, the processor 113, and the converter 114 to perform respective operations based on the first clock signal CLK1.

In this embodiment, the encoder 112 is configured to receive image data. DT, encoding the image data DT, and providing the encoded image data DT-E to the processor 113. In an embodiment, the encoder 112 can be an 8-bit to 9-bit encoder (8b/9b encoder) for using an 8-bit image. The material DT is encoded as a 9-bit encoded image data DT-E. In reality, however, the type of encoder 112 can vary depending on actual needs. In different embodiments, the encoder 112 may also be a 4-bit to 5-bit encoder or a 12-bit to 14-bit encoder, etc., and the present invention is not limited to the above embodiment.

In this embodiment, the processor 113 is configured to receive the encoded image. The image data DT-E, the setting data CONF, and the error signal LK from the receiving end 120. The processor 113 is configured to arrange the encoded image data DT-E and the setting data CONF according to a data format predefined by the data transmission system 100 to output the display data stream DS-P to the converter 114. For the specific content of the display data stream DS-P, refer to FIG. 4, and the relevant content will be detailed in the following paragraphs.

In addition, the processor 113 receives the error from the receiving end 120. In the case of the error number LK, the processor 113 can transmit the clock calibration signal TAJ to each of the receiving terminals 120 so that each receiving terminal 120 updates its clock signal accordingly. Specific details regarding the clock calibration signal TAJ will be detailed in subsequent paragraphs.

In this embodiment, the converter 114 is configured to receive the display data stream. DS-P, and converts the parallel display data stream DS-P into a serial display data stream DS-S according to a transmission format pre-defined by the data transmission system 100, and provides a display data stream DS-S in a serial form to The transmitter 115 is configured to cause the transmitter 115 to perform a transfer operation. In addition, in the present embodiment, the converter 114 generates the display data stream DS-S in a serial form according to the first clock signal CLK1. That is, in the period of each first clock signal CLK1, the converter 114 generates a display data stream in a serial form. DS-S. By doing so, the first clock signal CLK1 can be embedded in the display data stream DS-S for transmission.

In this embodiment, the transmitter 115 is configured to receive the serial form The data stream DS-S is displayed, and the display data stream DS-S in the form of a series is transmitted to the receiving end 120 through the transmission channel. In one embodiment, the transmitter 115 transmits a 2-bit display data stream DS-S in the form of a serial to the receiving end 120, and the bandwidth of the transmission channel is also 2 bits.

With the above settings, the transmitting end 110 can be based on the first clock. The signal CLK1 provides a display data stream DS-P to the receiving end 120.

FIG. 3B is a receiving end 120 according to an embodiment of the present disclosure. Schematic diagram. The receiving end 120 includes a receiver 121, a clock data recovery circuit 122, a converter 123, a debug module 124, a decoder 125, and a control module 126. In this embodiment, the receiver 121 is electrically connected to the clock data recovery circuit 122, the converter 123, and the control module 126. The clock data recovery circuit 122 is electrically connected to the converter 123, the debug module 124, and the decoder 125. The converter 123 is electrically connected to the error detection module 124 and the control module 126. The debug module 124 is electrically connected to the decoder 125. The decoder 125 is electrically connected to the control module 126. In this embodiment, the receiver 121, the clock data recovery circuit 122, the converter 123, the debug module 124, the decoder 125, and the control module 126 can all be implemented by circuits.

Those skilled in the art can clearly understand that the above receiver 121, the time The implementation of the pulse data recovery circuit 122, the converter 123, the error detection module 124, the decoder 125, and the control module 126 is not limited to the above embodiments, and the connection relationship is not limited to the above embodiment. Where is enough The connection mode and implementation manner in which the receiving end 120 implements the following technical contents can be applied to the present invention.

In this embodiment, the receiver 121 is configured to receive from the transmitting end. The data stream DS-S of the serialized form of 110 is provided, and the display data stream DS-S in the form of a series is provided to the clock data recovery circuit 122, the converter 123, and the control module 126. In the present embodiment, the receiver 121 can be implemented with a comparator. The form of the receiver 121 and the form of the transmitter 115 correspond to each other.

In this embodiment, the clock data recovery circuit 122 is configured to receive The serial display data stream DS-S generates a second clock signal CLK2 according to the serial display data stream DS-S, and provides the second clock signal CLK2 to the converter 123, the debug module 124, and the decoding. The device 125 is configured to cause the converter 123, the debug module 124, and the decoder 125 to perform respective operations based on the second clock signal CLK2. In an embodiment, the second clock signal CLK2 is substantially the same as the frequency of the first clock signal CLK1.

In still further embodiments, the clock data recovery circuit 122 The clock calibration signal TAJ in the display data stream DS-S in the form of a serial sequence is received, and the second clock signal CLK2 is generated or updated accordingly. The related operations will be detailed in the subsequent paragraphs.

In addition, in an embodiment, the clock data recovery circuit 122 can Implemented with a phase lock loop (PLL) or a delay lock loop (DLL).

In this embodiment, the converter 123 is configured to receive the second time pulse signal. No. CLK2 and serial display data stream DS-S, and according to the second clock signal CLK2, convert the display data stream DS-S in parallel form into parallel The display data stream DS-P. In the present embodiment, the form of the converter 123 and the form of the converter 114 correspond to each other.

In this embodiment, the debugging module 124 is configured to receive the second clock. The signal CLK2 and the display data stream DS-P from the converter 123 determine whether the display data stream DS-P has an error based on the contents of the second clock signal CLK2 and the display data stream DS-P. Then, the debugging module 124 is configured to provide the error signal LK to the transmitting end 110 according to the determination result, so that the processor 113 of the transmitting end 110 transmits the clock calibration signal TAJ through the display data stream DS-P/DS-S.

For example, the debug module 124 determines that the data stream DS-P is displayed. When there is an error, the debug module 124 provides an error signal LK (for example, a signal of a low voltage level) to the transmitting end 110. At this time, the processor 113 of the transmitting end 110 transmits the clock calibration signal TAJ to the clock data recovery circuit 122 in each of the source drivers 30 according to the error signal LK in the display data stream DS-P/DS-S. The clock data recovery circuit 122 updates the second clock signal CLK2 according to the clock calibration signal TAJ to realign the frequency and phase of the second clock signal CLK2 with the first clock signal CLK1 (it should be noted that due to the signal The delay is delayed, and the phase of the second clock signal CLK2 is actually slightly behind the first clock signal CLK1). Then, the transmitting end 110 can retransmit the same data (such as the same data frame) or directly transmit the second data (such as the next data frame or the data frame of the next frame).

Through the above mechanism, the second clock signal CLK2 is out of alignment and / Or when the data stream DS-S/DS-P is displayed in the transmission, the error detection module 124 can notify the transmitting end 110 to transmit the clock calibration signal due to the detection of the error. No. TAJ, so that the frequency and phase of the first and second clock signals CLK1, CLK2 are realigned. Then, the transmitting end 110 continues to transmit the data. Thereby, the display 10 can be made more stable.

In addition, in this embodiment, the decoder 125 is configured to receive from The debug module 124 displays the data stream DS-P and decodes the encoded image data DT-E in the display data stream DS-P to generate the decoded image data DT. Then, the decoder 125 can provide the decoded image data DT to the relevant components at the back end of the source driver 30, so that the related components generate the data signals D(1), . . . , D(M) according to the image data DT.

Furthermore, the decoder 125 can also provide the display data stream DS-P The data CONF is set to the control module 126 to cause the control module 126 to perform corresponding control according to the setting data CONF (for example, controlling the color depth bit of the source driver 30).

FIG. 4 is a schematic diagram of a display data stream DS-P according to an embodiment of the present invention. The display data stream DS-P includes a plurality of pen frame data FM. The display 10 displays an image of each frame in accordance with each frame data FM.

In this embodiment, each frame data FM sequentially includes a plurality of data frames L(1), L(2), ..., L(N), CN, VB of the frame. The data frames L(1)-L(N) of one frame data FM respectively include scan line data of the 1-Nth column of the frame. In each frame, display 10 is based on scan line data in columns 1-N of the frame to cause each column of pixels 106 to display an image of the frame, respectively.

In addition, the data frame CN includes a setting information CONF. The timing controller 20 controls the source driver 30 through the data frame CN. (eg, controlling the color depth bit of the source driver 30).

Furthermore, the data frame VB includes a vertical blanking code V-BK. data The frame VB is the last data frame of the frame data FM.

In this embodiment, the data frames L(1), L(2), ... L(N), Both CN and VB include horizontal occlusion code H-BK and operation data OPD. The operation data OPD of the data frames L(1), L(2), ... L(N) sequentially includes a bit alignment code BAC, a control code CTRL, an encoded image data DT-E, and an end code. EOL. The operation data OPD of the data frame CN sequentially includes a bit synchronization code BAC, a control code CTRL, a setting data CONF, and an end code EOL. The operation data OPD of the data frame VB sequentially includes a bit synchronization code BAC, a control code CTRL, and a vertical blanking code V-BK.

In this embodiment, the bit synchronization code (bit) in each data frame Alignment code) BAC is the first order data in the operating data OPD, corresponding to the starting position of the operating data OPD. The control code CTRL in each data frame is the second order data adjacent to the bit synchronization code BAC in the operation data OPD, and can be used to indicate the type of the data frame (for example, the data frame L(1)-L(N) ) or the information frame CN). Each end code EOL is the last order data in the data frame L(1), L(2), ... L(N), CN operation data OPD, corresponding to the data frame L(1), L(2), ...L(N), the end position of the operating data OPD of the CN. Each encoded image data DT-E is the first 1-N scan line data in the frame data FM.

In addition, the transmitting end 110 corresponds to the horizontal occlusion period of the display 10. Horizontal blanking period or vertical blanking period, horizontal shading code H-BK and vertical obscuration The code V-BK is to the receiving end 120.

In order to make the technical content of the embodiment of the present invention easier to understand, the following will be accompanied by the fifth to sixth figures, and the specific details of the present case will be described by an operation example.

Referring also to Figures 5 and 6, Figure 5 is a flow chart of a method of operation of display 10 in accordance with an embodiment of the present invention. FIG. 6 is a schematic diagram showing a display data stream DS-P/DS-S according to an operation example of the present application. The method of operation includes the following steps.

In step S1, after the display 10 is activated, the transmitting end 110 transmits the clock calibration signal TAJ to the receiving end 120 by displaying the data stream DS-S/DS-P (refer to the time point t0-t1 in FIG. 6).

In step S2, when the receiving end 120 receives the clock calibration signal TAJ, the receiving end 120 transmits the second clock signal CLK2 according to the clock calibration signal TAJ through the clock data recovery circuit 122. Then, before the second clock signal CLK2 is updated, the converter 123, the debug module 124, and the decoder 125 of the receiving end 120 operate according to the second clock signal CLK2.

In step S3, the transmitting end 110 transmits the horizontal blanking code H-BK to the receiving end 120 by displaying the data stream DS-S/DS-P (refer to the time point t1-t2 in Fig. 6).

In step S4, when the receiving end 120 receives the horizontal blanking code H-BK, the receiving end 120 determines whether the horizontal blanking codes H-BK have errors through the debugging module 124. More specifically, the debug module 124 is configured to determine whether at least one of the horizontal obscuration codes H-BK is consistent with the horizontal obscuration code H-BK and the preset obscured code encoding format. Preset mask There is no code encoding format, and it is determined whether to provide the error signal LK to the transmitting end 110. The term "mask code encoding format" as used herein means a coding format predefined by the designer. Since the normal occlusion code H-BK should conform to the preset occlusion code encoding format under normal conditions, according to whether the horizontal occlusion code H-BK received by the receiving end 120 conforms to the occlusion code encoding format, It is known whether an error occurs in the data stream DS-S/DS-P and/or the second clock signal CLK2.

One or more of these horizontal obscuration codes H-BK are not When the preset mask code encoding format is met, the receiving end 120 determines that an error has occurred through the debug module 124, and proceeds to step S14. Otherwise, step S5 is performed.

In step S14, the receiving end 120 transmits the error signal LK to the transmitting end 110 through the error detecting module 124, and the flow returns to step S1.

It should be noted that the condition that the error detection module 124 transmits the error signal LK (such as the number of consecutive errors in the horizontal occlusion code H-BK) may vary according to actual needs, and the present invention is not limited to the above embodiment.

In step S5, the transmitting end 110 sequentially transmits the bit synchronization code BAC and the control code CTRL to the receiving end 120 by referring to the data stream DS-S/DS-P (refer to the time point t2-t4 in FIG. 6).

In step S6, when the receiving terminal 120 receives the bit control code CTRL, the receiving end 120 determines through the debug module 124 whether the control code CTRL is correctly received. Specifically, after receiving the bit synchronization code BAC (ie, the first operation sequence data of the operation data OPD (refer to FIG. 4)), the error detection module 124 determines that the operation data OPD is adjacent to the bit synchronization code BAC. Whether the second-order data conforms to at least one preset control code encoding format to determine Whether the receiving end 120 correctly receives the control code CTRL. The "control code encoding format" is defined in advance by the designer and can be used to indicate the encoding format of the type of the data frame. Since the control code CTRL should normally conform to the control code encoding format, the display data stream DS-S/DS-P and/or the data stream can be known according to whether the control code CTRL received by the receiving end 120 conforms to the control code encoding format. Whether an error occurs in the second clock signal CLK2.

More specifically, in this operation example, the receiving end 120 is substantially It is determined whether the second order data adjacent to the bit synchronization code BAC in the operation data OPD conforms to a preset image frame encoding format, a preset setting frame encoding format, or a preset blanking frame encoding format.

Second in the operation data OPD adjacent to the bit synchronization code BAC If the order data does not match any of the preset control code encoding formats, the receiving end 120 determines that an error has occurred through the debug module 124, and proceeds to step S14. On the other hand, if the control code CTRL conforms to the preset video frame coding format, step S7 is performed. If the control code CTRL conforms to the preset frame coding format, step S10 is performed. In the case where the control code CTRL conforms to the preset mask code frame encoding format, step S12 is performed.

In step S7, the control code CTRL transmitted at the transmitting end 110 In the case that the preset video frame coding format is met, it means that the transmitting end 110 is transmitting one of the data frames L(1)-L(N), and the transmitting end 110 transmits the plurality of encoded image data DT- E (refer to time point t4-t5 in Fig. 6).

In step S8, when the receiving end 120 receives the encoded image data DT-E, the receiving end 120 determines the content through the debugging module 124. Whether at least one of the encoded image data DT-E conforms to a preset image data encoding format. The "image data encoding format" herein means the encoding format that the encoded image data DT-E should have. For example, in the case that the encoder 112 of the transmitting end 110 is an 8-bit to 9-bit encoder, the debugging module 124 determines whether the image data DT-E conforms to the 8-bit to 9-bit encoder. The output encoding format determines whether to transmit the error signal LK to the transmitting terminal 110. Since the DT-E of each encoded image data should conform to the image data encoding format under normal conditions, the display data stream DS can be known according to whether the image data DT-E received by the receiving end 120 conforms to the image data encoding format. -S/DS-P and/or second clock signal CLK2 whether an error has occurred.

In a case where one or a plurality of the encoded image data DT-E does not conform to the preset image data encoding format, the receiving end 120 determines that an error has occurred through the debugging module 124, and proceeds to step S14. Otherwise, step S9 is performed.

It should be noted that the condition that the error detection module 124 transmits the error signal LK (for example, the number of times the encoded image data DT-E does not conform to the image data encoding format continuously) may vary according to actual needs, and the present invention is not limited to the above embodiment.

In step S9, the transmitting end 110 transmits the end code EOL to the receiving end 120, indicating that the transmission of the data frame has ended (refer to the time point t5-t6 in Fig. 6). Then, the flow returns to step S3, and the transmitting end 110 starts transmitting the horizontal blanking code H-BK of the next data frame (for example, referring to the time point t6-t7 in Fig. 6).

On the other hand, in step S10, transmitted at the transmitting end 110 When the control code CTRL conforms to the preset setting frame encoding format, that is, the transmitting terminal 110 is transmitting the data frame CN, and the transmitting terminal 110 transmits the plurality of setting data CONF (refer to the time point t8-t9 in FIG. 6).

In step S11, the receiving terminal 120 receives the aforementioned setting capital. When the CONF is processed, the receiving end 120 determines whether at least one of the setting materials CONF conforms to the preset setting data encoding format through the debugging module 124. The "set data encoding format" herein means a pre-defined encoding format of the designer. When receiving the setting data having the format, the source driver 30 performs corresponding control (such as adjusting the color depth bit, etc.). Since the CONF of each setting data should conform to the setting data encoding format under normal circumstances, according to whether the setting data CONF received by the receiving end 120 conforms to the setting data encoding format, the display data stream DS-S/DS-P and / or whether the second clock signal CLK2 has an error.

One of the setting data CONF or the continuous multiple does not match In the case where the preset data encoding format is set, the receiving terminal 120 determines that an error has occurred through the debug module 124, and proceeds to step S14. Otherwise, step S9 is performed.

It should be noted that the debug module 124 transmits the strip of the error signal LK. The case (such as the number of times the setting data CONF does not meet the setting data encoding format continuously) can be changed according to actual needs, and the present case is not limited to the above embodiment.

In still another aspect, in step S12, the transmission is performed at the transmitting end 110. When the control code CTRL conforms to the preset mask code frame encoding format, that is, the transmitting terminal 110 is transmitting one of the data frames L(1)-L(N), and the transmitting terminal 110 transmits the plurality of vertical masks. No code V-BK (refer to time in Figure 6) Point t10-t11).

In step S13, the aforementioned vertical mask is received at the receiving end 120. When the V-BK is not coded, the receiving end 120 determines whether at least one of the vertical obscuration codes V-BK conforms to the preset obscuring code encoding format through the debugging module 124. Since the normal occlusion code V-BK should conform to the occlusion code encoding format under normal conditions, the vertical occlusion code V-BK received by the receiving end 120 conforms to the occlusion code encoding format, and the display can be known. Whether the data stream DS-S/DS-P and/or the second clock signal CLK2 has an error.

One or more of the vertical occlusion codes V-BK are not When the preset mask code encoding format is met, the receiving end 120 determines that an error has occurred through the debug module 124, and proceeds to step S14. Otherwise, the process returns to step S3 to cause the transmitting end 110 to transmit the next frame data FM.

It should be noted that the debug module 124 transmits the strip of the error signal LK. The case (such as the number of times the vertical occlusion code V-BK does not conform to the occlusion code coding format) may vary according to actual needs, and the present case is not limited to the above embodiment.

Through the above operations, the debug module 124 can be used to display The data stream DS-S/DS-P performs error detection. An error occurred in the horizontal blanking code H-BK, the vertical blanking code V-BK, the control code CTRL, the encoded image data DT-E, or the setting data CONF in the display data stream DS-S/DS-P. When the preset encoding format is not met, the debugging module 124 can notify the transmitting end 110 to enable the transmitting end 110 to perform error elimination control. Thereby, the stability of the display 10 can be improved.

Although the case has been disclosed above by way of example, it is not intended to limit In this case, anyone who is familiar with this skill will not leave the spirit and scope of the case. Within the scope of this patent, the scope of protection of this case shall be subject to the definition of the scope of the patent application.

S1-S14‧‧‧Steps

Claims (12)

A data transmission system for a display, comprising: a transmitting end for generating a first clock signal, and configured to provide a display data stream according to the first clock signal; and a receiving end electrically connected to the The transmitting end is configured to receive the display data stream, wherein the receiving end comprises: a debugging module, configured to determine, according to a second clock signal, whether the display data stream received by the receiving end has an error, and is used by Providing an error signal to the transmitting end according to the judgment result, so that the transmitting end transmits a clock calibration signal through the display data stream; and a clock data recovery circuit electrically connected to the debugging module, the clock data recovery circuit The second clock signal is updated according to the clock calibration signal. The data transmission system of claim 1, wherein the error detection module is further configured to determine whether at least one horizontal occlusion code or at least one vertical occlusion code in the display data stream conforms to an occlusion code encoding format, Determining whether to provide the error signal to the transmitting end, and the transmitting end respectively transmits the horizontal blanking period and a vertical blanking period corresponding to the display, and the horizontal blanking period and the vertical blanking period Vertical obscuration code. The data transmission system of claim 1 or 2, wherein the display The data stream includes a plurality of data frames, and at least one of the data frames includes a plurality of operation data, the operation data includes a synchronization code and a control code, and the bit synchronization code is in the operation data. a first order data, the control code is a second order data adjacent to the synchronization code in the operation data, and the debugging module is further configured to determine whether the receiving end correctly receives the control code to determine Whether to provide the error signal to the transmitter. The data transmission system of claim 3, wherein the error detection module is further configured to determine whether the second order data adjacent to the bit synchronization code in the operation data conforms to at least one control code encoding format to determine Whether the receiving end correctly receives the control code adjacent to the bit synchronization code in the display data stream. The data transmission system of claim 3, wherein the error detection module is further configured to determine whether the control code conforms to an image frame encoding format, and is configured to: when the control code conforms to the image frame encoding format, Determining whether at least one of the image data in the operation data conforms to an image data encoding format to determine whether to provide the error signal to the transmitting end. The data transmission system of claim 3, wherein the error detection module is further configured to determine whether the control code conforms to a set frame coding format, and is configured to: when the control code conforms to the set frame coding format, Determining whether at least one of the setting data of the operation data conforms to a setting data encoding format to determine whether the error signal is provided to the transmitting end. An operation method for a display, wherein the display includes a transmitting end and a receiving end, the operating method includes: transmitting, by the transmitting end, a display data stream according to a first clock signal; receiving, by the receiving end, receiving The display data stream determines whether the display data stream has an error according to a second clock signal, and provides an error signal according to the determination result; and transmits, by the transmitting end, a clock calibration by using the display data stream according to the error signal And receiving, by the receiving end, the second clock signal according to the clock calibration data. The operation method of claim 7, wherein the step of determining whether the displayed data stream has an error and providing the error signal according to the determination result comprises: determining at least one horizontal obscuration code or at least one vertical concealment in the display data stream. Whether the code does not conform to an obscuration code encoding format to determine whether to provide the error signal to the transmitting end, wherein the transmitting end transmits the horizontal obscuring code respectively for a horizontal blanking period and a vertical blanking period of the display And the vertical obscuration code. The operating method of claim 7 or 8, wherein the step of providing the display data stream comprises: Providing the display data stream including a plurality of data frames, wherein at least one of the data frames includes a plurality of operation data, the operation data includes a synchronization code and a control code, wherein the bit synchronization code is a first order data in the operation data, and the control code is a second order data adjacent to the synchronization code in the operation data; and determining whether the display data stream has an error, and providing the The step of the error signal includes: determining whether the control code is correctly received to determine whether to provide the error signal to the transmitting end. The operation method of claim 9, wherein determining whether the receiving end correctly receives the control code adjacent to the bit synchronization code in the display data stream to determine whether to provide the error signal to the transmitting end comprises: determining Whether the second order data adjacent to the bit synchronization code in the operation data conforms to at least one control code encoding format to determine whether the receiving end correctly receives the control adjacent to the bit synchronization code in the display data stream. code. The operation method of claim 9, wherein the step of determining whether the control code is correctly received comprises: determining whether the control code conforms to an image frame encoding format; and determining whether the displayed data stream has an error, and according to the determination result The step of providing the error signal includes: judging that the control code conforms to the image frame encoding format Whether at least one of the image data of the operation data conforms to an image data encoding format to determine whether the error signal is provided to the transmitting end. The operation method of claim 9, wherein the step of determining whether the control code is correctly received comprises: determining whether the control code conforms to a set frame encoding format; and determining whether the displayed data stream has an error, and according to the determination result The step of providing the error signal includes: if the control code conforms to the setting frame encoding format, determining whether at least one of the setting data meets a setting data encoding format to determine whether to provide the error signal to The transmitting end.