TW201517470A - DC-DC controller and control method thereof - Google Patents

Abstract

A DC-DC controller and a control method thereof are provided. The provided DC-DC controller is coupled to an output stage. The output stage receives an input voltage and to provide an output voltage. The DC-DC controller includes a transient boost circuit, a ramp oscillator, a combination logic circuit, a first comparator and a pulse-width-modulation (PWM) generator. The transient boost circuit generates an adjustment signal according to a variation of the output voltage. The combination logic circuit provides a ramp signal according to the adjusting signal and an output of the ramp oscillator. When the adjusting signal has a first logic level, the combination logic circuit adjusts the ramp signal so that the ramp signal is maintained at a first predetermined level for a predetermined time. The invention is capable of enhancing the transient response and providing the current rapidly.

Description

DC to DC controller and control method thereof

The invention relates to a DC to DC control technology, and in particular to a DC to DC controller and a control method thereof.

1 is a circuit block diagram of a conventional DC-to-DC converter. The DC-to-DC converter 100 converts the input voltage V _DD into an output voltage V _OUT , and the DC-to-DC converter 100 has a detection circuit 110 for detecting an output voltage V _OUT , wherein when the output voltage V is detected _OUT has a fast pumping phenomenon, and a logic high level is output to the logic circuit 120. Next, logic circuit 120 forces the metal oxide semiconductor within output stage 130 to conduct according to this logic high level, and provides the current required by the load terminal through buck circuit 140.

The DC to DC converter 100 has two loops, one loop via the feedback circuit 150 and the other loop via the detection circuit 110. In the conventional driving method, the two loops are used, and the logic circuit 120 forces the output stage 130 to be turned on according to the logic high level of the detecting circuit 110. This practice will affect the output of the feedback circuit 150 becoming less important, so the overall implementation is rougher and the integrity of the single loop of the feedback circuit 150 cannot be maintained, so conventional drive techniques still exist. Improved space.

In view of this, the present invention proposes a controller and converter for DC-to-DC applications, a multi-phase controller and a multi-phase converter to solve the problems described in the prior art.

The invention provides a DC to DC controller coupled to an output stage. The output stage receives the input voltage and provides an output voltage. The DC-to-DC controller includes a transient boost circuit, a ramp oscillator, a combinational logic circuit, a first comparator, and a pulse width modulation generator. The transient boost circuit generates an adjustment signal based on the variation of the output voltage. The combinational logic circuit is coupled to the transient boost circuit, and the ramp oscillator is controlled according to the adjustment signal to generate a ramp signal. The first comparator is coupled to the combination logic circuit to generate a first signal according to one of the output voltage correlations outputting the feedback voltage and the ramp signal. The pulse width modulation generator is coupled to the first comparator, and generates a pulse width modulation signal according to the first signal to control the operation of the output stage.

In an embodiment of the invention, the transient boosting circuit includes a compensation adjustment circuit and a second comparator. The compensation adjustment circuit receives the output voltage to generate a transient boost voltage, wherein the transient boost voltage has a steady state voltage compensation corresponding to the output voltage. The second comparator compares the output voltage with the transient boost voltage to generate an adjustment signal. Moreover, when the transient boost voltage is higher than the output voltage, the adjustment signal has a logic high level, and when the transient boost voltage is lower than the output voltage, the adjustment signal has a logic low level.

In an embodiment of the invention, when the adjustment signal has a logic high level, the combination logic circuit maintains the ramp signal at the first preset level, wherein the first preset The level is below the level of the error signal associated with the output voltage.

In an embodiment of the invention, the compensation adjustment circuit includes a first capacitor, Current source and resistance. The first capacitor is coupled to the first input of the second comparator for maintaining the transient boost voltage. The current source is coupled to the first input of the second comparator for generating a current. The resistor is coupled between the first input end and the second input end of the second comparator for generating voltage compensation. Among them, the impedance of the resistor is multiplied by the current to generate voltage compensation.

In an embodiment of the invention, the transient boost circuit includes a second capacitor And a third comparator. The second capacitor is used to maintain a transient boost voltage. The third comparator has a first input coupled to the output voltage and a second input coupled to the second capacitor, and has a compensation voltage derived between the first input and the second input of the third comparator, The third comparator compares the output voltage with the transient boost voltage to generate an adjustment signal. Wherein, when the transient boost voltage is higher than the output voltage, the adjustment signal has a logic high level, and when the transient boost voltage is lower than the output voltage, the adjustment signal has a logic low level.

The invention further provides a DC to DC control method for making an output stage The output voltage can be provided after receiving the input voltage. The DC-to-DC control method includes the following steps: generating an adjustment signal according to a variation of the output voltage; providing a ramp signal according to the output of the adjustment signal and the ramp oscillator; generating a first signal according to the output feedback voltage and the ramp signal associated with the output voltage; And generating a pulse width modulation signal according to the first signal to control the operation of the output stage.

In an embodiment of the invention, the step of generating the adjustment signal according to the variation of the output voltage further comprises: receiving the output voltage to generate a transient boost voltage, wherein the transient boost voltage has a steady state voltage corresponding to the output voltage Compensation; and comparison The output voltage and the transient boost voltage are used to generate an adjustment signal.

In an embodiment of the invention, when the transient boost voltage is higher than the output power When the voltage is applied, the adjustment signal has a logic high level, and when the transient boost voltage is lower than the output voltage, the adjustment signal has a logic low level.

In an embodiment of the invention, when the adjustment signal has a logic high level The step of providing a ramp signal according to the adjustment signal and the output of the ramp oscillator further includes: maintaining the ramp signal at a first preset level, wherein the first preset level is lower than the error signal associated with the output voltage quasi.

Based on the above, the present invention is produced by detecting a transient change in the output voltage. a trimming signal, the combination logic circuit provides a ramp signal according to the adjustment signal and the output of the ramp oscillator, wherein the combination logic circuit maintains the ramp signal at the first preset level when the adjustment signal has a logic high level, wherein the first preset bit Quasi-lower than the level of the error signal associated with the output voltage (for example, pulling the ramp signal to zero quickly) and maintaining a preset time, and after a preset time and when the adjustment signal returns to a logic low level, then cycle The ramp signal is generated. Therefore, the present invention can enhance the transient response and rapidly supply current. On the other hand, it is also avoided to affect the closed loop control of the feedback circuit in a conventional open circuit manner, while maintaining the integrity of the single loop control.

The above described features and advantages of the invention will be apparent from the following description.

100‧‧‧DC to DC converter

110‧‧‧Detection circuit

120‧‧‧Logical Circuit

130‧‧‧Output level

140‧‧‧Buck circuit

150‧‧‧Return circuit

200‧‧‧ (single phase) DC to DC converter

202‧‧‧current source

204‧‧‧resistance

206‧‧‧ Capacitance

208‧‧‧Compensated voltage source

210, 810‧‧‧DC to DC controller

220, 820‧‧‧ Transient boost circuit

222, 822‧‧‧ compensation adjustment circuit

224, 824‧‧‧ comparator

230, 830‧‧‧ combinational logic circuit

240, 840‧‧‧ slope oscillator

250, 852~858‧‧‧ first comparator

260, 860‧‧‧ pulse width modulation generator

270, 872~878‧‧‧ output stage

272, 274‧‧‧ drive

276, 278‧‧‧N type MOS transistor

280‧‧‧Buck circuit

290‧‧‧Return circuit

292‧‧‧Error amplifier

800‧‧‧ (Multiphase) DC to DC Converter

GND‧‧‧ Grounding voltage

I _LOAD ‧‧‧Load current

S _DRIVE , S _DRIVE1 ~S _DRIVE4 ‧‧‧ drive signal

S _PWM1 , S _PWM2 , S _PWM11 ~ S _PWM14 ‧‧‧ Pulse width modulation signal

S901~S907‧‧‧ steps of the DC-to-DC conversion method of the embodiment

T _B ‧‧‧Transient boost voltage

T _ON ‧‧‧ On time

T1‧‧‧Preset time

V _ADJ ‧‧‧Adjustment signal

V _COMP ‧‧‧ error signal

V _DD ‧‧‧ input voltage

V _FB ‧‧‧Responsive voltage

V _OUT ‧‧‧ output voltage

V _OFFSET , V _OFFSET1 ‧‧‧Compensation voltage

V _RAMP ‧‧‧Ramp signal

V _REF ‧‧‧reference voltage

V ₁ , V ₁₁ ~V ₁₄ ‧‧‧first signal

The following drawings are part of the specification of the invention and illustrate exemplary embodiments of the invention, together with the description principle.

1 is a circuit block diagram of a conventional DC-to-DC converter.

2 is a schematic diagram of a single phase DC to DC converter in accordance with an embodiment of the present invention.

3 is a waveform diagram of a fixed frequency architecture in accordance with an embodiment of the present invention.

4 is a transient boost circuit in accordance with an embodiment of the present invention.

FIG. 5 is a waveform diagram of a transient boosting circuit according to an embodiment of the invention.

6 is a transient boosting circuit in accordance with another embodiment of the present invention.

7 is a waveform diagram of a constant on-time architecture in accordance with an embodiment of the present invention.

8 is a schematic diagram of a multi-phase DC to DC converter in accordance with an embodiment of the present invention.

FIG. 9 is a flow chart of a DC-to-DC control method according to an embodiment of the invention.

Reference will now be made in detail be made to the embodiments of the invention In addition, the same or similar reference numerals are used in the drawings and the embodiments to represent the same or the like.

2 is a schematic diagram of a single phase DC to DC converter in accordance with an embodiment of the present invention. Please refer to Figure 2. The single-phase DC-DC converter 200 includes a DC-DC controller 210, a switch device 270, a buck circuit 280, and a feedback circuit. (feedback circuit) 290 and error amplifier 292. The DC to DC converter 200 is adapted to convert the input voltage V _DD to the output voltage V _OUT . And the DC-DC controller 210 includes a transient boost circuit 220, a combination logic circuit 230, a ramp oscillator 240, and a first comparator. 250 and a pulse-width-modulation (PWM) generator 260.

More specifically, the combinational logic circuit 230 is coupled to the transient boost circuit 220 and the ramp oscillator 240. The first comparator 250 is coupled to the output of the combinational logic circuit 230. The pulse width modulation generator 260 is coupled to the output of the first comparator 250. The output stage 270 is coupled to the output of the pulse width modulation generator 260. The buck circuit 280 is coupled to the output of the output stage 270.

The feedback circuit 290 can include a plurality of resistors (not shown) for dividing the output voltage V _OUT to generate a feedback voltage V _FB . The error amplifier 292 compares the feedback voltage V _FB with the reference voltage V _REF to generate an error signal V _COMP (output feedback voltage) associated with the output voltage V _OUT .

3 is a waveform diagram of a fixed frequency architecture in accordance with an embodiment of the present invention. Please refer to FIG. 2 and FIG. 3 together. The transient boosting circuit 220 receives the output voltage V _OUT and generates an adjustment signal V _ADJ according to the variation of the output voltage V _OUT . When the adjustment signal V _ADJ has a logic high level, it indicates that the transient phenomenon of the pumping is detected. The combinational logic circuit 230 provides a ramp signal V _RAMP based on the adjustment signal V _ADJ and the output of the ramp oscillator 240 , and the waveform of the ramp signal V _RAMP may be zigzag or triangular. When the adjustment signal V _ADJ has a logic high level, the combinational logic circuit 230 maintains the ramp signal V _RAMP at a first predetermined level, wherein the first predetermined level is lower than the level of the error signal V _COMP associated with the output voltage. For example, the ramp signal V _{RAMP is} quickly pulled to zero (or pulled to the lowest) and maintained for a preset time t1, and after the preset time t1 has elapsed and when the adjustment signal V _ADJ returns to a logic low level, it is generated periodically. Zigzag or triangular ramp signal V _RAMP .

Additionally, the transient boost circuit 220 can include an offset adjustment circuit 222 and a comparator 224. The compensation adjustment circuit 222 receives the output voltage V _OUT and then generates a transient boost voltage T _B having a compensation voltage corresponding to the output voltage V _OUT . The comparator 224 receives the output voltage V _OUT at the first end and the transient boost voltage T _{B at the} second end, and compares the output voltage V _OUT and the transient boost voltage T _B to generate an adjustment signal V _ADJ .

The first comparator 250 generates a first signal V ₁ according to the error signal V _COMP associated with the output voltage V _OUT and the ramp signal V _RAMP . When the error signal V _{COMP is} higher than the ramp signal V _RAMP , the first signal V ₁ generated by the first comparator 250 has a pulse wave of a logic high level. The pulse width modulation generator 260 generates a pulse width modulation signal S _PWM1 according to the first signal V ₁ for driving the output stage 270. From the overall circuit view, the combination logic circuit 230 can avoid the priority of the adjustment signal V _ADJ being higher than the error signal V _COMP , so that the control of the DC-DC controller 210 is relatively round and smooth, and can be controlled in a single loop.

Next, the output stage 270 converts the input voltage V _DD into a drive signal S _DRIVE according to the pulse width modulation signal S _PWM1 , so that the buck circuit 280 can generate the output voltage V _OUT according to the drive signal S _DRIVE . This output voltage V _OUT can be supplied to a load driven by direct current.

In the present embodiment, output stage 270 can include drivers 272 and 274, and N-type metal oxide semiconductor (NMOS) transistors 276 and 278. Drivers 272 and 274 receive pulse width modulated signal S _PWM1 and are converted to a switching signal for turning on one of N-type MOS transistors 276 and 278. The N-type MOS transistors 276 and 278 can convert the input voltage V _DD into a drive signal S _DRIVE according to the switching signal, wherein the drive signal S _DRIVE is a node voltage between the MOS transistors 276 and 278. Therefore, when the MOS transistor 276 is turned on and the MOS transistor 278 is turned off, the drive signal S _{DRIVE is} equivalent to the input voltage V _DD ; when the MOS transistor 278 is turned on and When the MOS transistor 276 is non-conductive, the drive signal S _{DRIVE is} equivalent to the ground voltage GND.

4 is a transient boost circuit 220 in accordance with an embodiment of the present invention. Please refer to Figure 4. The compensation adjustment circuit 222 can include a current source 202, a resistor 204, and a capacitor 206. The input compensation voltage V _OFFSET between the output voltage V _OUT and the transient boost voltage T _B depends on the impedance value of the resistor 204 and the current generated by the current source 202. The resistor 204 and the capacitor 206 together form a low pass filter (LPF) to stabilize the transient boost voltage T _B , so a compensation voltage V _OFFSET having a corresponding steady-state output voltage V _OUT can be used to correct the transient rise. Pressurized voltage T _B . Referring to FIG. 5, when the load is connected to the DC to DC converter 200, the output voltage V _OUT maintains an initial steady state, and the transient boost circuit 220 has a transient rise of the compensation voltage V _OFFSET corresponding to the output voltage V _OUT . Pressurized voltage T _B . When the output voltage V _OUT drops due to the current load, the transient boost voltage T _B cannot be immediately responded due to the low pass filter. Therefore, if the output voltage V _OUT drops below the transient boost voltage T _B , the comparator 224 generates a logic high level pulse as the adjustment signal V _ADJ . Conversely, if the output voltage V _OUT becomes higher than the transient boost voltage T _B , the comparator 224 generates a logic low level signal as the adjustment signal V _ADJ . The positive pulse wave adjustment signal V _ADJ will force the _MOS transistor 272 to conduct, thereby pulling up the output voltage V _OUT to supply more current to the load. One of the advantages of this embodiment is that the transient boost circuit 220 responds to the current load component faster than the pulse width modulation signal S _PWM1 because the error signal V _COMP will follow the output voltage V _OUT (with time delay). Variety.

FIG. 6 is a transient boost circuit 220 in accordance with another embodiment of the present invention. Please refer to Figure 6. Comparator 224A can perform a compensation adjustment. The comparator 224A has a compensation voltage source 208 therein, and the compensation voltage source 208 generally supplies an input compensation voltage V _OFFSET1 between the input output voltage V _OUT and the transient boost voltage T _B , and the capacitor 212 is often used for stabilizing the temporary State boost voltage T _B . To perform internal compensation voltage source 208 in comparator 224A, the input stage transistor dimensions of comparator 224A can be fabricated to be mismatched to produce input compensation. For example, the compensation voltage can be set to 100~200mV, and the compensation value can be determined according to the actual design rules.

Please refer to Figure 3 again. The dashed line depicted in FIG. 3 is a waveform as in the conventional FIG. 1 architecture, and the solid line is the waveform of the architecture of the embodiment of the present invention. The triangular wave in the fixed frequency architecture occurs periodically, and when the adjustment signal V _{ADJ is} generated, the transient state of the output voltage V _OUT occurs. The combinational logic circuit 230 quickly pulls the ramp signal V _RAMP to zero (or pulls it to a minimum) and maintains for a predetermined time t1. Therefore, during the preset time t1, the ramp signal of the solid line is zero, and the error signal V _COMP is higher than the ramp signal V _RAMP anyway, and the pulse width modulation generator 260 of FIG. 2 is generated during this period of time. The pulse width modulation signal S _PWM1 can extend the logic high level time, thus speeding up the transient response. When the pulse of the adjustment signal V _ADJ ends, the pulse width modulation generator 260 generates a PWM waveform of the normal pulse wave.

In the above, the pulse width modulation signal S _{PWM2 in} FIG. 3 is a waveform for comparison, and the pulse width modulation signal S _PWM2 is the output of the logic circuit 120 of FIG. The pulse width modulation signal S _{PWM1 of the} embodiment of the present invention can be maintained at a logic high level for a long period of time during the transient occurrence, so that the DC to DC converter 200 can supply more current to the load.

7 is a waveform diagram of a constant on-time architecture in accordance with an embodiment of the present invention. Please refer to Figure 7. Compared to FIG. 3, the waveform of the ramp signal V _RAMP here is an inverted triangle. The DC-to-DC converter 200 using a constant on-time architecture, when the load current I _LOAD increases, that is, the transient boost voltage T _B occurs to generate a positive pulse adjustment signal V _ADJ . The combinational logic circuit 230 can quickly pull the ramp signal V _RAMP to the valley and maintain a fixed preset time t1. During the pulling to the bottom of the valley, the first comparator 250 can know that the error signal V _{COMP is} higher than the ramp signal V _RAMP according to the comparison of the two signals, and the pulse width modulation generator 260 can always generate the pulse of the PWM pulse wave. Wide variable signal S _PWM1 . In this embodiment, one PWM pulse can be added during the transient period than the conventional pulse width modulation signal S _PWM1 . In addition, the high level on time T _ON of each PWM pulse is fixed and at least separated by a minimum off time, rather than extending the logic high level directly in the manner of FIG.

Furthermore, the pulse width modulation signal S _{PWM1 of} FIG. 7 can be maintained at a logic high level for a long period of time during transient occurrence compared to the prior art, so that the DC-to-DC converter 200 applying a constant on-time architecture can be supplied. More current to the load.

8 is a schematic diagram of a multi-phase DC to DC converter in accordance with an embodiment of the present invention. Please refer to Figure 8. The architecture and operation of the multiphase DC to DC converter 800 is similar to the DC to DC converter 200 of FIG. The DC-to-DC converter 800 includes a DC-to-DC controller 810, a plurality of output stages 872-878, a buck circuit 880, a feedback circuit 890, and an error amplifier 892. The DC-to-DC converter 800 is adapted to convert the input voltage V _DD into an output voltage V _OUT with a multi-phase channel, wherein the output of each output stage is equivalent to a phase channel, and the outputs of the plurality of output stages form a multi-phase channel. The DC-to-DC controller 810 includes a transient boost circuit 820, a combinational logic circuit 830, a ramp oscillator 840, first comparators 852-858, and a pulse width modulation generator 860.

The combinational logic circuit 830 is coupled to the transient boosting circuit 820 and the ramp oscillator 840. The first comparators 852-858 are coupled to the combinational logic circuit 830 and the pulse width modulation generator 860. The plurality of output stages 872-878 are coupled to the pulse width modulation generator 860. The buck circuit 880 is coupled to the outputs of these output stages 872-878.

The feedback circuit 890 can include a plurality of resistors (not shown) for dividing the output voltage V _OUT to generate a feedback voltage V _FB . The error amplifier 892 compares the feedback voltage V _FB with the reference voltage V _REF to produce an error signal V _COMP associated with the output voltage V _OUT . The operation of the transient boosting circuit 820 is the same as that of the transient boosting circuit 220 of FIG. 2, and the adjustment signal V _ADJ can be generated according to the variation of the output voltage V _OUT . The transient boost circuit 820 includes a compensation adjustment circuit 822 and a comparator 824. The compensation adjustment circuit 822 receives the output voltage V _OUT and then generates a transient boost voltage T _B having a compensation voltage corresponding to the output voltage V _OUT . The comparator 824 receives the output voltage V _OUT at the first end and the transient boost voltage T _{B at the} second end, and compares the output voltage V _OUT and the transient boost voltage T _B to generate the adjustment signal V _ADJ .

The combinational logic circuit 830 is _responsive to the adjustment signal V _ADJ and the output of the ramp oscillator 840 to provide a plurality of ramp signals V _RAMP1 VV _RAMP4 to the first ends of the corresponding first comparators _852-858 . The second end of each of the first comparators 852-858 receives an error signal V _COMP associated with the output voltage V _OUT . Each of the first comparator 852 ~ 858 _~ V RAMP4 generating a respective one of a first signal (V ₁₁ ~ V ₁₄ according to the error signal associated with the output voltage V _OUT V _COMP and the ramp signal thereto corresponding to V _RAMP1 ). The pulse width modulation generator 860 generates a plurality of pulse width modulation signals S _PWM11 ~S _PWM14 according to the first signal generations V ₁₁ VV ₁₄ . The output stage 872 ~ 878 according to the PWM signal _{S PWM11} ~ S PWM14 plurality of channels in a way to convert an input voltage V _DD to the driving signal _{S DRIVE1} ~ S DRIVE4. Next, the buck circuit 880 outputs energy to the load terminal based on the drive signals S _DRIVE1 to S _DRIVE4 to generate a sufficient output voltage V _OUT .

It is worth mentioning that in the embodiment of FIG. 8, four first comparators _852-858 are taken, and then four PWM phase pulse width modulation signals S _PWM11 ~ S _{RWM14 are generated} . This embodiment is only used for A multi-phase DC to DC converter is illustrated, and the number of multiphases can be varied without being limited to four phases, such as eight or sixteen phases. Everything depends on the actual design needs.

Based on the content disclosed in the above embodiments, a general DC to DC control method can be integrated. More specifically, FIG. 9 is a flow chart of a DC-to-DC control method according to an embodiment of the present invention. For convenience of description, please refer to FIG. 2 and FIG. 9. Referring to FIG. 2 and FIG. 9, the DC-DC control method of this embodiment may include the following steps.

As shown in step S901, an adjustment signal V _{ADJ is} generated according to the variation of the output voltage V _OUT .

Next, as shown in step S903, a ramp signal V _{RAMP is} generated based on the adjustment signal V _ADJ .

Next, as shown in step S905, the first signal V _{1 is} generated based on the output feedback voltage (eg, the error signal V _COMP ) associated with the output voltage and the ramp signal V _RAMP .

Then, as shown in step S907, a pulse width modulation signal S _{PWM1 is} generated according to the first signal V ₁ to control the operation of the output stage 270.

In addition, the detailed manner of performing step S901 may be as follows: receiving the output voltage V _OUT to generate a transient boosting voltage T _B , wherein the transient boosting voltage T _B has a steady state voltage compensation corresponding to the output voltage V _OUT ; The output voltage V _OUT and the transient boost voltage T _B are compared to generate an adjustment signal V _ADJ .

In addition, when the transient boost voltage T _{B is} higher than the output voltage V _OUT , the adjustment signal V _ADJ has a logic high level, and when the transient boost voltage T _{B is} lower than the output voltage V _OUT , the adjustment signal V _ADJ Has a logical low level. Furthermore, when the adjustment signal V _ADJ has a logic high level, the ramp signal V _RAMP can also be maintained at a first preset level, wherein the first preset level must be lower than the error signal V _COMP associated with the output voltage V _OUT The level of it.

In summary, the embodiment of the present invention uses a transient change in detecting an output voltage. In response to generating an adjustment signal, the combination logic circuit provides a ramp signal according to the adjustment signal and the output of the ramp oscillator, wherein when the adjustment signal has a logic high level, the combination logic circuit maintains the ramp signal at the first preset level, wherein the first pre- Set the level to be lower than the level of the error signal associated with the output voltage (for example, pull the ramp signal to zero quickly) and maintain a preset time, after a preset time and when the adjustment signal returns to a logic low level, The ramp signal is generated periodically. Therefore, the present invention can enhance the transient response and rapidly supply current. On the other hand, it is also avoided to affect the closed loop control of the feedback circuit in a conventional open circuit manner, while maintaining the integrity of the single loop control.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and those skilled in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

200‧‧‧DC to DC converter

210‧‧‧DC to DC controller

220‧‧‧Transient boost circuit

222‧‧‧Compensation adjustment circuit

224‧‧‧ Comparator

230‧‧‧Combined logic circuit

240‧‧‧Slope oscillator

250‧‧‧First comparator

260‧‧‧ Pulse width modulation generator

270‧‧‧ Output stage

272, 274‧‧‧ drive

276, 278‧‧‧N type MOS transistor

280‧‧‧Buck circuit

290‧‧‧Return circuit

292‧‧‧Error amplifier

GND‧‧‧ Grounding voltage

I _LOAD ‧‧‧Load current

S _DRIVE ‧‧‧ drive signal

S _PWM1 ‧‧‧ pulse width modulation signal

T _B ‧‧‧Transient boost voltage

V _ADJ ‧‧‧Adjustment signal

V _COMP ‧‧‧ error signal

V _DD ‧‧‧ input voltage

V _FB ‧‧‧Responsive voltage

V _OUT ‧‧‧ output voltage

V _RAMP ‧‧‧Ramp signal

V _RFF ‧‧‧reference voltage

V ₁ ‧‧‧first signal

Claims (20)

A DC-to-DC controller coupled to an output stage, the output stage receives an input voltage and provides an output voltage, the DC-DC controller includes: a transient boost circuit, generating a change according to the output voltage Adjusting a signal; a ramp oscillator; a combination logic circuit coupled to the transient boost circuit and the ramp oscillator, and providing a ramp signal according to the adjustment signal and the output of the ramp oscillator, wherein the adjustment signal Having a first logic level, the combination logic circuit adjusts the ramp signal to maintain the ramp signal at a first predetermined level for a first predetermined time, wherein the first preset level is lower than a first voltage comparator is coupled to the combination logic circuit, and generates a first signal according to the error signal and the ramp signal; and a pulse width modulation generator coupled The first comparator generates a pulse width modulation signal according to the first signal to control the operation of the output stage. The DC-to-DC controller of claim 1, wherein the transient boosting circuit comprises: a compensation adjusting circuit, receiving the output voltage to generate a transient boosting voltage, wherein the transient boosting The voltage-type voltage has a voltage compensation corresponding to the steady state of the output voltage; and a second comparator compares the output voltage and the transient boost voltage to generate the adjustment signal. The DC-to-DC controller of claim 2, wherein the adjustment signal has the first logic when the transient boost voltage is higher than the output voltage The level is determined, and when the transient boost voltage is lower than the output voltage, the adjustment signal has a second logic level. The DC-to-DC controller of claim 3, wherein when the adjustment signal has the second logic level, the combination logic circuit maintains the ramp signal to cause the ramp signal provided by the ramp oscillator Provided to the first comparator. The DC-DC controller of claim 2, wherein the compensation adjustment circuit comprises: a first capacitor coupled to the first input of the second comparator for maintaining the transient boost a current source coupled to the first input of the second comparator for generating a current; and a resistor coupled between the first input and the second input of the second comparator Used to generate this voltage compensation. The DC-to-DC controller of claim 5, wherein the impedance of the resistor is multiplied by the current to generate the voltage compensation. The DC-to-DC controller of claim 1, wherein the transient boosting circuit comprises: a second capacitor for maintaining a transient boosting voltage; and a third comparator having a first input end coupled to the output voltage and a second input end coupled to the second capacitor, and having a compensation voltage sourced between the first input end and the second input end of the third comparator The three comparators compare the output voltage with the transient boost voltage to generate the adjustment signal. For example, the DC-to-DC controller described in claim 7 of the patent scope, wherein When the transient boost voltage is higher than the output voltage, the adjustment signal has the first logic level, and when the transient boost voltage is lower than the output voltage, the adjustment signal has a second logic bit. quasi. A DC-to-DC control method for enabling an output stage to provide an output voltage after receiving an input voltage, the DC-DC control method comprising: generating an adjustment signal according to the variation of the output voltage; The output of the ramp oscillator provides a ramp signal; when the adjustment signal has a first logic level, the ramp signal is maintained at a first preset level for a first predetermined time, wherein the first preset bit a level lower than an error signal associated with the output voltage; generating a first signal according to the error signal and the ramp signal; and generating a pulse width modulation signal according to the first signal to control the output stage operating. The DC-DC control method of claim 9, wherein the step of generating the adjustment signal according to the variation of the output voltage further comprises: receiving the output voltage to generate a transient boost voltage, wherein the transient state The boost voltage has a voltage compensation corresponding to the steady state of the output voltage; and the output voltage and the transient boost voltage are compared to generate the adjustment signal. The DC-to-DC control method of claim 10, wherein when the transient boost voltage is higher than the output voltage, the adjustment signal has the first logic level, and when the transient boost If the voltage is lower than the output voltage, the adjustment signal has a second logic level. The DC to DC control method of claim 11, wherein the ramp signal is maintained and output when the adjustment signal has the second logic level. A DC-to-DC controller coupled to an output stage, the output stage receives an input voltage and provides an output voltage, the DC-DC controller includes: a transient boost circuit, generating a change according to the output voltage An adjustment signal having a logic level; a ramp oscillator; a combination logic circuit coupled to the transient boost circuit and the ramp oscillator, and providing a ramp signal according to the adjustment signal and the output of the ramp oscillator, The combination logic circuit adjusts the ramp signal level according to a logic level of the adjustment signal, wherein when the adjustment signal has the first logic level, the combination logic circuit adjusts the ramp signal to maintain at a first preset time The ramp signal is at a first preset level, wherein the first preset level is lower than a level of an error signal associated with the output voltage; a first comparator coupled to the combinational logic circuit, and The error signal and the ramp signal generate a first signal; and a pulse width modulation generator coupled to the first comparator to generate a pulse width modulation according to the first signal Number, to control the operation of the output stage. The DC-to-DC controller of claim 13, wherein the transient boosting circuit comprises: a compensation adjusting circuit, receiving the output voltage to generate a transient boosting voltage, wherein the transient boosting The voltage-type voltage has a voltage compensation corresponding to the steady state of the output voltage; and a second comparator compares the output voltage and the transient boost voltage to generate the adjustment signal. For example, the DC-to-DC controller described in claim 14 of the patent scope, wherein When the transient boost voltage is higher than the output voltage, the adjustment signal has the first logic level, and when the transient boost voltage is lower than the output voltage, the adjustment signal has a second logic Level. The DC-to-DC controller of claim 15, wherein the combination logic circuit outputs the ramp signal of the ramp oscillator when the adjustment signal has the second logic level. A DC-to-DC control method for enabling an output stage to provide an output voltage after receiving an input voltage, the DC-to-DC control method comprising: generating an adjustment signal according to the variation of the output voltage; and logic according to the adjustment signal a level and a ramp oscillator output to provide a ramp signal, wherein when the trim signal has a first logic level, the step of providing the ramp signal based on a logic level of the trim signal and an output of the ramp oscillator The method further includes: maintaining the ramp signal at a first preset level for a first preset time, wherein the first preset level is lower than a level of the error signal associated with the output voltage; according to the error signal Generating a first signal with the ramp signal; and generating a pulse width modulation signal based on the first signal to control operation of the output stage. The DC-DC control method of claim 17, wherein the step of generating the adjustment signal according to the variation of the output voltage further comprises: receiving the output voltage to generate a transient boost voltage, wherein the transient state The boost voltage has a voltage compensation corresponding to the steady state of the output voltage; and the output voltage and the transient boost voltage are compared to generate the adjustment signal. The DC-to-DC control method of claim 18, wherein when the transient boost voltage is higher than the output voltage, the adjustment signal has the first logic level, and when the transient boost If the voltage is lower than the output voltage, the adjustment signal has a second logic level. The DC to DC control method of claim 19, wherein when the adjustment signal has the second logic level, the step of comparing the output voltage and the transient boost voltage to generate the adjustment signal further comprises : Output the ramp signal.