M414763 本新型的另-目的在提供—種城式電源供應器之控制 電路。 為達上述之目的，就其中一個觀點言，本新型提供了一 種切換式電源供應器，包含：一功率級電路，包含至一個 功率電晶體Μ，藉由功率電晶體_的切換，而將輸入電 ，轉換為輸出電壓卜脈寬調變訊號產生器，根據該輸出電 查產生-脈寬調變訊號；-暫態升麼控制電路，根據該輸出 電壓及-賴升壓參考電壓而產生__調整訊號，其中於輸出電 壓低於健升縣考電叙朗，離訊齡於高鱗及低位 準間切換；-邏輯電路，與脈寬調變訊號產生器及暫態升壓 控制電路祕’以根據脈寬機峨和調整峨而產生一開 關訊號，藉此控制功率級電路中之功率電晶體開關。 就另-個觀齡，本新藤供了—種切換式電源供應器 之控制電路，_以控制—娜式電源供脑之輸出電壓， 包含：-補償產生n，接收該輸出電壓並產生—暫態升屢參考 電壓；-比較器’比較該輸出電壓及該暫態升壓式電壓以產生 -快速反雜號；以及-工俩触魏路，接_快速反應 訊號並產生-機訊號，其中當該輸出電壓低於該暫態升壓參 考電壓時，該調整訊號會於高位準及低位準間切換。 底下藉由具體實施例詳加說明，當更容易瞭解本新型之 目的、技術内容、特點及其所達成之功效。 【實施方式】· 本新型中的圖式均屬示意，主要意在表示各元件功能與各 元件間之訊號關係’至於尺寸、距離等則並未依照比例繪製。 請參閱第5圖，顯示一種切換式電源供應器的架構，亦 5 M414763 是本新型的一個實施例。切換式電源供應器50包含PW]V[訊 號產生器51、功率級52、回授電路53、誤差訊號產生電路 54、邏輯電路56、驅動電路57及暫態升壓控制電路58。回 授電路53可包括電阻器(參見圖6)，上述電阻器用來分壓輸出 電壓Vout，產生回授電壓FB。誤差訊號產生電路54根據回 授電壓FB以產生誤差訊號Comp，又PWM訊號產生器51則 根據誤差訊號Comp產生脈寬調變訊號。暫態升壓控制電路 58接收輸出電壓Vout，並根據輸出電壓Vout的變動產生調整 訊號QR一Max_Duty。邏輯電路56可為一邏輯閘(如或邏輯開 (OR gate；))，接收調整訊號QR_Max_Duty及PWM訊號，並產 生開關訊號SW。若調整訊號QR_Max_Duty與PWM訊號兩 者之一為高位準，則開關訊號SW為高位準。若上述兩者都為 低位準’則開關訊號為低位準。透過驅動電路57控制功率級 52中至少一個功率電晶體，以將輸入電壓vin轉換為輸出電 壓Vout。上述邏輯電路56和驅動電路57亦可以整合為一個電 路，並不受此實施例為限。此外，功率級52可為但不限於同 步或非同步之降壓型、升壓型、反壓型、或升降壓型功率轉換 電路’如第1〜4圖所示。 第6圖係本新型的一更詳細之實施例。回授電路53包含兩 串接電阻R1與R2 ’其中R1之一端與輸出電壓Vout耦接， R2之一端耦接至接地電位，回授訊號FB係擷取自電阻R2上 之分壓。誤差訊號產生電路54中誤差放大器541比較回授電 壓FB及參考電壓Vref，以產生誤差訊號c〇mp。補償電路542 可減緩誤差訊號Comp之變動(variation)，即當輸出電壓Vout 減少，則誤差信號Comp增加；當輸出電壓Vout增加，則誤 差訊號Comp減少。PWM訊號產生器51中PWM比較器512 6 會比較斜坡訊號產生器511輸出之斜坡信號Ramp及誤差訊號 Comp ’以產生PWM訊號。又斜坡訊號產生器511所產生的 鋸齒或三角訊號，可作為斜坡訊號Ramp。參見第7圖，當斜 坡訊號Ramp低於誤差訊號Comp，PWM訊號為高位準；但 當斜坡訊號Ramp高於誤差訊號Comp，PW1V[訊號為低位準。 暫態升壓控制電路58包括補償產生器（0ffset generator)58卜比較器582 (比較器582亦可以是運算放大器） 及工作週期控制電路583。補償產生器581接收輸出電壓 Vout ’並根據輸出電壓v〇ut而產生一暫態升壓參考電壓TB， 該電壓TB與輸出電壓Vout在穩態下具有對應的偏壓(offset) 關係’但電壓TB會延遲反應輸出電壓v〇ut之變化，亦即暫 態升壓參考電壓為相較低於輸出電塵Vout —偏壓值之延遲訊 號。詳言之’如第7圖所示，TB=Vout—V0FFSET，但該暫態升 壓參考電壓TB不會立即反應輸出電壓Vout之改變，會於一 定延遲時間後才進行補償，並採逐漸方式升高或降低位準。比 較器582於負輸入端接收輸出電壓Vout及正輸入端接收暫態 升壓參考電壓TB，比較該兩個電壓缘產生快速反應訊號QR。 參見第7圖，當負載59突然變大，輸出電壓v〇ut會立即低於 暫態升壓參考電壓TB，則該快速反應訊號qR由低電位改為 高電位。又當輸出電壓Vout高於暫態升壓參考電壓TB時， 則該快速反應訊號QR由南電位改回低電位。工作週期控制電 路583接受快速反應訊號qR並產生調整訊號 QR_Max_Duty，當快速反應訊號QR在高電位期間，調整訊 號QR_Max_Duty於高位準及低位準間迅速切換。圖中也顯 示，於輸出電壓Vout下降之期間，誤差訊號comp會升高， 使得PWM比較器512輸出之PWM訊號之工作比(dmy加叫 也提高。 邏輯電路56接收調整訊號QR_Max_Duty及PWM訊號， 並產生開關信號SW，若調整訊號QR_Max_Duty與PWM訊 號兩者之一為高位準’則開關訊號SW為高位準。若上述兩者 都為低位準，則開關訊號為低位準。驅動電路57接收邏輯電 路56所輸出之訊號，產生上橋電壓訊號UGATE及下橋電壓 訊號LGATE’用以對應導通功率電晶體521及522中之一者。 因此’當功率電晶體521被開啟(tum on)且功率電晶體522被 關閉(turn off)時’電流自輸入電壓vin端經過電感l流向輸出 電壓Vout端’以提升或維持輸出電壓v〇ut，並供應負載59所 需之足夠電壓。當功率電晶體521為不導通及功率電晶體522 為導通時，電感L之一端接地，經過電感l流向輸出電壓v〇ut 端之電流會逐漸變小，或甚至產生一反向電流。 根據本新型，由於在快速反應訊號QR由低電位改為高電 位，表不需要進行快速反應的期間，調整訊號QR_Max_Duty 在尚低位準之間轉換，使功率電晶體521不保持為恆開狀態， 故可避免功率電晶體被損害之問題，且仍能快速提升已突降之 輸出電壓Vout至指定之高位準。 第8〜10圖示出本新型之工作週期控制電路的多個實施 例，這些實施例中的電路均可用來作為第6圖實施例中的工作 週期控制電路583。但本新型之工作週期控制電路不受此等實 施例之限制’只要能將上述快速反應訊號QR中一連續處於高 位準之方波’魏為於高位準及低位賴迅速切換之多個脈衝 _Se)或錢之婦碱QR_伽—_，刺縣創作 之範圍。 如第8圖所示，其中一個實施例甲，工作週期控制電路 80包含高位準決定電路81、低位準 其中該高位準決定電㈣決定高位準輸閉83， 低位準轉為高位準時，則第 j 4迷反應訊號QR由 位準，此時第-電日俨81h。 輪出由高位準轉為低 平此W電日日體812就被關閉，且第 續對第-電容814充電。節勒Δ & 電冰/原813就持 815，由第1 的訊號會經過磁滞間電路 815由第一反向益816輪出至及閘83。當節點M414763 Another object of the present invention is to provide a control circuit for a city-type power supply. In order to achieve the above objectives, the present invention provides a switched power supply comprising: a power stage circuit comprising a power transistor Μ, which is input by switching of the power transistor _ Electric, converted into an output voltage pulse width modulation signal generator, according to the output of the electrical detection - pulse width modulation signal; - transient rise control circuit, according to the output voltage and - boost reference voltage generated _ _Adjust the signal, in which the output voltage is lower than that of Jiansheng County, which is switched from high-scale and low-level; - logic circuit, pulse width modulation signal generator and transient boost control circuit 'To generate a switching signal according to the pulse width and 峨, thereby controlling the power transistor switch in the power stage circuit. In another age, this new vine provides a control circuit for the switching power supply, _ to control - Na power supply for the brain's output voltage, including: - compensation to generate n, receive the output voltage and generate - temporarily The state rises the reference voltage; the comparator compares the output voltage with the transient boost voltage to generate a fast fast miscellaneous number; and the - worker touches the Wei road, receives the _ fast response signal and generates a -machine signal, wherein When the output voltage is lower than the transient boost reference voltage, the adjustment signal switches between a high level and a low level. The details, technical contents, features and effects achieved by the present invention are more readily understood by the detailed description of the specific embodiments. [Embodiment] The drawings in the present invention are schematic and are mainly intended to indicate the relationship between the function of each element and the signal between the elements. As for the size, distance, etc., it is not drawn to scale. Please refer to Figure 5, which shows the architecture of a switched power supply. Also, 5 M414763 is an embodiment of the present invention. The switching power supply 50 includes PW]V [signal generator 51, power stage 52, feedback circuit 53, error signal generating circuit 54, logic circuit 56, drive circuit 57, and transient boost control circuit 58. The feedback circuit 53 may include a resistor (see Fig. 6) for dividing the output voltage Vout to generate a feedback voltage FB. The error signal generating circuit 54 generates the error signal Comp according to the feedback voltage FB, and the PWM signal generator 51 generates the pulse width modulation signal according to the error signal Comp. The transient boost control circuit 58 receives the output voltage Vout and generates an adjustment signal QR_Max_Duty according to the variation of the output voltage Vout. The logic circuit 56 can be a logic gate (such as OR OR gate), receive the adjustment signal QR_Max_Duty and the PWM signal, and generate the switching signal SW. If one of the adjustment signals QR_Max_Duty and the PWM signal is at a high level, the switching signal SW is at a high level. If both of the above are low level, the switching signal is low. At least one power transistor in power stage 52 is controlled by drive circuit 57 to convert input voltage vin to output voltage Vout. The above logic circuit 56 and drive circuit 57 can also be integrated into one circuit, and are not limited to this embodiment. In addition, the power stage 52 can be, but is not limited to, a synchronous or non-synchronous buck, boost, back-pressure, or buck-boost power conversion circuit as shown in Figures 1 through 4. Figure 6 is a more detailed embodiment of the present invention. The feedback circuit 53 includes two series resistors R1 and R2', wherein one end of R1 is coupled to the output voltage Vout, one end of R2 is coupled to the ground potential, and the feedback signal FB is taken from the divided voltage on the resistor R2. The error amplifier 541 in the error signal generating circuit 54 compares the feedback voltage FB with the reference voltage Vref to generate an error signal c 〇 mp. The compensation circuit 542 can reduce the variation of the error signal Comp, that is, when the output voltage Vout decreases, the error signal Comp increases; when the output voltage Vout increases, the error signal Comp decreases. The PWM comparator 512 6 of the PWM signal generator 51 compares the ramp signal Ramp and the error signal Comp ' output by the ramp signal generator 511 to generate a PWM signal. The sawtooth or triangle signal generated by the ramp signal generator 511 can also be used as the ramp signal Ramp. Referring to Figure 7, when the ramp signal Ramp is lower than the error signal Comp, the PWM signal is at a high level; but when the ramp signal Ramp is higher than the error signal Comp, the PW1V [signal is a low level. The transient boost control circuit 58 includes a compensation generator 58 comparator 582 (the comparator 582 can also be an operational amplifier) and a duty cycle control circuit 583. The compensation generator 581 receives the output voltage Vout' and generates a transient boost reference voltage TB according to the output voltage v〇ut. The voltage TB has a corresponding offset relationship with the output voltage Vout at steady state. TB delays the change of the response output voltage v〇ut, that is, the transient boost reference voltage is a delay signal that is lower than the output dust Vout-bias value. In detail, as shown in Figure 7, TB = Vout - V0FFSET, but the transient boost reference voltage TB will not immediately reflect the change of the output voltage Vout, will be compensated after a certain delay time, and adopt a gradual approach. Raise or lower the level. The comparator 582 receives the output voltage Vout at the negative input terminal and the transient boost reference voltage TB at the positive input terminal, and compares the two voltage edges to generate a fast response signal QR. Referring to Fig. 7, when the load 59 suddenly becomes large and the output voltage v〇ut is immediately lower than the transient boost reference voltage TB, the fast response signal qR is changed from a low potential to a high potential. When the output voltage Vout is higher than the transient boost reference voltage TB, the fast response signal QR is changed from the south potential to the low potential. The duty cycle control circuit 583 receives the fast response signal qR and generates an adjustment signal QR_Max_Duty. When the fast response signal QR is at a high potential, the adjustment signal QR_Max_Duty is quickly switched between the high level and the low level. The figure also shows that during the falling of the output voltage Vout, the error signal comp will rise, so that the duty ratio of the PWM signal output by the PWM comparator 512 (the dmy call is also increased. The logic circuit 56 receives the adjustment signal QR_Max_Duty and the PWM signal, And the switching signal SW is generated. If one of the adjustment signal QR_Max_Duty and the PWM signal is high level, the switching signal SW is at a high level. If both of the signals are low, the switching signal is low. The driving circuit 57 receives the logic. The signal output by the circuit 56 generates an upper bridge voltage signal UGATE and a lower bridge voltage signal LGATE' for corresponding one of the conduction power transistors 521 and 522. Therefore, when the power transistor 521 is turned on and power When the transistor 522 is turned off, 'current flows from the input voltage vin terminal through the inductor 1 to the output voltage Vout terminal' to boost or maintain the output voltage v〇ut and supply a sufficient voltage for the load 59. When the power transistor When 521 is non-conducting and power transistor 522 is turned on, one end of inductor L is grounded, and the current flowing through inductor 1 to the output voltage v〇ut terminal is gradually reduced, or even produced. According to the present invention, since the fast response signal QR is changed from a low potential to a high potential, and the watch does not need to perform a rapid reaction, the adjustment signal QR_Max_Duty is switched between the low level, so that the power transistor 521 is not maintained. In the constant-on state, the problem of damage to the power transistor can be avoided, and the output voltage Vout that has been suddenly dropped can be quickly increased to a specified high level. Figures 8 to 10 show the multi-function duty cycle control circuit of the present invention. In one embodiment, the circuits in these embodiments can be used as the duty cycle control circuit 583 in the embodiment of Fig. 6. However, the duty cycle control circuit of the present invention is not limited by these embodiments as long as the above rapid response can be achieved. In the signal QR, a continuous wave of high-level square wave 'Wei is at the high level and low position is quickly switching between multiple pulses _Se) or Qian's gynecology QR_ gamma-_, the scope of the creation of the thorn county. As shown in FIG. 8, in one embodiment A, the duty cycle control circuit 80 includes a high level determining circuit 81, a low level, wherein the high level determines the power (4) determines the high level shift 83, and the low level shifts to the high level, then The j 4 response signal QR is leveled, and the first electric day is 81h. The turn-off is turned from the high level to the low level. The W-day day 812 is turned off, and the first capacitor 814 is continuously charged. The Δ & electric ice/original 813 holds 815, and the first signal passes through the interstitial circuit 815 and is rotated from the first reverse benefit 816 to the gate 83. When the node
=(:了—電容814被充電而未達-設定高電二G 一反向斋816亦持續輸出—高電位。於第—電容81 點A尚未到達高電位之時間 充電仁即= (: - Capacitor 814 is charged but not reached - set high power 2 G - reverse fast 816 also continues to output - high potential. At the first - capacitor 81 point A has not reached the high potential time
« ^ ^ ^ 及閘83因快速反應訊號QR 〇R 〇 ^ ^均為高電位而其輸出調整訊號 QR^ax_Duty轉於高電位，對應於第7财的Tqn期間。 ίΐΓ電容814被充電達到設定高電位時，則節點A亦被 =為處於南電位，因此第二反向器816輸出會由原先高電位轉 為低電位，同時及間83之輸出（訊號QR—Max_Duty)亦轉為 低電位。 當第二反向器816輸出會由原先高電位轉為低電位時， 第-電晶體822就被關閉’且第二電流源82 i就持續對第二電 谷823充電。當節點B升至—高電位(即第二電容823被充電 至-設定高電位)時，第三電晶體824會被開啟，則節點A藉 由該第二電晶體821接地而轉為低電位，此時調整訊號 QR_Max一Duty又回到高電位。於第二電容823充電但節點B 尚未升至高電位之時間内，及閘83因第二反向器816之輸出 為低電位而其輸出調整訊號QR—Max_Duty短暫地維持於低電 位，對應於第7圖中的Toff期間。 如第9圖所示，另一個實施例中，工作週期控制電路9〇 M414763 準決定電路91及低辦決定電路92，其愤高位準 ―、疋91決定高位準輸出之時間，又低位準決定電路92決 輸出之時間。D型正反器912與921之初始狀態均為 =及2-1。因此，第一電晶體914會被泛開啟，而第 、极源913之電流藉由第一電晶體914流至地端，如此節點£ 之位準亦為G，此時向器916之輸出為卜亦即，第一 D 3正反器912之^j亦會為卜因第二D型正反器921 的2-卜所以第二電晶體923被導通及節點F處於低電位， 此8^反向！| 925輸出為高電位，因此第二〇型正反器奶 的。當快速反應訊號qR由〇轉變為^時，第一電晶 體912的CLK(即及的輸出)為卜其Q轉為i(因為其d 之輸入VDD=1)及其泛轉為〇，域第一電晶體914會被泛關 閉，且第一電流源913就持續對第一電容915充電。當節點£ 尚未升至-高電位(即第-電容91S被充電而未達一設定高電 位)時，則第一反向器916亦持續輸出一高電位。於第一電容 915充電而節點E尚未升至高電位之時間内，調整訊號 QR一Max一Duty會維持於高電位，對應於第7圖中的t〇n期間。 但當第一電容915被充電達到設定高電位時 為已處於高電位，因此第一反向器916輸出會 為低電位，同時調整訊號QR_Max—Duty亦轉為低電位。 當調整訊號QR_Max_Duty轉為低電位時，第一 D型正反 器912之β就轉為1，同時第二D型正反器921之clk轉變 為1 (高位準）’使其Q=1及泛=0。此時，第二電晶體923就 被關閉，且第二電流源922就持續對第二電容924充電。當節 點F尚未升至一高電位(即第二電容924被充電至一設定高電 位)時，則第二反向器925亦持續輸出一高電位而使彳$^^ ^但§即點F升至一高電位時，第二反向器9« ^ ^ ^ and gate 83 due to the fast response signal QR 〇R 〇 ^ ^ are high potential and its output adjustment signal QR^ax_Duty turns to high potential, corresponding to the Tqn period of the seventh. When the capacitor 814 is charged to the set high level, the node A is also = at the south potential, so the output of the second inverter 816 will be changed from the original high potential to the low potential, and the output of the 83 (signal QR - Max_Duty) also goes low. When the output of the second inverter 816 is turned from the previous high level to the low level, the first transistor 822 is turned off' and the second current source 82 i continues to charge the second valley 823. When the node B rises to a high potential (ie, the second capacitor 823 is charged to - set a high potential), the third transistor 824 is turned on, and the node A is turned to a low potential by the second transistor 821 being grounded. At this time, the adjustment signal QR_Max-Duty returns to high potential. During the time when the second capacitor 823 is charged but the node B has not risen to the high level, and the gate 83 is low due to the output of the second inverter 816, the output adjustment signal QR_Max_Duty is temporarily maintained at a low potential, corresponding to the 7 during the Toff period. As shown in FIG. 9, in another embodiment, the duty cycle control circuit 9 〇 M414763 quasi-determination circuit 91 and low-decision decision circuit 92, the anger level is high, 疋91 determines the time of the high level output, and the low level is determined. Circuit 92 determines the time of the output. The initial states of the D-type flip-flops 912 and 921 are both = and 2-1. Therefore, the first transistor 914 is turned on, and the current of the first source 913 flows to the ground through the first transistor 914, so that the position of the node is also G, and the output of the transmitter 916 is That is, the first D 3 flip-flop 912 will also be the second of the second D-type flip-flop 921, so that the second transistor 923 is turned on and the node F is at a low potential, this 8^ Reverse! The 925 output is high, so the second type of flip-flop milk. When the fast response signal qR is changed from 〇 to ^, the CLK of the first transistor 912 (ie, the output of the sum) is changed from Q to i (because its input of VDD is VDD=1) and its overturn is 〇, domain The first transistor 914 is turned off and the first current source 913 continues to charge the first capacitor 915. When the node £ has not yet risen to a high potential (i.e., the first capacitor 91S is charged and does not reach a set high potential), the first inverter 916 also continues to output a high potential. During the time when the first capacitor 915 is charged and the node E has not yet risen to a high level, the adjustment signal QR-Max-Duty is maintained at a high potential, corresponding to the period tnn in FIG. However, when the first capacitor 915 is charged to the set high level, it is already at a high potential, so the output of the first inverter 916 will be low, and the adjustment signal QR_Max_Duty also goes low. When the adjustment signal QR_Max_Duty is turned to a low potential, the β of the first D-type flip-flop 912 is turned to 1, and the clk of the second D-type flip-flop 921 is changed to 1 (high level) to make Q=1 and Pan=0. At this point, the second transistor 923 is turned off and the second current source 922 continues to charge the second capacitor 924. When the node F has not risen to a high potential (ie, the second capacitor 924 is charged to a set high level), the second inverter 925 also continues to output a high potential to make 彳$^^^ but § point F When rising to a high potential, the second inverter 9
Qn , m 此第一 D型正反器921之ρ轉為1，此時及 决速反應訊號QR及第二D型正反器921之g均 雷位而輪出改為卜於第二電容924充電而節點f尚未升至= 之時間内’調整訊號qR—Μ狀短地; 位’對應於第7㈣的TGFF_。 、低電 如第1〇圖所示，另一個實施例中，工作週期控制電路100 ^含高位準決定電路1a (包括第-NMQS電晶體1U、第二 讀〇S電晶體112和第一電流源113)、低位準決定電路化 (包括第-PMOS電晶體12卜第二電流源122和第：pM〇s 電b曰體123)、電容ld、磁滯閘電路le和及閘。，其中該高 位準決定電路ia蚊高鱗触之_，又餘準決定電ς lb決定低位準輸出之_。陳速反應訊號QR之初始狀態 為低電位，所以訊號QR—Max_Duty之初始狀態為低電位，因 此初始狀態下第二；PMOS電晶體123開啟，第二NMOS電晶 f 112關閉，第- PM0S電晶體121與第二電流源122對電 容Μ充電，故節點G已位於高電位，亦即磁滯閘電路&之 輸出已位於高電位。當快速反應訊號QR由低位準轉為高位準 時，及閘lc輸出之調整訊號qr—Max一Duty亦轉為高位準， 則第一 PMOS電晶體121與第二PM0S電晶體123 一同被關 閉，且第一 NMOS電晶體ill與第二丽08電晶體112 一同 被開啟，已充電至高電位之電容Id會經由第一 電晶體 111、第一NMOS電晶體112與第一電流源113放電至地端。 當節點G電位因電容Id被逐漸放電至低於一預定電位，磁滯 閘電路le之輸出會轉為低電位，從而及閘ic輸出之調整訊號 QR_Max一Duty亦轉為低電位；電容id自高電位被放電至低於 該預定電位的期間，對應於第7圖中的ΤΟΝ期間。訊號 QR—Max一Duty轉為低電位時，第二pM〇s電晶體123被開啟， 及第二NMOS電晶體U2被關閉，因此第二電流源122會供 應電流至電容ld ’當節點G電位高於·定電位，磁滞開電 路le之輸出會轉為高電位，從而及閘化輸出之調整訊號 QR_Max一Duty亦轉為高電位。亦即，電容u充電但節點^ 電位尚未綠該默電位之時_，触峨QR—吻 短暫地維持於低電位，對應於第7财的恤_。一 以上已針對較佳實施例來說明本新型，唯以上所述者， 僅係為使熟悉本技術者易於了解本新型㈣容而已，並非用 來限定本_之_細。在本新型之侧精神下，孰采本 技術者可以思及各種等效變化。例如，實施例中之磁滯問電 路可以移除’或是轉衝電路取代。前述各元件輸出之電位 定義^此實施例為限，應視輸出訊號賦予之意義而定，亦 即’南低電位所代表的意義可以互換，僅需適當地對應改變 電路設計即可。再如，各實施例中圖示直接連接的兩電路或 讀間，可插置不影響主要功能的其他電路或元件。因此， 本新型的範圍應涵蓋上述及其他所有等效變化。 【圖式簡單說明】 第1圖至第4圖分別示出先前技術之降壓型、升壓型、反壓型、 及升降壓型電源供應電路。 第5圖示出本新型切換式電源供應器的一實施例。 第6圖示出本新型切換式電源供應器的-詳細實施例。 第7圖示出本新型切換式電源供應器中訊號的波形圖。 第8〜10圖不出本新型之工作週期控制電路的多個實施例。 M414763Qn , m The ρ of the first D-type flip-flop 921 is turned to 1, and the g-return signal QR and the second D-type flip-flop 921 are both turned and replaced by the second capacitor. 924 is charged and node f has not risen to = time 'adjustment signal qR-Μ short; place' corresponds to TGFF_ of 7th (fourth). As shown in FIG. 1 , in another embodiment, the duty cycle control circuit 100 includes a high level determining circuit 1a (including a first-NMQS transistor 1U, a second read 〇S transistor 112, and a first current). The source 113) and the low level determine the circuitization (including the first PMOS transistor 12 and the second current source 122 and the :pM〇s electrical b body 123), the capacitor ld, the hysteresis gate circuit le and the gate. Among them, the high level determines the circuit ia mosquitoes to touch the scalp, and the balance determines the power ς lb determines the low level output _. The initial state of the Chen speed response signal QR is low, so the initial state of the signal QR_Max_Duty is low, so the second state in the initial state; the PMOS transistor 123 is turned on, the second NMOS transistor f 112 is turned off, and the -PM0S is turned off. The crystal 121 and the second current source 122 charge the capacitor ,, so the node G is already at a high potential, that is, the output of the hysteresis gate & is already at a high potential. When the fast response signal QR is changed from the low level to the high level, and the adjustment signal qr_Max_Duty of the gate lc output is also turned to the high level, the first PMOS transistor 121 is turned off together with the second PMOS transistor 123, and The first NMOS transistor ill is turned on together with the second NMOS transistor 112, and the capacitor Id that has been charged to a high potential is discharged to the ground via the first transistor 111, the first NMOS transistor 112, and the first current source 113. When the potential of the node G is gradually discharged to a predetermined potential due to the capacitance Id, the output of the hysteresis gate circuit le will be turned to a low potential, and the adjustment signal QR_Max-Duty of the gate ic output also turns to a low potential; The period during which the high potential is discharged below the predetermined potential corresponds to the chirp period in FIG. When the signal QR-Max-Duty turns to a low potential, the second pM〇s transistor 123 is turned on, and the second NMOS transistor U2 is turned off, so the second current source 122 supplies current to the capacitor ld' when the node G potential Above the constant potential, the output of the hysteresis circuit will turn to a high potential, and the adjustment signal QR_Max-Duty of the sluice output also turns to a high potential. That is, when the capacitor u is charged but the node ^ potential is not yet green, the moment _, the touch QR-kiss is temporarily maintained at a low level, corresponding to the shirt of the seventh money. The above description has been made with respect to the preferred embodiments, and the above description is only for making the present invention easy to understand the present invention, and is not intended to limit the scope of the present invention. Under the spirit of this new type, the skilled person can think of various equivalent changes. For example, the hysteresis circuit in the embodiment can be removed or replaced by a bypass circuit. The potential definition of the output of each of the above components is limited to the meaning of the embodiment, and the meaning represented by the output signal can be interchanged, that is, the meaning represented by the south low potential can be interchanged, and only the circuit design needs to be appropriately changed. As another example, the two circuits or inter-reads that are directly connected in the various embodiments illustrate other circuits or components that do not affect the primary function. Therefore, the scope of the novel should cover the above and all other equivalent variations. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 to 4 show a prior art step-down, step-up, back-pressure, and buck-boost power supply circuits, respectively. Fig. 5 shows an embodiment of the switching power supply of the present invention. Figure 6 shows a detailed embodiment of the novel switched power supply. Fig. 7 is a waveform diagram showing signals in the switching power supply of the present invention. Figures 8 through 10 illustrate various embodiments of the novel duty cycle control circuit. M414763
【主要元件符號說明】 1降壓型電源供應電路 2升壓型電源供應電路 3反壓型電源供應電路 4升降壓型電源供應電路 10控制電路 100工作週期控制電路 111第一 NMOS電晶體 112第二NMOS電晶體 113第一電流源 121第一 PMOS電晶體 122第二電流源 123第二PMOS電晶體 la高位準決定電路 lb低位準決定電路 lc及閘 Id電容 le磁滯閘電路 50切換式電源供應器 51 PWM訊號產生器 511斜坡訊號產生器 512PWM比較器 52功率級 521、522功率電晶體 53回授電路 54誤差訊號產生電路 541誤差放大器 542補償電路 56邏輯電路 57驅動電路 58暫態升壓控制電路 581補償產生器 582比較器 583工作週期控制電路 59負載 80工作週期控制電路 81高位準決定電路 811第一反向器 812第一電晶體 813第一電流源 814第一電容 815磁滞閘電路 816第二反向器 82低位準決定電路 821第二電流源 822第二電晶體 823第二電容 824第三電晶體 83及閘 90工作週期控制電路 91高位準決定電路 13 M414763 911及閘 Q1，Q2功率電晶體 912第一 D型正反器 Rl、R2電阻 913第一電流源 FB回授電壓 914第一電晶體 QR快速反應訊號 915第一電容 SW開關訊號 916第一反向器 TB暫態升壓參考電壓 92低位準決定電路 Vin輸入電壓 921第二D型正反器 Vout輸出電壓 922第二電流源 Vref參考電壓 923第二電晶體 924第二電容 925第二反向器 Ramp斜坡訊號 Comp誤差訊號 LGATE下橋電壓訊號 A、B、E〜G節點 UGATE上橋電壓訊號 L電感 QR_Max_Duty調整訊號 14[Main component symbol description] 1 step-down power supply circuit 2 step-up power supply circuit 3 reverse voltage type power supply circuit 4 buck-boost type power supply circuit 10 control circuit 100 duty cycle control circuit 111 first NMOS transistor 112 Two NMOS transistor 113 first current source 121 first PMOS transistor 122 second current source 123 second PMOS transistor la high level determining circuit lb low level determining circuit lc and gate Id capacitor le hysteresis gate circuit 50 switching power supply Provider 51 PWM signal generator 511 ramp signal generator 512 PWM comparator 52 power stage 521, 522 power transistor 53 feedback circuit 54 error signal generation circuit 541 error amplifier 542 compensation circuit 56 logic circuit 57 drive circuit 58 transient boost Control circuit 581 compensation generator 582 comparator 583 duty cycle control circuit 59 load 80 duty cycle control circuit 81 high level decision circuit 811 first inverter 812 first transistor 813 first current source 814 first capacitor 815 hysteresis gate Circuit 816 second inverter 82 low level decision circuit 821 second current source 822 second transistor 823 second capacitor 824 third transistor 83 Gate 90 duty cycle control circuit 91 high level decision circuit 13 M414763 911 and gate Q1, Q2 power transistor 912 first D type flip-flop Rl, R2 resistor 913 first current source FB feedback voltage 914 first transistor QR Fast response signal 915 first capacitor SW switch signal 916 first inverter TB transient boost reference voltage 92 low level decision circuit Vin input voltage 921 second D-type flip-flop Vout output voltage 922 second current source Vref reference voltage 923 second transistor 924 second capacitor 925 second inverter Ramp ramp signal Comp error signal LGATE lower bridge voltage signal A, B, E ~ G node UGATE upper bridge voltage signal L inductance QR_Max_Duty adjustment signal 14