TW201426958A - Stacked package device and manufacturing method thereof - Google Patents

Abstract

This invention provides a stacked package device. The stacked package structure includes a substrate, a stacked structure and at least one conductive band. The stacked structure is disposed on the substrate. The stacked structure has a top surface and a plurality of sidewalls. The stacked structure includes a plurality of conductive pattern layers, wherein the conductive bands connected to some of the conductive pattern layers.

Description

Stacked package and manufacturing method thereof

The present invention relates to a stacked package, and more particularly to a stacked package having conductive traces.

The structure of the current semiconductor component stacked package includes Die Stacking and Package Stacking. In order to improve the line density of the entire semiconductor component and reduce the package size, the semiconductor component stacked package is generally used. Integration of three-dimensional vertical stacking (VIC).

Regarding the existing three-dimensional vertical stacking method, a common wafer stacking structure is to use a through-silicon via (TSV) semiconductor process technology to form vias on each die or wafer, and then conductive materials. The vias are filled in to form internal vertical conductive traces, and finally the wafers are stacked and bonded. In addition, in package stacking, solder balls or tin pillars are usually used as internal conductive lines between the layers of the circuit boards, and each layer of the circuit board is provided with a plurality of electronic components, and then the sealing is performed. Made into a package structure.

In general, in a turn-on stacked package, the conductive traces of the semiconductor elements of each layer are located inside the stacked package. With the thinning and thinning of the stacked packages, the design of the conductive lines is becoming more dense and complicated, so that the package structure and the manufacturing method of the stacked packages tend to be complicated, and the manufacturing difficulty is also improved.

Embodiments of the present invention provide a stacked package having a guide The electrical tape can be electrically connected to different semiconductor components.

Embodiments of the present invention provide a stacked package including a substrate, a stacked structure, and at least one conductive strip. The stacked structure is located on the substrate, the stacked structure has a top surface and a multi-faceted sidewall, and the stacked structure comprises a plurality of conductive pattern layers, wherein the sidewalls expose the conductive pattern layer. The conductive strip is disposed on the sidewall, and the conductive strip is electrically connected to at least two conductive pattern layers therein.

Embodiments of the present invention provide a method of fabricating a stacked package to improve the existing process for electrically connecting the stacked packages.

Embodiments of the present invention provide a method of fabricating a stacked package, the method of manufacturing the stacked package including forming a stacked structure on a substrate, the stacked structure having a top surface and a multi-sided sidewall, and the stacked structure includes a plurality of conductive layers a pattern layer in which the sidewalls expose a conductive pattern layer. The stacked structure is patterned to form at least one conductive strip, wherein the conductive strip is on the sidewall and connects at least two of the conductive pattern layers therein.

In summary, the stacked package has a conductive strip, and the length, the number, and the distribution position of the conductive strip are changed, so that the conductive strip can be electrically connected as a stacked structure, thereby simplifying the package structure and the manufacturing method thereof. Since the conductive strips are disposed on the sidewalls of the stacked structure and are connected to at least two conductive pattern layers exposed by the sidewalls, the semiconductor elements are electrically connected to each other through the conductive strips, thereby simplifying the process structure of the package.

The detailed description of the present invention and the accompanying drawings are to be understood by the claims The scope is subject to any restrictions.

Some illustrative embodiments are shown in the accompanying drawings and will be referred to hereinafter The drawings are to more fully describe the various exemplary embodiments. It should be noted that the inventive concept may be embodied in many different forms and should not be construed as being limited to the illustrative embodiments set forth herein. In particular, the present invention is to be construed as being illustrative and not restrictive. In each of the figures, the size and relative sizes of the layers and regions may be exaggerated for clarity and clarity, and like numerals indicate similar elements.

Although the terms first, second, third, etc. may be used herein to describe various elements, such elements are not limited by the terms. The terms are used to distinguish one element from another, and thus the first element discussed below may be referred to as a second element without departing from the teachings of the inventive concept. In addition, the term "and/or" may be used herein to indicate that it includes all of the associated listed items and all combinations of one or more.

The stacked package of the present invention may be a package structure applied to a semiconductor element. The stacked package uses the conductive strips on the sidewalls as electrical connections between the semiconductor components to simplify the process structure and method flow of the package. The stacked package of the present invention includes various embodiments, and the stacked structure of the stacked package of one embodiment of the present invention may be a plurality of wafers or a plurality of circuit board assemblies exhibiting a three-dimensional stacked arrangement. The above stacked package will be described below with reference to FIGS. 1A to 2 .

1A is a top plan view of a stacked package according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along line P-P of FIG. 1A. Referring to FIGS. 1A and 1B , the stacked package 100 includes a substrate 110 , a stacked structure 120 , and a conductive strip 130 . The stack structure 120 is disposed above the substrate 110. The conductive strips 130 are disposed on the sidewalls 124 of the stack structure 120. The semiconductor strips 122 of the different layers of the stack structure 120 are electrically connected through the distribution of the conductive strips 130.

The stack structure 120 is disposed on the substrate 110. In practice, the substrate 110 can be used as a carrier for the circuit and the electronic component, that is, a wafer carrier or a circuit substrate on which the chip/electronic component is not disposed. A pad (pad) and a trace are disposed on the substrate 110, and the material of the substrate 110 is usually an epoxy resin, a Cyanate ester core (CE core), or a double-butadiene. Material such as Bismaleimide core (BMI core). However, the present invention does not limit the material of the substrate 110.

The stacked structure 120 has a top surface 122 and a multi-sided sidewall 124. Each side wall 124 is coupled to the top surface 122 and surrounds the top surface 122. Further, in this embodiment, the number of the side walls 124 is four sides, however, the present invention does not limit the number of side walls.

The stacked structure 120 includes a plurality of conductive pattern layers 126 and a plurality of semiconductor elements 128a, 128b, 128c, and 128d. The conductive pattern layer 126 is on the semiconductor elements 128a, 128b, 128c, and 128d, and the semiconductor elements 128a, 128b, 128c, and 128d are stacked on each other. In detail, the semiconductor elements 128a, 128b, 128c, and 128d each have a first surface S1 and a second surface S2 opposite to the first surface S1, and each of the conductive pattern layers 126 is disposed on the first surface of each of the semiconductor elements 128, respectively. S1 is formed to form a circuit layer. The first surface S1 is located below the second surface S2 of the other semiconductor component 128. For example, the first surface S1 of the semiconductor component 128b is located below the second surface of the semiconductor component 128a. However, the conductive pattern layer 126 may also be disposed on the first surface S1 and/or the second surface S2, and the invention is not limited thereto.

It should be noted that the conductive pattern layer 126 is a redistribution layer (RDL) for reconfiguring the wiring disposed on the semiconductor element 128 at the edge of the semiconductor element 128. Conductive pattern The layer 126 includes a first pattern layer P1 and a second pattern layer P2, the first pattern layer P1 is a pad, and the second pattern layer P2 is a trace, wherein the second pattern layer P2 and the first pattern layer P1 Connected. Accordingly, an electrical signal can be input to and output from the semiconductor element 128 via the conductive pattern layer 126.

In addition, in the present embodiment, the semiconductor elements 128 may include various types, that is, the types of the semiconductor elements 128 may not necessarily be identical. The plurality of semiconductor components 128 can be different electronic components such as a wafer, a capacitor, an inductor, or a circuit board assembly or the like. The types of the semiconductor elements 128 may be different from each other, and FIG. 1B is represented by the semiconductor elements 128a, 128b, 128c, and 128d. However, the present invention does not limit the number and type of semiconductor elements 128.

The stacked structure 120 includes a plurality of insulating layers 127, each of which is disposed between two adjacent semiconductor elements 128. The insulating layer 127 is used to avoid unnecessary electrical connection or short circuit between the conductive pattern layers 126, and the insulating layer 127 can also be used to protect and bond the semiconductor elements 128. The insulating layer 127 is disposed between the respective semiconductor elements 128, so that the appearance of the stacked structure 120 is stereoscopically stacked. A conductive pattern layer 126 is disposed on the top surface 122 of the stacked structure 120, and each side sidewall 124 exposes the conductive pattern layer 126 between the semiconductor elements 128.

It should be noted that the insulating layer 127 may be a die bond adhesive for bonding the respective wafers, such as a die attach adhesive layer (DAF), silver paste, or the like. In addition, the insulating layer 127 may also be formed of a viscous preimpregnated material layer, such as a glass fiber prepreg, a carbon fiber prepreg (Carbon fiber). Prepreg) or epoxy resin (Epoxy resin), etc. To join the various package modules.

The conductive strips 130 are disposed on the sidewalls 124, and the conductive strips 130 are connected to at least two adjacent conductive pattern layers 126 exposed by the sidewalls 124, and the semiconductor elements 128 are electrically connected to each other through the conductive strips 130. However, in other embodiments, the conductive strips 130 may also be disposed on the top surface 122 and the substrate 110 for different electrical connection considerations. For example, the semiconductor component 128a is a circuit board assembly having a plurality of components thereon, and the conductive tape 130 may be disposed on the components to electrically connect the plurality of components.

In order to meet the different electrical connection design of the stacked package, the length, number and distribution position of the conductive strip 130 can be designed according to the requirements of the product. As shown in FIG. 1B , in all the conductive strips 130 , the conductive strips 130 may be pads and lines extending from the conductive pattern layer 126 of the semiconductor device 128 a to the substrate 110 , so that the semiconductor device 128 a is electrically connected to the substrate 110 . . The conductive strip 130 may also be extended from the conductive pattern layer 126 of the semiconductor element 128b to the conductive pattern layer 126 of the semiconductor element 128c, so that the semiconductor element 128b is electrically connected to the semiconductor element 128c. However, the present invention does not limit the shape, number, and distribution of the conductive strips.

The stacked package 100 may further include a molding layer 140 covering the stacked structure 120 and the conductive strip 130, and the molding layer 140 also covers the substrate 110. Generally, the encapsulation layer 140 is an encapsulant for covering the stacked structure 120, which reduces the stack structure 120 from being adversely affected by external force, moisture or temperature or being attacked by other substances. The mold sealing layer 140 may be a polymer material, such as an epoxy resin compound (EMC), polyimide (PI), phenolic resin (Phenolics) or silicone resin (Silicones), etc. Transfer molding covers the stacked structure 120. Further, the mold layer 140 may also be a ceramic material. However, the present invention The material of the molding layer is not limited.

In addition, the stacked package 100 may further include a conductive layer 150 overlying the mold layer 140 according to product requirements of each stacked package. The conductive layer 150 acts as an Electromagnetic Interference (EMI) layer to reduce electromagnetic interference effects and radio frequency interference effects. The conductive layer 150 may be a metal material such as copper, aluminum or silver nickel. The conductive layer 150 may also be a conductive polymer material, for example, polyaniline (PAn), polypyrrole (PYy) or polythiophene (PTh). However, the present invention does not limit the material of the conductive layer 150.

2A-2E are schematic views of a semi-finished product formed in each step of the method for manufacturing a stacked package according to an embodiment of the present invention. Next, please refer to Figure 2A~2E in order.

First, a substrate 110 is provided, and a stacked structure 120 is disposed on the substrate 110. Referring to FIG. 2A, in particular, a semiconductor component 128d is provided, and the semiconductor component 128d has a first surface S1 and a second surface S2 opposite the first surface S1. The semiconductor element 128d is disposed on the substrate 110 and electrically connected to the substrate 110.

In detail, the traces and pads of the originally designed semiconductor elements 128a, 128b, 128c, and 128d are changed by rewiring the semiconductor elements 128a, 128b, 128c, and 128d. In detail, first, a conductive pattern to be reconfigured is defined by Photolithography, and then a conductive pattern layer 126 is formed by plating and/or etching, thereby enabling wiring on the semiconductor elements 128a, 128b, 128c, and 128d. The semiconductor elements 128a, 128b, 128c, and 128d and their edges are reconfigured to form a conductive pattern layer 126. The conductive pattern layer 126 is disposed on each of the semiconductor elements 128a, 128b, 128c, and 128d On the first surface S1. In the above, the conductive pattern layer 126 is a rewiring layer, and the first pattern layer P1 is a pad and the second pattern layer P2 is a trace.

Thereafter, the second surface S2 of one of the semiconductor elements 128d may be attached to the substrate 110 using a film type adhesive layer, silver paste or resin. Alternatively, a surface soldering technique (SMT) may be used to deposit a solder paste on the substrate 110 to form a solder spot, and after the device is positioned, the semiconductor device 128d is electrically connected to the substrate 110 by reflow. However, the present invention does not limit the manner in which the semiconductor element 128d is adhered.

Referring to FIG. 2B, a plurality of insulating layers 127 are adhered between the respective semiconductor elements 128. The insulating layer 127 is disposed on the first surface S1 of one of the semiconductor elements 128 and attached to the second surface S2 of the other semiconductor element 128. To overlap each of the semiconductor elements 128, thereby forming a stacked structure 120. In detail, in the process of adhering the insulating layer 127, first, the insulating layer 127 is disposed over the semiconductor element 128d, wherein the conductive element layer 126 is disposed on the semiconductor element 128d, and the semiconductor element 128c is disposed on the semiconductor element 128d. On the upper insulating layer 127, an insulating layer 127 is then disposed on the semiconductor element 128c. In this form, the semiconductor elements 128a, 128b, 128c, and 128d are all disposed on the substrate 110. Next, a process of pressing is performed so that the semiconductor elements 128 are bonded together, and the stacked structure 120 is formed. It should be noted that the insulating layer 127 may also be a die bond, and the present invention does not limit the method of forming the stacked structure 120.

Next, referring to FIG. 2C, the mask 160 is overlaid on the stacked structure 120. The mask 160 has a plurality of openings 162, and the openings 162 may be disposed on the top and sides of the mask 160. The opening 162 is used to expose the conductive pattern layer 126 on the top surface 122 and the sidewalls 124. It should be noted that the shapes of the openings 162 are usually long and can be set according to different electrical connection considerations. The length, number, and distribution position of the openings 162 are measured so that the position of the conductive pattern layer 126 to be exposed can be exposed. For example, the opening 162 may be a position extending from the top surface of the mask 160 to the substrate 110 such that the conductive pattern layer 126 of the sidewall 124 of the stacked structure 120 and the pads of the substrate 110 are exposed, or the top surface of the mask 160 There may be no openings 162 provided, but only the sides 162 are formed on the sides of the mask. However, the present invention does not limit the design of the opening 162.

Subsequently, a conductive material is formed on the mask 160, and the conductive material not only adheres to the outer surface of the mask 160 but also adheres to the stacked structure 120 through the shape of the opening 162, thereby forming the conductive strip 130. In detail, a conductive material is deposited on the mask 160 by a process such as spraying, sputtering, Ion Plating, or evaporation deposition.

Referring to FIG. 2D, the mask 160 is removed to form the conductive strip 130 on the top surface 122 of the stacked structure 120 and the sidewalls 124. It is worth noting that the thickness of the conductive strip 130 can be controlled in accordance with the length of time the conductive material is deposited. In addition, the material of the conductive tape 130 is a metal such as aluminum, copper or silver. However, the present invention does not limit the plating method and material of the conductive tape 130. Through the above steps, the stacked package is substantially formed.

Referring to FIG. 2E, a molding layer 140 is formed overlying the stacked structure 120, the conductive strip 130, and the substrate 110. The material selection of the mold layer 140 needs to take into account the coefficient of thermal expansion to reduce the occurrence of warping deformation of the substrate 110. The mold sealing layer 140 may be a polymer material, such as an epoxy resin compound (EMC), a polyimide (PI), a phenolic resin (Phenolics), or a silicone resin (Silicones). The mold layer 140 can be fabricated by transfer molding. In detail, the stacked package is first placed in the cavity, and the polymer material to be filled is heated in the preheating box. After the oxidation, the molten polymer material is introduced into the runner and the cavity by means of pressurized transfer, and the mold layer 140 is overlaid on the stacked structure 120 after being cooled and aged. In addition, the mold layer 140 may also be a ceramic material that is formed into a mold layer 140 after sintering. However, the present invention does not limit the material of the mold layer 140 and the manner in which it is made.

Referring again to FIG. 1B, a conductive layer 150 is formed on the mold layer 140. The conductive layer 150 may be a metal material and may be formed on the mold layer 140 by spraying or sputtering. Further, the conductive layer 150 may also be a conductive polymer material. However, the material and manufacturing method of the conductive layer 150 are merely illustrative and are not intended to limit the invention.

In summary, the embodiments of the present invention provide a stacked package having a conductive strip, and the length, the number, and the position of the conductive strip are changed, so that the conductive strip can be electrically connected as a stacked structure, thereby simplifying the package structure and Production method. Since the conductive strips are disposed on the sidewalls of the stacked structure and are bonded to the conductive pattern layers exposed by some of the sidewalls, the semiconductor elements are electrically connected to each other through the conductive strips, and the process structure of the package can be simplified.

In addition, embodiments of the present invention provide a method for forming a stacked package by covering a stacked structure with a mask, and then depositing a conductive material on the mask, and the conductive material is allowed to pass through the opening. The conductive strip is formed on the stacked structure, and therefore, the method flow of the package can be simplified.

The above is only an embodiment of the present invention, and is not intended to limit the scope of the invention. It is still within the scope of patent protection of the present invention to make any substitutions and modifications of the modifications made by those skilled in the art without departing from the spirit and scope of the invention.

100‧‧‧Stacked package

110‧‧‧Substrate

120‧‧‧Stack structure

122‧‧‧ top surface

124‧‧‧ side wall

126‧‧‧conductive pattern layer

127‧‧‧Insulation

128a, 128b, 128c, 128d‧‧‧ semiconductor components

130‧‧‧ Conductive tape

140‧‧•mold layer

150‧‧‧ Conductive layer

160‧‧‧ mask

162‧‧‧ openings

P1‧‧‧ first pattern layer

P2‧‧‧ second pattern layer

S1‧‧‧ first surface

S2‧‧‧ second surface

FIG. 1A is a top plan view of a stacked package according to an embodiment of the invention.

1B is a schematic cross-sectional view taken along line P-P of FIG. 1A.

2A-2E are schematic views of a semi-finished product formed in each step of the method for manufacturing the stacked package of FIG. 1B;

100‧‧‧Stacked package

110‧‧‧Substrate

120‧‧‧Stack structure

122‧‧‧ top surface

124‧‧‧ side wall

126‧‧‧conductive pattern layer

127‧‧‧Insulation

128a, 128b, 128c, 128d‧‧‧ semiconductor components

130‧‧‧ Conductive tape

140‧‧•mold layer

150‧‧‧ Conductive layer

S1‧‧‧ first surface

S2‧‧‧ second surface

Claims (14)

A stacked package includes: a substrate; a stacked structure on the substrate, the stacked structure has a top surface and a multi-sided sidewall, and the stacked structure includes a plurality of conductive pattern layers, wherein the sidewalls expose the conductive And a patterned layer; and at least one conductive strip disposed on the at least one sidewall, the conductive strip being electrically connected to the at least two conductive pattern layers. The stacked package of claim 1, wherein the stacked structure further comprises a plurality of semiconductor elements stacked side by side, and wherein one of the conductive pattern layers is located between the adjacent two semiconductor elements, The conductive strip electrically connects two of the semiconductor elements. The stacked package of claim 2, wherein the semiconductor component is a wafer. The stacked package of claim 2, wherein the semiconductor component is a package module. The stacked package of claim 1, wherein the conductive pattern layer is a rewiring layer. The stacked package of claim 2, wherein the stacked structure further comprises a plurality of insulating layers, each of the insulating layers being located between two adjacent semiconductor elements. The stacked package of claim 1, wherein the stacked structure further comprises a molding layer covering the stacked structure and the conductive strip and disposed on the substrate. The stacked package of claim 7, wherein the stacked structure comprises a conductive layer covering the mold layer. A method of manufacturing a stacked package includes: forming a stacked structure on a substrate, the stacked structure having a top surface and a multi-sided sidewall, and the stacked structure includes a plurality of conductive pattern layers, wherein the sidewalls expose the a conductive pattern layer; and patterning the stacked structure to form at least one conductive strip, wherein the conductive strip is on the sidewalls and connects at least two of the conductive pattern layers. The method of manufacturing a stacked package according to claim 9, wherein the step of forming the stacked structure on the substrate comprises: providing a plurality of semiconductor elements, wherein each of the semiconductor elements has a first surface and a a second surface opposite to the first surface; rewiring the semiconductor elements to form a layer of the conductive pattern on each of the first surfaces; forming a protective layer on each of the first surfaces, wherein the protection The layer covers the conductive pattern layers; and the semiconductor elements are stacked, and the first surface of one of the semiconductor elements is located under the second surface of the other semiconductor element, and each of the protective layers is located adjacent to the second Between the semiconductor components. The method for manufacturing a stacked package according to claim 9, wherein the step of patterning the stacked structure comprises: covering a mask on the stacked structure; depositing a conductive material on the mask ; and remove the mask. The method of manufacturing a stacked package according to claim 11, wherein the mask has a plurality of openings for exposing portions of the conductive pattern layers on the top surface and the sidewall. The method for manufacturing a stacked package according to claim 9, further comprising: forming a mold layer covering the stack structure and the conductive strip. The method for manufacturing a stacked package according to claim 13, further comprising: forming a conductive layer covering the mold layer.