TW201330109A - Method of manufacturing vertical transistor - Google Patents

Abstract

A method of manufacturing a vertical transistor, which is to form a plurality of first trenches on a substrate, and sequentially forming a first polarity layer and a channel layer on the first trench in an epitaxial growth manner, and further forming a first barrier layer on the channel layer, followed by etching the first barrier layer and the channel layer in the direction perpendicular to the first trench in order to form a plurality of pillars, and then to form a gate at the first sidewall and the second sidewall of the plurality of pillar, finally removing the first barrier layer on the pillars and then epitaxially growing a second polarity layer. The aforementioned steps of forming a vertical transistor structure of the present invention is characterized by epitaxially forming the first polarity layer, the channel layer and the second polarity layer, so as to have the advantage of uniform ion distribution.

Description

Vertical transistor manufacturing method

The invention relates to a method for fabricating a transistor, in particular to a method for fabricating a vertical transistor.

The continuous improvement of semiconductor process technology has greatly reduced the size of electronic components on the one hand, and greatly reduced the manufacturing cost of electronic components on the other hand. The semiconductor process technology used in the past years is limited to the formation of planar semiconductor structures by etching, ion cloth values, wiring, etc. on the substrate, and the minimum wafer size can reach 6F2. However, at present, such technologies tend to be flattened with the miniaturization of the feature size, and the area occupied by the semiconductor on the wafer cannot be significantly reduced. Thus, vertical (or three-dimensional) semiconductor process technology is gradually evolving, which reduces the area occupied by the transistor on the wafer surface by vertically growing the semiconductor on the wafer, and further The chip size is reduced to 4F2.

A method of fabricating a vertical transistor disclosed in "Vertical transistor of semiconductor device and method for forming the same" and "Methods of forming vertical transistor structures" in US Pat. Pub. No. 2006/0258086, After forming a plurality of columnar bodies by etching the ruthenium substrate, ion implantation is used to dope or diffuse to form an ion implantation region on the columnar body, thereby forming a source region, a channel region, and Bungee area. Please refer to "Figure 1" for the ion concentration distribution of source region 1, channel region 2 and drain region 3. Because of the technical limitations of ion implantation, the channel ions in the vertical direction of channel region 2 The distribution of concentration 4 is not uniform, but exhibits a Gaussian distribution. Therefore, as the depth of the ion input is controlled, the distribution position of the ion concentration 4 of the channel is changed, and thus the channel ion concentration 4 and the source ion concentration may be caused. Or the distribution region of the radon ion concentration 6 has a phenomenon of a high concentration overlap section 7 and a low concentration overlap section 8, which may cause a leakage or an unconformable condition, which affects the quality of the vertical transistor.

The main object of the present invention is to solve the problem of uneven ion concentration distribution of a vertical transistor of the prior art.

In order to achieve the above object, the present invention provides a method for fabricating a vertical transistor, comprising the steps of: defining at least one trench region and at least one insulating region on a substrate, and forming a first trench in the trench region; S2: forming a first polarity layer and a channel layer in the first trench in an epitaxial growth manner, and forming a first barrier layer on the channel layer; S3: using the first barrier layer Etching the insulating region to a level lower than the first polarity layer and an etching depth from the first polarity layer, so that the substrate is connected to the first polarity layer to form a connection portion, which is defined to be stacked The connecting portion, the first polarity layer, the channel layer and the first barrier layer are an integrated layer, and the integrated layer has opposite sides; S4: forming a first insulating layer, forming the first side An insulating layer; S5: forming a plurality of second trenches in the integrated layer to form at least one columnar body, wherein the columnar body has a first sidewall and a second sidewall corresponding to the plurality of second trenches, by etching the integrated layer Go Retaining the first polarity layer in addition to the channel layer, forming the second trench, the second trench is perpendicular to the first trench; S6: forming a gate on the first sidewall and the second sidewall, respectively; S7: removing The first barrier layer on the columnar body; and S8: epitaxially growing a second polarity layer on the columnar body.

It can be seen from the above description that the first polar layer, the channel layer and the second polar layer are formed by epitaxial method, and have the advantages of uniform ion concentration distribution, thereby obtaining better vertical transistor quality.

The detailed description and technical contents of the present invention will now be described as follows:

Referring to FIG. 2A to FIG. 2J, the present invention is a method for fabricating a vertical transistor, comprising the following steps:

S1: forming a trench, defining at least one trench region 13 and at least one insulating region 14 on a substrate 10, and forming a first trench 12 in the trench region 13, the invention is exemplified by making a transistor matrix. Especially suitable for use in the structure of dynamic random redemption memory (DRAM). In this embodiment, there are a plurality of trench regions 13 and a plurality of insulating regions 14, and the plurality of trench regions 13 and the plurality of insulating regions 14 are spaced apart from each other. In more detail, step S1 includes the following steps: S1a: forming an extension layer 11 on the substrate 10, as shown in FIG. 2A, the extension layer 11 is formed of an oxidized material and has insulating properties. The material of the substrate 10 is 矽; S1b: etching the extension layer 11 and the substrate 10 to form the first trench 12, as shown in FIG. 2B, the first trench 12 completely penetrates the extension layer 11 The first trench 12 thus has a plurality of and corresponds to each other corresponding to the trench region 13.

S2: performing epitaxial growth, as shown in FIG. 2C and FIG. 2D, forming a first polarity layer 21 and a channel layer in the first trench 12 in an epitaxial growth mode. 22, it should be noted that the epitaxial growth material is not pure germanium, and the epitaxial growth is performed by mixing doped P-type or N-type ions, thereby forming the first polar layer 21 having uniform ion concentration distribution and the The channel layer 22, the material of the first polarity layer 21 may be an N-type ion or a P-type ion, depending on the type of transistor to be fabricated, and the material of the channel layer 22 is a P-type ion or N. Type ions. And as shown in FIG. 2E, a first barrier layer 23 is further formed on the channel layer 22. The first barrier layer 23 can be tantalum nitride, and the chemical mechanical device as shown in FIG. 2F can be further performed. The first barrier layer 23 is ground to the same level as the extension layer 11 by chemical mechanical polishing (CMP).

S3: etching the substrate 10, as shown in FIG. 2G and FIG. 2H, using the first barrier layer 23 as a mask to etch the extended layer 11 of the insulating region 14 and the substrate 10 below a first polarity layer 21, and an etching depth d1 from the first polarity layer 21, so that the substrate 10 is connected to the first polarity layer 21 to form a connecting portion 24, defining the connecting portion 24 formed by overlapping layers, The first polarity layer 21, the channel layer 22 and the first barrier layer 23 are an integrated layer 20, and the integrated layer 20 has opposite side faces 25, and the integrated layer 20 also has a plurality of corresponding trench regions 13.

After completing step S3, please refer to "FIG. 2I". In order to complete the subsequent process, step A1 can be performed: the two sides 25 are repaired by the In Situ Steam Generation (ISSG) and formed into a The repair layer 31 is on the surface of the integrated layer 20, whereby the surfaces of the two side faces 25 are flattened. In addition, by performing step A2: implanting a counter ion 15 opposite to the ion of the first polarity layer 21 to the substrate 10 between the plurality of integrated layers 20, by the counter ion 15 The arrangement can enhance the possibility of blocking the mutual conduction between the adjacent integrated layers 20, so as to avoid the problem of distortion or signal damage caused by mutual interference when the adjacent layer 20 of the integrated layer is electrically transmitted for signal transmission.

S4: forming a first insulating layer 32, as shown in FIG. 2J, forming the first insulating layer 32 on the two side faces 25, and in the embodiment, using a spin-on medium (Spin On Dielectric) The technique of SOD) fills the insulating material 64 between the plurality of integrated layers 20 to form the first insulating layer 32.

The above steps are completed in the first stage process, that is, the process of the first polarity layer 21 and the channel layer 22 is completed. Please refer to the figure of FIG. 3, which is a schematic view of the first stage after the completion of the first stage process, Figure 2A" to Figure 2J are schematic diagrams showing the process of the AA section of Figure 3, and please refer to Figure 4A to Figure 4G. The second stage of the process is followed by The direction of the BB section of "Fig. 3" is schematically illustrated.

S5: forming a plurality of second trenches 50 to form at least one columnar body 51 on the integrated layer 20, please refer to "FIG. 4A", "FIG. 4B" and "FIG. 5", and "FIG. 4A" is "Figure 3" is a schematic view of the BB section, and "Fig. 5" is a top view of "Fig. 4B". In FIG. 4B, an etching position is defined by a plurality of second barrier layers 40 disposed on the first barrier layer 23, and the integrated layer 20 is etched to remove the channel layer 22 to retain the first polarity layer 21, thereby forming The second trench 50 is perpendicular to the first trench 12, and the unetched region forms a plurality of pillars 51 by etching the first trench 12 and the second trench 50. The columnar body 51 has a first side wall 511 and a second side wall 512 corresponding to the plurality of second trenches 50.

After step S5, there is a step A3 of forming an insulating protection structure. As shown in FIG. 4C, a protective layer 61 is formed on the bottom surface of the second trench 50, and a second insulating layer 62 is formed on the first sidewall. 511 and the surface of the second sidewall 512, thereby avoiding the problem that the subsequent process is directly connected to the substrate 10, the first sidewall 511 and the second sidewall 512 to cause leakage, and in the embodiment, the second insulation The material of layer 62 is formed using In-Situ Steam Seneration (ISSG).

S6: a gate 63 is formed on the first sidewall 511 and the second sidewall 512, as shown in FIG. 4D. In the embodiment, the gate 63 and the first sidewall 511 and the second sidewall are The second insulating layer 62 is disposed between 512, thereby isolating the electrical conduction between the gate 63 and the columnar body 51. The method of forming the gate 63 can be performed by directly filling a conductive material in the second trench 50, and then separating the conductive material by means of photoresist definition etching to form two separated and attached to the first sidewall 511 and the a gate 63 of the second sidewall 512; a conductive layer may be deposited on the surface of the second trench 50 by linear deposition, and then directly removed from the bottom surface of the second trench 50 by etch back The conductive layer forms two gates 63 separated from each other and attached to the first sidewall 511 and the second sidewall 512. It should be noted that the protective layer 61 disposed on the bottom surface of the second trench 50 can be used as an adjustment of the relative position between the gate 63 and the first polar layer 21.

After the step S6 is completed, please refer to FIG. 4E, and step A4 can be performed to fill an insulating material 64 in the second trench 50 having the gate 63, thereby being completely isolated from the first sidewall 511. The two gates 63 on the second sidewall 512 are electrically conductive to each other and the possibility of the external environment affecting the gate 63 is avoided.

S7: The first barrier layer 23 on the columnar body 51 is removed, as shown in FIG. 4F.

S8: A second polarity layer 80 is grown on the columnar body 51 by epitaxy. Please refer to FIG. 4G and FIG. 2G for the material of the second polarity layer 80 being the same as the first Polar layer 21. Forming a vertical transistor structure through the positional arrangement of the first polarity layer 21, the channel layer 22, the second polarity layer 80, and the gate 63 on the columnar body 51, the first polarity layer 21 and the The second polarity layer 80 can serve as the source or drain of the transistor, respectively. Therefore, the electrical conduction state of the channel layer 22 is adjusted by the control of the voltage on the gate 63, and the electrical connection between the first polarity layer 21 and the second polarity layer 80 is controlled.

Between step S7 and step S8, a step A5 can be further performed: forming a height adjustment layer 70 on the surface of the channel layer 22, so that the height adjustment layer 70 is formed on the channel layer 22 and the second polarity layer 80. The material of the height adjustment layer 70 may be the same as the channel layer 22 or may be made of tantalum material, that is, the material of the height adjustment layer 70 may be pure tantalum or low-doped N-type ions. The growth mode of 70 can be grown by using the epitaxial method.

Specifically, the height adjustment layer 70 is disposed to adjust the relative position of the second polarity layer 80 and the gate 63. If the second polarity layer 80 and the gate 63 are relatively overlapped, that is, the The height position of the gate 63 away from one end of the substrate 10 is higher than the position of the second polarity layer 80 and the height adjustment layer 70, and the problem of electric leakage is easy to occur; but when the gate 63 is away from the one end of the substrate 10 When the height position is far lower than the position of the second polarity layer 80 and the height adjustment layer 70, it is easy for the gate 63 to control the electrical path formed by the channel layer 22 to be ineffectively connected to the second polarity layer 80. Unable to form an effective circuit switch.

In summary, since the present invention forms the first polarity layer 21, the channel layer 22, and the second polarity layer 80 by epitaxy, it has the advantage of uniform ion concentration distribution, thereby obtaining a preferred vertical transistor. quality. In addition, the present invention further discloses the arrangement of the protective layer 61 and the height adjustment layer 70, thereby adjusting the position of the gate 63 relative to the first polarity layer 21 and the second polarity layer 80, and can be matched The arrangement of the channel layer 22 avoids the effect of not achieving an electrical switch. Therefore, the present invention is highly progressive and conforms to the requirements of the invention patent application, and the application is filed according to law, and the praying office grants the patent as soon as possible.

The present invention has been described in detail above, but the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the scope of the invention. That is, the equivalent changes and modifications made by the scope of the present application should remain within the scope of the patent of the present invention.

Conventional technology

1. . . Source area

2. . . Channel area

3. . . Bungee area

4. . . Channel ion concentration

5. . . Source ion concentration

6. . . Boiler ion concentration

7. . . High concentration overlap section

8. . . Low concentration overlap section

this invention

10. . . Substrate

11. . . Extension layer

12. . . First ditches

13. . . Ditch area

14. . . Insulated area

15. . . Counter ion

20. . . Integrated layer

twenty one. . . First polarity layer

twenty two. . . Channel layer

twenty three. . . First barrier

twenty four. . . Connection

25. . . side

31. . . Repair layer

32. . . First insulating layer

40. . . Second barrier

50. . . Second ditches

51. . . Columnar body

511. . . First side wall

512. . . Second side wall

61. . . The protective layer

62. . . Second insulating layer

63. . . Gate

64. . . Insulating material

70. . . Height adjustment layer

80. . . Second polarity layer

D1. . . Etching depth

Figure 1 is a schematic diagram showing the ion concentration distribution of the prior art.

2A-2J are schematic diagrams showing a first stage process of a preferred embodiment of the present invention.

Figure 3 is a top plan view of Figure 2J.

4A-4G are schematic diagrams showing a second stage process of a preferred embodiment of the present invention.

Figure 5 is a top plan view of Figure 4B.

10. . . Substrate

twenty one. . . First polarity layer

twenty two. . . Channel layer

61. . . The protective layer

62. . . Second insulating layer

63. . . Gate

64. . . Insulating material

70. . . Height adjustment layer

80. . . Second polarity layer

Claims (13)

A method for fabricating a vertical transistor includes the following steps: S1: defining at least one trench region and at least one insulating region on a substrate, and forming a first trench in the trench region; S2: growing by epitaxial growth Forming a first polarity layer and a channel layer in the first trench, and forming a first barrier layer on the channel layer; S3: etching the insulating region with the first barrier layer as a mask to Lower than the first polarity layer, and an etching depth from the first polarity layer, so that the substrate is connected to the first polarity layer to form a connection portion, and the connection portion, the first polarity is defined The layer, the channel layer and the first barrier layer are an integrated layer, and the integrated layer has opposite sides; S4: forming a first insulating layer, forming the first insulating layer on the two sides; S5: forming a plurality The second trench is formed in the integrated layer to form at least one columnar body. The columnar body has a first sidewall and a second sidewall corresponding to the plurality of second trenches. The etching is performed by etching the integrated layer to remove the channel layer. First pole Forming the second trench, the second trench is perpendicular to the first trench; S6: forming a gate on the first sidewall and the second sidewall respectively; S7: removing the first on the pillar a barrier layer; and S8: growing a second polarity layer on the columnar body in an epitaxial manner. The method for fabricating a vertical transistor according to claim 1, wherein in the step S1, the method comprises the steps of: forming an extension layer on the substrate; S1b: etching the extension layer and the base Material to form the first trench. The method for fabricating a vertical transistor according to claim 2, wherein the extension layer is made of an oxidized material. The method for fabricating a vertical transistor according to claim 2, wherein in step S3, the extension layer is removed by etching. The method for fabricating a vertical type of transistor according to claim 1, wherein between step S3 and step S4, there is a step A1: repairing the two sides by using a spot steam generation technique to smooth the surfaces of the two sides . The method for fabricating a vertical transistor according to claim 1, wherein in the step S4, the first insulating layer is formed by filling an insulating material between the plurality of integrated layers. The method for fabricating a vertical transistor according to claim 1, wherein the trench region and the insulating region have a plurality of and are spaced apart from each other, and the first trench has a plurality of parallel channels corresponding to the trench region The integrated layer also has a plurality of corresponding ditches. The method for fabricating a vertical transistor according to claim 7, wherein between step S3 and step S4, there is a step A2: implanting a counter ion of the doped ion of the first polarity layer The position of the substrate between the integrated layers is complex. The method of manufacturing the vertical type transistor according to the seventh aspect of the invention, wherein the step S5 and the step S6 further comprise a step A3: forming a protective layer on the bottom surface of the second trench, and forming a first Two insulating layers are on the first sidewall and the second sidewall surface. The method for fabricating a vertical type of transistor according to claim 1, wherein after step S6, there is a step A4 of filling an insulating material into the second trench having the gate. The method for fabricating a vertical transistor according to claim 1, wherein there is a step A5 between step S7 and step S8: forming a height adjustment layer between the channel layer and the second polarity layer. . The method for fabricating a vertical transistor according to claim 11, wherein the height adjustment layer is made of the same material as the channel layer or is tantalum. The method for fabricating a vertical transistor according to claim 11, wherein the height adjustment layer is formed by epitaxy.