TW201336075A - Semiconductor structure and manufacturing process thereof - Google Patents

Abstract

A semiconductor structure includes a substrate having a first conductive type, a well having a second conductive type formed in the substrate, a first doped region and a second doped region formed in the well, a field oxide, a first dielectric layer and a second dielectric layer. The field oxide is formed on a surface region of the well and between the first doped region and the second doped region. The first dielectric layer is formed on the surface region of the well and covers an edge portion of the field oxide. The first dielectric layer has a first thickness. The second dielectric layer is formed on the surface region of the well. The second dielectric layer has a second thickness smaller than the first thickness.

Description

Semiconductor structure and its process

The present invention relates to a semiconductor structure and process thereof, and more particularly to a metal oxide semiconductor structure and process thereof.

In high voltage systems, it is important for the MOS device to have a high turn-off breakdown voltage (Vbd) and a low on-resistance value (Ronsp) during operation so that the semiconductor device can withstand higher voltages and allow more current. Flow between the drain and the source to increase the power of the component. However, the shutdown breakdown voltage and the on-resistance are accompanied by an increase in the shutdown breakdown voltage, which in turn causes an increase in the on-resistance value. Therefore, when designing a semiconductor device, the shutdown breakdown voltage cannot be made to a maximum value. Therefore, how to improve the shutdown breakdown voltage of the semiconductor element and reduce the on-resistance during operation is a problem that the industry is eager to solve.

The present invention relates to a semiconductor structure and process thereof for reducing the hot carrier effect and increasing the breakdown voltage by varying the thickness and length of the dielectric layer.

According to an aspect of the invention, a semiconductor structure includes a substrate of a first conductivity type, a well region of a second conductivity type formed in the substrate, a first doped region, a second doped region, and a field. An oxide, a first dielectric layer, and a second dielectric layer. The first doped region and a second doped region are formed in the well region. The field oxide is formed in a surface region of the well region and is located between the first doped region and the second doped region. The first dielectric layer is formed on a surface region of the well region and covers an edge portion of the field oxide, the first dielectric layer having a first thickness. The second dielectric layer is formed on a surface region of the well region, and the second dielectric layer has a second thickness. The second thickness is less than the first thickness.

According to another aspect of the invention, a semiconductor process is proposed comprising the following steps. A substrate of a first conductivity type is provided. A well region of a second conductivity type is formed in the substrate. A first doped region and a second doped region are formed in the well region. A surface region of the oxide region is formed in the well region, and is located between the first doped region and the second doped region, and a channel region is formed between one edge portion of the field oxide and the second doped region. A first dielectric layer is formed to cover an edge portion of the field oxide, the first dielectric layer having a first thickness. A second dielectric layer is formed to cover a surface region of the well region, and the second dielectric layer has a second thickness. The second thickness is less than the first thickness.

In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

The semiconductor structure of the present invention and its process are covered with a thick dielectric layer at the edge portion of the field oxide, so that a higher tip electric field can be prevented from occurring at the edge portion of the field oxide to reduce the hot carrier effect (hot Carrier effect). In addition, the gate conductive layer can provide appropriate insulation by two dielectric layers having different thicknesses to prevent electrical collapse from occurring between the gate conductive layer and the body region.

The following is a detailed description of various embodiments, which are intended to be illustrative only and not to limit the scope of the invention.

Referring to FIG. 1, a schematic diagram of a semiconductor structure in accordance with an embodiment of the present invention is shown. The semiconductor structure 100 is, for example, a double-diffused metal semiconductor device including a substrate 110, a well region 120, a first doped region 130, a second doped region 180, a field oxide 140, and a first dielectric layer 151. And a second dielectric layer 160. The substrate 110 is, for example, a P-type substrate, the well region 120 is, for example, an N-type well region, and the well region 120 is formed in the substrate 110. The first doped region 130 and the second doped region 180 are located in the well region 120, and the first doped region 130 is, for example, an N-type doped region. The first doped region 130 has a heavily doped region 131, such as an N+ doped region, which can serve as a contact region for the germanium terminal 132. The second doped region 180 includes a body region 181 and a heavily doped region 182. The body region 181 is, for example, a P-type body region, and the heavily doped region 182 is, for example, an N+ doping region and a P+ doping region, and can be used as a contact region of the source terminal 133 and the base terminal 134, respectively. The field oxide 140 is formed in a surface region of the well region 120 and is located between the first doping region 130 and the second doping region 180, and is made of, for example, hafnium oxide. The field oxide 140 can also be a shallow trench isolation structure for isolating the first doped region 130 from the second doped region 180.

In the present embodiment, the first dielectric layer 151 and the second dielectric layer 160 are respectively formed on the surface area of the well region 120, and the first dielectric layer 151 covers an edge portion 141 of the field oxide 140 (for example, a bird's beak). unit). The first dielectric layer 151 has a first thickness X1 ranging between 950 and 1000 angstroms, such as 975 angstroms. In addition, the second dielectric layer 160 has a second thickness X2 ranging between 100 and 150 angstroms, for example 115 angstroms. In one embodiment, the first dielectric layer 151 can serve as a thick gate oxide layer and the second dielectric layer 160 can serve as a thin gate oxide layer. As the thickness of the gate oxide layer decreases, the gate voltage that the semiconductor device can withstand decreases. For example, the first dielectric layer 151 can withstand a 40V gate voltage while the second dielectric layer 160 can withstand a 5V gate voltage. Therefore, the turn-on voltage of the gate can be changed by changing the thicknesses of the first dielectric layer 151 and the second dielectric layer 160. In the present embodiment, since the gate oxide layer (second dielectric layer 160) having a small thickness is located on the portion of the P-type body region 181, the turn-on voltage of the gate does not increase.

In addition, the first dielectric layer 151 is adjacent to the second dielectric layer 160 and does not overlap. The first dielectric layer 151 covers a portion of the channel region 190 and a portion of the field oxide 140, and the second dielectric layer 160 covers the other portion of the channel region 190 and a portion of the second doped region 180. In addition, the gate conductive layer 170 is formed on the first dielectric layer 151 and the second dielectric layer 160, that is, above the body region 181, the channel region 190, and a portion of the field oxide 140, and is formed by the first dielectric. Layer 151 and second dielectric layer 160 provide suitable insulation to prevent electrical collapse from occurring between gate conductive layer 170 and body region 181. This embodiment modulates the voltage applied to the gate conductive layer 170 to control the turn-on voltage of the semiconductor structure 100 or to turn off the semiconductor structure 100. In addition, when there is a bias between the voltage applied to the first doping region 130 and the voltage applied to the second doping region 180, current may be applied to the first doping region 130 and the second doping region 180. Flow between. For example, under high voltage operation, the first doped region 130 is connected to a high voltage and the second doped region 180 is grounded.

In the present embodiment, the thickness (first thickness X1) of the first dielectric layer 151 is greater than the thickness (second thickness X2) of the second dielectric layer 160. Since the thick first dielectric layer 151 covers the edge portion 141 of the field oxide 140, a higher tip electric field can be prevented from occurring at the edge portion 141 of the field oxide 140 to reduce the hot carrier effect. In addition, since the one end portion 152 of the first dielectric layer 151 is exposed outside the gate conductive layer 170, and the first dielectric layer 151 covers the area of the field oxide 140 larger than the gate conductive layer 170 covers the field oxide 140. The area can be further increased by the breakdown voltage.

Next, please refer to FIGS. 2A-2F, which respectively illustrate schematic diagrams of a semiconductor process in accordance with an embodiment of the present invention. In FIG. 2A, a substrate 110 of a first conductivity type is provided and a well region 120 of a second conductivity type is formed in the substrate 110. A doping process is performed to form a first doped region 130 in the well region 120. The first conductivity type is, for example, a P type, and the second conductivity type is, for example, an N type. However, the present invention is not limited thereto. In one embodiment, the first conductivity type may be an N type, and the second conductivity type may be a P type.

In FIG. 2B, a partial thermal oxidation process is performed to form a field oxide 140 in the surface region of the well region 120. The field oxide 140 is used to isolate the first doping region 130 from the second doping region 180. The field oxide 140 is connected to the first doping region 130, for example, and has a channel region 190 between the second doping region 180. . Next, a dielectric material layer 150 is formed in the surface region of the well region 120 by thermal oxidation, and the dielectric material layer 150 covers the field oxide 140. The dielectric material layer 150 can be formed by etching to form the first dielectric layer 151. The first dielectric layer 151 has a first thickness X1 ranging between 950 and 1000 angstroms, such as 975 angstroms. The material of the first dielectric layer 151 may be an insulating material such as tantalum oxide, tantalum nitride or tantalum oxynitride. The oxidation state of the first dielectric layer 151 can be precisely controlled by the parameters of the thermal oxidation process such as heating temperature, heating time, and the like. In addition, the first dielectric layer 151 can also be formed by a sacrificial oxidation (SAC) method, which is not limited in the present invention.

In the 2C and 2D views, a mask layer 101 is formed on a portion of the dielectric material layer 150, and the mask layer 101 is, for example, a photoresist pattern for defining the pattern of the first dielectric layer 151. Then, for example, a dry etching or a wet etching process is performed to remove the exposed portion of the dielectric material layer 150 that is not covered by the mask layer 101, so that the patterned first dielectric layer 151 can cover the field oxide 140. Edge portion 141.

In FIG. 2E, a second dielectric layer 160 is formed in the surface region of the well region 120 by thermal oxidation. The second dielectric layer 160 has a second thickness X2 ranging between 100 and 150 angstroms, for example 115 angstroms. The material of the second dielectric layer 160 may be an insulating material such as tantalum oxide, tantalum nitride or tantalum oxynitride. The oxidation state of the second dielectric layer 160 can be appropriately controlled by the parameters of the thermal oxidation process such as the heating temperature, the heating time, and the like. In addition, the second dielectric layer 160 can also be formed by a sacrificial oxide (SAC) method.

In FIG. 2F, a gate conductive layer 170 is formed on the first dielectric layer 151 and the second dielectric layer 160, for example, by chemical vapor deposition. The gate conductive layer 170 is, for example, a doped polysilicon layer or a metal halide. In this embodiment, one end portion 152 of the first dielectric layer 151 is exposed outside the gate conductive layer 170, and the first dielectric layer 151 covers the area of the field oxide 140 larger than the gate conductive layer 170 is covered. The area of the oxide 140. When the gate conductive layer 170 is applied with a turn-on voltage to turn on the semiconductor device and a bias is applied between the first doping region 130 and the second doping region 180, the first doping region 130 and the second region may be applied. A current is generated between the doped regions 180 and flows through the gaps in the channel region 190.

Since the thick first dielectric layer 151 covers the edge portion 141 of the field oxide 140, a higher tip electric field can be prevented from occurring at the edge portion 141 of the field oxide 140 to reduce the hot carrier effect. In addition, the gate conductive layer 170 located above the body region 181, the channel region 190 and the portion of the field oxide 140 can be appropriately insulated by the first dielectric layer 151 and the second dielectric layer 160 to avoid electrical collapse. The phenomenon occurs between the gate conductive layer 170 and the body region 181.

Next, please refer to the following table, which lists the length (L), the turn-on voltage (Vt), the breakdown voltage (off-Vbd) when the semiconductor is turned off, the on-resistance value (Ronsp), and the breakdown voltage when the semiconductor is turned on (on-Vbd). And the relationship between quality factor (FOM). As shown in FIG. 2F, L1 indicates that the first dielectric layer 151 covers the length of the field oxide layer 140, and L2 indicates that the gate conductive layer 170 covers the length of the field oxide layer 140. According to the data of the comparison table, with respect to L1 < L2, when L1>L2, the shutdown breakdown voltage (off-Vbd) is increased to 94V, and the turn-on breakdown voltage is increased to 76V, so that the quality factor (Ronsp/off-Vbd) is lowered to 0.96, which in turn causes the semiconductor device to have a high breakdown voltage and a low on-resistance value.

The semiconductor structure 100 described above may be a metal oxide semiconductor device such as a vertical diffusion metal oxide semiconductor (VDMOS), a lateral double diffusion metal oxide semiconductor (LDMOS) or an enhanced metal oxide semiconductor (EDMOS) device, etc., but the present invention does not Limit it.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100. . . Semiconductor structure

101. . . Mask layer

110. . . Base

120. . . Well area

130. . . First doped region

131. . . Heavily doped region

132. . . Extreme

133. . . Source extreme

134. . . Base extreme

140. . . Field oxide

141. . . Edge portion

150. . . Dielectric material layer

151. . . First dielectric layer

152. . . Ends

160. . . Second dielectric layer

170. . . Gate conductive layer

180. . . Second doped region

181. . . Body area

182. . . Heavily doped region

190. . . Channel area

X1, X2. . . thickness

L1, L2. . . length

1 is a schematic view of a semiconductor structure in accordance with an embodiment of the present invention.

2A to 2F are schematic views respectively showing a semiconductor process according to an embodiment of the present invention.

100. . . Semiconductor structure

110. . . Base

120. . . Well area

130. . . First doped region

131. . . Heavily doped region

132. . . Extreme

133. . . Source extreme

134. . . Base extreme

140. . . Field oxide

151. . . First dielectric layer

152. . . Ends

160. . . Second dielectric layer

170. . . Gate conductive layer

180. . . Second doped region

181. . . Body area

182. . . Heavily doped region

190. . . Channel area

Claims (10)

A semiconductor structure comprising:
a substrate of a first conductivity type;
a second conductivity type well region formed in the substrate;
a first doped region and a second doped region are formed in the well region;
a field oxide formed in a surface region of the well region and located between the first doped region and the second doped region;
a first dielectric layer formed on a surface region of the well region and covering an edge portion of the field oxide, the first dielectric layer having a first thickness; and a second dielectric layer formed on the A surface region of the well region, the second dielectric layer having a second thickness, the second thickness being less than the first thickness. The semiconductor structure of claim 1, wherein the first dielectric layer and the second dielectric layer do not overlap, the first dielectric layer is a first gate oxide layer, and the second dielectric layer It is the second gate oxide layer. The semiconductor structure of claim 1, wherein the field oxide and the second doped region have a channel region, the first dielectric layer covering a portion of the channel region and a portion of the field oxide, And the second dielectric layer covers another portion of the channel region and a portion of the second doped region. The semiconductor structure of claim 1, wherein the first doped region is a drain doped region, the second doped region is a source doped region, the field oxide and the first doping The regions are connected and have a gap between the field oxide and the second doped region. The semiconductor structure of claim 1, further comprising a gate conductive layer formed on the first dielectric layer and the second dielectric layer, wherein one end of the first dielectric layer is exposed The gate is outside the conductive layer. A semiconductor process that includes:
Providing a substrate of a first conductivity type;
Forming a second conductivity type well region in the substrate;
Forming a first doped region and a second doped region in the well region;
Forming a surface region of the oxide in the well region between the first doped region and the second doped region;
Forming a first dielectric layer to cover the edge portion of the field oxide, the first dielectric layer having a first thickness; and forming a second dielectric layer to cover a surface region of the well region, The second dielectric layer has a second thickness that is less than the first thickness. The semiconductor process of claim 6, wherein the first dielectric layer and the second dielectric layer do not overlap, the first dielectric layer is a first gate oxide layer, and the second dielectric layer It is the second gate oxide layer. The semiconductor process of claim 6, wherein the field oxide and the second doped region have a channel region, the first dielectric layer covering a portion of the channel region and a portion of the field oxide, The second dielectric layer covers another portion of the channel region and a portion of the second doped region. The semiconductor process of claim 6, further comprising forming a gate conductive layer on the first dielectric layer and the second dielectric layer, wherein one end of the first dielectric layer is exposed Outside the gate conductive layer. The semiconductor process of claim 6, wherein a portion of the first dielectric layer is covered by a mask layer and an etching process is performed to define a pattern of the first dielectric layer.