TW201334161A - Semiconductor memory device - Google Patents

Abstract

The present invention achieves a small SRAM cell area in a Loadless 4T-SRAM composed of a vertical transistor SGT. In the static memory cell in which four MOS transistors are used, the MOS transistor system is a SGT in which a drain, a gate, and a source formed on a bulk substrate are arranged in a vertical direction, and A memory having a very small memory can be realized by forming a gate of the access transistor as a word line in a plurality of cells adjacent to the horizontal direction, and forming a contact for the word line by a plurality of cells. CMOS type Loadless4T-SRAM with cell area.

Description

Semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device comprising a SRAM (Static Random Access Memory).

In order to achieve high integration and high performance of a semiconductor device, a SGT (Surrounding Gate Transistor) which is a vertical gate transistor has been proposed, which is based on a semiconductor substrate. The surface of the columnar semiconductor has a gate electrode which is formed to surround the columnar semiconductor layer (for example, JP-A-2-188966). Since the drain, the gate, and the source are arranged in the vertical direction in the SGT, the occupied area can be greatly reduced compared to the conventional planar transistor.

When an LSI (large integrated circuit) is used to form an LSI (large integrated circuit), it is necessary to use an SRAM composed of a combination of SGTs as a cache memory for the LSIs. In recent years, there has been a strong demand for a large capacity of an SRAM mounted on an LSI. Therefore, it is necessary to realize an SRAM having a small cell area even when the SGT is used.

Patent Document 2 (Japanese Laid-Open Patent Publication No. 2011-61110) shows the use of four SGTs. A Loadless 4T-SRAM formed on a bulk substrate. Figure 1 shows the equivalent circuit diagram of Loadless4T-SRAM. In addition, Fig. 20 is a plan view showing a Loadless 4T-SRAM of Patent Document 2, and Fig. 21 is a sectional view showing a Loadless 4T-SRAM of Patent Document 2.

The following uses the equivalent circuit of Loadless4T-SRAM shown in Figure 1 to show the operation principle of Loadless4T-SRAM. The Loadless4T-SRAM is composed of two access transistors belonging to the PMOS for accessing the memory and two driver transistors belonging to the NMOS for driving the memory. Composition.

In the following, an operation of holding data of "L" in the memory node (node) Qa1 and storing data of "H" in the memory node Qb1 will be described as an example of the operation of the memory unit in Fig. 1. The data holding medium word line WL1 and the bit line BL1 and BLB1 are all driven to the "H" potential. The off leak flow system of the access transistor (Qp11, Qp21) is set to be about 10 times to 1000 times larger than the turn-off leakage current of the driver transistor. Therefore, the "H" level of the memory node Qb1 is held by the turn-off leakage current flowing from the bit line BLB1 to the memory node Qb1 via the access transistor Qp21. On the other hand, the "L" level of the memory node Qa1 is stably maintained by the driver transistor Qn11.

Fig. 20 is a view showing a layout of an SRAM memory cell of Embodiment 1 of Patent Document 2. In the SRAM cell array, the unit cell UC shown in Fig. 20 is repeatedly arranged. The 21st (a) to (d) drawings respectively show the cross-sectional structures of the cut lines A-A', B-B', C-C', and D-D' of the floor plan of Fig. 20.

First, the first embodiment of Patent Document 2 will be described using FIG. 20 and FIG. The layout of the SRAM cell. An n-well belonging to the first well 601a is formed in the SRAM cell array of the substrate, and the diffusion layer on the substrate is separated by the element isolation layer 602. The first memory node Qa6 formed by the diffusion layer on the substrate is formed by the first p+ diffusion layer 603a and the first n+ diffusion layer 604a, and is connected by the first vaporization layer 613a formed on the surface of the substrate. Similarly, the second memory node Qb6 formed by the diffusion layer on the substrate is formed by the second p+ diffusion layer 603b and the second n+ diffusion layer 604b, and is connected by the second germanide layer 613b formed on the surface of the substrate. . In order to suppress leakage from the n+ diffusion layer having the same conductivity type as that of the n-well belonging to the first well 601a, the first leakage prevention layer of the conductivity type different from the first well is formed on the upper portion of the first well. The diffusion layer 601b or the second leakage prevention diffusion layer 601c. The first and second leakage preventing diffusion layers are separated by a diffusion layer on each substrate by the element isolation layer 602.

Qp16 and Qp26 are access transistors belonging to the PMOS for accessing the memory cells, and Qn16 and Qn26 are driver transistors belonging to the NMOS for driving the memory cells.

One unit cell UC includes a transistor in which two rows are arranged in two rows on a substrate. The first row is connected to the first memory node Qa6, and the access transistor Qp16 and the driver transistor Qn16 are arranged from the upper side of the figure. Further, in the second row, the access transistor Qp26 and the driver transistor Qn26 are arranged on the second memory node Qb6 from the upper side of the figure. The SRAM cell array of the present embodiment is configured by continuously arranging such unit cells UC having four transistors in the vertical direction of the figure.

A contact 610a formed on the first memory node Qa6 is extended by a node connection wiring Na6 and a gate electrode formed on the slave driver transistor Qn26. The contact 611b on the gate wiring is connected. Further, the contact 610b formed on the second memory node Qb6 is connected to the contact 611a formed on the gate wiring extending from the gate electrode of the driver transistor Qn16 by the node connection wiring Nb6. A contact 606a formed on the upper portion of the access transistor Qp16 is connected to the bit line BL6, and a contact 606b formed on the upper portion of the access transistor Qp26 is connected to the bit line BLB6. A common contact 607 formed on the gate wiring extending from the gate electrode of the access transistor Qp16 and the access transistor Qp26 is connected to the word line WL6. The contacts (608a, 608b) formed on the upper portions of the driver transistors (Qn16, Qn26) are connected to the wiring layer Vss6 belonging to the ground potential.

Next, the configuration of the SRAM cell of Patent Document 2 will be described using the cross-sectional view of Fig. 21. As shown in Fig. 21(a), an n-well belonging to the first well 601a common to the SRAM cell array is formed on the substrate, and the diffusion layer on the substrate is separated by the element isolation layer 602. In the first memory node Qa6 formed by the diffusion layer on the substrate, the first p+ drain diffusion layer 603a is formed by implanting impurities or the like, and the second memory node formed by the diffusion layer on the substrate is formed. In Qb6, the second p+ drain diffusion layer 603b is formed by implanting impurities or the like. Further, first and second silicide layers (613a, 613b) are formed on the first and second p+ drain diffusion layers (603a, 603b), respectively. A columnar layer 621a constituting the access transistor Qp16 is formed on the p+ drain diffusion layer 603a, and a columnar layer 621b constituting the access transistor Qp26 is formed on the p+ drain diffusion layer 603b.

A gate insulating film 617 and a gate electrode 618 are formed around each of the columnar layer layers. A p+ drain diffusion layer 616 is formed on the upper portion of the columnar layer by implanting impurities or the like, and a vaporization layer 615 is formed on the surface of the source diffusion layer. The contact 606a formed on the access transistor Qp16 is connected to the bit line BL6 and formed on the access power. A contact 606b on the crystal Qp26 is connected to the bit line BLB6, and a contact 607 formed on the gate wiring 618a extending from the gates of the access transistors Qp16 and Qp26 is connected to the word line WL6.

As shown in Fig. 21(b), an n-well belonging to the first well 601a common to the SRAM cell array is formed on the substrate, and the diffusion layer on the substrate is separated by the element isolation layer 602. In the first memory node Qa6 formed by the diffusion layer on the substrate, the first n+ drain diffusion layer 604a is formed by implanting impurities or the like, and the second memory node formed by the diffusion layer on the substrate is formed. In Qb6, the second n+ drain diffusion layer 604b is formed by implanting impurities or the like. Further, the first and second vaporized layers (613a, 613b) are formed on the first and second n + drain diffusion layers, respectively. The contact 611a formed on the first drain diffusion layer 604a is formed in the vicinity of the boundary between the first p+ drain diffusion layer 603a and the first n+ drain diffusion layer 604a, and is connected to the slave driver via the memory node connection wiring Nb6. The gate electrode of the crystal Qn16 extends over the gate wiring 618b.

In order to suppress leakage from the first n+ diffusion layer 604a having the same conductivity type as that of the first well toward the substrate, the first prevention of the conductivity type different from the first well is formed in the lower portion of the first n+ diffusion layer and in the upper portion of the first well. The diffusion layer 601b is leaked, and in order to suppress leakage from the second n+ diffusion layer 604b having the same conductivity type as that of the first well, the upper portion of the second n+ diffusion layer and the upper portion of the first well are different from the first well. The second conductivity-preventing leakage preventing layer 601c.

As shown in Fig. 21(c), an n-well belonging to the first well common to the SRAM cell array is formed on the substrate, and the diffusion layer on the substrate is separated by the element isolation layer 602. In the first memory node Qa6 formed by the diffusion layer on the substrate, the first n+ drain diffusion layer 604a is formed by implanting impurities or the like, and is diffused on the substrate. In the second memory node Qb6 formed by the layer, the second n+ drain diffusion layer 604b is formed by implanting impurities or the like. Further, on the surfaces of the first and second n+ drain diffusion layers (604a, 604b), first and second vaporization layers (613a, 613b) are formed, respectively. In order to suppress leakage from the first n+ diffusion layer 604a having the same conductivity type as that of the first well toward the substrate, the first prevention of the conductivity type different from the first well is formed in the lower portion of the first n+ diffusion layer and in the upper portion of the first well. The diffusion layer 601b is leaked, and in order to suppress leakage from the second n+ diffusion layer 604b having the same conductivity type as that of the first well, the upper portion of the second n+ diffusion layer and the upper portion of the first well are different from the first well. The second conductivity-preventing leakage preventing layer 601c.

A columnar layer 622a for forming the driver transistor Qn16 is formed in the 1n+th gate diffusion layer 604a, and a columnar layer 622b for forming the driver transistor Qn26 is formed in the 2n+th gate diffusion layer 604b. A gate insulating film 617 and a gate electrode 618 are formed around each of the columnar layer layers. An n+ source diffusion layer 614 is formed on the upper portion of the columnar layer by implanting impurities or the like, and a vaporization layer 615 is formed on the surface of the source diffusion layer. The contacts (608a, 608b) formed on the driver transistors (Qn16, Qn26) are all connected to the ground potential Vss6 via the wiring layer.

As shown in Fig. 21(d), an n-well belonging to the first well common to the SRAM cell array is formed on the substrate, and the diffusion layer on the substrate is separated by the element isolation layer 602. In the second memory node Qb6 formed by the diffusion layer on the substrate, the second p+ drain diffusion layer 603b and the second n+ drain diffusion layer 604b are formed by implanting impurities or the like. The second vaporization layer 613b is formed on the drain diffusion layer, and the second p+ drain diffusion layer 603b and the second n+ drain diffusion layer 604b are directly connected by the second vaporization layer 613b. In order to suppress leakage from the second n+ diffusion layer 604b having the same conductivity type as that of the first well toward the substrate, the lower portion of the second n+ diffusion layer is the upper portion of the first well. A second leakage preventing diffusion layer having a conductivity type different from that of the first well 601a is formed.

A columnar layer 622b constituting the access transistor Qp26 is formed on the second p+ drain diffusion layer 603b, and a columnar layer 622b constituting the driver transistor Qn26 is formed on the second n+ drain diffusion layer 604b. A gate insulating film 617 and a gate electrode 618 are formed around each of the columnar layer layers, and a source diffusion layer is formed by implanting impurities or the like on each of the columnar layer layers, and a surface of the source diffusion layer is formed on the surface of the source diffusion layer. Telluride layer 615. A contact 608b formed on the access transistor Qp26 is connected to the bit line BLB6, and a contact 608b formed on the driver transistor Qn26 is connected to the ground potential Vss6.

A contact 610b is formed on the gate wiring 618c extending from the gate electrode of the driver transistor Qn26, and the contact 610b is connected to the contact formed on the first drain diffusion layer via the memory node connection wiring Na6. 611a. A contact 611b is formed on the second n+ drain diffusion layer 604b, and is connected to a contact 611a formed on the gate wiring 618b extending from the gate electrode of the driver transistor Qn16 via the memory node connection wiring Nb6.

[Previous Technical Literature] [Patent Literature]

Patent Document 1: Japanese Patent Laid-Open No. Hei 2-188966

Patent Document 2: Japanese Laid-Open Patent Publication No. 2011-61110

In the 4T-SRAM cell of FIGS. 20 and 21, a dead space is generated in the up and down direction due to the word line contact formed on the gate between the access transistors, and the efficiency cannot be efficiently performed. A smaller SRAM cell is formed.

In view of the above circumstances, an object of the present invention is to realize a Loadless 4T-SRAM unit using a SGT which is smaller than a conventionally used SGT loadless 4T-SRAM.

The present invention provides a semiconductor memory device including a plurality of static memory cells in which four MOS transistors are arranged on a substrate, and each of the four MOS transistors functions as an access of the first and second PMOSs. The function of the transistor and the driver transistors of the first and second NMOS, wherein the first and second PMOS access crystal systems are used to supply charge and access the memory in order to retain the memory cell data, and the first and The driver circuit of the second NMOS is used to drive the memory node in order to read the data of the memory cell; the first and second PMOS access cell system P for supplying the charge in order to maintain the memory cell data and accessing the memory The first diffusion layer, the first columnar semiconductor layer, and the P-type second diffusion layer are arranged on the substrate in a vertical direction in a vertical direction, and the first columnar semiconductor layer is disposed on the first columnar semiconductor layer. a first gate is formed between the bottom of the first diffusion layer and the second diffusion layer formed on the upper portion of the first columnar semiconductor layer; and a first gate is formed on a sidewall of the first columnar semiconductor layer; Memory list The first and second NMOS driver cell systems for driving the memory node, the N-type third diffusion layer, the second columnar semiconductor layer, and the N-type fourth diffusion layer are arranged hierarchically on the substrate in the vertical direction, and the second The columnar semiconductor layer is disposed between the third diffusion layer formed on the bottom of the second columnar semiconductor layer and the fourth diffusion layer formed on the upper portion of the first columnar semiconductor layer. a second gate is formed on a sidewall of the second columnar semiconductor layer; the first PMOS access transistor and the first NMOS driver transistor system are adjacent to each other; and the second PMOS access transistor and the second NMOS are The driver transistor systems are arranged adjacent to each other; a first well for sharing a potential to the plurality of memory cells is provided on the substrate; and the P-type is formed at a bottom of the first PMOS access transistor The first diffusion layer and the N-type third diffusion layer formed at the bottom of the driver transistor of the first NMOS are connected to each other, and the P-type first diffusion layer and the N-type diffusion layer which are connected to each other are used. The function of the first memory node for retaining the data stored in the memory cell; and the N-type third diffusion layer for preventing leakage between the N-type third diffusion layer or the P-type first diffusion layer and the first well Or forming a bottom portion of the first leakage preventing diffusion layer having a conductivity type opposite to the first well between the P-type first diffusion layer and the first well; and the first leakage preventing diffusion layer With the aforementioned P The first diffusion layer or the N-type third diffusion layer is directly connected; the P-type first diffusion layer formed at the bottom of the second PMOS access transistor; and the N-type formed at the bottom of the driver transistor of the second NMOS The third diffusion layers are connected to each other; and the P-type first diffusion layer and the N-type third diffusion layer connected to each other function as a second memory node for holding data stored in the memory cell. In order to prevent leakage between the N-type third diffusion layer or the P-type first diffusion layer and the first well, between the N-type third diffusion layer or the P-type first diffusion layer and the first well Forming a bottom portion of the second leakage preventing diffusion layer having a conductivity opposite to that of the first well, and forming the second leakage preventing diffusion layer and the P-type first diffusion layer or the N-type third diffusion The gates are directly connected; the gates of the first and second PMOS driver transistors are connected to each other by a first gate wiring, and the first gate wiring is connected to two or more adjacent ones The gates of each of the first and second PMOS access transistors in the memory cell are connected to each other to form a word line; and each of the plurality of memory cells adjacent to the two or more groups belongs to A first contact is formed on the first gate wiring of the word line.

In the semiconductor memory device of the above aspect of the invention, in a region in which the first contact is formed on the first gate line belonging to the word line, a pillar may be disposed in the same manner as the region of the memory cell.

In the semiconductor memory device of the above aspect of the invention, the second gate wiring extending from the gate of the driver transistor of the first NMOS can function as the second memory node by the common second contact. The diffusion layer is connected; the third gate wiring extending from the gate of the driver transistor of the second NMOS is connected to the diffusion layer functioning as the first memory node by a common third contact.

In the semiconductor memory device of the above invention, it is possible to: The peripheral length of the side wall of the columnar semiconductor layer forming the driver circuits of the first and second NMOSs has a value equal to or larger than the length of the circumference of the side wall of the columnar semiconductor layer forming the first and second PMOS access transistors. Or the length of the side wall of the columnar semiconductor layer forming the driver transistors of the first and second NMOSs is equal to or smaller than the circumference of the sidewall of the columnar semiconductor layer forming the first and second PMOS access transistors. Value.

In the semiconductor memory device of the above aspect of the invention, the four MOS transistor systems may be arranged in two rows and two rows on the insulating film, and the first PMOS access transistor system may be arranged in the first row (row). a first row (column); the first NMOS driver crystal system is arranged in the second row and the first row; the second PMOS access transistor system is arranged in the first column and the second row; and the second NMOS driver electro-crystal system Arranged in the second row of the second column.

In the semiconductor memory device of the above aspect of the invention, the first PMOS access transistor and the second PMOS access transistor are arranged adjacent to each other in the four MOS transistor systems; and the first PMOS access transistor is formed And a direction in which one of the adjacent PMOS access transistors is orthogonal to each other, wherein the first NMOS driver transistor system is adjacent to the first PMOS access transistor; and the first PMOS access transistor In the other direction in which the adjacent directions of the second PMOS access transistors are orthogonal to each other, the driver epoch system of the second NMOS is adjacent to the access transistor of the second PMOS.

101a, 210a, 601a‧‧‧ first well

101b, 201b, 601b‧‧‧1st leakage prevention diffusion layer

101c, 201c, 601c‧‧‧2nd leakage prevention diffusion layer

102, 202, 302, 402, 502, 602‧‧‧ component separation layer

103, 103a, 103b, 203a, 203b, 603a, 603b‧‧‧p+ diffusion layer

104a, 104b, 204a, 204b, 604a, 604b‧‧‧n+ diffusion layer

106, 106a, 206a, 306a, 406a, 506a, 606a, 106b, 206b, 306b, 406b, 506b, 606b‧‧‧ access to the contacts on the columnar layer of the transistor

107, 507‧‧‧ character line contacts

108a, 208a, 308a, 408a, 508a, 608a, 108b, 208b, 308b, 408b, 508b, 608b‧‧‧ drive contacts on the columnar layer of the transistor

110a, 210a, 410a, 610a, 110b, 210b, 410b, 610b‧‧‧ contacts on the memory node

111a, 211a, 411a, 611a, 111b, 211b, 411b, 611b‧‧‧ gate wiring contacts

310a, 310b, 510a, 510b‧‧‧ common contacts

113, 113a, 113b, 115, 213a, 213b, 215, 613a, 613b, 615‧‧‧ 矽 层

114, 214, 614‧‧‧ pillar upper N+ diffusion layer

116, 216, 616‧‧‧ pillar upper P+ diffusion layer

117, 217, 617‧‧ ‧ gate insulation film

118, 218, 618‧‧ ‧ gate electrode

118a, 118b, 218c, 218a, 218b, 118c, 618a, 618b, 618c‧‧‧ gate wiring

118a, 218a, 318a, 418a, 518a‧‧‧ character lines

119‧‧‧ Mask layer such as oxide film

120‧‧‧矽

121, 121a, 121b, 221a, 221b, 621a, 621b‧‧‧ access to the transistor columnar layer

122a, 122b, 222a, 222b, 622a, 622b‧‧‧ drive transistor columnar layer

124, 224, 624‧‧‧P+ injection area

125, 225, 625‧‧‧N+ injection area

131‧‧‧矽Oxide film

132‧‧‧矽Nitrided film sidewall

133‧‧‧Resist

134‧‧‧矽 nitride film

BL1, BL3, BL4, BL5, BL6, BLB1, BLB3, BLB4, BLB5, BLB6‧‧‧ bit lines

Na1, Nb1, Na2, Nb2, Na4, Nb4, Nb6, Nb6‧‧‧ node connection wiring

P20‧‧‧Power potential wiring

Qa1, Qb1, Qa2, Qb2, Qa3, Qb3, Qa4, Qb4, Qa5, Qb5, Qa6, Qb6‧‧‧ memory nodes

Qp11, Qp21, Qp12, Qp22, Qp13, Qp23, Qp14, Qp24, Qp15, Qp25, Qp16, Qp26‧‧‧ access transistor

Qn11, Qn21, Qn12, Qn22, Qn13, Qn23, Qn14, Qn24, Qn15, Qn16, Qn26‧‧‧ drive transistor

Vss1, Vss2, Vss3, Vss4, Vss5, Vss6‧‧‧ Ground potential line

Fig. 1 is an equivalent circuit showing the SRAM of the present invention.

Fig. 2 is a plan view showing an SRAM of a first embodiment of the present invention.

Fig. 3 (a) and (b) are plan views showing an SRAM of a first embodiment of the present invention.

Fig. 4(a) is a cross-sectional view showing the SRAM of the first embodiment of the present invention.

Fig. 4(b) is a cross-sectional view showing the SRAM of the first embodiment of the present invention.

Fig. 4(c) is a cross-sectional view showing the SRAM of the first embodiment of the present invention.

Fig. 4 (d) is a cross-sectional view showing the SRAM of the first embodiment of the present invention.

Fig. 4(e) is a cross-sectional view showing the SRAM of the first embodiment of the present invention.

Fig. 5(a) is a cross-sectional view showing the SRAM of the first embodiment of the present invention.

Fig. 5(b) is a cross-sectional view showing the SRAM of the first embodiment of the present invention.

Fig. 5(c) is a cross-sectional view showing the SRAM of the first embodiment of the present invention.

Fig. 5(d) is a cross-sectional view showing the SRAM of the first embodiment of the present invention.

Fig. 6 (a) and (b) are process diagrams showing the manufacturing method of the present invention in order of steps.

Fig. 7 (a) and (b) are process diagrams showing the manufacturing method of the present invention in order of steps.

Fig. 8 (a) and (b) are process diagrams showing the manufacturing method of the present invention in order of steps.

Fig. 9 (a) and (b) are process diagrams showing the manufacturing method of the present invention in order of steps.

Fig. 10 (a) and (b) are process diagrams showing the manufacturing method of the present invention in order of steps.

Fig. 11 (a) and (b) are process diagrams showing the manufacturing method of the present invention in order of steps.

Figure 12 (a) and (b) show the steps of the manufacturing method of the present invention in order of steps. Figure.

Fig. 13 (a) and (b) are process diagrams showing the manufacturing method of the present invention in order of steps.

Fig. 14 (a) and (b) are process diagrams showing the manufacturing method of the present invention in order of steps.

Figure 15 is a plan view showing an SRAM of a second embodiment of the present invention.

Figure 16 is a plan view showing an SRAM of a third embodiment of the present invention.

Figure 17 is a plan view showing an SRAM of a fourth embodiment of the present invention.

Figure 18 is a plan view showing an SRAM of a fifth embodiment of the present invention.

Fig. 19 (a) and (b) are plan views showing an SRAM of a fifth embodiment of the present invention.

Figure 20 is a plan view showing an SRAM using a conventional SGT.

Fig. 21(a) is a cross-sectional view showing an SRAM using a conventional SGT.

Fig. 21(b) is a cross-sectional view showing an SRAM using a conventional SGT.

Fig. 21(c) is a cross-sectional view showing an SRAM using a conventional SGT.

Fig. 21 (d) is a cross-sectional view showing an SRAM using a conventional SGT.

[Example 1]

Fig. 1 is an equivalent circuit diagram showing a memory unit of a Loadless 4T-SRAM used in the present invention. In Fig. 1, BL1 and BLB1 display the bit line, WL1 shows the word line, Vss1 shows the ground potential, and Qp11 and Qp21 show the function of charging the memory node to "H" in order to access the memory. The access transistor, Qn11 and Qn21 show the driver transistor that drives the memory node in order to read the data of the memory cell, and Qa1 and Qb1 show the memory used to memorize the data. node.

Fig. 2 is a layout view showing an SRAM memory cell in Embodiment 1 of the present invention. The unit cell UC shown in Fig. 2 is repeatedly arranged in the SRAM memory cell array. Figs. 4(a) to 4(d) show the cross-sectional structures of the cutting lines A-A', B-B', C-C', and D-D' of the floor plan of Fig. 2, respectively.

First, the layout of this embodiment will be described with reference to Figs. 2 and 4. An n-well belonging to the first well 101a is formed in the SRAM cell array of the substrate, and the diffusion layer on the substrate is separated by the element isolation layer 102 composed of an insulating film such as an oxide film. The first memory node Qa1 formed by the diffusion layer on the substrate is formed by the first p+ diffusion layer 103a and the first n+ diffusion layer 104a, and is connected by the first germanide layer 113a formed on the surface of the substrate. Similarly, the second memory node Qb1 formed by the diffusion layer on the substrate is formed by the second p+ diffusion layer 103b and the second n+ diffusion layer 104b, and is formed by the second germanide layer 113b formed on the surface of the substrate. connection. In order to suppress leakage from the n+ diffusion layer having the same conductivity type as that of the n-well belonging to the first well 101a, the lower portion of the first and second n+ diffusion layers and the upper portion of the first well 101a are formed differently from the first well. The conductive type first leakage preventing diffusion layer 101b and the second leakage preventing diffusion layer 101c. The first and second leakage preventing diffusion layers are separated by the diffusion layer on each substrate by the element isolation layer 102.

Qp11 and Qp21 are access transistors belonging to the PMOS for accessing the memory cells, and Qn11 and Qn21 are the driver transistors of the NMOS for driving the memory cells.

In the present embodiment, one unit cell UC is provided with a transistor in which two rows and two rows are arranged on a substrate. In the first row, the access transistor Qp11 and the driver transistor Qn11 are arranged on the first memory node Qa1 from the upper side of the figure. In addition, in In the second row, the access transistor Qp21 and the driver transistor Qn21 are arranged on the second memory node Qb1 from the upper side of the figure. The SRAM cell array of the present embodiment is configured by continuously arranging such unit cells UC having four transistors in the vertical direction of the figure.

The contact 110a formed on the first memory node Qa1 is connected to the contact 111b formed on the gate wiring extending from the gate electrode of the driver transistor Qn21 via the node connection wiring Na1. Further, the contact 110b formed on the second memory node Qb1 is connected to the contact 111a formed on the gate wiring extending from the gate electrode of the driver transistor Qn11 via the node connection wiring Nb1. The contact 106a formed on the upper portion of the access transistor Qp11 is connected to the bit line BL1, and the contact 106b formed on the upper portion of the access transistor Qp21 is connected to the bit line BLB1. The gate wirings 118a extending from the gate electrodes of the access transistors Qp11 and Qp21 are connected as a word line to a plurality of memory cells adjacent in the lateral direction. The contacts (108a, 108b) formed on the upper portion of the driver transistors (Qn11, Qn21) are connected to the wiring layer Vss1 belonging to the ground potential.

Further, in order to share the wiring of the bit line and the ground potential, it is preferable to connect the layers of the wiring which is higher than the node connection wiring of the wiring in each of the memory cells.

In addition, as an example of the configuration of the above-described hierarchical wiring, the node connection wiring (Na1), the node connection wiring (Nb1), and the ground potential wiring Vss1 can be realized, and the layer wiring lower than the bit line (BL1, BLB1) can be realized. The configuration is such that the wires do not come into contact with contacts that should not be in contact.

The second figure shows the n+ implant region 125 and the p+ implant region 124. In the SRAM cell array region of the embodiment, an n+ implant region 125 and a p+ implant region are formed. The pattern of 124 is formed by simple lines and spaces. Therefore, the influence of the size offset or the alignment offset is small, and the margin of the size near the boundary between the n+ implanted region and the p+ implanted region can be suppressed to a minimum, so as to be effective in terms of the schema. The length of the SRAM cell in the longitudinal direction (the length of the connection direction of each SRAM cell) is reduced.

Figure 3(a) is a plan view showing a portion of an SRAM memory cell array composed of a plurality of SRAM memory cells. In the Cell array Area in the figure, a plurality of memory cells are arranged in the horizontal direction, and word lines 118a are common to a plurality of memory cells arranged in the horizontal direction. The word line is connected to the wiring of the upper layer by the contact 107 formed in the Contact Area, and is patterned by the wiring layer as needed. Therefore, unlike the SRAM cell of Patent Document 2, since it is not necessary to form a contact for a word line in each cell, the area of the SRAM cell can be reduced.

By connecting a plurality of cells to the word line 118a, in a cell farther from the word line contact 107, there is a possibility that the read or write delay is caused by the delay of the signal of the word line. Therefore, the number of cells connected to the word line can be determined within the range of the problem of no delay in reading or writing.

Figure 3(b) is a plan view showing a portion of an SRAM cell array composed of a plurality of SRAM cells in other cases. In the cell array region in the figure, a plurality of memory cells are also arranged in the lateral direction, and word cells 118a are commonly formed in the memory cells arranged in the lateral direction. However, in Fig. 3(b), even in the contact region, pillars are arranged in the same manner as the cell array region. Thus, by arranging the pillars in the same pattern as the memory cell region in the contact region, even in the joint region, the regularity of the same pillar arrangement in the cell array can be maintained, so that the adjacent nodes can be adjacent to each other. Pillars of the area and pillars not adjacent to the joint area The difference in size between the two is reduced, and the error of the characteristics of the SGT adjacent to the contact region and the characteristics of the SGT not adjacent to the contact region can be minimized.

In the third (a) and (b) of FIG. 3, the configuration of the word line and the word line contact has been described using the layout of the first embodiment as an example. However, the layout of the first embodiment is not limited to the above. In the layout of other embodiments, the same character line and word line contact configuration can also be applied.

In the present invention, the source and drain of each of the transistors constituting the SRAM are defined as follows. Regarding the driver transistor (Qn11, Qn21), a diffusion layer formed on an upper portion of the columnar semiconductor layer connected to the ground potential is defined as a source diffusion layer, and a diffusion layer formed under the columnar semiconductor layer is defined as Bungee diffusion layer. Regarding the access transistor (Qn11, Qp21), the diffusion layer formed on the upper portion of the columnar semiconductor layer and the diffusion layer formed on the lower portion may become the source or the drain depending on the operation state, but for the sake of convenience A diffusion layer formed on an upper portion of the columnar semiconductor layer is defined as a source diffusion layer, and a diffusion layer formed on a lower portion of the columnar semiconductor layer is defined as a drain diffusion layer.

Next, the configuration of the SRAM of the present invention will be described with reference to the cross-sectional structure of Fig. 4. As shown in FIG. 4(a), an n-well belonging to the first well 101a common to the SRAM cell array is formed on the substrate, and the diffusion layer on the substrate is formed of an insulating film made of an oxide film or the like. The layer 102 is separated and separated. In the first memory node Qa6 formed by the diffusion layer on the substrate, the first p+ drain diffusion layer 103a is formed by implanting impurities or the like, and the second memory node formed by the diffusion layer on the substrate is formed. In Qb1, the second p+ drain diffusion layer 103b is formed by implanting impurities or the like. Further, the first and second vaporized layers (113a, 113b) are formed on the first and second p+ drain diffusion layers (103a, 103b), respectively. Formed on the p+ drain diffusion layer 103a The columnar layer 121a constituting the access transistor Qp11 is formed, and the columnar layer 121b constituting the access transistor Qp21 is formed on the p + drain diffusion layer 103b.

A gate insulating film 117 and a gate electrode 118 are formed around each of the columnar layer layers. A p+ source diffusion layer 116 is formed on the upper portion of the columnar layer by implanting impurities or the like, and a vapor layer 115 is formed on the surface of the source diffusion layer. The contact 106a formed on the access transistor Qp11 is connected to the bit line BL1, and the contact 106b formed on the access transistor Qp21 is connected to the bit line BLB1. The gate wiring 118a extending from the gate electrodes of the access transistors Qp11 and Qp21 is connected as a word line to a plurality of memory cells adjacent to the lateral direction.

As shown in FIG. 4(b), an n-well belonging to the first well 101a common to the SRAM cell array is formed on the substrate, and the diffusion layer on the substrate is formed of an insulating film made of an oxide film or the like. The layer 102 is separated and separated. In the first memory node Qa1 formed by the diffusion layer on the substrate, the first n+ drain diffusion layer 104a is formed by implanting impurities or the like, and the second memory node formed by the diffusion layer on the substrate is formed. In Qb1, the second n+ drain diffusion layer 104b is formed by implanting impurities or the like. Further, the first and second vaporized layers (113a, 113b) are formed on the first and second n + drain diffusion layers, respectively. The contact 111a formed on the first drain diffusion layer 104a is formed in the vicinity of the boundary between the first p+ drain diffusion layer 103a and the first n+ drain diffusion layer 104a, and is connected to the slave driver via the memory node connection wiring Na1. The gate electrode of the crystal Qn11 extends over the gate wiring 118b.

In order to suppress leakage from the first n+ diffusion layer 104a having the same conductivity type as that of the first well toward the substrate, the first prevention of the conductivity type different from the first well is formed in the lower portion of the first n+ diffusion layer and in the upper portion of the first well. The diffusion layer 101b is leaked, and in order to suppress leakage from the second n+ diffusion layer 104b having the same conductivity type as that of the first well toward the substrate, A second leakage preventing diffusion layer 101c having a conductivity type different from that of the first well is formed in a lower portion of the second n+ diffusion layer and in the upper portion of the first well. The bottom portions of the first and second leakage preventing diffusion layers are formed to be shallower than the bottom of the element isolation layer, and the first and second leakage preventing diffusion layers are separated by the element separation layer.

As shown in FIG. 4(c), an n-well belonging to the first well common to the SRAM cell array is formed on the substrate, and the diffusion layer on the substrate is separated by the element isolation layer 102. In the first memory node Qa1 formed by the diffusion layer on the substrate, the first n+ drain diffusion layer 104a is formed by implanting impurities or the like, and the second memory node formed by the diffusion layer on the substrate is formed. In Qb1, the second n+ drain diffusion layer 104b is formed by implanting impurities or the like. Further, on the surfaces of the first and second n + drain diffusion layers (104a, 104b), first and second vaporization layers (113a, 113b) are formed, respectively. In order to suppress leakage from the first n+ diffusion layer 104a having the same conductivity type as that of the first well toward the substrate, the first prevention of the conductivity type different from the first well is formed in the lower portion of the first n+ diffusion layer and in the upper portion of the first well. The diffusion layer 101b is leaked, and in order to suppress leakage from the second n+ diffusion layer 104b having the same conductivity type as that of the first well, the upper portion of the second n+ diffusion layer and the upper portion of the first well are different from the first well. The second conductivity-preventing leakage preventing layer 101c. The bottom portions of the first and second leakage preventing diffusion layers are formed to be shallower than the bottom of the element isolation layer, and the first and second leakage preventing diffusion layers are separated by the element separation layer.

A columnar layer 122a for forming the driver transistor Qn11 is formed in the 1n+th gate diffusion layer 104a, and a columnar layer 122b for forming the driver transistor Qn21 is formed in the 2n+th gate diffusion layer 104b. A gate insulating film 117 and a gate electrode 118 are formed around each of the columnar layer layers. In the upper portion of the columnar layer, an n+ source diffusion layer 114 is formed by implanting impurities or the like, and a germanium is formed on the surface of the source diffusion layer. Compound layer 115. The contacts (108a, 108b) formed on the driver transistors (Qn11, Qn21) are all connected to the ground potential Vss1 via the wiring layer.

As shown in FIG. 4(d), an n-well belonging to the first well common to the SRAM cell array is formed on the substrate, and the diffusion layer on the substrate is separated by the element isolation layer 102. In the second memory node Qb1 formed by the diffusion layer on the substrate, the second p+ drain diffusion layer 103b and the second n+ drain diffusion layer 104b are formed by implanting impurities or the like. The second vaporization layer 113b is formed on the drain diffusion layer, and the second p+ drain diffusion layer 103b and the second n+ drain diffusion layer 104b are directly connected by the second vaporization layer 113b. In order to suppress leakage from the second n+ diffusion layer 104b having the same conductivity type as that of the first well to the substrate, a second conductivity type is formed on the lower portion of the second n+ diffusion layer and has a conductivity type different from that of the first well 101a. The leakage diffusion layer 101c is prevented from leaking. In the present embodiment, although the N+ drain diffusion layer and the P+ drain diffusion layer are connected by a germanide, the contact resistance between the N+ drain diffusion layer and the P+ drain diffusion layer is extremely small, and no germanide is formed. . In addition, the N+ drain diffusion layer and the P+ drain diffusion layer may be connected by a contact at the N+ drain diffusion layer instead of the germanium to connect the N+ drain diffusion layer and the P+ drain diffusion layer, or by other methods. The N+ drain diffusion layer and the P+ drain diffusion layer are connected.

Fig. 4(e) shows the cross-sectional structure of E-E' in Fig. 3(a). A P+ drain diffusion layer 103 composed of a germanium layer and a right side cell is formed on the substrate. A vaporized layer 113 is formed on each of the drain diffusion layers. A columnar layer 121 for forming an access transistor is formed on each of the P+ drain diffusion layers 103. A gate insulating film 117 and a gate electrode 118 are formed around each of the columnar layer layers. A P+ source diffusion layer region 116 is formed in the upper portion of the columnar layer by implanting impurities or the like, and a vaporization layer 115 is formed on the surface of the source diffusion layer region. Formed in each deposit A contact 106 on the take-up transistor is connected to the bit line, and a contact 107 formed on the word line 118a is connected to a lower resistance word line formed by the wiring layer of the upper layer.

The columnar tantalum layer 121b constituting the access transistor Qp21 is formed on the second p+ drain diffusion layer 103b, and the columnar tantalum layer 122b constituting the driver transistor Qn21 is formed on the second n+ drain diffusion layer 104b. A gate insulating film 117 and a gate electrode 118 are formed around each of the columnar layer layers, and a source diffusion layer is formed by implanting impurities or the like on each of the columnar layer layers, and a surface of the source diffusion layer is formed on the surface of the source diffusion layer. Telluride layer 115. The contact 106b formed on the access transistor Qp21 is connected to the bit line BLB1, and the contact 108b formed on the driver transistor Qn21 is connected to the ground potential Vss1.

A contact 111b is formed on the gate wiring 118c extending from the gate electrode of the driver transistor Qn21, and the contact 111b is connected to the contact formed on the first drain diffusion layer via the memory node connection wiring Na1. 110a. A contact 110b is formed on the second n+ drain diffusion layer 104b or the second p+ drain diffusion layer 103b, and is connected to a gate electrode formed from the gate electrode of the driver transistor Qn11 via the memory node connection wiring Nb1. A contact 111a on the wiring 118b.

As shown in the fifth (a) to (d) diagrams, the first well 201a is p-well, and the first leakage preventing diffusion layer 201b and the second leakage prevention are formed between the p+ diffusion layer and the first well. In the structure of the N-type diffusion layer of the diffusion layer 201c, an SRAM cell can also be formed. At this time, the first leakage preventing diffusion layer 201b is formed on the lower portion of the p+ drain diffusion layer 203a and the upper portion of the first well, and the second prevention is formed on the lower portion of the p+ drain diffusion layer 203b and the upper portion of the first well. Leakage of the diffusion layer 201c suppresses leakage from the diffusion layer to the first well.

An example of a method of manufacturing the semiconductor device of the present invention will be described below with reference to FIGS. 6 to 14. In each of the figures, (a) shows a plan view, and (b) shows a cross-sectional view between D-D'.

As shown in Fig. 6, a ruthenium nitride film or the like is formed on a substrate, and a pattern of columnar ruthenium layers (121a, 122a, 121b, 122b) is formed by photolithography, and etching is performed. Thereby, a tantalum nitride film mask 119 and columnar tantalum layers (121a, 122a, 121b, 122b) are formed. Next, an n-well belonging to the first well 101a is formed in the SRAM cell array by implanting impurities or the like.

The element isolation layer 102 is formed as shown in FIG. The element isolation layer is formed by first etching a trench pattern, and burying an insulating film such as an oxide film in a trench pattern by CVD (Chemical Vapor Deposition) or the like to deposit an excess oxide film on the substrate. It is formed by a method of removing by dry etching or wet etching or the like. Thereby, a pattern of the diffusion layers that become the first memory node Qa1 and the second memory node Qb1 is formed on the substrate.

As shown in Fig. 8, impurities are introduced into the p+ implanted region 124 and the n+ implanted region 125 by ion implantation or the like, respectively, and a drain diffusion layer (103a, 103b, 104a, 104b) of a lower portion of the columnar germanium layer is formed on the substrate. ). The second leakage preventing diffusion layer 101c is formed in order to suppress leakage from the n+ diffusion layer 104b having the same conductivity type as that of the n-well belonging to the first well 101a toward the substrate. The second leakage preventing diffusion layer 101c can be formed by performing impurity implantation or the like by using a mask of the n+ implantation region 125.

As shown in Fig. 9, the gate insulating film 117 and the gate conductive film 118 are formed into a film. The gate insulating film 117 is formed by an oxide film or a High-k film. Further, the gate conductive film is formed by a polysilicon or a metal film or a stacked structure.

As shown in Fig. 10, a gate wiring pattern is formed by photolithography using a resist 133 or the like.

As shown in Fig. 11, the gate conductive film 118 and the gate insulating film 117 are removed by etching with the resist 133 as a mask. Thereby, gate wirings (118a to 118c) are formed. Thereafter, the mask 19 on the pillars is removed.

As shown in Fig. 12, an insulating film such as a tantalum nitride film is formed, and then etchback is performed, and the sidewalls and gates of the columnar layer are formed by an insulating film 134 such as a tantalum nitride film. The side wall of the pole electrode is covered.

As shown in Fig. 13, impurities are introduced into the p+ implanted region 124 and the n+ implanted region 125 by ion implantation or the like to form source diffusion layers (114, 116) on the upper portion of the columnar layer. Next, a metal such as Ni is sputter-plated and heat-treated to form a telluride layer (113a, 113b) on the drain diffusion layer and a vaporization layer 115 on the source diffusion layer on the upper portion of the columnar layer. .

Here, by insulating the insulating film 134 such as a tantalum nitride film covering the side walls of the columnar layer and the gate electrode, it is possible to suppress the between the gate-gate and the source-gate due to the germanide layer. Short circuit.

As shown in Fig. 14, after forming the tantalum oxide film belonging to the interlayer film, contacts (106a, 106b, 108a, 108b, 110a, 110b, 111a, 111b) are formed.

(Example 2)

Fig. 15 shows the SRAM layout of Embodiment 2. The point different from the first embodiment in this embodiment is that the shape of the columnar layer forming the access transistor is different from the size of the columnar layer forming the driver transistor. In the Loadless 4T-SRAM of the present invention, it is necessary to set the leakage current of the access transistor to be larger than the leakage current of the driver transistor. As increasing the leakage current of the access transistor One means is to increase the leakage current by setting the columnar layer of the access transistor to be larger as shown in Fig. 15. The shape of the columnar layer is not a circle but an elliptical shape.

On the other hand, when the read margin is to be improved, the read margin can be improved by increasing the current of the driver transistor by forming the columnar germanium layer of the driver transistor to be large.

In the present embodiment, the layout of the pillars similar to those of the first embodiment is used as an example. However, the layout of the first embodiment is not limited to the first embodiment, and the present embodiment is also applicable to the layout of the other embodiments.

The other points are the same as those of the first embodiment, and therefore the description thereof will be omitted.

(Example 3)

Figure 16 shows the layout of the SRAM cell of Embodiment 3. In the present embodiment, the following points are different from the first embodiment. The Qa3 of the memory node formed by the first diffusion layer on the substrate and the gate wiring extending from the gate electrode of the driver transistor Qn23 are connected by a common contact 310a formed by the two. The Qb3 of the memory node formed by the second diffusion layer on the substrate and the gate wiring extending from the gate electrode of the driver transistor Qn13 are connected by a common contact 310b formed by the two. As described above, by directly connecting the gate and the memory node by the contact instead of the wiring layer, the number of contacts in the SRAM cell can be reduced, so that the cell can be reduced by adjusting the configuration of the columnar layer or the contact. area.

As an example of the configuration of the hierarchical wiring, the wiring of the following layers can be realized to form Vss3, and the wiring of the upper layer can form the bit lines (BL3, BLB3). In addition, in this embodiment, the node connection wiring and the node connection wiring are connected by a contact point. form.

In the present embodiment, the layout of the pillars similar to those of the first embodiment is used as an example. However, the layout is not limited to the layout, and the present embodiment is also applicable to other layouts.

The other points are the same as those of the first embodiment, and therefore the description thereof will be omitted.

(Example 4)

Figure 17 shows the layout of the SRAM cell of Embodiment 4. In the present embodiment, it differs from Embodiment 1 in the following points. In the first embodiment, in the memory node Qa1, the contact 110a is disposed only adjacent to the driver transistor Qn11, but on the memory node Qb1, the contact 110b is disposed in the driver transistor Qn21 and the access transistor Qp21. On the diffusion layer. Due to the asymmetry of this layout, asymmetry is generated in the characteristics of the SRAM cell, and the operation margin is narrowed. In this embodiment, the access transistor Qp14, the contacts (410a, 411a) and the driver transistor Qn14 on the first memory node Qa4 and the access transistor Qp24 and the contacts (410b) on the second memory node Qb4 are present. The arrangement of 411b) and the driver transistor Qn24 is symmetrical, so that there is no deterioration of the operation margin due to the asymmetry as described above, and an SRAM cell having a wider operation margin can be achieved.

Further, in order to share the wiring of the bit line and the ground potential, it is preferably a layer that is disposed above the node connection wiring of the wiring in each of the memory cells in order to share the wiring with the other memory cells. In the present embodiment, the node connection wiring is formed by a contact.

As an example of the configuration of the hierarchical wiring, the wiring of the following layers can be realized to form the wiring of Vss4 and the above layers to form the bit lines (BL4, BLB4).

(Example 5)

Figure 18 shows the layout of the SRAM cell of Embodiment 5. In the present embodiment, as in the fourth embodiment, the layout is symmetrical, so that an SRAM cell having a wide operation margin can be achieved. Further, in the same manner as in the third embodiment, the Qa5 of the memory node formed by the first diffusion layer on the substrate and the gate wiring extending from the gate electrode of the driver transistor Qn25 are connected by the commonality of the two. Point 510a is connected, and the Qb5 of the memory node formed by the second diffusion layer on the substrate and the gate wiring extending from the gate electrode of the driver transistor Qn15 are connected by the common contact 510b And connected.

Further, in order to share the wiring of the bit line and the ground potential, it is preferably a layer that is disposed above the node connection wiring of the wiring in each of the memory cells in order to share the wiring with the other memory cells. In the present embodiment, the node connection wiring is formed by a contact.

As an example of the configuration of the hierarchical wiring, the wiring of the following layers can be realized to form Vss5, and the wiring of the upper layer can form the bit lines (BL5, BLB5). Further, in the present embodiment, the node connection wiring Na5 and the node connection wiring Nb5 are formed by contacts.

Figure 19(a) is a plan view showing a portion of an array of SRAM memory cells composed of a plurality of SRAM memory cells. In the cell array region in the figure, a plurality of memory cells are arranged in the lateral direction, and among the plurality of memory cells arranged in the lateral direction, the word line 518a is commonly used. The word line is connected to the wiring of the upper layer by the contact 507 formed in the contact region, and the wiring layer substrate is used as needed. Therefore, unlike the SRAM cell of Patent Document 2, since it is not necessary to form a contact for a word line in each cell, the area of the SRAM cell can be reduced.

By connecting a plurality of cells to the word line 518a, in the cell farther from the word line contact 507, there is a possibility that the read or write delay is caused by the delay of the signal of the word line. Therefore, the number of cells connected to the word line can be determined within the range of the problem of no delay in reading or writing.

Figure 19(b) is a plan view showing a portion of an SRAM cell array composed of a plurality of SRAM cells in other cases. In the cell array region in the figure, a plurality of memory cells are also arranged in the lateral direction, and word cells 518a are commonly formed in the memory cells arranged in the lateral direction. However, in Fig. 19(b), even in the contact region, pillars are arranged in the same manner as the cell array region. By arranging the pillars in the contact region as described above, it is possible to minimize the error of the characteristics of the SGT adjacent to the contact region and the characteristics of the SGT not adjacent to the contact region.

As described above, according to the present invention, in the static type memory cell formed using four MOS transistors, the MOS transistor system is an SGT in which a drain, a gate, and a source are arranged in a vertical direction, and A memory having a very small memory can be realized by forming a gate of the access transistor as a word line in a plurality of cells adjacent to the horizontal direction, and forming a contact for the word line by a plurality of cells. CMOS type Loadless4T-SRAM with cell area.

107‧‧‧ character line contacts

118a‧‧‧gate wiring

118a‧‧‧ character line

Claims (6)

A semiconductor memory device comprising a plurality of static memory cells in which four MOS transistors are arranged on a substrate, and each of the four MOS transistors functions as an access transistor for the first and second PMOS, and The functions of the first and second NMOS driver transistors, the first and second PMOS access crystal systems for supplying charge and accessing the memory for holding the memory cell data, and the first and second NMOS drivers The electro-crystal system is used to drive the memory node in order to read the data of the memory cell; in the first and second PMOS access transistors, the P-type first diffusion layer, the first columnar semiconductor layer, and the P-type second The diffusion layer is arranged on the substrate in a vertical direction, and the first columnar semiconductor layer is disposed on the first diffusion layer formed on the bottom of the first columnar semiconductor layer, and is formed in the first columnar shape. a first gate is formed between the second diffusion layers on the upper portion of the semiconductor layer, and a sidewall is formed on the sidewall of the first columnar semiconductor layer. The first and second NMOS driver transistors have N-type third diffusion. Layer, second columnar semiconductor layer and N-type fourth The diffusion layer is arranged hierarchically on the substrate in the vertical direction, and the second columnar semiconductor layer is disposed on the third diffusion layer formed on the bottom of the second columnar semiconductor layer, and is formed in the second columnar shape. a second gate is formed between the fourth diffusion layers on the upper portion of the semiconductor layer, and a second gate is formed on a sidewall of the second columnar semiconductor layer; and the first PMOS access transistor and the first NMOS driver are in contact with each other Adjacent arrangement; the second PMOS access transistor and the second NMOS driver The crystal systems are arranged adjacent to each other; a first well for sharing a potential to the substrate to the plurality of memory cells is formed on the substrate; and the P-type first diffusion is formed at a bottom of the first PMOS access transistor. The layer and the N-type third diffusion layer formed on the bottom of the driver transistor of the first NMOS are connected to each other; and the P-type first diffusion layer and the N-type diffusion layer connected to each other serve to maintain memory The function of the first memory node of the data of the memory cell; and the N-type third diffusion layer or the P-type in order to prevent leakage between the N-type third diffusion layer or the P-type first diffusion layer and the first well A bottom portion of the first leakage preventing diffusion layer having a conductivity type opposite to the first well is formed between the first diffusion layer and the first well, and the first leakage preventing diffusion layer is a P-type first diffusion layer or an N-type third diffusion layer is directly connected; the P-type first diffusion layer formed at the bottom of the second PMOS access transistor and the bottom portion formed at the bottom of the second NMOS driver transistor N-type third diffusion layer Connecting; the P-type first diffusion layer and the N-type third diffusion layer connected to each other function as a second memory node for holding data stored in the memory cell; and in order to prevent the N-type third diffusion layer Or leakage between the P-type first diffusion layer and the first well is formed in a shallower manner between the N-type third diffusion layer or the P-type first diffusion layer and the first well than the element isolation layer 1st a bottom of the second leakage preventing diffusion layer of the opposite conductivity type; the second leakage preventing diffusion layer is directly connected to the P-type first diffusion layer or the N-type third diffusion layer; and the first and the second PMOS driver are electrically connected The gates of the crystals are connected to each other by a first gate wiring, and the first gate wiring is formed by the first and second PMOS of the plurality of memory cells adjacent to each other. The gates of each of the access transistors are connected to each other to form a word line; and the first contact is formed on the first gate wiring belonging to the word line in a plurality of adjacent memory cells. The semiconductor memory device according to the first aspect of the invention, wherein the region in which the first contact is formed on the first gate line belonging to the word line is arranged in the same manner as the region of the memory cell There are pillars. The semiconductor memory device according to the first aspect of the invention, wherein the second gate wiring extending from the gate of the driver transistor of the first NMOS is used as the second memory by a common second contact The diffusion layer connection of the function of the node; the third gate wiring extending from the gate of the driver transistor of the second NMOS is connected to the diffusion layer functioning as the first memory node by the common third contact. The semiconductor memory device according to claim 1, wherein a length of a side wall of the columnar semiconductor layer forming the driver transistors of the first and second NMOSs is equal to or larger than a length of the first and second PMOSs. a value of a length of a circumference of a side wall of the columnar semiconductor layer of the access transistor; or a columnar half of the driver transistor forming the first and second NMOSs The length of the circumference of the side wall of the conductor layer has a value equal to or smaller than the length of the circumference of the side wall of the columnar semiconductor layer forming the first and second PMOS access transistors. The semiconductor memory device according to claim 1, wherein the four MOS electro-crystal systems are arranged in two rows and two rows, and the first PMOS access crystal system is arranged in the first row and the first row; The driver circuit of the 1 NMOS is arranged in the first row of the second column; the access cell system of the second PMOS is arranged in the second row of the first column; and the driver cell system of the second NMOS is arranged in the second row and the second row. The semiconductor memory device according to claim 1, wherein the first PMOS access transistor of the four MOS transistor systems is adjacent to the access transistor of the second PMOS, and is stored in the first PMOS. In a direction in which one of the adjacent transistors of the second PMOS access transistor is orthogonal to each other, the first NMOS driver transistor system is adjacent to the first PMOS access transistor; and the first PMOS is stored. In the other direction in which the adjacent direction of the transistor and the access transistor of the second PMOS are orthogonal to each other, the driver epoch system of the second NMOS is adjacent to the access transistor of the second PMOS.