TW201320275A - Chip package structure - Google Patents
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Abstract
本發明揭露一種晶片封裝結構，包含一晶片、一保護層、複數凸塊、一絕緣薄膜層、一可撓性基板及一封裝膠體。其中，該可撓性基板具有複數個引腳與該等凸塊對應電性連接，該保護層及該等凸塊均形成於該晶片上，該絕緣薄膜層形成於該保護層上，且相鄰之各該凸塊間之該絕緣薄膜層具有至少一凹槽，藉此，將可減少凸塊析出之離子產生遷移現象而造成的電性短路或漏電流問題。The invention discloses a chip package structure comprising a wafer, a protective layer, a plurality of bumps, an insulating film layer, a flexible substrate and an encapsulant. The flexible substrate has a plurality of pins electrically connected to the bumps, and the protective layer and the bumps are formed on the wafer, and the insulating film layer is formed on the protective layer, and the phase The insulating film layer between the adjacent bumps has at least one groove, thereby reducing the problem of electrical short circuit or leakage current caused by the phenomenon of ion migration caused by the protrusion of the bump.
Description
本發明係關於一種晶片封裝結構；特別是一種利用捲帶自動接合封裝技術所製成之晶片封裝結構。The present invention relates to a chip package structure; and more particularly to a chip package structure fabricated by a tape and tape automated bonding package technique.
隨著科技進步，半導體元件（例如晶片）已成為許多電子產品中不可或缺的零組件之一。當半導體元件製作完成後，通常需進一步進行封裝作業，以與其他外部元件電性連接，並同時保護半導體元件之電路。其中，捲帶自動接合（Tape Automatic Bonding，TAB）封裝技術於封裝後具有可彎折、輕薄、微小間距(fine pitch)及高腳數等特性，特別適用於顯示器之驅動晶片封裝。其中，捲帶自動接合封裝又分成薄膜覆晶（Chip On Film，COF）封裝及捲帶承載封裝（Tape Carrier Package，TCP）。然而，因應電子產品微型化、高處理速度、多功能、高效能等需求，晶片則必須在縮小尺寸的同時還需增加輸出入(I/O)端點密度，這使得輸出入端點間距更趨微小化，當半導體裝置運作時高電壓施加於金屬導電端點，加上高溫及濕氣環境，使得金屬導電端點產生金屬離子遷移(ion migration)現象，在微小間距的導電端點之間造成橋接、電性短路或漏電流等狀況。As technology advances, semiconductor components such as wafers have become one of the indispensable components in many electronic products. After the semiconductor device is fabricated, it is usually necessary to further perform a packaging operation to electrically connect with other external components while protecting the circuit of the semiconductor component. Among them, the Tape Automatic Bonding (TAB) packaging technology has the characteristics of being bendable, light and thin, fine pitch and high number of pins after packaging, and is particularly suitable for the driving chip package of the display. Among them, the tape automatic bonding package is further divided into a Chip On Film (COF) package and a Tape Carrier Package (TCP). However, in response to the demand for miniaturization, high processing speed, versatility, high performance, etc., the wafer must be reduced in size while increasing the input/output (I/O) endpoint density, which makes the output-to-end spacing more Miniaturized, when a semiconductor device operates, a high voltage is applied to the metal conduction end point, and a high temperature and moisture environment causes a metal ion migration phenomenon to occur between the conductive terminals of the fine pitch. Causes bridging, electrical short circuit or leakage current.
習知利用捲帶自動接合封裝技術所製成之晶片封裝結構1，如第1圖所示，具有一晶片11、一保護層(passivation layer)12、複數金屬凸塊13及可撓性基板14，保護層12及該等金屬凸塊13設置於晶片11上，可撓性基板14之複數引腳141係分別對應各金屬凸塊13，而與各金屬凸塊13電性連接，使得晶片11得藉由可撓性基板14與其他外部元件電性連接。A chip package structure 1 manufactured by a tape automated bonding method, as shown in FIG. 1 , has a wafer 11 , a passivation layer 12 , a plurality of metal bumps 13 , and a flexible substrate 14 . The protective layer 12 and the metal bumps 13 are disposed on the wafer 11. The plurality of pins 141 of the flexible substrate 14 respectively correspond to the metal bumps 13 and are electrically connected to the metal bumps 13 so that the wafer 11 is The flexible substrate 14 is electrically connected to other external components.
承上所述，於實際使用時，晶片11會與可撓性基板14透過該等金屬凸塊13及引腳141電性導通，施加高電壓及大量電流通過之下，產生大量之熱能，使得金屬凸塊13析出金屬離子131，再加上濕氣助長，則可能發生金屬離子131遷移現象，而金屬離子131通常會沿著保護層12之表面游離遷移至相鄰之其他金屬凸塊13 (如第1圖虛線箭頭所示為金屬離子131的遷移路徑)，使得各金屬凸塊13間因不當的橋接導通而造成電性短路或漏電流等問題，尤其是在微小間距的設計中，此問題更趨嚴重，而應用習知晶片封裝結構1之電子產品也將因此發生功能錯誤或損壞等狀況。As described above, in actual use, the wafer 11 is electrically connected to the flexible substrate 14 through the metal bumps 13 and the leads 141, and a large amount of heat is generated by applying a high voltage and a large amount of current. The metal bumps 13 are precipitated by the metal bumps 13, and the migration of the metal ions 131 may occur, and the metal ions 131 usually migrate along the surface of the protective layer 12 to the adjacent metal bumps 13 ( As shown by the dotted arrow in FIG. 1 , the migration path of the metal ions 131 causes electrical short circuits or leakage currents due to improper bridge conduction between the metal bumps 13 , especially in the design of a small pitch. The problem is more serious, and the electronic products using the conventional chip package structure 1 will also suffer from malfunction or damage.
有鑑於此，提供一種晶片封裝結構，可降低金屬凸塊產生之離子遷移至相鄰金屬凸塊的機率，而減少電性短路或漏電流現象發生，以使電子產品之品質有所提升，乃為此一業界亟待解決的問題。In view of the above, a chip package structure is provided, which can reduce the probability of ions generated by metal bumps from migrating to adjacent metal bumps, and reduce the occurrence of electrical short circuits or leakage currents, so as to improve the quality of electronic products. For this reason, an industry has to solve the problem.
本發明之ㄧ目的在於提供一種晶片封裝結構，得降低晶片上之凸塊產生的離子遷移至相鄰凸塊的機率，以避免晶片封裝結構於實際使用時發生電性短路或漏電流等問題。It is an object of the present invention to provide a chip package structure that reduces the probability of ions generated by bumps on a wafer from migrating to adjacent bumps, thereby avoiding problems such as electrical short circuits or leakage currents in actual use of the chip package structure.
為達上述目的，本發明揭露一種晶片封裝結構，包含一晶片、一保護層、複數凸塊、一絕緣薄膜層、一可撓性基板及一封裝膠體。其中，該晶片具有一主動面及複數銲墊設置於該主動面上，該保護層形成於該主動面上，且該保護層係局部顯露各該銲墊，該等凸塊分別形成於各該銲墊上，並與該銲墊電性連接，該絕緣薄膜層形成於該保護層上，該絕緣薄膜層係顯露該等凸塊，且相鄰之各該凸塊間之該絕緣薄膜層形成有至少ㄧ凹槽，該可撓性基板具有複數個引腳，該晶片與該可撓性基板接合，使該等引腳與該等凸塊對應電性連接，該封裝膠體填充於該晶片及該可撓性基板所形成之空間中。To achieve the above objective, the present invention discloses a chip package structure including a wafer, a protective layer, a plurality of bumps, an insulating film layer, a flexible substrate, and an encapsulant. Wherein, the wafer has an active surface and a plurality of solder pads disposed on the active surface, the protective layer is formed on the active surface, and the protective layer partially exposes each of the solder pads, and the bumps are respectively formed on each of the pads And electrically connected to the soldering pad, the insulating film layer is formed on the protective layer, the insulating film layer reveals the bumps, and the insulating film layer between adjacent ones of the bumps is formed At least a recessed surface, the flexible substrate has a plurality of pins, the wafer is bonded to the flexible substrate, and the pins are electrically connected to the bumps, and the encapsulant is filled on the wafer and the In the space formed by the flexible substrate.
為達上述目的，本發明揭露另一種晶片封裝結構，包含一晶片、一保護層、複數凸塊、複數絕緣突起、一可撓性基板及一封裝膠體。其中，該晶片具有一主動面及複數銲墊設置於該主動面上，該保護層形成於該主動面上，該保護層係局部顯露各該銲墊，該等凸塊分別形成於各該銲墊上，並與該銲墊電性連接，該等絕緣突起形成於該保護層上，且相鄰之各該凸塊間具有至少一該絕緣突起，該可撓性基板，具有複數個引腳，該晶片係與該可撓性基板接合，使該等引腳與該等凸塊對應電性連接，該封裝膠體填充於該晶片及該可撓性基板所形成之空間中。To achieve the above object, the present invention discloses another chip package structure comprising a wafer, a protective layer, a plurality of bumps, a plurality of insulating protrusions, a flexible substrate and an encapsulant. Wherein, the wafer has an active surface and a plurality of solder pads disposed on the active surface, the protective layer is formed on the active surface, and the protective layer partially exposes the solder pads, and the bumps are respectively formed on each of the solder pads And electrically connected to the pad, the insulating protrusions are formed on the protective layer, and at least one of the insulating protrusions is adjacent between the adjacent bumps, the flexible substrate has a plurality of pins, The wafer is bonded to the flexible substrate, and the leads are electrically connected to the bumps. The package is filled in a space formed by the wafer and the flexible substrate.
綜上所述，藉由至少一凹槽或至少一絕緣突起形成於相鄰之各該凸塊之間，當晶片與可撓性基板電性導通而使得凸塊因電壓、過熱及濕氣而析出金屬離子時，將可增長金屬離子遷移路徑，進而降低金屬離子遷移至相鄰凸塊，避免因各凸塊之間的金屬離子互相碰觸而造成電性短路或漏電流等現象。In summary, at least one recess or at least one insulating protrusion is formed between adjacent bumps, and when the wafer is electrically connected to the flexible substrate, the bump is caused by voltage, overheating and moisture. When metal ions are precipitated, the metal ion migration path can be increased, thereby reducing the migration of metal ions to adjacent bumps, thereby avoiding electrical short circuits or leakage currents due to metal ions between the bumps.
本發明第一實施例之晶片封裝結構2如第2A圖及第2B圖所示，第2A圖為晶片封裝結構2之剖面示意圖，第2B圖為晶片封裝結構2之晶片21的局部俯視示意圖。晶片封裝結構2包含一晶片21、複數凸塊22、一保護層23、一絕緣薄膜層24、一可撓性基板25及一封裝膠體26。The wafer package structure 2 of the first embodiment of the present invention is shown in FIGS. 2A and 2B. FIG. 2A is a schematic cross-sectional view of the chip package structure 2, and FIG. 2B is a partial top plan view of the wafer 21 of the chip package structure 2. The chip package structure 2 includes a wafer 21, a plurality of bumps 22, a protective layer 23, an insulating film layer 24, a flexible substrate 25, and an encapsulant 26.
承上所述，其中，晶片21具有一主動面211及複數銲墊212，該等銲墊212設置於主動面211上，保護層23則形成於主動面211上且局部顯露各銲墊212。該等凸塊22分別形成於各銲墊212上並與銲墊212電性連接，這些凸塊22係沿晶片21之至少二相對側邊213、214間隔排列，且於本實施例中，凸塊22係覆蓋在部分之保護層23上。絕緣薄膜層24形成於保護層23上並顯露該等凸塊22，相鄰各凸塊22間之絕緣薄膜層24具有至少一凹槽242。可撓性基板25具有複數個引腳251，晶片21與可撓性基板25接合，使該等引腳251與該等凸塊22對應電性連接，封裝膠體26則填充於晶片21及可撓性基板25所形成之空間中。As described above, the wafer 21 has an active surface 211 and a plurality of pads 212 disposed on the active surface 211. The protective layer 23 is formed on the active surface 211 and partially exposes the pads 212. The bumps 22 are respectively formed on the pads 212 and electrically connected to the pads 212. The bumps 22 are spaced along at least two opposite sides 213 and 214 of the wafer 21, and in this embodiment, convex. Block 22 is overlaid on a portion of protective layer 23. The insulating film layer 24 is formed on the protective layer 23 and the bumps 22 are exposed. The insulating film layer 24 between the adjacent bumps 22 has at least one recess 242. The flexible substrate 25 has a plurality of pins 251. The wafer 21 is bonded to the flexible substrate 25, and the pins 251 are electrically connected to the bumps 22. The package 26 is filled with the wafer 21 and is flexible. The space formed by the substrate 25 is formed.
當晶片21與可撓性基板25電性導通而使得凸塊22產生離子221析出及遷移現象時，如第2A圖之虛線箭頭係繪示離子221之遷移路徑，藉由二相鄰各凸塊22間之絕緣薄膜層24形成至少ㄧ凹槽242，使得離子221遷移路徑增長，可減少離子221遷移至相鄰之凸塊22的機率，甚至於遷移的過程中，離子221可被限制於凹槽242中，而避免相鄰各凸塊22間因離子221遷移而產生橋接、電性短路或漏電流等現象。再者，封裝膠體26藉由填充於凹槽242中，亦可增加封裝膠體26與晶片21之附著力。When the wafer 21 and the flexible substrate 25 are electrically connected to cause the protrusion 22 to generate ions 221 to precipitate and migrate, the dotted arrow in FIG. 2A shows the migration path of the ions 221, and the adjacent adjacent bumps The insulating film layer 24 of the 22 layers forms at least the recess 242, so that the migration path of the ions 221 is increased, and the probability of the ions 221 migrating to the adjacent bumps 22 can be reduced. Even during the migration, the ions 221 can be confined to the concave. In the groove 242, a phenomenon such as bridging, electrical short circuit or leakage current due to migration of ions 221 between adjacent bumps 22 is avoided. Furthermore, the encapsulant 26 can be filled in the recess 242 to increase the adhesion of the encapsulant 26 to the wafer 21.
詳細而言，晶片21之二相對側邊分別為一第一側邊213及一第二側邊214。請續參考第2B圖，係繪示出凸塊22及凹槽242於晶片21上之相對位置，為清楚區別凸塊22及凹槽242之差異，凸塊22係以具花紋之方形表示。凸塊22係沿晶片21之第一側邊213及第二側邊214間隔排列，各凸塊22具有二相對之邊壁222，邊壁222垂直第一側邊213或第二側邊214，兩相鄰間隔排列之該等凸塊22的邊壁222相互投影所形成的投影區具有一平面重疊區域A1(如第2B圖斜線區域所示)，而凹槽242係延伸截斷平面重疊區域A1 ，使平面重疊區域A1分成兩區，分別鄰接兩相鄰排列之凸塊22。如此可以確保各凸塊22析出之離子221於遷移的路徑上會經過凹槽242(如第2B圖之虛線箭頭所示為離子221的遷移路徑)。In detail, the opposite sides of the wafer 21 are a first side 213 and a second side 214, respectively. Referring to FIG. 2B, the relative positions of the bumps 22 and the recesses 242 on the wafer 21 are shown. To clearly distinguish the difference between the bumps 22 and the recesses 242, the bumps 22 are represented by squares having a pattern. The bumps 22 are spaced apart along the first side 213 and the second side 214 of the wafer 21 . Each of the bumps 22 has two opposite side walls 222 , and the side wall 222 is perpendicular to the first side 213 or the second side 214 . The projection area formed by the projection of the side walls 222 of the two adjacently spaced apart projections 22 has a planar overlapping area A1 (as indicated by the oblique line area in FIG. 2B), and the recess 242 extends the truncated plane overlapping area A1. The plane overlapping area A1 is divided into two areas, respectively adjacent to two adjacently arranged bumps 22. In this way, it is ensured that the ions 221 precipitated by the respective bumps 22 pass through the grooves 242 on the path of migration (as indicated by the dotted arrow in FIG. 2B, the migration path of the ions 221).
於本實施例中，絕緣薄膜層24之一厚度T較佳者係介於5至10微米，而至少一凹槽242之一深度D較佳者係介於2至5微米之間。需說明的是，本發明之晶片封裝結構，可依凸塊22之數量、凸塊22間之間距及凸塊22之離子221的遷移狀態而調整各凸塊22間之凹槽242的數量及尺寸，舉例而言，如第3圖所示，係顯示凸塊22及凹槽242之其他態樣及配置方式，凸塊22亦同樣以具花紋之方形繪示。於此實施例中，晶片21之四個側邊均設置有複數凸塊22，各凸塊22之間可具有至少一凹槽242或者是形成有複數凹槽242，且只要至少一凹槽242正好可截斷平面重疊區域A1，各凹槽242之寬度或長度均可加以調整，例如，可將各凹槽242由晶片21之第一側邊213向第二側邊214延伸。於其他實施例中，凹槽242還可為斜向延伸，只要適可截斷平面重疊區域A1，使凸塊22產生的離子221遷移的路徑一定會經過凹槽242，進而避免相鄰各凸塊22間因離子221遷移而產生橋接、電性短路或漏電流等現象。In the present embodiment, the thickness T of one of the insulating film layers 24 is preferably between 5 and 10 microns, and the depth D of at least one of the grooves 242 is preferably between 2 and 5 microns. It should be noted that, in the chip package structure of the present invention, the number of the grooves 242 between the bumps 22 can be adjusted according to the number of the bumps 22, the distance between the bumps 22, and the migration state of the ions 221 of the bumps 22, and Dimensions, for example, as shown in FIG. 3, show other aspects and arrangements of the bumps 22 and the recesses 242. The bumps 22 are also illustrated in a square shape. In this embodiment, the four sides of the wafer 21 are provided with a plurality of bumps 22, and each of the bumps 22 may have at least one recess 242 or a plurality of recesses 242 formed therein, and only at least one recess 242 The plane overlap area A1 can be cut off, and the width or length of each groove 242 can be adjusted. For example, each groove 242 can be extended from the first side 213 of the wafer 21 toward the second side 214. In other embodiments, the groove 242 may also extend obliquely. As long as the plane overlapping area A1 is properly cut, the path of the ions 221 generated by the bump 22 must pass through the groove 242, thereby avoiding adjacent bumps. 22 cases of bridging, electrical short circuit or leakage current due to migration of ions 221.
本發明第二實施例之一晶片封裝構造3與第一實施例之相異處在於本第二實施例係直接將複數絕緣突起形成於保護層上。請參考第4A圖及第4B圖，分別為本第二實施例之剖面示意圖及局部俯視示意圖，晶片封裝結構3包含晶片31、複數凸塊32、一保護層33、複數絕緣突起34、一可撓性基板35及一封裝膠體36。The chip package structure 3 of the second embodiment of the present invention is different from the first embodiment in that the second embodiment directly forms a plurality of insulating protrusions on the protective layer. Please refer to FIG. 4A and FIG. 4B , which are respectively a schematic cross-sectional view and a partial top view of the second embodiment. The chip package structure 3 includes a wafer 31 , a plurality of bumps 32 , a protective layer 33 , a plurality of insulating protrusions 34 , and a plurality of insulating protrusions 34 . The flexible substrate 35 and an encapsulant 36.
其中，晶片31具有一主動面311及複數銲墊312，該等銲墊312設置於主動面311上，保護層33則形成於主動面311上且局部顯露各銲墊312。該等凸塊32分別形成於各銲墊312上並與銲墊312電性連接，這些凸塊32係沿晶片31之至少二相對側邊313、314間隔排列，且於本實施例中，凸塊32係覆蓋在部分之保護層33上。該等絕緣突起34形成於保護層33上，且相鄰之各凸塊32間具有至少一絕緣突起34，可撓性基板35具有複數個引腳351，晶片31與可撓性基板35接合，使該等引腳351與該等凸塊32對應電性連接，封裝膠體36則填充於晶片31及可撓性基板35所形成之空間中。The wafer 31 has an active surface 311 and a plurality of pads 312. The pads 312 are disposed on the active surface 311, and the protective layer 33 is formed on the active surface 311 and partially exposes the pads 312. The bumps 32 are respectively formed on the pads 312 and electrically connected to the pads 312. The bumps 32 are spaced along at least two opposite sides 313, 314 of the wafer 31, and in this embodiment, convex Block 32 is overlaid on a portion of protective layer 33. The insulating protrusions 34 are formed on the protective layer 33, and at least one insulating protrusion 34 is disposed between the adjacent bumps 32. The flexible substrate 35 has a plurality of pins 351, and the wafer 31 is bonded to the flexible substrate 35. The pins 351 are electrically connected to the bumps 32, and the encapsulant 36 is filled in the space formed by the wafer 31 and the flexible substrate 35.
與本發明第一實施例相同，當晶片31與可撓性基板35電性導通而使得凸塊32產生離子321析出及遷移現象時，如第4A圖之虛線箭頭係繪示離子321之遷移路徑，藉由各凸塊32間之至少ㄧ絕緣突起34，使得離子321遷移路徑增長，可減少離子321遷移至相鄰之凸塊32的機率，至少一絕緣突起34甚至可形成一擋牆使離子321停留在各凸塊32及絕緣突起34之間，進而避免相鄰各凸塊32間因離子321遷移而產生橋接、電性短路或漏電流等現象。再者，封裝膠體36藉由填充於各絕緣突起34及各凸塊32之間，亦可增加封裝膠體36與晶片31之附著力。As in the first embodiment of the present invention, when the wafer 31 and the flexible substrate 35 are electrically connected to cause the protrusion 32 to generate and migrate ions 321 , the dotted arrow in FIG. 4A shows the migration path of the ions 321 . By at least the germanium insulating protrusions 34 between the bumps 32, the migration path of the ions 321 is increased, the probability of the ions 321 migrating to the adjacent bumps 32 can be reduced, and at least one of the insulating protrusions 34 can form a barrier wall to make ions. The 321 stays between the bumps 32 and the insulating protrusions 34, thereby avoiding the phenomenon of bridging, electrical short circuit or leakage current due to the migration of the ions 321 between the adjacent bumps 32. Furthermore, the encapsulant 36 can be filled between the insulating protrusions 34 and the bumps 32 to increase the adhesion between the encapsulant 36 and the wafer 31.
詳細而言，晶片31之二相對側邊分別為一第一側邊313及一第二側邊314。請續參考第4B圖，係繪示出凸塊32及絕緣突起34於晶片31上之相對位置，為清楚區別凸塊32及絕緣突起34之差異，凸塊32以具花紋之方形表示。各凸塊32係沿晶片31之第一側邊313及第二側邊314間隔排列，各凸塊32具有二相對之邊壁322，邊壁322垂直第一側邊313或第二側邊314，兩相鄰間隔排列之該等凸塊32的邊壁322相互投影所形成的投影區具有一平面重疊區域A2(如第4B圖斜線區域所示)，而絕緣突起34係延伸截斷平面重疊區域A2，使平面重疊區域A2分成兩區，分別鄰接兩相鄰排列之凸塊32。In detail, the opposite sides of the wafer 31 are a first side 313 and a second side 314, respectively. Referring to FIG. 4B, the relative positions of the bumps 32 and the insulating protrusions 34 on the wafer 31 are shown. To clearly distinguish the difference between the bumps 32 and the insulating protrusions 34, the bumps 32 are represented by squares having a pattern. Each of the bumps 32 is spaced along the first side 313 and the second side 314 of the wafer 31. Each of the bumps 32 has two opposite side walls 322. The side walls 322 are perpendicular to the first side 313 or the second side 314. The projection regions formed by the projections of the side walls 322 of the two adjacently spaced projections 32 have a planar overlapping area A2 (as indicated by the oblique line in FIG. 4B), and the insulating protrusions 34 extend the truncated plane overlapping area. A2, the plane overlapping area A2 is divided into two areas, respectively adjacent to two adjacently arranged bumps 32.
於本實施例中，各絕緣突起34之一高度H較佳者係介於2至10微米之間。同樣地，與本發明第一實施例相同，本實施例之絕緣突起34亦可依需求進行數量及尺寸上的調整，此乃熟知本領域技術者可輕易推及之，於此不再贅述。In the present embodiment, the height H of each of the insulating protrusions 34 is preferably between 2 and 10 microns. Similarly, as in the first embodiment of the present invention, the insulating protrusions 34 of the present embodiment can also be adjusted in quantity and size according to requirements, which can be easily referred to by those skilled in the art, and will not be described herein.
請進一步參第4C圖，於本發明其他實施例中，晶片封裝結構3更可包含一絕緣薄膜層37形成於保護層33上，絕緣薄膜層37係顯露該等凸塊32，且該等絕緣突起34係形成於該絕緣薄膜層37上。4C, in another embodiment of the present invention, the chip package structure 3 further includes an insulating film layer 37 formed on the protective layer 33, the insulating film layer 37 reveals the bumps 32, and the insulation The protrusions 34 are formed on the insulating film layer 37.
此外，不論是本發明第一實施例、第二實施例或其他實施例的絕緣薄膜層及絕緣突起之材料，均可選自聚醯亞胺（Polyimide，PI）、光阻焊劑(solder resist，SR)或苯環丁烯（benzocyclobutene，BCB）。而凸塊之種類可選自電鍍凸塊、無電鍍凸塊、結線凸塊或導電聚合物凸塊，其材料則可選自金、銀、銅、銦、鎳/金、鎳/鈀/金、銅/鎳/金、銅/金、鋁、導電高分子材料及其組合等。In addition, the material of the insulating film layer and the insulating protrusion of the first embodiment, the second embodiment or other embodiments of the present invention may be selected from the group consisting of polyimide (PI) and solder resist (solder resist, SR) or benzocyclobutene (BCB). The type of bumps may be selected from electroplated bumps, electroless bumps, junction bumps or conductive polymer bumps, and the material may be selected from the group consisting of gold, silver, copper, indium, nickel/gold, nickel/palladium/gold. , copper / nickel / gold, copper / gold, aluminum, conductive polymer materials and combinations thereof.
綜上所述，本發明揭露之晶片封裝結構於各凸塊之間的絕緣薄膜層形成有凹槽或設置絕緣突起，不僅能增加封裝膠體與晶片之附著力，亦得增加凸塊產生之離子之遷移路徑，藉此，可減少離子遷移至相鄰之凸塊的機率，以降低晶片封裝結構發生電性短路或漏電流等現象，進而提升晶片封裝結構的可靠度。In summary, the wafer package structure disclosed in the present invention has grooves or insulating protrusions formed on the insulating film layer between the bumps, which not only increases the adhesion between the package colloid and the wafer, but also increases the ions generated by the bumps. The migration path can reduce the probability of ions migrating to adjacent bumps, thereby reducing the phenomenon of electrical short circuit or leakage current in the chip package structure, thereby improving the reliability of the chip package structure.
上述之實施例僅用來例舉本發明之實施態樣，以及闡釋本發明之技術特徵，並非用來限制本發明之保護範疇。任何熟悉此技術者可輕易完成之改變或均等性之安排均屬於本發明所主張之範圍，本發明之權利保護範圍應以申請專利範圍為準。The embodiments described above are only intended to illustrate the embodiments of the present invention, and to explain the technical features of the present invention, and are not intended to limit the scope of protection of the present invention. Any changes or equivalents that can be easily made by those skilled in the art are within the scope of the invention. The scope of the invention should be determined by the scope of the claims.
1．．．晶片封裝結構1. . . Chip package structure
11．．．晶片11. . . Wafer
12．．．保護層12. . . The protective layer
13．．．金屬凸塊13. . . Metal bump
131．．．金屬離子131. . . Metal ion
14．．．可撓性基板14. . . Flexible substrate
141．．．引腳141. . . Pin
2．．．晶片封裝結構2. . . Chip package structure
21．．．晶片twenty one. . . Wafer
211．．．主動面211. . . Active surface
212．．．銲墊212. . . Solder pad
213．．．第一側邊213. . . First side
214．．．第二側邊214. . . Second side
22．．．凸塊twenty two. . . Bump
221．．．離子221. . . ion
222．．．邊壁222. . . Side wall
23．．．保護層twenty three. . . The protective layer
24．．．絕緣薄膜層twenty four. . . Insulating film layer
242．．．凹槽242. . . Groove
25．．．可撓性基板25. . . Flexible substrate
251．．．引腳251. . . Pin
26．．．封裝膠體26. . . Encapsulant
3．．．晶片封裝結構3. . . Chip package structure
31．．．晶片31. . . Wafer
311．．．主動面311. . . Active surface
312．．．銲墊312. . . Solder pad
313．．．第一側邊313. . . First side
314．．．第二側邊314. . . Second side
32．．．凸塊32. . . Bump
321．．．離子321. . . ion
322．．．邊壁322. . . Side wall
33．．．保護層33. . . The protective layer
34．．．絕緣突起34. . . Insulation protrusion
35．．．可撓性基板35. . . Flexible substrate
351．．．引腳351. . . Pin
36．．．封裝膠體36. . . Encapsulant
37．．．絕緣薄膜層37. . . Insulating film layer
A1．．．平面重疊區域A1. . . Plane overlap area
A2．．．平面重疊區域A2. . . Plane overlap area
T．．．厚度T. . . thickness
D．．．深度D. . . depth
H．．．高度H. . . height
第1圖係為先前技術之晶片封裝結構之剖面示意圖；Figure 1 is a schematic cross-sectional view of a prior art wafer package structure;
第2A圖係為本發明第ㄧ實施例之晶片封裝結構之剖面示意圖；2A is a schematic cross-sectional view showing a wafer package structure according to a third embodiment of the present invention;
第2B圖係為本發明第一實施例之晶片封裝結構之晶片的局部俯視示意圖；2B is a partial top plan view of a wafer of a wafer package structure according to a first embodiment of the present invention;
第3圖係為本發明其他實施例之晶片封裝結構之晶片的局部俯視示意圖；3 is a partial top plan view of a wafer of a chip package structure according to another embodiment of the present invention;
第4A圖係為本發明第二實施例之晶片封裝結構之剖面示意圖；4A is a schematic cross-sectional view showing a wafer package structure according to a second embodiment of the present invention;
第4B圖係為本發明第二實施例之晶片封裝結構之晶片的局部俯視示意圖；以及4B is a partial top plan view of a wafer of a wafer package structure according to a second embodiment of the present invention;
第4C圖係為本發明其他實施例之晶片封裝結構之剖面示意圖。4C is a schematic cross-sectional view showing a wafer package structure according to another embodiment of the present invention.
2．．．晶片封裝結構2. . . Chip package structure
21．．．晶片twenty one. . . Wafer
211．．．主動面211. . . Active surface
212．．．銲墊212. . . Solder pad
22．．．凸塊twenty two. . . Bump
221．．．離子221. . . ion
222．．．邊壁222. . . Side wall
23．．．保護層twenty three. . . The protective layer
24．．．絕緣薄膜層twenty four. . . Insulating film layer
242．．．凹槽242. . . Groove
25．．．可撓性基板25. . . Flexible substrate
251．．．引腳251. . . Pin
26．．．封裝膠體26. . . Encapsulant
D．．．深度D. . . depth
T．．．厚度T. . . thickness
Claims (10)
一晶片，具有一主動面及複數銲墊，該等銲墊設置於該主動面上；
一保護層，形成於該主動面上，該保護層係局部顯露各該銲墊；
複數凸塊，分別形成於各該銲墊上，並與該銲墊電性連接；
一絕緣薄膜層，形成於該保護層上，該絕緣薄膜層係顯露該等凸塊，且相鄰之各該凸塊間之該絕緣薄膜層具有至少一凹槽；
一可撓性基板，具有複數個引腳，該晶片係與該可撓性基板接合，使該等引腳與該等凸塊對應電性連接；以及
一封裝膠體，填充於該晶片及該可撓性基板所形成之空間中。A chip package structure comprising:
a wafer having an active surface and a plurality of pads, the pads being disposed on the active surface;
a protective layer formed on the active surface, the protective layer partially revealing each of the pads;
a plurality of bumps respectively formed on each of the pads and electrically connected to the pads;
An insulating film layer is formed on the protective layer, the insulating film layer reveals the bumps, and the insulating film layer between adjacent ones of the bumps has at least one groove;
a flexible substrate having a plurality of pins, the chip being bonded to the flexible substrate to electrically connect the pins to the bumps; and an encapsulant filled on the wafer and the In the space formed by the flexible substrate.
一晶片，具有一主動面及複數銲墊，該等銲墊設置於該主動面上；
一保護層，形成於該主動面上，該保護層係局部顯露各該銲墊；
複數凸塊，分別形成於各該銲墊上，並與該銲墊電性連接；
複數絕緣突起，形成於該保護層上，且相鄰之各該凸塊間具有至少一該絕緣突起；
一可撓性基板，具有複數個引腳，該晶片係與該可撓性基板接合，使該等引腳與該等凸塊對應電性連接；以及
一封裝膠體，填充於該晶片及該可撓性基板所形成之空間中。A chip package structure comprising:
a wafer having an active surface and a plurality of pads, the pads being disposed on the active surface;
a protective layer formed on the active surface, the protective layer partially revealing each of the pads;
a plurality of bumps respectively formed on each of the pads and electrically connected to the pads;
a plurality of insulating protrusions formed on the protective layer, and at least one of the insulating protrusions between adjacent ones of the bumps;
a flexible substrate having a plurality of pins, the chip being bonded to the flexible substrate to electrically connect the pins to the bumps; and an encapsulant filled on the wafer and the In the space formed by the flexible substrate.
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| TW100139893A TWI462256B (en) | 2011-11-02 | 2011-11-02 | Chip package structure |
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