TW201316457A - Memory and manufacturing method thereof - Google Patents

Abstract

A memory and a manufacturing method thereof are provided. A plurality of stacked structures extending along a first direction is formed on a substrate. Each of the stacked structures includes a plurality of first insulating layers and a plurality of second insulating layers. The first insulating layers are stacked on the substrate and the second insulating layers are respectively disposed between the adjacent first insulating layers. A plurality of trenches extending along the first direction is formed in each of the stacked structures. The trenches are respectively located at two opposite sides of each of the second insulating layers. A first conductive layer is filled in the trenches. A plurality of charge storage structures extending along a second direction is formed on the stacked structures and a second conductive layer is formed on each of the charge storage structures.

Description

Memory and its making method

The present invention relates to a memory and a method of fabricating the same, and more particularly to a memory having a high memory density and a method of fabricating the same.

Non-volatile memory has the advantage that it does not disappear after power-off, so many electrical products must have such memory to maintain the normal operation of the electrical products when they are turned on.

As the size of the electronic components shrinks, the size of the memory composed of the memory cell array also shrinks. However, limited by current lithography techniques, generally two-dimensional memory cell arrays are also limited in size reduction (eg, reducing the spacing between adjacent memory cells). In addition, due to the size reduction of the memory cells, the memory density is also reduced.

In order to increase the data storage capacity of the memory, the three-dimensional memory cell array has been highly concerned by the industry. However, for the current three-dimensional memory cell array process, it has a high complexity, and is still limited by the existing lithography technology in terms of size reduction.

The invention provides a method for fabricating a memory, which can produce a memory having a higher memory density.

The invention further provides a memory having a higher memory density.

The invention provides a method for fabricating a memory, in which a plurality of stacked structures extending in a first direction are formed on a substrate. Each stacked structure includes a plurality of first insulating layers and a plurality of second insulating layers. The first insulating layers are stacked on the substrate, and the second insulating layers are respectively located between the adjacent first insulating layers. Then, a plurality of grooves extending in the first direction are formed in each of the stacked structures. These trenches are located on opposite sides of each of the second insulating layers. Next, a first conductor layer is filled in the trench. Thereafter, a plurality of charge storage structures extending in the second direction are formed on the stacked structures and a second conductive layer is formed on each of the charge storage structures.

According to the method of fabricating the memory of the embodiment of the invention, the etching rate of the first insulating layer is, for example, smaller than the etching rate of the second insulating layer.

According to the method of fabricating a memory device according to the embodiment of the invention, the material of the first insulating layer is, for example, an oxide, a nitride or an oxynitride.

According to the method of fabricating the memory device of the embodiment of the invention, the material of the second insulating layer is, for example, an oxide, a nitride or an oxynitride.

According to the method of fabricating the memory according to the embodiment of the invention, the method for forming the trench is, for example, performing an isotropic etching process to remove a portion of each of the second insulating layers.

According to the method for fabricating a memory according to the embodiment of the invention, the method for forming the stacked structure is, for example, forming a first insulating material layer and a second insulating material layer on a substrate, and the uppermost layer is a first insulating material layer. Then, a plurality of mask layers extending in the first direction are formed on the uppermost first insulating material layer. Thereafter, a portion of the first insulating material layer and the second insulating material layer are removed by using the mask layer as a mask.

According to the method of fabricating a memory device according to the embodiment of the invention, the method for forming the first conductor layer is, for example, forming a layer of a conductor material on a substrate. A layer of conductive material covers the stacked structure and is filled into the trench. Thereafter, an anisotropic etching process is performed to remove the layer of the conductor material outside the trench.

According to the method for fabricating the memory according to the embodiment of the invention, the method for forming the charge storage structure and the second conductor layer is, for example, forming a layer of the charge storage material covering the stacked structure on the substrate. A layer of conductor material is then formed over the layer of charge storage material. Next, a plurality of mask layers extending in the second direction are formed on the conductor material layer. Thereafter, a portion of the conductor material layer and a portion of the charge storage material layer are removed by using the mask layer as a mask.

The invention further provides a memory comprising a plurality of stacked structures, a plurality of charge storage structures, and a plurality of word lines. The stacked structure is disposed on the substrate and extends in the first direction. Each stacked structure includes a plurality of first insulating layers, a plurality of second insulating layers, and a plurality of bit lines. These first insulating layers are stacked on the substrate. The second insulating layers are respectively disposed between the adjacent first insulating layers. The bit lines are disposed on opposite sides of each of the second insulating layers. The charge storage structure is disposed on the substrate and extends in the second direction and covers the stacked structure. The word lines are arranged on the charge storage structure.

According to the memory device of the embodiment of the invention, the material of the first insulating layer is different from the material of the second insulating layer.

According to the memory device of the embodiment of the invention, the material of the first insulating layer is, for example, an oxide, a nitride or an oxynitride.

According to the memory of the embodiment of the invention, the material of the second insulating layer is, for example, an oxide, a nitride or an oxynitride.

According to the memory device of the embodiment of the invention, the material of the bit line is, for example, polycrystalline germanium or amorphous germanium.

According to the memory of the embodiment of the invention, the material of the charge storage structure is, for example, an oxide/nitride/oxide, an oxide/nitride/oxide/nitride/oxide or a high dielectric constant material.

According to the memory of the embodiment of the invention, the material of the above-mentioned word line is, for example, polycrystalline germanium.

Based on the above, the present invention alternately stacks insulating layers having different etching rates on a substrate, and forms a region filled with bit lines by etching a portion of the insulating layer, thereby forming a smaller size by breaking the limitations of the existing lithography technique. Bit line. In addition, by controlling the thickness of the insulating layer to reduce the distance between the bit lines of the upper and lower layers (ie, reducing the spacing between adjacent memory cells), it is also possible to break through the existing lithography techniques in adjacent memory cells. The limit on the spacing. Thereby, the memory formed by the present invention can have a higher memory density.

The above described features and advantages of the present invention will be more apparent from the following description.

1A to FIG. 1E are perspective views showing a process of fabricating a memory according to an embodiment of the invention. First, referring to FIG. 1A, a plurality of stacked structures 102 extending in the Y direction are formed on the substrate 100. The substrate 100 is, for example, a dielectric substrate formed on a germanium wafer. The material of the substrate 100 is, for example, an oxide. Each of the stacked structures 102 includes a plurality of first insulating layers 102a and a plurality of second insulating layers 102b. The first insulating layers 102a are stacked on the substrate 100, and the second insulating layers 102b are respectively located between the adjacent first insulating layers 102a. That is, the first insulating layer 102a and the second insulating layer 102b are sequentially formed alternately on the substrate 100, and the uppermost layer is the first insulating layer 102a. The material of the first insulating layer 102a is, for example, different from the material of the second insulating layer 102b. In the present embodiment, the etching rate of the first insulating layer 102a is smaller than the etching rate of the second insulating layer 102b to facilitate the subsequent etching process, which will be described in detail below. The material of the first insulating layer 102a may be an oxide (Hf ₂ O, Al ₂ O ₃ , SiO ₂ , cerium-rich SiO _{2 ,} etc.), a nitride (Si ₃ N ₄ , cerium-rich Si ₃ N _{4 ,} etc.) ) or nitrogen oxides (SiON). The material of the second insulating layer 102b may also be an oxide, a nitride or an oxynitride as long as the etching rate of the first insulating layer 102a is smaller than the etching rate of the second insulating layer 102b in the subsequent etching process. In particular, the etch rate of the substrate 100 is also less than the etch rate of the second insulating layer 102b to avoid severe damage to the substrate 100 during subsequent etching processes.

Further, the stacking structure 102 is formed by, for example, sequentially forming a first insulating material layer and a second insulating material layer on the substrate 100, and the uppermost layer is a first insulating material layer. Then, a plurality of mask layers extending in the Y direction are formed on the uppermost first insulating material layer, which cover the regions where the stacked structure 102 is to be formed. Thereafter, using the mask layer as a mask, an anisotropic etching process is performed to remove a portion of the first insulating material layer and the second insulating material layer. In the present embodiment, only three stacked structures 102 are illustrated for clarity of the drawing, but the invention is not limited thereto. Moreover, the present invention also does not limit the number of layers in the stacked structure 102.

Then, referring to FIG. 1B, a plurality of trenches 104 extending in the Y direction are formed in each of the stacked structures 102. These trenches 104 are located on opposite sides of the second insulating layer 102b of each layer. The method of forming the trench 104 is, for example, performing an isotropic etching process to remove a portion of the second insulating layer 102b. In particular, since the etching rate of the first insulating layer 102a and the substrate 100 is smaller than the etching rate of the second insulating layer 102b, it can be easily removed from the two sides of the stacked structure 102 during the isotropic etching. A portion of the second insulating layer 102b forms a plurality of trenches 104 without causing serious damage to the second insulating layer 102b and the substrate 100. The trench 104 is a region where the bit line is subsequently formed, and the depth thereof can be adjusted by controlling the etching time to control the size of the subsequently formed bit line. Further, in the present embodiment, the region in which the bit line is arranged is formed by etching, so that the size of the element can be further reduced by breaking the limitation of the existing lithography technique.

Next, referring to FIG. 1C, the conductor layer 106 is filled in the trench 104. The conductor layer 106 serves as a bit line in the memory formed subsequently. The material of the conductor layer 106 is, for example, polycrystalline germanium or amorphous germanium. The conductor layer 106 is formed by, for example, forming a layer of a conductor material on the substrate 100. A layer of conductive material covers the stacked structure 102 and is filled into the trenches 104. Thereafter, an anisotropic etching process is performed to remove the layer of conductor material outside the trenches 104. At this time, each of the stacked structures 102 includes a first insulating layer 102a, a second insulating layer 102b, and a conductor layer 106 (bit lines), and in the same layer, the two conductor layers 106 are respectively located at the second insulating layer 102b. Two sides.

Then, referring to FIG. 1D, a charge storage material layer 108 covering the stacked structure 102 is conformally formed on the substrate 100. The charge storage material layer 108 is, for example, a composite layer composed of an oxide layer/nitride layer/oxide layer (ie, an ONO layer), and a composite layer composed of an oxide layer/nitride layer/oxide layer/nitride layer/oxide layer. (ie ONONO layer) or high dielectric constant layer. Methods of forming the charge storage material layer 108 are well known to those skilled in the art and will not be described herein. Then, a conductor material layer 110 is formed on the charge storage material layer 108. The material of the conductor material layer 110 is, for example, polycrystalline germanium. Next, a plurality of mask layers 112 extending in the X direction are formed on the conductor material layer 110. The mask layer 112 is, for example, a photoresist layer that covers areas where subsequent word lines are to be formed.

Thereafter, referring to FIG. 1E, a portion of the conductive material layer 110 and a portion of the charge storage material layer 108 are removed with the mask layer 112 as a mask to form a plurality of charge storage structures 114 extending in the X direction and covering the stacked structure 102. And word lines 116 on these charge storage structures 114. As a result, the three-dimensional memory 10 having a higher memory density can be formed.

In the memory 10 of the present embodiment, each of the stacked structures 102 has a first insulating layer 102a and a second insulating layer 102b which are alternately stacked in sequence, and a bit is disposed on each of the two sides of the second insulating layer 102b of each layer. The line 106 is thus effective in increasing the memory density of the memory 10.

In detail, the memory 10 has four second insulating layers 102b, and one bit line 106 is disposed on each of the two sides of the second insulating layer 102b of each layer. In addition, five charge storage structures 114 and word lines 116 are disposed on each of the stacked structures 102. Therefore, for the memory 10 shown in FIG. 1E, each of the stacked structures 102 and the charge storage structure 114 and the word line 116 above thereof can constitute 40 memory cells (the memory cells can be as shown at the broken line), and thus Has a higher memory density.

Further, in the memory 10, the pitch between the memory cells of the upper and lower layers is the thickness of the first insulating layer 102a. In other words, in the embodiment, the spacing between the memory cells of the upper and lower layers can be controlled by controlling the thickness of the first insulating layer 102a, so that the limitation of the existing lithography technology can be further reduced to further reduce the adjacent memory cells. The spacing between them.

In addition, for the memory 10 of the present embodiment, a general well-known FN injection (Fowler-Nordheim injection) can be used to perform the staging step and the erasing step.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10. . . Memory

100. . . Base

102. . . Stack structure

102a. . . First insulating layer

102b. . . Second insulating layer

104. . . Trench

106. . . Conductor layer

108. . . Charge storage material layer

110. . . Conductor material layer

112. . . Mask layer

114. . . Charge storage structure

116. . . Word line

1A to 1E are perspective views showing a process of fabricating a memory according to an embodiment of the invention.

10. . . Memory

100. . . Base

102. . . Stack structure

102a. . . First insulating layer

102b. . . Second insulating layer

106. . . Conductor layer

114. . . Charge storage structure

116. . . Word line

Claims (10)

A method of fabricating a memory, comprising: forming a plurality of stacked structures extending in a first direction on a substrate, each stacked structure comprising a plurality of first insulating layers and a plurality of second insulating layers, the first insulating layers Stacking a layer on the substrate, and the second insulating layers are respectively located between the adjacent first insulating layers; forming a plurality of trenches extending in the first direction in each stacked structure, the trenches a slot is located on opposite sides of each of the second insulating layers; a first conductor layer is filled in the trenches; and a plurality of charge storage structures extending in a second direction are formed on the stacked structures and A second conductor layer is formed on a charge storage structure. The method of fabricating the memory of claim 1, wherein the etching rates of the first insulating layers are smaller than the etching rates of the second insulating layers. The method of fabricating the memory of claim 2, wherein the forming of the trenches comprises performing an isotropic etching process to remove a portion of each of the second insulating layers. The method of fabricating the memory of claim 1, wherein the forming method comprises: forming a plurality of first insulating material layers and a plurality of second insulating material layers on the substrate, and the uppermost layer a first insulating material layer; a plurality of mask layers extending in the first direction are formed on the first layer of the first insulating material; and the mask layer is used as a mask to remove portions of the layer a layer of insulating material and a portion of the second layer of insulating material. The method for fabricating a memory according to the first aspect of the invention, wherein the method for forming the first conductor layer comprises: forming a layer of a conductor material on the substrate, the layer of conductor material covering the stacked structures, and filling And forming an anisotropic etching process to remove the layer of the conductor material outside the trenches. The method of fabricating the memory of claim 1, wherein the method of forming the charge storage structure and the second conductor layers comprises: forming a charge storage material layer on the substrate, the charge storage material layer Covering the stacked structures; forming a conductive material layer on the charge storage material layer; forming a plurality of mask layers extending in the second direction on the conductive material layer; and using the mask layers as a mask, A portion of the layer of conductive material and a portion of the layer of charge storage material are removed. A memory comprising: a plurality of stacked structures disposed on a substrate and extending in a first direction, each stacked structure comprising: a plurality of first insulating layers stacked on the substrate; a plurality of second insulating layers Between the adjacent first insulating layers; and a plurality of bit lines disposed on opposite sides of each of the second insulating layers; a plurality of charge storage structures disposed on the substrate, and Extending in a second direction and covering the stacked structures; and a plurality of word lines disposed on the charge storage structures. The memory of claim 7, wherein the material of the first insulating layer is different from the material of the second insulating layer. The memory of claim 8, wherein the material of the first insulating layer comprises an oxide, a nitride or an oxynitride. The memory of claim 8, wherein the material of the second insulating layer comprises an oxide, a nitride or an oxynitride.