TW201230902A - Substrate with fine metal pattern, print circuit board and semiconductor device; and production method of substrate with fine metal pattern, print circuit board and semiconductor device - Google Patents

Abstract

The invention provides a production method of a substrate with fine metal pattern which can be prevented from resulting abnormal deposition of metal on the base resin surface, when performing nickel-palladium-gold electroless on the surface of the fine metal pattern on the substrate, as the terminals of the printed circuit board. The invention also provides a substrate with fine metal pattern, print circuit board and semiconductor device, which is formed by the production method and having a plated surface with a better quality. After a grooves is formed on a surface as a support base resin, an the bottom part of the metal pattern is embedded in the support base resin, and then the upper part of the metal pattern is plated by performing nickel-palladium-gold electroless, wherein the ratio(X/Y) of the height (X) of a projection of the metal pattern in the region performing the above-mentioned electroless and the minimum distance (Y) between the patterns is not more than 0.8.

Description

201230902 VI. Description of the Invention: [Technical Fields of the Invention] The present invention relates to a substrate with a fine metal pattern, a printed wiring board, a semiconductor device, and a method of manufacturing the same. [Prior Art] The circuit on the printed wiring board is gold-plated for the purpose of ensuring connection reliability such as solder bonding and wire bonding. As one of the representative methods of gold plating, there is an electroless gold forging method. In this method, after the plating target is pretreated by an appropriate method such as a cleaner, a palladium catalyst is supplied, and thereafter, electroless nickel plating treatment and electroless gold plating treatment are sequentially performed. ENIG method (Electroless Nickei

Immersion Gold) is a method of electroless nickel-gold plating, which is a method of performing substitution gold treatment (Immersi〇nG〇id) in the stage of electroless gold bonding. When the terminal portion is gold-plated by the ENIG method, when the terminal portion is heat-treated for bonding of the bonding wires, nickel is diffused on the gold film to lower the connection reliability. In the problem of nickel diffusion, electroless gold plating is further performed on the nickel-gold film, and heat resistance is ensured by thickening the thickness of gold. However, from the viewpoint of environmental countermeasures, the melting temperature of the lead-free solder required in the future is about 260 〇C, which is higher than the melting temperature of the prior art lead solder. Therefore, when considering the correspondence of lead-free solder, the gold plating of the portion of the terminal 100121202 4 201230902 requires higher heat resistance than the prior art. The ENIG method is not suitable for high-temperature heating in the case of lead-free soldering, and there is a problem that the higher the heat resistance and the thicker the thickness of gold, the higher the cost. In order to solve the above problems, the application of the electroless nickel-palladium-gold plating method was reviewed. This method is subjected to electroless nickel plating treatment after the electroless nickel plating treatment by the above electroless nickel-gold plating method, followed by electroless gold plating treatment. ENEPIG method (Electroless Nickel mectr〇less palladium

Immersion Gold) is a method of electroless nickel-palladium-gold plating, which is a method of replacing gold plating (Immersion Gold) in the electroless gold plating process of electroless nickel-palladium-gold plating (Patent Document υ). The electroless nickel-palladium gold plating method makes it possible to prevent the diffusion of the conductor material in the circuit or the terminal portion, improve the corrosion resistance, prevent nickel oxidation and prevent diffusion. Moreover, the electroless nickel _ the gold-gold deposit method is used. By setting the electroless button to prevent the nickel from being oxidized by gold, the reliability of the lead-free solder joint with a large thermal load can be improved, and even if the thickness of the gold film is not thickened, the diffusion does not occur. 'There is also an advantage that it can be made more cost-effective than the electroless nickel-gold plating method. [Patent Document 1] Japanese Patent Laid-Open Publication No. 2008-144188 (Draft of the Invention) Electroless nickel-gold plating method, the above-mentioned electroless recording-push-gold 100121202 < 201230902 clock application method has high connection reliability for high heat load. However, when electroless nickel is applied to the circuit of the printed wiring board I gold plating (four), is Found: in the stage of electroless palladium treatment, this phoenix, _ sub-partial week _ analysis: genus::=:: one even becomes a face-to-face sentence (four) correcting the original = face quality decline ' again, also found: With the miniaturization of the circuit, the adjacent conductors are more accommodating on the surface (4);;; the narrower than the present invention, in order to solve the above problems, the two parts of the resin of the terminal of the printed wiring board are produced. The gold of the branch building == the surface of the body circuit or other surface of the object can be inhibited from being applied to the surface of the gold/side treated object on the gold surface of the electroless nickel. The abnormal precipitation occurs in the resin belonging to the substrate. In addition, the metal month is intended to provide a substrate having a metal-coated fine pattern having a good quality processing surface, a means for solving the problem, a wiring board, and a semiconductor device. The above object is achieved by the following invention (1)~ (10) A substrate in which at least the metal fine pattern is attached, wherein the metal fine pattern substrate is characterized in that the fine metal lower portion is embedded in a support surface made of a resin. Set to The portion of the portion that is not in contact with the surface of the above-mentioned repeating groove 100121202 201230902 is covered with a nickel-palladium-gold plating layer, and is protruded from the surface of the branch of the metal fine pattern in the region having the above-mentioned recording-push-money coating layer. The height is set to x (where XS0 (zero) is treated as X_0), and the ratio (X/Y) when the minimum distance between patterns is set to Y is less than 0.8. (2) As above (1) A substrate having a metal fine pattern, wherein a line-to-space ratio (L/S) of a region of the metal fine pattern having a nickel-palladium-gold plating layer is 5 to ΐ〇〇Απι/5 to 1 〇 (3) A printed wiring board characterized in that at least a lower portion of a conductor circuit is buried in a trench provided on a support surface composed of a core substrate or an insulating layer, at least in the conductor circuit - the portion of the partial region that is not in contact with the surface of the groove is covered with a smudged gold plating layer, and the height of the support surface of the conductor circuit in the region having the nickel I mica layer is set to be taken at X When turning), the same as Χ-0), when the minimum distance between circuit patterns is set to γ (Xiao) is less than 0.80 board, wherein the conductor-circuit has a domain-to-space ratio (L/S) of (4) as in the above (3), the printed wiring record - 1 bar-gold deposit District 5~100jUm/5~lOOjum. (5) As in (3) or (4) above (10), 0, ϋ has a region where the gold layer is recorded, and is a circuit for forming a terminal (6) - a type of semi-conductive "set, material sign, at V" printed wiring board 100121202 201230902 A semiconductor element is mounted thereon, and the terminal of the printed wiring board is connected to the output/input part of the semiconductor element. (7) A method for producing a substrate having a fine metal pattern, comprising: preparing to embed at least a lower portion of the fine metal pattern into a groove provided on a support surface made of a resin a step of treating the substrate; performing an electroless nickel-palladium-gold plating step on a portion of the at least a portion of the metal fine pattern of the processing substrate that is not in contact with the groove surface; The height of the metal fine pattern in the electroless nickel-palladium-gold plating region is set to X by the support surface (where XX0 (zero) is regarded as X=0), and the minimum distance between the patterns is set. The ratio of Y (X/Y) is less than 0.8. (8) The method for producing a substrate having a fine metal pattern as described in the above (7), wherein a line-to-space ratio (L/S) of the region in which the metal fine pattern is subjected to electroless nickel-palladium-gold plating It is 5~100/xm/5~ΙΟΟμηι. (9) The method for producing a substrate having a fine metal pattern according to the above (7) or (8), wherein the step of preparing the substrate for processing is performed by using a laser on a support surface of the substrate for processing A trench is formed and metal is deposited in the trench to form a fine metal pattern. (10) The method for producing a substrate having a fine metal pattern as described in the above (7) or (8), wherein, in the step of preparing the substrate for processing, the metal of the fine metal 100121202 8 201230902 pattern transfer sheet The fine pattern is transferred to the heat-treated support of the substrate for processing. (11) A method of manufacturing a printed wiring board, comprising: preparing to embed at least a lower portion of the conductor circuit into the core substrate or insulating a step of processing the wiring board formed in the trench provided on the support surface formed by the layer; and performing no portion of the portion of the conductor circuit of the processing wiring board that is not in contact with the surface of the trench a step of electrolytic nickel-palladium-gold plating; a height protruding from the support surface in an area where electroless nickel-palladium-gold plating is performed on the conductor circuit described above is set to X (wherein, at XS0 (zero), The ratio (Χ/γ) when X = 0) and the minimum distance between circuit patterns is set to Y is less than 0 · 8. (12) The method for producing a printed wiring board according to the above (11), wherein a line-to-space ratio (L/S) of the electroless nickel-palladium-gold plating region of the conductor circuit is 5 to 100/im. /5~lOOjttm. (13) The method of manufacturing a printed wiring board according to the above (11) or (12), wherein the region of the conductor circuit on which the nickel-palladium-gold plating layer is formed is a region where the terminal is formed. (14) The method of manufacturing a printed wiring board according to any one of the above (11) to (13), wherein, in the step of preparing the wiring board for processing, a laser is formed on a surface of the branch of the processing wiring board A trench is formed and gold is accumulated in the trench to form a conductor circuit. The method of manufacturing a printed wiring board according to any one of the above (9) to (10), wherein, in the step of preparing the wiring board for processing, the conductor circuit of the conductor circuit transfer sheet is transferred to the processing wiring board It is heated and softened on the support surface. (Effect of the Invention) According to the present invention, by embedding a fine metal pattern of a substrate having a metal fine pattern on a surface of a resin and performing a plating treatment on the surface of the exposed conductor circuit, the plating bath can be reduced. Since the exposed area of the conductor circuit is reduced, the reaction field generated by the presence of the fine metal pattern (the space in which the reaction activity of the plating bath is high) can be reduced. Further, by embedding the fine metal pattern on the surface of the resin, the unevenness of the circuit on the surface of the resin (the difference between the top of the circuit and the surface of the resin) is small, so that the surface of the resin can be improved, and the palladium catalyst can be improved. Removal. Therefore, according to the present invention, it is possible to prevent the occurrence of abnormal appearance of metal around the fine metal pattern of the substrate to which the metal fine pattern is attached. Further, in the present invention, in order to reduce the exposed area of the fine metal pattern, the conductor circuit is buried on the surface of the resin, so that it is not necessary to reduce the thickness of the fine metal pattern (the circuit sectional area is reduced, and therefore, according to the present invention, not only It is possible to prevent abnormal precipitation of metal and to avoid the problem that the signal transmission speed becomes sluggish. The present invention is a preferred application even for a conductor circuit surface of an electronic component other than a printed wiring board, and further, besides the electronic component In the field of various types 100121202 201230902, the case where the fine metal pattern supported on the resin substrate is bonded is also a preferable application to obtain a mineral coated surface excellent in quality.

When the electroless gold plating is applied to the conductor circuit of the printed wiring board, the cause of abnormal precipitation around the conductor circuit is as follows: I. Pretreatment in the case of electroless recording of gold ore for the conductor circuit of the printed wiring board After the catalyst is applied to the treated surface, the electroless key recording is performed, and in the stage of the I bar catalyst administration step, the metal Pd is selectively attached to the surface of the terminal to be sufficiently mixed, and the surface Pd2+ ion is completely It is difficult to remove the resin from the surface of the support, which is one of the reasons. It is considered that the ruthenium ions remaining on the surface of the resin are caused by the ruthenium (zero) price of the electroless ship material, and the reduced Pd becomes a nucleus to grow the metal granules. In addition, the reason why the abnormal precipitation limit occurs on the surface of the resin of the conductor circuit (4) is considered to be that the reaction of the slit bath is active at the terminal, and the nickel is eluted from the nickel film, and a large amount occurs from the Ni to the Pd near the nickel dissolution site. Replacement (dissolved surface, (10) W). (..., the surface of the grease 100121202, especially the area sandwiched between the adjacent conductor circuits, is because the conductor circuit is dense, so the plating bath B% becomes extremely high. Moreover, it can be considered that when the circuit is miniaturized The smaller the active distance of the conductor is, the higher the density of the conductor circuit is. Therefore, the reaction of the mouth dressing at the conductor circuit (4) between the phases is the same as that of the mouth dressing = 2012. The inventor found that By embedding the conductor circuit on the surface of the resin, precipitation of metal around the conductor circuit can be suppressed, and in particular, precipitation of metal in a region sandwiched between the adjacent conductor circuits can be suppressed. The conductor circuit is buried in the resin surface. In addition, since the exposed area of the conductor circuit of the plating bath is reduced, the reaction field generated by the presence of the conductor circuit (the space in which the reaction activity of the plating bath is high) can be reduced. On the surface of the resin, the unevenness of the circuit on the surface of the resin (the difference between the top of the circuit and the surface of the resin) becomes small, so that the cleansing property of the resin surface can be improved, and High palladium catalyst removal. Even if the conductor circuit is not buried in the resin surface, the thickness of the conductor circuit can be reduced (reduced height), so that the exposed area of the conductor circuit for the plating bath is reduced, and When the surface roughness of the resin surface is reduced, the cross-sectional area of the conductor circuit is reduced, so that the resistance is increased and the signal transmission speed is delayed. Especially when the circuit is finer, the signal is transmitted. On the other hand, in order to reduce the exposed area of the conductor circuit, the conductor circuit is buried in the surface of the resin, so that the thickness of the conductor circuit is not required to be thinned. According to the present invention, not only the abnormal precipitation of the metal can be prevented, but also the problem that the signal transmission speed becomes sluggish can be avoided. Further, as described above, the electroless nickel-palladium-gold plating is performed on the conductor circuit of the printed wiring board. The abnormal precipitation during the application is due to the miniaturization of the conductor circuit, and the smaller the distance between the conductor circuits, the easier it is to cause, and the signal transmission speed is 100121202 12 In 201230902, the cross-sectional area of the circuit becomes smaller and slower due to the miniaturization of the conductor circuit. The present invention is effective in performing electroless nickel-palladium-gold plating on the conductor circuit which has been miniaturized. The metal is prevented from being deposited, and the problem that the signal transmission speed becomes slow can be avoided. The present invention is also applicable to the surface of the conductor circuit of the electronic component other than the printed wiring board, and even in various fields other than the electronic component. Appropriate application is carried out in the case where plating is performed on a metal fine pattern supported on a resin substrate, and a plated surface having good quality can be obtained. According to the above findings, the following invention is provided. The substrate of the present invention having a metal fine pattern is provided. Characterizing that at least a lower portion of the fine metal pattern is buried in a groove provided on a support surface composed of a resin, and a portion of at least a portion of the metal fine pattern that is not in contact with the surface of the groove is characterized by Covered by a nickel-palladium-gold plating layer, which is supported by a fine metal pattern in the region having the nickel-palladium-gold plating layer described above. A height of the protruding surface X (wherein, when in XS0 (zero), as if X = 0), the ratio (X / Y) Y when the minimum distance between the pattern lines is less than 0.8 is set. Further, the printed wiring board of the present invention is characterized in that at least a lower portion of the conductor circuit is buried in a groove provided on a support surface composed of a core substrate or an insulating layer, in at least a portion of the conductor circuit The portion in contact with the surface of the groove is covered with a nickel-palladium-gold plating layer, and the height of the support surface of the conductor circuit in the region having the nickel-palladium-gold plating layer is set to 100121202 13 201230902. x (where XS0 (zero) is regarded as x = 0), and the ratio (X/Y) when the minimum distance between circuit patterns is Y is less than 0.8. Further, the semiconductor device of the present invention is characterized in that a semiconductor element is mounted on the printed wiring board of the present invention, and the terminal of the printed wiring board is connected to the output/input portion of the semiconductor element. Moreover, the method for producing a substrate having a metal fine pattern according to the present invention is characterized in that it comprises: preparing to embed at least a lower portion of the fine metal pattern into a groove provided on a support surface made of a resin. a step of using a substrate; performing an electroless nickel-palladium-gold plating step on a portion of at least a portion of the metal fine pattern of the substrate for processing which is not in contact with the surface of the groove; The height of the fine pattern in the region of electroless nickel-palladium-gold plating is set to x by the support surface (where x0 (zero), which is x = 0), and the minimum distance between the patterns is set to The ratio of Y (X/Y) is less than 0.8. Moreover, the method of manufacturing a printed wiring board according to the present invention includes a processing wiring prepared by embedding at least a lower portion of a conductor circuit in a trench provided on a support surface composed of a core substrate or an insulating layer. a step of performing electroless nickel-palladium-gold plating on a portion of at least a portion of a conductor circuit of the processing wiring board that is not in contact with the surface of the trench; In the electroless nickel-palladium-gold plating region of the circuit, the height protruding from the support surface is set to X (where XX0 (zero), which is regarded as X=0), and the minimum distance between the conductor circuits is set to The ratio of Y (X/Y) is less than 0.8. Hereinafter, the present invention will be described by taking a case where a copper circuit is formed on the outermost layer of the printed wiring board and the terminal region is plated. First, the structure of the printed wiring board will be described. Fig. 1 is a cross-sectional view schematically showing an example of a printed wiring board to which the present invention pertains. The printed wiring board 1 has a core substrate 2 and has conductor circuit layers on both sides thereof. On the upper surface side of the core substrate 2, four layers of conductor circuit layers 3a, 3b, 3c, and 3d are sequentially laminated via the interlayer insulating layers 4a, 4b, and 4c, and an interlayer insulating layer 4d is interposed therebetween. 4, 4e, 4f are sequentially laminated with four layers of conductor circuit layers 5a, 5b, 5c, 5d. The conductor circuit layers 3a to 3d and 5a to 5d are formed on a support surface composed of a core substrate or an interlayer insulating layer. Further, the outermost layer circuit 3d is buried in the trench provided on the interlayer insulating layer 4c, and the conductor circuit layers (3a to c, 5a to d) other than the outermost layer circuit 3d can be buried in the support surface or not buried. In. The upper and lower conductor circuit layers are connected to each other through the via holes. The outermost layer circuit 3d on the upper side of the core substrate is mostly covered by the solder resist layer 6, and the terminal region 7 is exposed from the solder 100121202 15 201230902. The outermost layer circuit 3<1 of the sub-area 7 is covered by a groove, and the outer layer of the sub-area 7 is electrically covered with a 5 gold-plated plating layer 8. The lower surface of the core substrate is most preferably covered by the coal portion, the portion 6a, and the opening portion 6a for connection to the main board or the like. The printed wiring board 1 is connected to the lining (4) from the above-mentioned member, and is connected by a contact lining machine (four) such as a solder ball. The above opening portion & can be the portion 7c. / The structure in which the gap is provided between the antimony and tin resists 6 may be a structure in which the spacer H is broken by the solder _6. In the figure, an opening portion 6a having a structure in which a gap is provided between the (four) port 1 and the solder resist 6 is shown. The second two factors: the 6' system can include a plurality of connection terminals as in the terminal region 7 described above. 6 = = short circuit is formed. Therefore, the above-mentioned opening portion is another known surface treatment method. ',,, electrolytic nickel I gold ore, or according to another, the printed wiring board is tied to the core layer of the laminated structure, but the hair insulating layer I7 brush wiring board is not limited thereto, only in the case of substrate material It has a cut-and-edge structure, and may be a structure in which only the core substrate is provided without an interlayer insulating layer. ...8 Figure 2 is to enlarge the terminal area 7 by 1 point to see the so-called material (four) cents for the material layer and the electron = ^ domain, the edge of the material is covered by the electric I7b contact point of the women's 7& and "the neighborhood near 100121202 201230902 Fig. 3 is a cross-sectional view schematically showing the AA cross section of Fig. 2, that is, the groove 9 and the vicinity of the terminal 7b buried in the groove. A trench 9 is provided on the interlayer insulating layer 4c, and a lower portion of the vicinity of the terminal 7b is buried in the trench. The groove 9 has a bottom surface 9a and a side surface 9b, and the groove surface formed by the bottom surface and the side surface comes into contact with the lower side portion of the terminal vicinity 7b. The upper portion of the vicinity 7b near the terminal is protruded by the groove and covered by the nickel-palladium-gold plating layer 8. Though not shown in detail, the "recording-and-golden coating" refers to a composite plating layer in which a nickel film, a palladium film, and a gold film are sequentially laminated from the side of the keying surface. Further, the cross-sectional view of the circuit shown in Fig. 3 is a rectangular shape. However, the cross-sectional shape of the circuit of the printed wiring board of the present invention is not particularly limited, and it is preferably a rectangle or a square, and may be a trapezoid or the like. The term "buried" in the present invention means a state in which the groove of the support surface is filled by forming a material of the fine metal pattern. Then, the state in which the fine metal pattern of the conductor circuit or the like is buried in the groove exhibits an appearance in which the fine pattern of the metal coincides with the pattern of the grooves and overlaps each other, and at least the lower portion of the fine metal pattern sinks into the support surface. In the present invention, the height (thickness) of the fine metal pattern may be greater than the depth of the trench, may be equal to the depth of the trench, or may be smaller than the depth of the trench. Here, the height (thickness) of the metal fine pattern means the height from the bottom surface of the groove to the top of the metal fine pattern, and is not the "highness of protrusion" from the support surface. 100121202 17 201230902 The case where the height of the fine metal pattern is larger than the depth of the groove means the state shown in Fig. 3. That is, it means that the material forming the fine metal pattern (in this case, the vicinity of the terminal 7b) is completely filled into the groove 9 of the support surface (in this case, the interlayer insulating layer 4c), and the fine metal pattern is further protruded from the support surface. Further, the case where the height of the fine metal pattern is equal to the depth of the groove means the state shown in Fig. 4(A). That is, it means that the material forming the fine metal pattern completely fills the groove 9 of the support surface, and the top surface of the fine metal pattern 7b' is in a state of being coincident with the support surface 4c'. The portion which is not in contact with the surface of the groove is only the top surface of the fine metal pattern 7b', and only the top portion is covered by the nickel-palladium-gold plating layer 8. Further, the case where the height of the fine metal pattern is smaller than the depth of the groove means the state shown in Fig. 4(B). That is, it means that the material forming the fine metal pattern 7b' is filled in the middle of the depth of the groove of the support surface 4c', and the metal fine pattern 7b' is recessed from the support surface. The portion which is not in contact with the groove surface is only the top surface of the fine metal pattern 7b', and only the top surface is covered by the nickel-palladium-gold plating layer 8. The protruding height of the conductor circuit of the terminal region 7 is limited in order to effectively suppress metal deposition around the conductor circuit. That is, the present invention is as shown in Fig. 5, in which the height of the support surface 4c' of the metal fine pattern 7b' in the region having the nickel-push-timepiece layer 8 is set to X (where When XS0 (zero), as X = 〇), the ratio of the minimum distance between the patterns is set to Y (X/Y) is less than 0.8 to adjust 100121202 18 201230902 = inch _; here, the so-called The case where the protruding height X is 0 means that the fineness of the fine metal pattern is the same as the groove depth (Fig. 4(a)). Further, the case where the protruding height X is regarded as 0 means that the height of the fine metal pattern is smaller than the depth of the groove (Fig. 4 (8)). Further, the height of the metal fine pattern is small; the actual protrusion height at the groove depth is not particularly limited, and it is preferable that "heart x" is particularly good. Here, the case where the protrusion height 乂 is a negative value means that the metal fine pattern is recessed with respect to the support surface. In addition, the minimum distance between the patterns refers to, for example, the case of the top view shown in Fig. 2, which is the distance indicated by 乂 in lowercase letters of English, and if it is the case of the sectional view shown in Fig. 2, it is γ in uppercase with English letters. Show distance, which is the minimum distance between circuits of irrelevant circuit shape. For example, if the shape of the circuit is trapezoidal, the distance between the circuits on the bottom surface, if the circuit shape is inverted trapezoidal, the distance between the circuits above is 'the distance between the circuits, and the shape of the circuit is cylindrical' is the distance between the circuits in the center of the circuit. In the printed wiring board 1 described above, the resin surface around the terminal region 7 has a small amount of abnormal precipitation on the resin surface at a position sandwiched between circuits adjacent to each other. Therefore, the quality of the plating treatment surface is excellent, and it is difficult to cause a short circuit. The abnormal precipitation conductor circuit due to nickel-palladium-gold plating is miniaturized so that the distance between the conductor circuits is smaller, and the signal transmission speed is also miniaturized by the conductor circuit, so that the circuit is cross-cut. The smaller the area, the more sluggish it is. According to the present invention, the line-to-space ratio (L/s) of the region of the conductor circuit to be subjected to electroless bromine-palladium-gold plating is 100121202 201230902 5~ΙΟΟμπι/5 In the range of ~100/rni, metal precipitation can be effectively prevented. Further, in the present invention, in order to reduce the exposed area of the conductor circuit and embed the conductor circuit on the surface of the resin, it is not necessary to reduce the thickness of the conductor circuit. Therefore, it is possible to prevent not only the abnormal precipitation of the metal but also the problem that the signal transmission speed becomes sluggish. Further, the line-to-space ratio (L/s) of the region of the conductor circuit to be subjected to electroless nickel-palladium-gold plating is preferably 5 to 50 Mm/5 to 50 μm, more preferably 5 to 25 μm to 5 to 25 μm. Fig. 6 is a cross-sectional view schematically showing a single side of a semiconductor device using the above printed wiring board i. The semiconductor device 11 is mounted on the printed wiring board 1 by a semiconductor. The outermost circuit 3 on the upper side of the printed circuit board k (1 is covered with a solder resist layer 6 and the terminal region is protruded from the material resistance riding groove by a nickel cut layer 8 covered by a cover & The semiconductor element 11 of the domain is fixedly attached to the solder resist layer 6 of the printed wiring board 1 via a die bonding material hardened layer 13 such as an epoxy resin. The semiconductor; the electrode pad 12' is an electrode profile 12 and The connection terminals of the outermost circuit of the printed cloth 2 are connected by a gold wire. The conductor of the conductor device 10 is sealed. The side of the load side is connected by components such as epoxy resin. Other connection means Fig. 6 shows a case where the semiconductor portion is applied to a region array type package or the like by means of wire bonding, and the terminal portion is gold plated. 100121202 20 201230902 Next, the manufacture of the printed wiring board of Fig. 1 will be described. First, a wiring board for processing of electroless nickel-palladium-gold plating is prepared. In the case of the printed wiring board 1, the wiring board for processing is prepared to have a defect from the printed wiring board 1 shown in FIG. Lamination of the structure of the nickel-palladium-gold plating layer 8 Here, the "processing wiring board" when manufacturing a printed wiring board is an intermediate product to be subjected to electroless nickel-palladium-gold plating, and has the following structure: on the surface of the core substrate or the core substrate Providing a trench on a surface of the interlayer insulating layer covered by the laminated conductor circuit layer, and embedding at least a lower portion of the conductor circuit into the trench so that at least a portion of a portion of the portion not in contact with the trench surface of the conductor circuit is In the case of the nickel-palladium-gold plating treatment, the "processing substrate" when the substrate having the metal fine pattern other than the printed wiring board is produced is referred to as having a resin. The base material of the ruling surface has a structure in which at least a lower portion of the conductor circuit is buried in a groove provided on a surface of the branch. Further, the surface of the substrate is made of a resin, and if the metal can be buried In the case of a fine pattern, the deeper portion may be made of a material other than a resin. The support made of resin is formed as a conductor circuit layer buried in an interlayer insulating layer or the like. The method of constructing the surface is, for example, performing laser processing on a support surface composed of a resin to form a groove having the same pattern as the conductor circuit layer, and forming the conductor layer on the support having formed the groove 100121202 21 201230902 In the method of removal (after the laser surface, the conductor layer in the area other than the groove is grooved). Also, the other material preparation will be the green color of the green _ constituting the support: the base material of Table 2 is used to transfer the carrier film by removing the surface of the substrate, and softening the shape P to remove the carrier film by peeling or dissolving. The method (transfer method). As a form of the transfer method, a dry film resist using photosensitivity is used, and a circuit is formed by electrolyzing the surface of the material by the process of electrolysis, and the system is formed by the system. The method of laminating the surface of the support surface in the state of thermal softening of the denomination, and removing the nickel foil by the name after the press forming. 7A and 7B are views showing a sequence of steps of laser processing. In addition, FIG. 7A and FIG. 7 are only schematic views showing one side of the printed wiring board. Hereinafter, the procedure of manufacturing a wiring board for processing by laser processing will be described in detail. First, in the step sequence (a), three layers of conductor circuit layers (3a, 3b, 3c) are laminated on the upper surface side of the core substrate 2 via the interlayer insulating layers (4a, 4b), and the conductor circuit layer 5 is formed. On the lower side, each conductor circuit layer is laminated to form a layer. The core substrate is a known one such as a glass epoxy substrate. The deposition of the conductor circuit layer on the core substrate can also be carried out by a known method such as a semi-additive method (SAP) using a known material. 100121202 22 201230902 Further, the insulating layer 4c is prepared to be laminated on the resin sheet of the carrier film 16. A resin sheet can also be used by a known person to transfer an interlayer insulating layer. The resin composition constituting the insulating layer 4c" is preferably composed of a resin composition containing a thermosetting resin. Thereby, the heat resistance of the resin layer can be improved. Further, the above-mentioned insulating layer 4c" also contains glass fibers. A substrate such as a substrate. Examples of the thermosetting resin include a phenolic varnish-type phenol resin, a phenol varnish resin such as a bisphenol A phenol varnish resin, and an unmodified soluble phenol resin and tung oil. , linseed oil, walnut oil, etc., modified oil-denatured soluble phenol resin, etc., soluble phenolic resin such as phenol tree, bisphenol A epoxy resin, bisphenol F epoxy resin, double cool E Epoxy resin, double s-type epoxy resin, double-presence z-type epoxy resin, bisphenol P-type epoxy resin, bisphenol M-type epoxy resin, etc., bisphenol type epoxy resin, stupid-acid varnish type Epoxy resin, secret varnish epoxy resin, etc. _ Epoxy resin, biphenyl S epoxy dragon, biphenyl aryl burning type 琢 reading grease, aryl stretching wire epoxy resin, naphthalene epoxy resin, Epoxy type epoxy resin, stupid epoxy type epoxy resin, dicyclopentadiene type epoxy resin: epoxy resin, clothing such as reduced-type epoxy resin, diamond-fired epoxy resin type 1 epoxy resin Urea resin, melamine resin, etc. , Polyimide resin, poly-imide resin stuffed Lai, said poly amino acid acetate resin, diallyl S series resins purpose, gamma (iv), the tree having a benzo ring months ah said purpose, 100 121 202 23 201 230 902 III. Well resin, benzocyclobutene resin, cyanic acid, bis-cis-butadiene imine compound, and the like. "The medium is preferably one or more selected from the group consisting of an oxygen resin, a benzene resin, a nitrite resin, a bis-butene = quinone compound, and a benzocyclobutane resin. It is a cyanic acid resin, whereby the resin layer can be reduced in the coefficient of expansion, and the resin layer is excellent in electrical properties (low dielectric constant, low dielectric positive connection) and mechanical strength.乍 is cyanide's specific system, such as age-old varnish-type cyanate-branched tree 曰 曰 纷 纷 A type cyanate g resin, double E-type (four) resin, tetramethyl bis (tetra) cyanate _ lipid, etc. Double-type cyanic acid-forming resin, etc. Among them, the preferred lacquer-type cyanate-lipid. The acid varnish-type nitrite resin can reduce the thermal expansion coefficient of the tree layer and the mechanical strength of the resin layer. It is also excellent in electrical properties (low dielectric constant 'low dielectric positive connection), etc. The weight average molecular weight of the cyanic acid S resin is not particularly limited, and is preferably a weight average molecular weight of 500 to 4,500, particularly preferably 6 〇〇. 3, 〇〇〇. When the weight average molecular weight is less than the above lower limit, there is a resin layer cured product In the case where the mechanical strength is lowered, in addition, when the resin layer is formed, the viscosity is generated, and the transfer of the resin occurs. Further, when the weight average molecular weight exceeds the above upper limit, the hardening reaction becomes faster. In the case of a substrate (particularly a circuit substrate), molding failure may occur, or the peeling strength between layers may be lowered. In addition, the weight average molecular weight of the resin for the succinic acid δ is for example, GPC (gel permeation color) The layer analysis method, the standard substance········································· Bis-m-butylene diimide, o-phenyl bis-bis-butylene diimide, p-phenylene bis-butane quinone imine, 2,2'-[4-(4-heptene醯iminophenoxy)phenyl]propane, bis(3-ethyl-5-fluorenyl-4-maleimidophenylene) decane, 4-mercapto-purine, 3-stretch Phenylbis-n-butenyl-imine, N,N'-extended ethyldimethyleneimine, N,N,_hexamethylenedimethyleneimine Etc. As the poly(n-butylene diimide), polyphenyl fluorene-succinimide, etc. are mentioned, wherein when the high water absorption rate of the test is high, 2, r_double [ 4_(4_cis-butyl diimide phenoxy) phenyl]propane, bis-(3_ethyl·5-methyl_4_cis-butanediamine phenyl)methane is preferred. The content of the thermosetting resin is not particularly limited, and is preferably 5 to 50% by weight of the resin composition 1, and particularly preferably 1 to 4% by weight. When the content is less than the lower limit, it will be _ (4) In the case of (4), when the upper limit is exceeded, the strength of the resin layer may be lowered. Heat = tree: =: yes _ varnish type gas vinegar tree 峨 is an atom) X 4 combined epoxy resin (substantially free of dentate

Examples of the Ζ 树 腊 ' 系 系 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 虱 虱 虱 虱 虱 虱 虱 虱 虱 虱 虱 虱 虱 虱 虱 虱 虱 虱 虱 虱 虱 虱 虱 虱 虱 虱Resin, etc. 25 201230902 Double-type epoxy resin, benzene secret varnish type epoxy resin, T-age secret varnish epoxy resin, etc. (4) varnish type epoxy resin, biphenyl type epoxy tree moon 曰, this two F base Epoxy resin, biphenyl aryl-based epoxy resin, etc., aryl-based epoxy resin, naphthalene epoxy resin, onion-type epoxy resin, phenoxy epoxy resin, dicyclopentane _ Epoxy resin, thin epoxy resin, adamantane epoxy resin, bismuth epoxy resin, etc. The epoxy resin may be used alone or in combination of two or more kinds of different weight average molecular weights, or may be used in combination with two or more kinds of the prepolymers. The content of epoxy resin is determined by the amount of material, which is called the whole product of the seam = the upper part of the assembly. ##The amount of the product is not 之, Β, 'There will be a decrease in the reactivity of the resin, or the result is reduced. When the above upper limit is exceeded, s has a low heat sensitivity and a low heat resistance. The weight of the epoxy resin is about the nominal name. The average molecular weight The average molecular weight is less than the above: _~15, _. When the weight is flat, the H-denier limit will cause a viscous tin on the surface of the resin layer. When the average molecular weight exceeds the above upper limit, the solder heat resistance may decrease. == (Standard 100121202 201230902 The resin composition of the resin layer constituting the printed wiring board of the present invention may be an inorganic filler. The average particle size of the inorganic filler which can be contained in the resin composition constituting the resin layer It is preferable to use 〇·〇5 μmη or more and 〇5 μmη or less. Thereby, fine wiring having high insulation reliability and excellent signal responsiveness can be formed. The measurement of the average particle diameter of the inorganic filler can be performed by, for example, laser diffraction. The scattering method is used for measurement. The inorganic filler is dispersed by ultrasonic waves in water. 'The laser diffraction type particle size distribution measuring device (manufactured by H〇RIBA, LA-500) is made into an inorganic filler by volume basis. The particle size distribution is measured as the average particle diameter. The maximum particle diameter of the inorganic filler contained in the resin composition constituting the resin layer is preferably 2.0% or less. The fine wiring having high insulation reliability and excellent signal responsiveness is not particularly limited, but the maximum particle diameter of the inorganic filler is preferably 1·8 μm or less, and particularly preferably 丨 or less. The effect of improving the insulation reliability and the signal responsiveness can be effectively exhibited. The average particle diameter of the inorganic filler which can be contained in the resin composition constituting the resin layer exceeds the above upper limit value or the maximum particle diameter of the inorganic filler. When the above-mentioned upper limit is exceeded, the inorganic filler may interfere with the laser processing, and there may be a case where the resin layer cannot form a groove. Even if the time for forming the groove by the laser light becomes long, workability is lowered. Possibility. Moreover, due to the inorganic filler remaining on the sidewall surface of the trench after laser processing, the surface of the conductor layer after plating 100121202 27 201230902 will become larger for the high-density printing #线板The accuracy is worse, in addition, in the case of more than 1 GHz &lt; high fresh area reliability, this will damage the signal responsiveness. There will be a result of the skin effect. When the average particle diameter is less than the above-mentioned lower limit value, the number of the inorganic fillers and the physical property e of the elastic modulus of the three components of I are the reliability of the thermal expansion system of the composition of the tree. The tree material which can form the tree layer is not particularly limited, and is, for example, inorganically filled unfired clay, mica, glass, etc., which has talc, fired clay, cerium oxide, and fused silica. Oxide, etc., carbonate, molybdenum hydroxide, sulphate, calcium carbonate, magnesium carbonate, hydroxide, barium sulfate, sulfuric acid, oxidized acid, acid oxidized acid Salt, zinc sulphate, sulphuric acid, sulphate, sulphate, sulphate, sulphate, nitrite, nitrite, etc. The titanate or the like: a nitride such as carbon nitride or the like, which may be an inorganic filler, may be excellent in thermal expansion property, flame retardancy, and elastic modulus. Among them, it is better to reduce the limestone eve. Preferably, c is 'dioxy spherical sulphur dioxide. Among them, it is preferable that the carrier film 16 of the resin sheet has a mold release property capable of transferring the insulating layer 4c to the circuit layer of the conductor 100121202 28 201230902. The carrier film does not use a polymer film or a metal ▲, a limit &amp;, and can be stupid-to-molecular phase, and a poly-peptidic resin such as a polyethylene terephthalate or a polybutylene terephthalate. Polyimide resin, etc. quot&quot;' '' ::metal _ can be made of copper and / or copper alloy, :::: gold, iron and / or iron alloy, silver and / / alloy, gold and / Sheet metal gold, zinc and/or zinc alloys, metal parts such as tin and alloys, alloys, etc. t tin and/or tin lanthanum = the thickness of the film is not particularly limited, when the thickness i is used. ~ Zheng M, when the resin sheet is installed, the rationality is good and better. The thickness of the insulating layer on the j-body film is not particularly difficult, and the immortal ~ Qing m = _ good. It is preferable that the thickness of the tree raft is improved by the insulation: it is preferably at least the above lower limit value, and it is preferably equal to or less than the above upper limit value in order to achieve the crepe film formation of the multilayer printed wiring board. The method for producing the resin film is not particularly limited, and the resin composition may be prepared by dissolving and dispersing the resin composition in a solvent to prepare a resin varnish, and applying the resin varnish to the carrier film using various coating apparatuses. A method of drying the material or a method of drying the material by spraying a varnish on a carrier film using a spray device. Among them, a method in which a resin varnish is applied onto a carrier film by various coating apparatuses such as a dot coater or a pattern coater, and then the article is dried is preferably used. Thereby, a wax sheet having a uniform (four) layer thickness can be efficiently produced. 100121202 29 201230902 The surface film may be roughened or may be a system: If there is a method of physically roughening with a grinder by __agent, etc. ===_ The order (8) is in the order of the above steps (·after preparation, in the order of steps:; eucalyptus wax thin layer insulation layer 4C. The carrier film is peeled off to form an interlayer layer:, '邑 层 layer 4. The carrier has been The surface of the film peeling side is subjected to a roughening treatment. The method of using (7) and the method of interlaminar/ruthenium treatment is, for example, a carrier film which is roughened by a contact surface of _crude 2^2, and is insulated. a method in which the surface of the layer and the surface thereof are peeled off and the contact surface of the stripped layer 4c is widened; (b) a roughening is performed by using (4) stripping treatment with the interlayer insulating layer film; (^) And or by passing the surface of the carrier film without the (4) _ without roughening, 4C, by electropolymerization and/or slag removal, and on the surface of the interlayer insulating layer 4G, the carrier film is in the step: roughening Method, etc. Step:: After laser processing, it is defeated; it is not peeled off and is formed on the surface of step 4c described later. The trench 9 is in the region of the interlayer insulating layer 100121202, and in the region where the conductor circuit formed in the trench 201230902 is finally subjected to nickel-palladium-gold plating, As described above, the ratio (χ/γ) of the height X protruding from the circuit of the support surface to the minimum distance Y between the circuit patterns is less than 〇8, and the size and shape of the groove are adjusted. It is preferable that the depth 幵 of the trench 9 is 50% or less of the thickness of the interlayer insulating layer 4c. The laser light is preferably a pseudo-molecular laser or a YAG laser. By using the laser light. 'The fine wiring can be formed with high precision and shape. Although it is not particularly limited, the laser wavelength of the excimer laser is preferably 193 nm, 308 nm, 248 nm, particularly preferably 193 nm, 248 m^, which is effective. The effect of forming a fine wiring with good accuracy and good shape is exhibited. The wavelength of the YAG laser is preferably 355 nm. The other wavelengths include a resin composition p constituting the interlayer insulating layer and laser light, and fine wiring. Failing to form next, in step sequence (e) , after the interlayer insulation layer - 18 'definitely (four) (four) shape _ route, (4) no transfer plating on the surface of the reed insulation layer 4c to form an electroless gold layer 19. The metal type between the layers is no special mosquito, preferably The coating layer 19 such as copper and nickel is additionally formed in the step of forming the groove 9 and the through hole 18, and it is also possible to add the second step for the second step, and the step sequence (f) is required to form the electrolytic money coating electrolysis. The plating system can be electrolytically plated with copper sulfate. S. 100121202 201230902 Next, in the step sequence (g), the electroless plating layer 19 and the electrolytic plating layer 20 in the region other than the trench are removed, and only A portion of the trench 9 forms the outermost layer circuit 3d. Although it is not particularly limited, the method of removing the electroless plating layer 19 and the electrolytic plating layer 20 is preferably a chemical etching treatment, a polishing treatment, a polishing treatment, or the like. Thereby, only the electroless plating layer 19 and the electrolytic plating layer 20 on the surface of the resin can be effectively removed, and the conductor circuit can remain only in the portion of the trench 9. Then, in the step sequence (h), the solder resist layer 6 is formed on the outermost layer circuit 3d, and at this time, only the portion of the terminal region 7 (not shown) is exposed from the solder resist layer 6, and the wiring for processing can be obtained. board. The wiring board for processing obtained through the above-described step sequences (a) to (h) is exposed from the solder resist layer only in the terminal region 7 of the outermost layer circuit, so that the electroless nickel can be selectively selected for the terminal region of the outermost circuit. - Palladium-gold plating. In the present invention, in the case of performing electroless nickel-palladium-gold plating only for a partial region of a conductor circuit or a fine metal pattern, a soluble resist and a shape may be used in addition to a permanent resist as a solder resist layer. Other masks for plating treatment such as product masks. Fig. 8 is a block diagram showing the sequence of steps of electroless nickel-palladium-gold plating. Hereinafter, the procedure of the above electroless nickel-palladium-gold plating will be described in detail. When the outermost layer copper circuit of the printed wiring board is bonded by the present invention, the surface treatment can be performed by one or two or more methods for the terminal portion as needed before the step of applying the palladium catalyst. In the figure 100121202 32 201230902 8, the 'pre-treatment system shows a detergent (Sla), a soft type (S_, a pickling treatment (Sic), a pre-dip coating (sld), but may be processed other than the above. After the pretreatment, the donor, the electroless nickel plating, the electroless palladium plating, and the electroless gold plating may be sequentially performed to form a nickel-prepared gold (Ni-Pd-Au) film. - the gold-plating method, the pretreatment (S1), the catalyst application step (S2), the electroless recording (S3), the electroless treatment (S4), Electrolytic gold treatment (μ). Hereinafter, the respective processing stages of S1 to S5 will be described in order. <Pre-treatment (Si)&gt; (1) Detergent treatment (Sia) Detergent which is one of the pre-treatments The treatment (s丨a) is carried out by contacting the acid type or the cleaning type detergent liquid on the surface of the terminal, thereby removing the organic film from the surface of the terminal, activating the metal on the surface of the terminal, and improving the wettability of the surface of the terminal. The smear-type type of clearing agent mainly uses the extremely thin part of the terminal surface to be insulted and the surface As a person who is effective for copper terminals, a solution containing a hydroxycarboxylic acid, ammonia water, salt, or a surfactant (for example, ACL-007 of Shangcun Industrial Co., Ltd.) can be used as the other acid which is effective for the copper terminal. For type cleaners, it is also possible to use a solution containing sulfuric acid, a surfactant, and a vaporized sodium (for example, ACL-738 of Shangcun Industrial Co., Ltd.), which is a wetness South 0 100121202 33 201230902 Alkaline type cleaner Mainly to remove organic film,

5 rice cooker, as a copper surfactant, 2-ethanolamine, and other pre-treatment soft (four) treatment (Slb), the extremely thin portion of the terminal surface is side, and (4) oxygen removal is removed. As a copper terminal, it has a soft (four) m' ray containing an acidic liquid containing (iv) sulphur and sulfuric acid. The softening is performed by dipping, spraying, etc., and when the soft buttoning process is performed, the etchant can be washed with water after contacting the terminal portion. (3) Pickling treatment (Sic) The pickling treatment (slc) belonging to other pretreatments is carried out in order to remove stains (copper particles) from the surface of the terminal or the resin surface in the vicinity thereof. As the pickling liquid effective for the copper terminal, sulfuric acid can be used. When the pickling treatment is carried out, the pickling liquid is brought into contact with the terminal portion by dipping, spraying or the like, and then washed with water. (4) Pre-dip coating treatment (Sid) belongs to other treatments such as pre-dip coating treatment (Sid), which is immersed in sulfuric acid of about the same concentration as the catalyst-administered liquid before the step of giving the catalyst, or is The hydrophilicity of the surface of the terminal is raised, and the adhesion to the Pd ions contained in the catalyst-donating liquid 100121202 34 201230902 is increased, or the inflow of the washing water to the catalyst-donating liquid is avoided, and the catalyst can be repeatedly used. The liquid is supplied or removed for the purpose of removing the oxide film. Sulfuric acid can be used as the prepreg coating. When the prepreg treatment is performed, the terminal portion is immersed in the above prepreg coating liquid. In addition, after the prepreg treatment, no water washing was performed. &lt;Palladium catalyst administration step (S2)&gt; An acidic liquid (catalyst-donating solution) containing Pd2+ ions is brought into contact with the surface of the terminal, and Pd2+ can be formed on the surface of the terminal by ionization tendency (Cu+Pd2, Cu2++Pd). The ion is replaced by a metal Pd. The Pd adhered to the surface of the terminal acts as a catalyst for electroless plating. As the palladium salt belonging to the Pd2+ ion supply source, sulfuric acid Ib or gasification can be used. Palladium sulfate is weaker than vaporized palladium and is easy to remove Pd, so it is suitable for fine line formation. As the palladium sulfate-based catalyst-administering liquid system which is effective for the copper terminal, a strong acid liquid containing sulfuric acid, a palladium salt, and a copper salt (for example, KAT-450 of Uemura Industrial Co., Ltd.) and a hydroxycarboxylic acid, sulfuric acid, and palladium salt can be used. Strong acid solution (for example, MNK-4 of Shangcun Industrial Co., Ltd.). On the other hand, since palladium chloride is strongly adsorbed and highly substituted, it is difficult to remove Pd. Therefore, when electroless plating is performed under conditions in which plating is not easily adsorbed, the effect of preventing plating from being adsorbed can be obtained. In the palladium catalyst application step, the catalyst application liquid may be washed with water after being contacted with the terminal portion by dipping, spraying or the like. &lt;Electroless Nickel Plating Treatment (S3)&gt; 100121202 35 201230902 The electroless nickel plating bath may be, for example, a plating bath containing a water-soluble nickel salt, a reducing agent, and a distoring agent. The details of the electroless nickel plating bath are described in, for example, Japanese Laid-Open Patent Publication No. Hei 8-269726. As the water-soluble nickel salt, nickel sulfate, nickel chloride or the like is used, and the concentration thereof is set to about 0.01 to 1 mol/liter. As the reducing agent, hypophosphite such as hypophosphite or sodium hypophosphite, dinonylamine borane, tridecylamine borane, hydrazine or the like is used, and the concentration thereof is set to about 0.01 to 1 mol/liter. As the error-promoting agent, a carboxylic acid such as malic acid, succinic acid, lactic acid, citric acid or the like and a sodium salt thereof, an amine group such as glycine, arginine, imine diacetic acid, alanine or glutamic acid are used. The concentration of the acid is set to about 0.01 to 2 mol/liter. The plating bath was adjusted to pH 4 to 7, and used at a bath temperature of about 40 to 90 °C. In the case where the plating bath uses hypophosphorous acid as a reducing agent, the next main reaction is carried out on the surface of the copper terminal by the Pd catalyst to form a Ni plating film.

Ni2+ + H2P02· + H20 + 2e' ^ Ni + H2P03' + H2 &lt;electroless palladium plating treatment (S4)&gt; As an electroless ore bath, for example, a compound, a distoring agent, a reducing agent, A bond bath of an unsaturated tetamine compound. For the I ba compound, for example, chlorination, sulfuric acid, acetic acid, palladium tartaric acid, tetraamine palladium hydrochloride, etc. may be used, and the concentration thereof is based on palladium, and is set at 100121202 36 201230902 0·001~0.5 Ears / liters or so. As the distoring agent, ammonia water or an amine compound such as mercaptoamine, dinonylamine, decylenediamine or EDTA may be used, and the concentration thereof is set to be about 0.001 to 10 mTorr/liter. The reducing agent is a hypophosphite such as sub-sub-acid, sub-sodium sulfite or sub-Asian acid, and the concentration thereof is set to about 0.001 to 5 m/d. As the unsaturated carboxylic acid compound, unsaturated tracism such as acrylic acid, mercaptoacrylic acid or cis-succinic acid, such acid anhydrides, salts of such sodium salts and money salts, and ethyl esters and phenyl esters thereof are used. Such as derivatives, etc., the concentration is set to about 0 001~10 m / liter. The plating bath was adjusted to pH 4 to 10 and used at a bath temperature of about 40 to 90 °C. In the case where the plating bath uses hypophosphorous acid as a reducing agent, the next main reaction is carried out on the surface of the copper terminal (actually the surface of the nickel) to form a Pd ore coating.

Pd2+ + H2P〇2- + H20 Pd + H2P03' + 2H+ &lt;electroless gold plating treatment (S5)&gt; As an electroless gold plating bath, for example, a water-soluble gold compound, a distorer, and a compound can be used. Mineral bath. The details of the electroless gold bath are described, for example, in Japanese Laid-Open Patent Publication No. 2008-144188. The water-soluble gold compound is, for example, a gold cyanide salt such as gold cyanide, gold potassium cyanide, sodium cyanide or gold ammonium cyanide, and the concentration thereof is set to about 0.0001 to 1 mol/liter on the basis of gold. 100121202 37 201230902 Acid, wine', use ~ acid, boric acid, citric acid, gluconic acid, lactic acid, apple brewed r _, ethylenediamine, triethanolamine, ethylenediaminetetraacetic acid, the concentration is set to 0.001~1 mole / liters around. The secret compound (reduction _ for example, using (4), ethyl alcohol saturated disk, y-di fat H peas, fatty acid unsaturated, benzene fm or p-nitrobenzene, aromatic squama, glucose, galactose, etc. (4) The sugar of the base (collar), etc., the money is set to about 0.0001~0.5 m / liter. The bed is rounded to pH 5~1〇, and the bath temperature is 4〇~9〇. In the case of this plating bath, the next two substitution reactions are performed on the surface of the copper terminal (actually the surface of the surface) to form an Au plating film. Pd + Au + Pd2+ + Au + e' e_ (by Au Catalytic action, obtained by oxidizing the components in the plating bath) + Au+ — Au

In addition, regarding the above-mentioned electroless recording-push-gold plating, Pd which is adsorbed on the surface of the resin can be carried out at any stage before the catalyst is given to the step (S2) and before the electroless palladium treatment (S4) is carried out. The step of removing the medium (post-dip coating step). The post-dip coating step is, for example, a method of using KCN to react a Pd2+ ion with KCN to form a counter ion, a method of inactivating it as a catalyst, or a method of rinsing Pd2+ ions with an acidic liquid. Through the above-described sequence of steps, a Ni-Pd-Au film of good quality is formed on the circuit of the printed wiring board, and a plated surface having a good quality in which the surface of the resin 100121202 38 201230902 around the terminal is not abnormally precipitated can be secured. By mounting the semiconductor device in the form of a printed wiring board of the present invention, it is possible to manufacture a semiconductor device having high connection reliability. [Embodiment] The town is hereinafter referred to as the present invention, but is not limited thereto. &lt;Example 1&gt; (Preparation of test piece) A secret varnish type cyanate ester (manufactured by LQnza Co., Ltd.) nmaset PT-3 〇 'weight average molecular weight approximately · 2 parts by weight, methoxynazepine 35 parts by weight of bismuth-based epoxy resin (manufactured by Otsuka Ink Chemical Industry Co., Ltd., ΕΧΑ-7320), phenoxy resin (manufactured by Nippon Epoxy Co., Ltd., jER4275), 5 parts by weight, compound (four countries) Industrial Co., Ltd., Curezol 1B2PZ (1_¥ base_2_phenyl-saliva muscle 2 parts by weight dissolved and dispersed in methyl ethyl oxime. Next, a laminated filter cartridge (Sumitomo 3M Co., Ltd.) ) For the spherical molten cerium oxide (Electrical Chemical Industry Co., Ltd., SFP-20M), the maximum particle size exceeds .2 Zheng m, and the average particle (4) is 0, and 40 parts by weight is added. Then, 'Add Epoxy Stone Xiyuan Coupling Agent (ge _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Resin varnish. Thickness of resin film after drying using a dot coating device 100 121 202 39 201 230 902 4〇 to the Post

• Insulation layer. Halogen-free FR-5 material, 'thickness 0.4mm • Conductor layer. Copper foil thickness 18μιη, L/s=12〇/18〇/mi, through-hole ΙηιιηΦ, 3ιηπιΦ, slit 2mm in stripped carrier film ( After PET), a groove having a line-to-space ratio (L/S) = 40/40 and a target depth of 15 μm was formed by a resin layer having a substrate having a resin layer having a pseudo-molecular laser having a wavelength of I93 nm. The obtained laminate was immersed in a swelling liquid at 60 ° C (Swelling DIP Securiganth P500, manufactured by Atotech Japan Co., Ltd.) for 10 minutes, and then a potassium permanganate aqueous solution (manufactured by Atotech Japan Co., Ltd., at 80 ° C, Concentrate Compact CP) After 2 minutes of dipping, 'neutralize and carry out slag treatment. After the step of degreasing, catalyst application, and activation, the formation of an electroless copper layer is about 0.2 μm. Next, an electroless copper layer was used as an electrode, and electrolysis was carried out at 3 A/dm 2 . 100121202 40 201230902 ore (Toplucina 〇〇 60 minutes by Okuno Pharmaceutical Co., Ltd.) to form a conductor layer having a thickness of about 20 μm from the surface layer of the resin. A dry film resist (AR320 manufactured by Tokyo Ohka Kogyo Co., Ltd.) was laminated on the surface of the conductor layer, and a predetermined negative film was used for exposure and development to form a necessary plating resist on the conductor circuit. The part was removed by flash etching (SAC process of Ebara Electric Co., Ltd.), and the dry film was peeled off (removal liquid, Mitsubishi Gas Chemical Co., Ltd., R-100, peeling time: 240 seconds). Next, an insulating resin layer was formed. After the temperature is completely cured at 200 ° C for 60 minutes, the circuit is roughened (roughening treatment liquid: CZ8101, 1/mi coarsening condition), and has a line-to-space ratio (Ι73)=40μιη Test piece of copper circuit of /40μιη, protrusion height (X)=20/xm, Χ/Υ=0.50 (electroless nickel-palladium-gold plating step (ENEPIG step)) In the next step sequence, Above test The sheet was subjected to the ENEPIG step 'to obtain the four-layer printed wiring board of Example 1. (1) The cleaning agent was treated with ACL-007 manufactured by Uemura Industrial Co., Ltd. as a cleaning liquid, and the above test piece was immersed in a liquid temperature of 50 ° C for cleaning. After 5 minutes in the liquid, the mixture was washed three times. (2) Soft etching treatment After the cleaning agent treatment, a mixture of sodium persulfate and sulfuric acid was used as a soft etching solution, and the test piece was immersed at a liquid temperature of 25. (: After 1 minute, the soft etching solution was washed with water three times. 100121202 41 201230902 (3) After the pickling treatment, the test piece was immersed in sulfuric acid at a liquid temperature of 25 ° C for 1 minute, and then subjected to a soft etching treatment. (3) Pre-dip coating treatment After the pickling treatment, the test piece was immersed in a liquid temperature of 25. (1: sulfuric acid for 1 minute. (5) The catalyst application step was performed after the pre-dip coating treatment 'In order to supply a palladium catalyst to the wiring portion, KAT-450 manufactured by Uemura Kogyo Co., Ltd. was used as a palladium catalyst doping liquid. The test piece was immersed in a liquid temperature of 25. (: Palladium catalyst doping liquid 2 After a minute, it was washed 3 times. (6) Electroless Ni plating treatment

After 35 minutes, it was washed 3 times.

The test piece was immersed in a liquid temperature of 8 CTC (7) electroless Pd plating treatment after electroless Ni plating treatment,

(8) Electroless Au plating treatment 'Immerse the upper test piece in liquid temperature TPD-30) 15 minutes 'The above test piece was immersed in liquid temperature industrial (share) TWX-40) 18 points After the electroless Pd plating treatment, the electroless Au bell bath at 80 ° C (Shang Cun Gong 100121202 42 201230902) was washed 3 times. <Example 2> In addition to the 5 history, the line-to-space ratio (L/S) In the same manner as in the first embodiment, a four-layer printed wiring board was produced in the same manner as in the example 1 except that the height of the protrusions (15) and the protrusion height (Χ) = 15 μm and Χ / γ = 0.75. 3&gt; In addition to setting the line-to-space ratio (L/S) = 25jnm/25gm, after the electrolysis of the copper, the electrolytic copper is etched away by 20 μm to make the protrusion height (χ) = 〇μηα, X/Y = 〇 'Operation was carried out in the same manner as in Example 1 to produce a four-layer printed wiring board. <Example 4 &gt; In addition to the line-to-space ratio (L/S) = 25/mi/25 pm, after the shovel copper was The electrolytic copper was etched away by 25/mi so that the protrusion height (X) &lt; 〇Mm (actually Χ = -5 μιη) and χ / γ = 〇 were operated in the same manner as in the example i to fabricate a four-layer printed wiring. Plate. &lt;Comparative Example 1&gt; A four-layer printed wiring board was produced in the same manner as in Example 1 except that the line-to-space ratio (L/S)=25jLtm/25jLtm, the protrusion height (Χ)=20μηι, and χ/γ=0.8〇. Comparative Example 2&gt; The same as Example 1, except that the line-to-space ratio (L/S)=25/xm/25 jiim, the protrusion height (X)=25/xm, and χ/γ=1. The operation is carried out to produce a four-layer printed wiring board. 100121202 43 201230902 ▲The following flat evaluations are made for each real and smeared printed material board. The results are shown in the "F. Table 1 ° &lt;Presence of abnormal precipitation&gt; The terminal portion of the printed wiring board was observed by an electron microscope (reflected electron image) to evaluate the presence or absence of abnormal precipitation. 〇: No abnormal precipitation was observed Δ: There were some abnormal precipitation at the edge of the circuit X: Abnormal precipitation in the entire space &lt;Insulation test&gt; The presence or absence of a short circuit between the wirings of the printed wiring boards obtained in the examples and the comparative examples was examined using a conduction tester (Ηΐοκΐ: χ=yc Hightester 1116). X : There is conduction [Table 1]

Example 1 Example 2 Example 3 Example 4 Comparative Example 1 Comparative Example 2 L/S (μπι/μιη) 40/40 20/20 25/25 25/25 25/25 25/25 Two degrees of protrusion (X ) (nm) 20 15 0 X&lt;〇* 20 25 Space 40 20 25 25 25 25 X/Y 0.50 0.75 0 is called 0 0.80 1 1.00 Abnormal precipitation 〇Δ 〇〇X . X Insulation test 〇〇〇〇 XX * Actual The protruding height (X) is -5 jum. 100121202 44 201230902 In the printed wiring board obtained in the first to fourth embodiments, the abnormal precipitation between the wirings is not or relatively v. Even after the ENEPIG step, the insulation between the wirings m can be maintained. It is possible to confirm the abnormal precipitation and confirm the short circuit between the wirings. Therefore, it is known that the conductor circuit is buried on the surface of the resin, and the ratio (χ/γ) of the height X of the conductor circuit protruding from the surface of the branch to the minimum distance γ between the circuit patterns is less than 0.8. The printed wiring board of the invention prevents abnormal precipitation of metal around the circuit from being effective for insulation between wirings. &lt;Comparative Example 3&gt; The line-to-space ratio of the region of the conductor circuit where electroless nickel-palladium-gold plating is to be performed is set as an example! The same 4〇μιη/4〇μιη, and the conductor circuit and the embodiment in which the conductor circuit is not buried on the resin surface, and the thickness of the conductor circuit existing only on the surface of the resin is set to 20/xm. Compared to the conductor circuit, the cross-sectional area is only about 6 G%, and the resistance is increased by about two times. According to the present invention, not only the &lt;prevention of abnormal precipitation of metals, but also the problem of slow transmission of the k-number can be avoided. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view schematically showing an example of a printed wiring board to which the present invention pertains. Fig. 2 is a plan view showing a part of a terminal area of a printed wiring board in an enlarged manner. Fig. 3 is a view schematically showing a section taken along line VIII of Fig. 2. Fig. 4 is a cross section of the buried w-shaped portion of the circuit board layer 100121202 45 201230902. Fig. 5 is a conceptual diagram illustrating the relationship between the height X of the metal fine pattern protruding from the support surface and the minimum distance Y between the patterns. Fig. 6 is a cross-sectional view schematically showing one side of a semiconductor device to which the present invention pertains. Fig. 7A is a plan view showing the sequence of the steps (first half) of the laser processing. Fig. 7B is a one-sided view showing the sequence of steps (second half) of the laser processing. Fig. 8 is a block diagram showing the sequence of steps of electroless nickel-palladium-gold plating. [Description of main component symbols] 1 Printed wiring board 2 Core substrate 3 (3a, 3b, 3c, 3d) Conductor circuit layer 4 (4a, 4b, 4c, 4d, 4e, 4f) on the upper side Interlayer insulating layer 4c' Support surface 4c,, 5 (5a, 5b, 5c, 5d) 6 6a 7 7a 7b 7b, conductor circuit layer on the lower side of the insulating layer, solder resist layer opening portion, terminal region, pad metal pad pattern, near the pad metal pad pattern 100121202 46 201230902 7c Pad portion 8 Nickel-bismuth-gold ore deposit 9 Groove 9a Bottom surface 9b Side surface 10 Semiconductor device 11 Semiconductor component 12 Electrode pad 13 Grain bonding material hardened layer 14 Gold wire 15 Sealing material 16 Carrier film 17 Laser light 18 through hole 19 electroless plating layer 20 XY y electrolytic plating layer minimum distance between the height patterns of the height pattern of the metal micro pattern supporting surface 100121202 47

Claims (1)

201230902 VII. Patent application scope: 1. A substrate with a fine metal pattern, characterized in that at least a lower portion of the fine metal pattern is embedded in a groove provided on a support surface composed of a resin, A portion of at least a portion of the metal fine pattern that is not in contact with the surface of the trench is covered with a nickel-palladium-gold plating layer, and a metal fine pattern is used in the region having the nickel-palladium-gold plating layer. The height at which the support surface protrudes is set to χ (wherein, when XS0 (zero), the same Χ = 〇), and the ratio (χ/γ) when the minimum distance between the patterns is γ is less than 〇8. 2. The substrate having the fine metal pattern of the first aspect of the patent application, wherein the line-to-space ratio (L/S) of the region of the metal fine pattern having the nickel-Ιε-gold plating layer is 5~ lOO/im/5~100/mi. 3. A printed wiring board characterized in that at least a lower portion of a conductor circuit is buried in a trench provided on a support surface composed of a core substrate or an insulating layer, in at least a portion of the conductor circuit a portion in contact with the surface of the trench is covered with a nickel-palladium-gold plating layer, and a height protruding from the support surface of the conductor circuit in the region having the nickel-palladium-gold plating layer is set to χ (where When χ$〇 (zero), the same as χ=〇), the ratio of the minimum distance between circuit patterns is set to Υ (Χ/Υ) is less than 0.8. 4. The printed wiring board according to item 3 of the patent application, wherein a line-to-space ratio (L/S) of the region of the conductor circuit having a nickel ore deposit is 100121202 48 201230902 5~100μηι/5~ΙΟΟμηι . 5. The printed stretcher of claim 3 or 4 wherein the conductor circuit has an area in which the gold bond layer is recorded to form a soul domain. ○ &lt;Zone-type semiconductor device, characterized in that 'the semiconductor device is mounted on the printed wiring board of the above-mentioned patent range, and the terminal of the printed wiring board and the output/input portion of the semiconductor element Connect. 7. A method for producing a substrate having a fine metal pattern, comprising: preparing a process for burying at least a lower portion of the metal fine into a groove provided on a support surface made of a resin. a step of applying a substrate to the portion of the metal fine pattern of the processing substrate that is not in contact with the surface of the groove, and performing the step of applying an electroless nickel to the metal; The height of the pattern in the electroless nickel-palladium-gold plating area is set to χ (wherein, when xg 〇 (zero), the same Χ = 〇), and the minimum distance between the patterns is set to The ratio of γ (χ/γ) is less than 0.8. 8. The method for producing a substrate having a fine metal pattern according to item 7 of the patent scope of the invention, wherein the metal fine pattern has a line-to-space ratio (L/s) of an electroless nickel-palladium-gold plating region. ) for 5~1〇〇师/5~ι〇_. 9: A method for producing a substrate having a metal fine pattern according to the seventh or δth aspect of the patent application, in the step of preparing the substrate for processing, using a substrate of 100121202 49 201230902 for laser treatment A groove is formed on the support surface, and the metal is deposited in a 5-well groove to form a fine metal pattern. 10. The method for producing a substrate having a metal fine pattern according to the seventh or eighth aspect of the patent application, wherein the metal fine pattern of the metal fine pattern transfer sheet is transferred to the step of the substrate for the food preparation The heated substrate of the substrate for treatment is softened. A method of manufacturing a printed wiring board, comprising: preparing a processing wiring board in which at least a lower portion of a conductor circuit is buried in a trench provided on a support surface formed of a core substrate or an insulating layer; a step of performing electroless nickel-palladium-gold plating on a portion of at least a portion of a conductor circuit of the processing wiring board that is not in contact with the surface of the trench; performing electroless electrolysis on the conductor circuit The height of the nickel-palladium-gold plated region protruding from the support surface is set to χ (wherein χ$〇 (zero), which is regarded as X-0), and the minimum distance between circuit patterns is set to Y. The ratio (X/Y) is less than 0.8, such as the manufacturing method of the printed wiring board of the U through the patent application scope, wherein the line-to-space ratio of the area of the electroless nickel-palladium-gold plating of the conductor circuit is L/S) is 5~1〇〇μιη/5~ΙΟΟμηι. 13. The method of manufacturing a printed wiring board according to the invention of claim 5, wherein the region of the conductor circuit on which the nickel-palladium-gold plating layer is formed is a region where the terminal is formed. The method of manufacturing a printed wiring board according to any one of the preceding claims, wherein the step of preparing the wiring board for processing is performed by using a laser beam on a support surface of the wiring board for processing A trench is formed thereon and metal is deposited in the trench to form a conductor circuit. The method of manufacturing a printed wiring board according to any one of the preceding claims, wherein in the step of preparing the wiring board for processing, the conductor circuit of the conductor circuit transfer sheet is transferred to a process for processing The wiring board is heated and softened on the support surface. 100121202 51