TW201230577A - Power supply with open-loop and short-circuit protection - Google Patents

Abstract

The power supply according to the present invention comprises a transformer, a power switch, a signal generating circuit, a turn-on detection circuit, and a delay circuit. The transformer receives an input voltage and generates an output voltage. The power switch switches the transformer for adjusting the output voltage. The signal generating circuit produces a switching signal to control switching of the power switch. The turn-on detection circuit detects a turn-on time of the power switch and generates a short-circuit signal. The delay circuit counts to a first delay time or to a second delay time for generating a turn-off signal according to a feedback signal and the short-circuit signal of the power supply. The turn-off signal controls the signal generating circuit to latch the switching signal.

Description

201230577 VI. Description of the Invention: [Technical Field] The present invention relates to a power supply, and more particularly to a power supply having open circuit protection and short circuit protection. [Prior Art] A general power supply can provide stable voltage and current. In order to comply with safety regulations, the power supply must provide open circuit protection (〇pen_1〇〇ppr〇tecti〇n) and short circuit protection to ensure that the power supply itself and the application circuit at the load side are not affected. . Referring to Figure 1, there is shown a circuit diagram of a conventional power supply with open loop protection. A conventional power supply includes a transformer 、, a reset circuit 14, a signal generating circuit 10, an oscillator 12, a power switch 仏 ' feedback detection circuit 16, a delay circuit 18, and a drive circuit 20. As shown in Figure 1, the transformer 具有 has a primary winding NP and a secondary winding ns for storing energy and power conversion. The transformer ^ is coupled to the input voltage Vin of the power supply to generate an output voltage V. . The power switch Q switches the transformer T to convert the energy stored in the primary winding of the transformer 至1 to the secondary winding Ns. The energy converted to the secondary winding Ns is rectified by the output rectification benefit Do and the output capacitor C 并 to generate an output voltage v 。. The current sensing resistor Rs is connected in series with the power switch 4. The current sensing resistor Rs generates a current signal Vcs according to the primary side switching current Ip of the transformer Τι. In addition, the output voltage of the power supply unit provides a feedback signal to the reset circuit 14 and the feedback detection circuit 16 through a feedback method. The reset circuit 14 includes a logic circuit 144, a power limit comparator 146, and a pwM (Pulse Width Modulation) comparator 148. The reset circuit 14 generates a clear signal CLR according to the current signal Ves, the power limit signal VuT and the feedback signal vFB to turn off the switching signal vTM. Power Limit 201230577 The comparator 146 and an input of the PWM comparator us are coupled to the current sense resistor 仏' to receive the current signal Vcs. The other input of the power limit comparator 146 receives the power limit signal Vlmt. The other input of the PWM comparator 148 receives the feedback signal vFB. When the current signal Vcs is greater than the power limit signal Vlmt, the output of the power limit comparator 146 will output a low level overcurrent signal 〇c. In addition, when the current signal Vcs is greater than the feedback signal VFB, the output of the PWM comparator 148 will generate a low-level feedback control signal CNTR. The two input terminals of the logic circuit 144 are coupled to the outputs of the power limit comparator ι46 and the pwM comparator 148, respectively. Therefore, the output of the logic circuit 144 will generate a low-level clear signal CLR according to the over-current signal 〇c and/or the feedback control signal CNTR to turn off the switching signal Vpm. In other words, the reset circuit 14 is controlled according to feedback. The logic level of the signal CNTR or the logic level of the overcurrent signal 〇c determines the logic level of the clear signal CLR. The signal generating circuit 10 includes a logic circuit 1〇1, a flip-flop 1〇3, and a logic circuit 1〇5. The logic circuit 101 is an inverter having an input coupled to the oscillator 12 for receiving the clock signal PLS output from the oscillator 12. The output terminal of the logic circuit 101 is coupled to the clock input terminal 正 of the flip-flop 1〇3 to drive the flip-flop 103. The input terminal of the flip-flop 103 is connected to the output terminal of the delay circuit 18. The output terminal Q of the flip-flop 103 is coupled to one of the input terminals of the logic circuit 1〇5, and the other input terminal of the logic circuit 1〇5 receives the clock signal PLS via the logic circuit m. The output of the logic circuit 1〇5 generates a switching signal VP. The logic circuit 105 is a gate (10)_). The reset input terminal r of the flip-flop 1〇3 is connected to the output terminal of the reset circuit 14 to receive the clear signal aR, and the test circuit (4) is connected to the output terminal of the reset circuit 14 and the reset circuit 14. The generation circuit 1() generates a switching subtraction vTM based on the clock signal PLS output from the violin 12 . The drive circuit 20 receives the switching signal u to generate the drive signal vG. The drive signal Vg is used to control the switching of the power switch Qi to adjust the input voltage %. 201230577 Since the switching money VTM is supplied to the driving circuit 20 to drive the driving signal VG, the switching signal vTM is also used to control the switching of the power switch Qi. The signal generating circuit 1 切换 switches the pulse width of the VpWM according to the clear signal ω outputted by the reset circuit μ, so that the output voltage ν〇 of the electric secret device is stably adjusted, and the output power is limited.

Referring to FIG. 1, the input terminals of the feedback detecting circuit 16 respectively receive the feedback signal ~ and the threshold signal Vumt to generate a pull-up (puU_high) signal SpH. When the power supply is in normal operation, the feedback signal VFB is lower than the critical signal νυϊ” At this time, the output of the feedback side circuit 16 generates a low-level pull Saki SPH. The delay circuit 18 receives the low level pull-up. The signal will not be counted afterwards, and the cut-off signal &1? of the direct input level will be sent to the signal generating circuit 1G. The signal generating circuit 1 receives the cut-off signal of the level 3^. It does not latch the switching signal. 'When the open circuit (0pen L00p) state occurs at the output of the power supply, the level of the feedback signal I is pulled up to the supply voltage I through the pull-up resistor RPH. When the feedback signal ~ is pulled When the value is higher than the threshold 峨%, the input (4) of the __ way 16 generates a high level, and the threshold SPH delay circuit 18 will count according to the high level s s s, and at ten (the late time reads low) The cut-off signal & "signal generation circuit will be based on the low level _ stop _ S. Side locks the city weaving%, miscellaneous _ test county 1 this, back to her road〗 6 fine Wei 18 fine touch ^ tender Yu Gao (4) Drive the signal to generate the circuit 10 to lock the switching signal for open circuit protection. π people call muscle νπϊ< Than the pull-up resistor ^ is pulled high to the supply voltage Vc. The feedback detection circuit 16 is the pull-up signal of the position ~ (late circuit 8 will enter the (four) number, and after the count to the delay _ after the fresh The bit-cut signal '. The weaving circuit 1G will switch the signal according to the low-level (four) cut-off signal ^, 201230577 == should be 11 峨, the reward _ the same as the open circuit, the application of the t-shirt Therefore, in order to improve the safety of the power supply, when the power supply is short-circuited, the signal (4) should check the switching signal (4) short-circuit protection as soon as possible. Therefore, how to make the power supply correctly distinguish the power supply The supply is open circuit or short circuit, and it is an important issue in the design of the tearing wire.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a power supply having an open loop and a short secret. When the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ In this way, the power supply can be short-circuit protected for a short time when the power supply is short-circuited. The power supply device with open loop protection and short circuit protection includes: a transformer, a power switch, a signal generating circuit, a conduction detecting circuit and a delay circuit. Wherein the transformer receives an input voltage for generating an output voltage. The power switch is coupled to the transformer and switches the transformer to adjust the output voltage. The signal generating circuit generates a switching signal to control the switching of the power switch. The conduction detection circuit detects an on-time of the power switch to generate a short-circuit signal. The delay circuit generates a cutoff signal according to the short circuit signal and one of the power supply feedback signals. Cutoff signal The control signal generation circuit locks the switching signal. The turn-on detection circuit detects the turn-on time of the power switch' to determine whether the power supply is shorted or open circuit to generate a short circuit signal. The delay circuit counts the first-delay time or the second delay time based on the short 201230577 way-down decision. In this way, after the delay circuit counts the delay scales in different conditions (short-circuited Rina), that is, Zhao Zhuang minus the control signal generating circuit check lock switching signal 'to make the power supply as appropriate as possible. In order to enable the reviewing committee to have a better understanding and understanding of the technical features and the efficacies of the present invention, please refer to the detailed description of the preferred implementation and explain the following: [Embodiment] μ refers to 22 ® BRIEF DESCRIPTION OF THE DRAWINGS A circuit diagram of a first embodiment of a power supply having a chest circuit. In addition to the prior art shown in Fig. i, the present invention adds a conduction detecting circuit 30, a confirming circuit 4, and a depletion 5G. The conduction side circuit 3 () receives the drive signal V. Or switching the signal Vp„' to detect the on-time of the power switch Qi, and generating the short-circuit signal & In addition, the conduction detecting circuit 30 further receives the clock signal of the vibrating device 12. The short-circuit signal

Sa is provided to Gu Zu 4〇. Lai Wei 4 (H is suspected of rugged & and the reference Saki produces selective subtraction, the reference signal can be shredded ^ ^, or phase. Switching signal v_ drive minus VG or clock signal pLSe clock decrement from PLS 12, and synchronized with the drive message. When the power supply is short-circuited, the output current will rise and the output power (4) will drop. Because the output voltage V. and the input voltage V|N, the sub-ender group (4) and the second tender The N-number ratio of the group is proportional to the conduction _ of the power switch Qi, and the success ratio of the input voltage V|N is a fixed value. Therefore, the voltage V of the turn-off voltage is decreased, that is, the conduction-change sentence field of the identification Qi is determined. The level of the screaming signal Vfb is greater than the threshold signal K side circuit 16 generates a high level of the pull-up signal & bucket and the conduction detection circuit 3G _ power switch Q, the conduction time is short, the time gate is shaken, indicating 201230577 power supply The short circuit occurs in the supplier. In addition, when the detecting circuit 16 generates the high level pull-up signal ^, if the power switch & the on-time continues to be higher than the preset time threshold, indicating that the power supply is open circuit. The present invention utilizes The turn-on detection circuit 30 detects the on-time of the power switch Q, and The short circuit state is recognized, and the open circuit state is confirmed by the confirmation circuit 4〇. The confirmation circuit 4 is coupled to the conduction detection circuit 30 and receives the short circuit signal Sa and the reference signal to confirm that the conduction time of the power switch Qi continues to be higher than the pre-test. The time threshold is set, and the selection signal & a is generated. The delay circuit 19 is coupled to the detection circuit 16 and the confirmation circuit 4A, and receives the pull-up signal & and the selection signal SSEL. The delay circuit 19 is pulled according to the high level. The high signal SpH and the selection signal generate a cutoff signal after the preset first delay time or the second delay time. The signal generation circuit 10 will check the switching signal vTM according to the cutoff signal S〇FF for short circuit protection or opening. Loop protection: Since the level of the pull-up signal SPH is determined by the level of the feedback signal Vfb, the delay circuit 19 starts counting according to the feedback signal V to drive the signal generating circuit 1 to perform short-circuit protection or open loop protection. Wherein the 'first delay time is shorter than the second delay time; the first delay time corresponds to the short circuit protection' and the second delay time corresponds to the open circuit protection. The circuit 4 is configured to generate the selection SsEL according to the short-circuit signal Sa to determine that the delay circuit 19 counts to the preset first delay time or the second delay time to generate the cut-off signal ', so the delay circuit 19 determines the count according to the short-circuit signal heart. - After the delay time or the second delay time, open circuit protection or short circuit protection is performed. The frequency divider 50 is connected to the oscillator 12 and receives the basic pulse signal ακ generated by the oscillator 12. The frequency divider 30 divides the basic pulse signal. CLK to generate the first pulse signal & and the second pulse signal I brother - pulse wave signal ^ the frequency is higher than the second pulse wave signal ^ frequency, that is, the first pulse wave

The week of Feu 201230577 is in the period of the first: pulse wave signal SaK. The first-pulse number & and the second pulse signal ^ is __路19, extension _ 19 according to the 仏 仏 _ pulse signal W second pulse signal & count for the time reference (-) - Delay time or second delay time. See the implementation of the circuit of the invention of m County. As shown, the conduction detection circuit 30 includes a mineral tooth signal generation circuit, a comparator coffee and a counting circuit. And, the surface signal generating circuit comprises an inverter, a current, a transistor and a capacitor. The sigma signal generating circuit generates a recording number ^ according to the power opening (four) conduction time. The input of the inverter receives the drive signal or the switching signal Vw. The output of the inverter 3〇ι is connected to the Han, and the crystal is controlled by the crystal. The source of the electric crystal is connected to the ground. The current source 302 is nested between the supply voltage Va and the terminal of the capacitor for use, and the other end of the 304 is connected to the ground. The transistor 3〇3 is connected to the capacitor 304 for discharging the capacitor 3〇4. The driving signal switching signal VpB (when enabled, the inverter 3G1 cuts off the transistor network, and the current source 302 charges the battery valley 304. The driving signal Vc or the switching signal Vra (when disabled, the inverter conducts the crystal 303, and The capacitor 304 is discharged. Thus, the sawtooth signal Vm is generated in the capacitor 3〇4. The driving time of the driving signal V. or the switching signal v M is reduced by the conduction time of the discriminating (four). In other words, the ore signal generating circuit is According to the on-time of the power switch 4, the wrong input signal VSA is generated. The negative input terminal and the positive input terminal of the comparator 305 respectively receive the recording tooth signal v and the door shaking signal vTH to compare the ore tooth signal VsAW with the door shaking signal, and compare The output of the device 3〇5 generates a periodic signal Sduty. 201230577 As shown in Fig. 6A, when the V tooth reduction Vsw is smaller than the gate magnetic signal Vth, the level is high. The number Vs is in the gate. In Vth, the level of the periodic signal s_ is low. In other words, when the power-on Q1 is short, the _Vsw is the age signal vTM' and the periodic signal LV is at the high level. The power switch Qi has a long conduction time, and the mineral tooth signal Vs «is secret Threshold signal Vth 'level and the number s_ periphery of GU at the low level. Shake gate signal v ™ level of time-based threshold, of the subtraction, the level at the high level, i.e. unlock represents _

The on-time is lower than the time gate. The periodic signal and the level are low, which means that the on-time of the power switch Qi is higher than the time threshold. Ten circuits ^ forward and reverse devices 306 and 307. The counting circuit is used to confirm that the on-time of the power switch 并非 is not a malfunction of the power supply and is temporarily lower than the time. Pros and cons

Clock terminal 0 (receive New Zealand to break the outline, send the message to purchase the county's butterfly signal I or the clock signal PLS. The input terminal D in the flip-flop receives the supply voltage v "the input of the forward and reverse _ to The output of the flip-flop is Q. The inverting output of the flip-flop 3〇7 is short-circuited and reduced. In addition, the 'reverse-reverse write is shared with the reset terminal r of 3G? to the output of the comparator fox. It is used to receive the periodic signal Sduty. Therefore, when the on-time of the power_ is less than the time (10) and the periodic signal S_ is at the high level, the positive and negative are set. The count is based on the drive, the switching signal Vm or the clock 峨 PLS. Counting. The counting circuit counts, after the 5th time is enough, the short-circuit signal S〇L of the low level is generated. When the conduction switch of the power switch Q丨 is at the time threshold and the periodic signal L_ is low level The flip-flops 306 and 307 will be reset, and the level of the 罝I 矾I Sa is high. If the feedback signal VTM is higher than the critical signal v(10) (see ww' and short-circuit «Sa The level is 201230577 low level, which means that the power supply channel signal Sol is at a high level and short circuit. If the return value of Vkb is higher than the critical signal That is to say, the power supply is open circuit. No. VUMT, and short please refer to _, the embodiment of the circuit diagram of the confirmation circuit of the county invention. As shown in the figure, the confirmation circuit AG includes positive and negative ^ and surgery. Short circuit minus SflL

The power-on time of the power-on _ is continued for the secret time service, rather than the power supply's secret action and is temporarily higher than the time surface. The positive and negative (10) clock terminal CK receives the drive susceptibility, and switches the W-go clock signal PLS ' to receive the input signal VG according to the drive signal VG, the switching signal L or the clock signal yang, and the D-number positive and negative 401 Supply voltage ~. The input end of the forward and reverse ship _ is connected to the positive and negative. In addition, the reset terminals R of the flip-flops 401 and 402 receive the short-circuit signal & When the power switch Q, the on-time is held by the time threshold and the short-circuit signal & the level is low level, the flip-flop and the 402 will be reset, and the level of the selection signal ‘ is low. When the on-time of the power switch Q is greater than the time when the switch is shorted and the short-circuited state is at a high level, the flip-flop and the 402 are not reset, and the drive signal %, the switching signal i or the clock signal are similar. count. If the on-time of the power switch Q is greater than the time gate during the period of the preset drive signal Vc, the switching signal % or the clock signal pLs, it is confirmed that the power switch_on time is slaved to the time rm. The flip-flop 402 generates a high-level selection signal ‘. " Fig. 5 is an embodiment of a circuit diagram of the delay circuit 19 of the present invention. The delay circuit μ package is now 192 194, "195, the inverter 196, or the gate 197, the first switch 198 and the second switch 199 ° the first switch 198 and the second switch 199 are connected Frequency converter 5() (as shown in FIG. 2) to respectively receive the first pulse signal Fcu and the second pulse signal & the first switch kiss and the other end of the 12 201230577 first switch 199 are respectively The two inputs of the gate 197. The first switch 198 transmits the first pulse signal $FaK to the OR gate 197 via the inverter 196 controlled by the selection signal sSEL. The second switch 199 is directly controlled by the selection signal ^ and transmits The second pulse signal 'to or 97' or the gate 197 read terminal produces an output signal SpCK. In other words, the output minus & is the first pulse signal Fan or the second pulse signal S〇k.

The clock terminal CK of the flip-flop 192 is connected to the output terminal of the gate m to receive the output signal ^ (the first pulse signal Fax or the second pulse signal & heart. the input of the flip-flops 192, 194, · 195 The terminal D receives the supply voltage Va. The clock terminals (3) of the flip-flops 194 and 195 are connected to the output 4 of the upper-stage flip-flop. For example, the clock terminal CK of the flip-flop 194 is connected to the output of the flip-flop. The inverting output terminal /Q of the QK flip-flop 195 generates a cut-off signal. In addition, the flip-flop is removed, and the reset terminal R of 194 195 is commonly transferred to the output terminal of the gamma-j circuit 16 (see FIG. 2) for Receiving the pull-up signal Sph, wherein the delay circuit 19 counts according to the first pulse signal--, P is the tenth delay time. The delay circuit 19 counts according to the second pulse signal ^^, that is, the tip-delay In other words, the 'delay circuit Μ according to the selection signal ― controls the first 1 switch 198 or the _ switch 199 ′ to control the flip flop according to the first pulse minus & or the second pulse minus Scu. The delay circuit μ depends on the selection of the first delay time or the second delay coffee. When the first-track number ^ is shorter than the second pulse During the period of the signal ', the first delay time is shorter than the second delay time. 〇W < source supply 11 operation is normal! The feedback signal W will be lower than the critical signal m_ circuit 16 output end low level (four) pull high After the delay signal 19 receives the low level pull-up signal & the positive and negative, please, the rhyme, see the i-th] 13 201230577 5 figure) will be reset. Therefore, the delay circuit 19 does not count, and the inverted output terminal /Q of the flip-flop 195 of the last stage of the delay circuit 19 directly outputs the high-level cutoff signal s 〇 FF. In other words, when the power supply is operating normally, the cutoff signal & 1 is a high level, so the signal generating circuit 1 并不 does not pick up the switching signal Vpwm. In addition, the power supply is in the open circuit state or the short circuit state, and the feedback signal θ is pulled to the supply voltage Vcc (south the critical signal vL1J(T). Therefore, the feedback detection circuit 16 generates The south level of the pull-up signal Sp „. The turn-on detection circuit 3 〇 detects whether the power switch &

More than the pre-" time threshold, determine whether the power supply is open circuit or short circuit. When the on-time of the power switch & is greater than the time threshold, the level of the short-circuit signal & is the high level, indicating that the power supply is open. At this time, the transmission confirmation circuit 4G confirms that the power-related (four) conduction time continues to be longer than the time threshold. The confirmation circuit 4G will generate a high-level constellation number ^. Delay plus 9 selects the signal according to the high level & counts the second delay time (the delay circuit 19 counts according to the second pulse signal ^) and the reverse of the final-stage flip-flop 195 gives a low level The stop of the bit depends on the tester · 1G, (four) switch _ % into _. In this way, the power supply is protected by open circuit. On the contrary, t 嶋 嶋 、 、 、 、 、 、 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ At this time, it is true that the selection signal Sa of the low level is generated. The delay circuit 19 counts the first delay according to the selection of the low-order slogan Ssa

Between (the delay circuit 19 is based on the first pulse signal F. 咕 仃 juice number), in order to generate a low level of cutoff 唬 ^. The signal hybrid circuit 1G switches the signal VTM according to the low level ··κ 戬 矾唬 拴 拴 lock. As such, the power supply is short-circuit protected. 201230577 Please refer to Sections 6A and 6B for waveform diagrams of the power supply of the present invention. Please refer to Figure 2, 3, and 4'. As shown in Figure 6A, when the power supply is operating normally, the feedback signal vFB will be lower than the critical signal vLm ' and the level of the pull-up signal Sph will be low. . The delay circuit 19 will be reset by the low level pull-up signal Sph. Therefore, the delay circuit 19 does not count, but directly outputs the cutoff Sw of the south level to the subtraction generating circuit 10. The switching city VwM is not latched, and the driving signal VG is not latched, so the power supply remains in normal operation. As shown in Fig. 6A, when the drive signal VG starts to be enabled (power switch Q| is turned on), the level of the sawtooth signal L is slightly increased. The age of the test is forbidden, and the sawing rate is low. Thus, the surface signal ^ 卩 is related to the on-time of the power phase _. #齿齿信号v&w When the threshold rij is at the threshold signal VTM, the level of the periodic signal S_ changes from the high level to the low level, and the level of the short signal Sa changes from the low level to the high level. . When the level of the short circuit signal & turns to the high level, it means that the power switch Q, the on time is greater than the time stick. Then, the confirmation circuit 40 confirms that the on-time of the power switch Qi continues to be higher than the time threshold according to the short-circuit signal of the high level (ie, the period after the short-circuit signal & L turns to the high level)) The choice of the standard 峨Ssa. The selection signal s of the delay circuit 19 turning to the high level will change the output signal Spck, and the first pulse wave signal u is converted into the second pulse signal & and is counted according to the second pulse signal. In other words That is, the pro-circuit 19 selects the second pulse signal 8^' according to the short-circuit signal Sa. The delay circuit 19 counts the delay time h of the second delay (after the low-level cutoff signal Sw is generated to the signal generating circuit 1〇, The switching signal ^ is shackled (that is, the driving signal Veit is shackled) to perform open circuit protection. In addition, as shown in Fig. 6B, when the enabling time of the driving signal Vg is short (power switch Qi [S] 15 201230577 At this time, the on-time of the periodic signal is short), the level of the sawtooth signal VSA* will be lower than the threshold signal Vth; the level is the tij level, which means that the on-time of the switch is closed. According to the counting circuit shown in Figure 3 (including the positive and negative device and 3G7)), according to the cycle signal 5, the count-segment_ is changed from the standard level to the low level. The short circuit signal of the 4Q low level is determined. Sol output low level selection ΐ峨". When the return VpB is higher than the critical signal w, and the on-time of the power switch is less than the time gate, it indicates that the power supply is short-circuited. The delay circuit 19 will change the output signal ^ according to the low level selection signal, by the second pulse

The wave signal SaK is converted to the first pulse signal Fcu (the period of the first pulse signal is shorter than the period of the second pulse signal SCLK). The delay circuit 19 counts according to the first pulse signal FaKit. In other words, Delay 19 _ er minus (four) select H sharp 贱 妨 。 。 。 。 。 。 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟 延迟That is, the drive minus I is picked up and locked, so that the cycle of the first pulse is short, so the first delay time K is short, so that the test can be corrected and corrected quickly. The application circuit of the Weiji secret device and the load terminal is damaged. Figure 7 is a circuit diagram of a power supply of another embodiment of the present invention. As shown in the figure, the difference between this real example and the first real side is here. There is no miscellaneous circuit 4Q (as shown in Fig. 2) and the conduction detecting circuit 3 is directly connected to the delay circuit. The figure, the conduction ', the output signal _ road signal is transmitted to the delay circuit 19 to control the delay circuit 228 and the second switch 199 (as shown in FIG. 5). Therefore, the short circuit number of this embodiment is used as the selection signal & of the second figure to select the first pulse signal Fok or the first [S1 16 201230577 two pulse signal ScLK. When the level of the Susie signal VSA* is higher than the gate signal VtH (as shown in the figure below), the periodic signal Smm is at a low level and the short-circuit signal Sot is at a high level, indicating that the on-time of the power switch is greater than the time. threshold. The high-level short-circuit signal S〇L turns on the second switch 〖99 (refer to Figure 5)' to transmit the second pulse signal Soj (to the flip-flop 192) for open loop protection.

In addition, when the level of the sawtooth signal is lower than the threshold signal VTM, the periodic signal Sdutv is at a high level. The short circuit signal Sol is at a low level, indicating that the power switch Q has an on time less than the time gate. The low-level short-circuit signal Sou turns on the first switch 198 via the inverter 196 (shown in FIG. 5) to transmit the first pulse signal Fok to the flip-flop 192 for short-circuit protection. Therefore, the present invention has new chicks and progressive sisters who can be employed in the industry. The requirements for the patents of China's patent law are undoubtedly 爰 提出 提出 提出 提出 提出 提出 提出 提出 提出 提出 提出 提出 提出 提出 发明 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 However, the above description is only for the purpose of the present invention, and it is intended to limit the implementation of the invention, and the equivalent of the thief, structure, characteristics and spirit of the invention. It is included in the towel material of the present invention. [Simple description of the drawing] ^ Power supply with open circuit protection and short circuit protection. Fig. 1 is a circuit diagram of a conventional power supply with open circuit protection; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3 is a circuit diagram of a continuity detecting circuit of the present invention; FIG. 4 is a circuit diagram of a confirmation circuit of the present invention - an embodiment; 201230577 5 is a circuit diagram of a delay circuit of the present invention - an embodiment; * FIG. 6B is a waveform diagram of a power supply with open loop protection and short circuit protection of the present invention; and "a diagram of the present invention" The second embodiment has a circuit diagram of a power supply with open circuit protection and short circuit protection. ~. [Figure number comparison description]

10 signal generation circuit D〇 output rectifier 101 logic circuit Fclk first pulse signal 103 positive and negative device Ip primary side switching current 105 logic circuit Np primary side winding 12 oscillator 7s secondary winding 14 reset circuit PLS clock signal 144 Logic circuit Q. Power switch 146 Power limit comparator Rph Ranan resistor 148 PWM comparator Rs Current sense resistor 16 Feedback detection circuit ScLK Brother one pulse wave number 18 Delay circuit Sduty Cycle signal 19 Delay circuit SoFF Cutoff signal [ S] 18 201230577

192 forward and reverse Sol short circuit signal 194 forward and reverse device Spck output signal 195 forward and reverse Sph Ranan signal 196 inverter SsEL select signal 197 or gate Tl transformer 198 first switch Tdl second delay time 199 second switch Tds first Delay time 20 drive circuit Vcc supply voltage 30 turn-on detection circuit Vcs current signal 301 inverter Vfb feedback signal 302 current source Vg drive signal 303 transistor VlN input voltage 304 capacitor Vlimt critical signal 305 comparator Vlmt power limit signal 306 positive Counter Vo output voltage 307 Forward and reverse Vpwm Switch signal 40 Confirm circuit VsAW Mine tooth signal 401 Forward and reverse Vth Threshold signal [s] 19 201230577 402 Reversible device 50 Frequency divider Co Output capacitor CLK Basic pulse signal CLR Clear signal CNTR feedback control signal

Claims (1)

201230577 VII. Patent application scope: 1 · A power supply with open circuit protection and short circuit protection: - Transformer, the transformer receives - input voltage to generate - output voltage; a power _, the power _ coupling The device switches the transformer to adjust the output voltage; a signal generating circuit, the signal generating circuit generates a switching signal to control switching of the power switch; a conduction detecting circuit, and the remote conduction detecting circuit detects the power switch a turn-on time for generating a short-circuit signal, and a delay circuit for counting a first delay time or a second delay time according to a feedback signal of the power supply and the short circuit signal Generating a cutoff signal to the signal generating circuit to lock the switching signal; wherein the delay circuit determines to count the first delay time or the second delay time according to the short circuit signal. 2. The power supply device with circuit protection and short circuit protection as described in claim 1 further includes: a confirmation circuit, the confirmation circuit confirms the power switch according to a reference signal and the short circuit signal The on-time is continuously higher than a time threshold and generates a selection signal, wherein the delay circuit determines to count the first delay time or the second delay time according to the selection signal. 3. 3. As described in claim 2 The power supply has open circuit protection and short circuit protection, wherein the reference signal is related to the switching signal. [S] 21 201230577 4_The power supply device with open circuit protection and short circuit protection as described in claim 1, wherein the conduction detection circuit detects the conduction time of the power switch, and the conduction time is less than one a time threshold and the feedback signal is higher than a critical signal indicating that the power supply is shorted, and the delay circuit counts the first delay time according to the short circuit signal, the conduction time is greater than the time gate and the feedback signal is higher than the The threshold signal indicates that the power supply is open circuit, and the delay circuit breaks the sixty-one delay time according to the short circuit, and the first delay time is shorter than the second delay time. 5) The power supply device with open circuit protection and short circuit protection as described in claim 1, wherein the conduction detection circuit comprises: a recording signal generating circuit, wherein the silver tooth signal generating circuit is configured according to the power switch The on-time generates a sawtooth signal; a comparator, the comparator compares the sawtooth signal with a threshold signal to generate a periodic signal; and a counting circuit that counts according to a trigger signal and the periodic signal, and generates the short circuit Signal. 6. The power supply device for open circuit protection and short circuit protection according to claim 1, further comprising: an oscillator that generates a basic pulse signal; and a frequency divider. The frequency divider receives the basic pulse wave signal and divides the basic pulse wave signal to generate a first pulse wave signal and a second pulse wave signal; wherein the delay circuit selects the first pulse wave signal according to the short circuit signal Or the second pulse wave 22 201230577' to count the first delay time or the second delay time according to the first pulse signal or the second pulse signal. 7. The power supply device for open circuit protection and short circuit protection according to claim 1 of the patent application, further comprising: an oscillator, the oscillator generates a clock signal, and the signal generating circuit is based on the clock signal The switching signal is generated. 8. The power supply device with open circuit protection and short circuit protection according to claim 1, further comprising: a feedback detection circuit, wherein the feedback detection circuit is based on the feedback signal of the power supply A pull signal is generated, and the delay circuit counts the first delay time or the second delay time according to the pull-up signal and the short-circuit signal. 9_ The power supply with open loop protection and short circuit protection according to claim 8 , wherein the feedback detection circuit generates the pull-up signal according to the feedback signal and a threshold signal. 10_ The power supply device with open circuit protection and short circuit protection as described in claim 1 of the patent scope includes: - a reset circuit, the read reset circuit is based on one of the power supply, a power limit The signal and the feedback signal generate a clear signal to end the switching signal. [s] 23