TW201236340A - Synthetic ripple regulator with frequency control - Google Patents

Abstract

A synthetic ripple regulator including frequency control based on a reference clock. The regulator includes an error network, a ripple detector, a combiner, a ripple generator, a comparator network and a phase comparator. The error network provides an error signal indicative of relative error of the output voltage. The ripple detector provides a ramp control signal based on the input and output voltages and a pulse control signal. The combiner adjusts the ramp control signal based on a frequency compensation signal to provide an adjusted ramp control signal. The ripple generator develops a ripple control signal based on the adjusted ramp control signal. The comparator network develops the pulse control signal to control switching based on the error signal and the ripple control signal. The phase comparator compares the pulse control signal with the reference clock and provides the frequency compensation signal.

Description

201236340 VI. Description of invention: [Reciprocal reference of related application] This application claims the priority of US Provisional Application No. 61/411, 〇36, filed on November 8th, 2010. The US provisional application is for all Intention and purpose are hereby incorporated by reference in its entirety. BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a synthetic chopper regulator, and more particularly to a synthetic chopper regulator with frequency control. [Prior Art] A DC/DC switching regulator using synthetic chopping modulation achieves excellent performance in response to load transients. The synthetic chopping modulation system is described and depicted in various publications, including the United States. Patent No. 6,79i, 3g6, U.S. Patent No. 7,132,82 (), U.S. Patent No. 7,145,317, U.S. Patent No. 2, GG9/G14G711, each of which is hereby incorporated herein by reference. Ref: ° As a general matter, an auxiliary electrical I waveform has been developed, which effectively replicates the chopping current by rotating the inductor. The auxiliary voltage wave is broken to control the cut-off of a comparator (for example, a hysteresis comparator or the like) = as in the 'in the non-limiting embodiment, the second axis of the mutual conductance amplifier system The voltage of the inductor is output, and an electrical waveform representing the inductor voltage is supplied, wherein the capacitor voltage is the auxiliary switching: waveform. The artificial or synthetic chopping waveform controls the regulator's operation, reduces output ripple, simplifies compensation, and improves DC compliance. The operating frequency of the 201236340 synthetic chopper regulator is changed to 1 in response to load transients to achieve the desired performance. However, the steady operating frequency of the synthetic chopper regulator has become more difficult to control. It is desirable to have a fixed or known steady operating frequency to maximize performance and minimize noise (e.g., electromagnetic interference (EMI) and the like). The challenge is to synthesize the skew when there is an input voltage VIN, an output current (eg, load current), an output voltage νουτ, or an equivalent series resistance (esr) of the output capacitor, among other factors. The slope of the wave also changes, so the switching frequency changes, which produces a fixed hysteresis window size. The dedicated circuit is made to have a fixed frequency across the temperature, the input/output voltage, and the output filter. [Inventive content] The following is proposed so that the general knowledge of the technology is sufficient. And the invention as set forth in the context of a particular application and its needs is utilized. However, various modifications to the preferred embodiment will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the specific embodiments of the inventions and The disclosure describes a new architecture that allows the converter to operate at a fixed frequency or to synchronize to an external clock. A phase lock loop (PLL) is inserted into the regulator to control the slope of the resultant modulated ramp wave to facilitate control of the frequency. Therefore, by integrating a phase-locked loop into the 201236340 chopper regulator, the regulator is transported to an external clock while maintaining its superiority, making the composite chopper regulator suitable for use in a fixed The frequency or the application of the same general purpose of the load transient response quality. step

Q [Embodiment] FIG. 1 is a D Γ npf, g 取 L _ 交换 交换 p p ( ( ( ( ( ( ( ( ( ( ( ( ( ( p p p p p p p p p p p p p p p p p p p p p p p p A block diagram of an electronic device (10) of a power supply or similar power supply or the like. The electronic device 100 is shown to include an electric power; also ι〇ι, the battery 101 provides a battery voltage VBAT to - voltage selection (VS is an input of a circuit, the VSEL circuit 1 〇 5 has a slave rectifier ι 3 Receiving a further input of a DC voltage (VDC), the rectification H1〇3, receiving an ac or DC voltage from an external power source (eg, a parent current (AC) power source (not shown), and converting the received The voltage becomes the VDC voltage. If the battery 101 is rechargeable, the rectifier 103 can include a battery charger for charging the battery, or a separate battery charger (not shown). The VSEL circuit 1〇5 provides an input voltage VIN to an input of the voltage regulator 107. The voltage regulator 1〇7 has an input for receiving a reference clock signal RCLK and has an output, the output system An output voltage ν 〇υ τ is provided on the power bus 1 09 or the like to provide a supply voltage to a load that is shown as device circuit 111. The device circuit lu generally includes circuitry of the electronic device 100 as shown The device circuit can There is a processor 113 coupled to a memory 11 5 , and both the processor ii 3 and the memory 115 are coupled to the power bus 1 〇 9 for receiving the supply from the 201236340 damper 07 7 Voltage (eg, ν〇υτ). Other types of electronic devices that do not have a processor or memory are also contemplated. The βH electronic device 1〇〇 can be any type of electronic device that includes a mobile portable, or Handheld devices, for example, any type of personal digital assistant (PDA), personal computer (pq, portable computer, laptop, etc., subscription 4' personal media device, etc. In an alternate embodiment, The electronic device 100 is not powered by a battery, but is powered by a power source or other source of power. In general, the voltage regulator 1〇7 is configured for use in computers, industries, consumers, etc. Application and/or power conditioner for battery powered applications. The main function of the electronic device 100 is performed by the device circuit m in the illustrated configuration. In one embodiment, the battery 1〇1 Is an arbitrary appropriate type Rechargeable battery (which includes a car battery), although a non-rechargeable battery is also contemplated. In various embodiments t, the voltage of VIN is lower than ν 〇υ τ for the boost configuration. Vm is higher than νουτ' for voltage configuration or for various other configurations, such as single-ended primary inductance converter (SEPIC) or buck-boost conversion or the like, the range of V NN relative to VOUT can be Anywhere in the middle. Although other types of regulators are also contemplated, the regulator i〇7 is depicted herein as a buck-type synthetic chopper regulator. Figure 2 is an embodiment according to an embodiment. A schematic block diagram of a synthetic chopping regulator 107 with frequency control. The turn-in voltage VIN is provided to an input node 202. - the first electronic switch S1 has a current terminal switched between the node 2〇2 and a phase node 206, the phase node 2〇6 is issued

8 201236340 A phase signal LX is exhibited. A second electronic switch S2 i〇8 has a current terminal connected between the phase node 206 and a reference node, such as ground. An output inductor 210 is coupled between the phase node 2〇6 and an output voltage node 2丨2 for providing the output voltage VOUT. An output capacitor 214 is coupled between the output node 212 and ground. Each of the electronic switches 204 and 208 is driven in response to a control signal from a driver block 2 16 that is provided to a corresponding control terminal of the switching transistors 204 and 208. In one embodiment, electronic switches Q1 and Q2 are shown as a pair of metal oxide semiconductor field effect transistors (MOSFETs) as is known to those skilled in the art. Switch S1 is shown as a P-channel transistor such that its source is coupled to input node 2〇2 and its drain is lightly coupled to phase node 206, and switch s2 is one such that its source is coupled to ground and its The drain is coupled to the N-channel transistor of the phase node 2〇6. The gates of switches S1 and S2 receive gate drive control signals from the driver block 216. Other types of electronic switching devices can also be utilized that include FETs of the type 与 and the like, or other types of transistors, such as a bipolar junction transistor (BJ) or an insulated gate bicarrier. Transistors (IGBTs) and the like, and so on. The driver block 216 receives a pulse width modulation (P WM) control signal from a PWM comparator 21 8 . The non-inverting input of the P WM comparator 2 丨 8 is coupled to a node 236 ′ and its inverted input is coupled to a chopping node 244 . Node 236 receives the control signal selected by one of error amplifier 220 and the window network. The error amplifier 22 is coupled such that its inverted input is coupled to receive a V〇UT from the wheeling node 2丨2 or to receive a 201236340 feedback voltage VFB, which is one of VOUT sensing To the version. For example, although not shown, the VOUT can be provided to an output voltage sensing network, such as a resistive voltage divider or the like, which asserts VFB as a proportional voltage indicative of VOUT. The non-inverting input of the error amplifier 220 receives a reference voltage VREF having a voltage level indicative of which of VOUT or VFB is provided to one of the levels of the error amplifier 220. The output of the error amplifier 220 provides a compensation signal VCOMP that is provided to a central node 222 of the window network. The window network includes window resistors 228 and 234, window current sources 224 and 230, controlled single pole single throw (SPST) switches 238 and 242, and inverter 240. The current source 224 is coupled to provide a window current IW from a supply voltage VDD to a first window node 226, which develops a high window voltage VUP. The first window resistor 228 is coupled between the nodes 226 and 222, and the second window resistor 234 is coupled between the node 222 and a node 232. The node 232 develops a low window. Voltage VDOWN. The current source 230 is coupled to sink the window current IW from the node 232 to ground. The window resistors 228 and 234 each have a window resistance of approximately RW which forms a balanced configuration between VUP and VD0WN and the central node 222 receiving the VCOMP. In particular, the current IW flowing into each of the resistors RW develops a window voltage VW, thus VUP = VCOMP + VW, and VDOWN = VCOMP - VW. Switch 238 is coupled between VUP and node 236 (at the comparator)

10 201236340 218 is a non-inverting input), and switch 242 is coupled between vd〇wn and point 236. The signal at the output of the comparator 218 is provided to a control input of the switch 238 and the input of the inverter 24A. The output of the inverter 240 is connected to the control input of the switch 242. In this manner, when PWM is asserted high, the switch 238 is closed and switch 242 is open, so vup is provided to node 236 and is therefore provided to the non-inverting input of compare 3 218 . Similarly, when PWM is asserted low, the switch 238 is open and the switch 242 is closed, so instead VD 〇 WN is provided to node 236 and thus provided to the comparator 2 1 8 Inverted input.

The chopping node 2 coupled to the inverted input of the comparator 218 is a chopping node that develops a chopping voltage VR. A chopper capacitor 246 having a chopping capacitor CR is coupled between the chopping node 244 and ground. A chopper resistor 248 having a resistor RR is coupled between the chop node 244 and the common voltage node 250, and the common voltage node 25 receives a common voltage VCOMM. The chopping node 244 receives an adjusted ramp current ir from a combiner network 252. The combiner network 252 combines a ramp current IRAMP and a frequency compensation voltage FC〇Mp to develop the ramp wave. Current IR. As further described herein, the ramp current IR charges and discharges the chopper capacitor 246 (alternating between positive and negative current levels, as further described herein) to develop the chopping voltage VR, The chopping voltage VR has a sawtooth waveform. The common voltage vc 〇 MM is set at a target level for the midpoint of the action of the synthesized chopping voltage during steady state operation. 201236340 The phase node 106 develops the phase voltage LX, which is provided to a non-inverting input of a transconducting network 254 that receives at its inverted input. VOUT. The transconductance network 254 develops an IRAMP at its output that has a current level that is proportional to the difference between LX and VOUT. The gain GMR of the transconductance network 254 determines the ratio between the difference between LX and VOUT and the IRAMP. In a conventional synthetic ramp regulator, an IRAMP is provided as the ramp current to the chopping node 244 to charge/discharge the chopper capacitor 246. For the regulator 107, the IRAMP is instead adjusted by the combiner network 2 5 2 by F C Ο Μ P to achieve frequency control as further described herein. In operation, the error amplifier 220 develops a VCOMP that is at a level indicative of the error level of VOUT. The window network develops VUP and VDOWN to follow VCOMP, and as previously described, VUP and VDOWN separate the window voltage VW from VCOMP, respectively. Assuming PWM is high, the switch 238 couples the VUP to the comparator 1 1 8 and the driver turns on the upper switch S 1 204 and turns off the lower switch S2 208. The phase node 206 is coupled to the input node 202, which drives the voltage level of LX to VIN. In a buck converter, the VIN is greater than VOUT, which induces current to flow through the output inductor 2 1 0 to charge the output capacitor 214, which tends to increase the voltage level of VOUT. Since LX is driven up to VIN, the transconductance network 254 generates IRAMP as a positive current proportional to the difference between VIN and VOUT. Ignoring FCOMP and the combiner network 252, the ramp current IR is charging

12 201236340 Chopper capacitor 246 causes the chopping voltage VR to ramp up towards νυρ. When the VR reaches VUP or exceeds VUP, the comparator 2i 8 switches and pulls the PWM low. The switch 238 is open and the switch 242 is closed so that VDOWN is coupled to the comparator 218 in accordance with the function of hysteresis. Moreover, the driver block 216 turns off the switch S1 and turns the switch S2 on, so that the phase node 2〇6 is effectively coupled to ground, which pulls the LX low to ground. This tends to slow down and/or reverse the current through the output inductor 2 10 and tends to lower the voltage level of ν 〇υ τ. Since LX is driven low, the transconductance network 254 generates jramp as a negative current proportional to the difference between VIN and VOUT, and thus the ramp current IR discharges the chopper capacitor 246. Therefore, the chopping voltage VR drops toward the VDOWN ramp. When VR arrives or falls below VDO WN, the comparator 2 18 switches and pulls the PWM back high. The switch 238 is closed and the switch 242 is open, so that the VUP is again coupled to the comparator 1丨8 in accordance with the function of the hysteresis. Furthermore, the driver block 216 turns off the switch S2 and turns the switch S1 back to conduction, so that the phase node 2〇6 is effectively pulled back to VIN. For a continuous PWM period' it repeats the action in this manner. A voltage LX-VOUT across the output inductor 210 is applied to the input of the transconductance network 254. When LX switches between VIN and ground, a chopping current is developed through the output inductor 210. The transconductance network 254 develops an IRAMp that is provided as the ramp current (ignoring the combiner network 252) to charge and discharge the chopper capacitor 246 to develop the chopping voltage vr. Thus, VR is an auxiliary voltage wave 13 201236340 shape that effectively replicates the chopping current waveform through the output inductor 21 and is used to control the switching of the comparator 2 18 . The window network provides the hysteresis function of the center at the compensation voltage VCOMP. In response to a transient increase in load, VOUT tends to decrease, which causes VCOMP to increase, and temporarily increases the switching frequency to quickly maintain regulation in response to the increased transient of the load. Similarly, in response to a reduced load transient, νουτ tends to increase, which causes vc〇Mp to decrease, thereby temporarily reducing the switching frequency to quickly maintain the regulation in response to the reduced transient of the load. As previously stated, the steady state operating frequency of a synthetic chopper regulator (including the regulator 1〇7) has been relatively difficult to control. It is desirable to have a fixed or known steady state operating frequency to maximize performance and minimize noise such as EMI and the like. A change in VIN, ν 〇υ τ, steady state load (eg, output current) or ESR of the output capacitor 214 will change the slope of the composite ramp voltage VR within a fixed hysteresis window size, which may change The steady state switching frequency. A phase comparator 300 compares the reference clocks RCLK and pwM and develops the frequency compensation signal FC〇Mp, which is provided to the combiner network 25. The rclk can be externally provided or generated by a clock generator or the like (not shown). The designer can choose the frequency of rclk based on the voltage level or voltage range of VIN and ν〇υτ, the output capacitor & ESR, and other circuit variables. The combiner network 252 combines FC〇Mp with IRAMp to provide an adjusted ramp current IR that is an IRAMP and FC0MP function. FCOMP can be provided internally or externally. As described here

14 201236340

The slope of the synthesized chopping voltage VR is 蕤A ^ The fine tuning is controlled by adjusting the IR to maintain the steady state switching frequency at the desired level. 3 is a schematic block diagram of a phase comparator 3A that can be utilized to develop the frequency compensation signal f. The FC0M^RCLK is applied to a D-type flip-flop (DFF) 3〇1, according to an embodiment. The clock turns into the Qing 3〇1 <the system makes its D input is pulled high. The _3()1" output provides a signal UP, which is provided to a node 3〇3. The pwM signal is supplied to the clock input of another DFF3G5, and the DFF3Q5 is such that its D input is pulled high. To the side, the Q output of the DFF 305 provides a signal d〇wn to a node 307. The 2 inputs and gates 3〇 are such that their individual inputs are coupled to points 303 and 307 for logically combining the Up and d〇wn signals. The output of the AND gate 309 is coupled to the clear input of both DFFs 3〇1 and 3〇5. The node 303 is coupled to provide the up signal to a control input of a spST switch 3Π. The node 3〇7 is coupled to provide the d〇wn signal to a control input of another SPST switch 3 1 3. The current source 3丨5 is coupled to obtain current from VDD and is provided to node 3 17, and The switching terminal of the switch 3 is coupled between the node 317 and a node 319. The switching terminal of the switch 313 is coupled between the node 319 and a node, and the other current source 323 is coupled. The current is drawn to the ground from the node 32. The current source 3 1 5 is supplied with a current if from VDD and supplied to the node 3丨7, and the electricity The source 323 absorbs the current IF from the node 321 to ground. When the corresponding control signals UP and DOWN are low, respectively, each of the switches 3丄i and 3 13 is open, and when the corresponding control signal is up And DOWN are respectively high, then it is closed. A resistor-capacitor (Rc) 201236340 ”'s-path includes a resistor R j and a capacitor C coupled in series between node 3 1 9 and ground. 1. Another electric current benefit C2 coupled between the node 3丨9 and the ground. The node 319 develops the fc〇mp signal. The RC network including the resistor R1 and the capacitors C1 and C2 all form a frequency compensation network to filter the FCOMP. The PWM signal establishing the actual switching frequency of the regulator ι7 is compared with the RCLK signal by the DFFs 301 and 305, which is set to the desired switching frequency of one of the regulators 107. If the rising edge of RClk is earlier than the next rising edge of PWM, this indicates that the switching frequency of the regulator is slower than the target frequency established by RCLK, so the up signal is latched high and switch 3U is closed. And the switch 313 is kept open. The current source 315 provides the IF current to charge the frequency compensation network (7), Cl, C2) to increase the frequency compensation voltage fcomp. Eventually, the PWM signal becomes high W, which causes the DC) wn signal to be flash locked high to close the switch 313. When both switches 311 and 313 are closed, the current IF provided by the current source 315 is redirected by the current source 323 = leaving the frequency compensation network. Furthermore, the gate 3G9 becomes high and the two chats 3〇1 and 305' are generated and the UP and coffee signals are pulled back: Therefore, the time delay between the rising edges of RCLK and PWM determines how long the IF current is supplied to the frequency compensation network to increase the Fc 〇 Mp time. If the rising edge of the PWM appears instead of the rising edge of RCLK, the switching frequency of the regulator is programmed to be higher than the target, so the DOWN signal is triggered high, and the switch below JL 16 201236340 313 is turned on, and the upper switch 311 is maintained as an open circuit. In this example, the current source 323 absorbs the IF current to discharge the frequency compensation network (8), Cl, C2) to lower the frequency compensation voltage fc〇Mj^ eventually, the rclk signal becomes high' The UP signal is flash locked high to close the switch 3U. When the two switches 311 and 313 are closed, the current IF supplied by the power source 3! 5 is supplied to the current source 323, and the gate 309 becomes high and the two DFFs are cleared. 1 and, therefore, the 哆UP and DOWN signals are pulled back low. Therefore, the time delay between the rising edges of ρψΜ and rclk determines how long the IF current is pulled away from the frequency compensation network to reduce FCOMp. The reference clock RCLK is provided externally or internally. During the steady state condition, the 'FCOMP system remains stable, and the switching frequency determined by the PWM in the regulator ι7 is the frequency of the mrclk, which is substantially the same as the voltage level of the VIN& ν〇υτ. And the output capacitance: a change in the value of the ESR of 2 ,, during which the switching frequency of the regulator 107 is appropriately changed to respond quickly to maintain the desired adjustment level. After the transient condition, the (four) frequency is again controlled to be substantially equal to the frequency of RCLK. 9 is a simplified schematic block diagram of a more detailed configuration of one of the transconducting network 254 and the combiner network 252. The transconductance network 254 includes two transconductance amplifiers 903 and 915 and a sample and hold (SH) network 9 (H. The transconductance amplifiers 903 & 915 have a mutual conductance (10), respectively. The LX is provided to an input of the Sh network 901 which samples Lx when the PWM is high and provides a sample and hold 17 201236340 round VIN'. As previously stated, when PWM is High, LX becomes approximately vm high (after switching is stable), and thus, has approximately the same voltage level as the full. Although VIN can be directly utilized in other embodiments, the SH network 901 A method of indirect sampling is provided. VIN is supplied to the non-inverting phase of the transimpedance amplifier (1). The input j-transconductance amplifier 9G3 is connected such that its inverted input is coupled to GND. The transconductance amplifier 9G3 develops at its output - a current having IRAMP1-GM·VIN or a current proportional to VIN. νουτ is supplied to the non-inverting (1) input of the transconductance amplifier 915, The transconductance amplifier 915 is such that its inverted input is coupled to qnd In this manner, the transconductance amplifier 915 develops a current having IRAMP2 = GM.VOUT or a current proportional to ν 〇υ at its output. The sigma combiner network 252 contains two Combiners 9〇5(c〇MBINERl) and 917(COMBINER2), a pair of P-type MOS transistors 9〇7 and 9〇9, and a switch 911. IRAMP1 is provided to one of the first combiner 9〇5 Input, the first combiner 905 receives FC〇Mp at another input, and develops a first adjusted ramp current JR 1 at its output. The p-type MOS transistors 907 and 909 are coupled. Connected to a current mirror to mirror the current IR1 through the switch 91 1 to the chopping node 244. The sources of the transistors 9〇7 and 909 are coupled to VDD, and the gates of the transistors are The drain of transistor 907 is coupled together at the output of the combiner 9〇5 to draw the output current IR1. IRAMP2 is provided to an input of the second combiner 917, the second combiner 917 Receives 18 201236340 FCOMP at another input and develops a second adjusted ramp current IR2 at its output The IR2 system is provided directly to draw current from node 244. The P WM system is provided to the control input of switch 9 1 1 which is open when PWM is low and is when PWM is high In operation, the transconductance amplifier 903 develops a ramp current IRAMP 1 proportional to VIN, which is adjusted by the FCOMP via the combiner 905 and is provided as the adjustment. After the ramp current IR1. When PWM is high, IR1 is mirrored to provide a current proportional to VIN to the chopping node 244. The transconductance amplifier 9 15 develops a ramp current IRAMP2 proportional to VOUT, which is adjusted by FCOMP via the combiner 917 and is supplied as the adjusted ramp current IR2. In this manner, when P WM is high, the chopper capacitor 246 is continuously discharged by IR2 and is charged by IR1-IR2. 4 is a schematic diagram of an exemplary embodiment of a combiner 400 that can be utilized to implement either or both of combiners 905 and 917, in accordance with an exemplary embodiment. The FCOMP is provided to a non-inverting input of an operational amplifier 401 that has its output coupled to the gates of two N-type M〇S transistors 403 and 405. The source of transistor 403 is coupled to the inverting input of amplifier 40 1 and to one of resistors 409 having a resistor R. The source of the transistor 403 is coupled to one of the other ends of the resistor 4 11 which also has a resistance R. The other ends of the resistors 409 and 41 are coupled to ground. A P-type MOS transistor 407 is diode-coupled such that its source is coupled to the supply voltage VDD and its gate and drain-coupled 19 201236340 is connected to the drain of the transistor 403. The drain of transistor 405 is coupled to a node 4 12 . The amplifier 401, the transistors 403, 405 and 407 and the resistors 409 and 411 are all formed as a buffer or a voltage to current converter circuit for converting the FCOMP voltage into a corresponding current IFCOMP. The amplifier 401 operates to control the transistor 4〇3 to maintain its inverted input voltage at the source of the transistor 403 at the same voltage level as fc〇MP. In this manner, a current IFCOMP = FCOMP/R is developed through the resistor 409. The transistor 4〇5 may be substantially matched to the transistor 4〇3. Thus, the current IFCOMP flows from the node 412 through the transistor 405 and the resistor 41. The resistors 409 and 4 1 1 are configured. Alternatively, it is selected to determine a gain between the voltage FCOMP and the current IFCOMP. Although the buffer converter circuit is shown as part of the combiner 4, this is only a design preference. The buffer converter circuit is either detachable or includes a portion of the output of the phase comparator 3A to directly supply the IFC 〇 Mp current to the combiner 4 〇〇. A pair of P-type MOS transistors 413 and 415 are connected as a current mirror' to mirror the current IFCOMP through node 4 12 to one of the inputs 417 of the current combiner network 419. The sources of transistors 413 and 415 are coupled to VDD, and the gates of the transistors and the sum of the transistors 413 are coupled together at node 4 12. In an embodiment, the current combiner network 4丨9 can be implemented as a Gilbert structure (Gnbert “丨丨” or the like. The current combiner network 4丨9 includes a dual carrier junction The crystals (BJT) 42l, 42 5, 427 and 431 and a 20 201236340 current source 429 which develops the reference current IREF. The collectors of the transistors 421 and 427 are coupled to VDD, and the base thereof is at the node receiving the IFCOMP. 4 1 is coupled together. The emitter of transistor 42 1 is coupled to another input node 423, which is further coupled to the base of transistor 425. The collector of transistor 425 The base of the transistor 427 is coupled to an input of the current source 429 and coupled to the base of the transistor 43 1 . The current source is coupled to the node 4 1 7 . The output of the 429 is coupled to the ground. The emitter of the transistor 43 1 is coupled to the ground, and its collector is coupled to the chopping node 244 and develops an adjusted ramp current IRX. Any of IR1 or IR2. IREF is a fixed current level that is configured to select the current combiner The gain of the path 419. A pair of N-type MOS transistors 433 and 435 are coupled as a current mirror to mirror an input current IRAMPX to a node 423 at an input of the current combiner network 419] RAMPX representative Any one of IRAMP1 or IRAMP2. The sources of transistors 433 and 435 are coupled to ground, and the gates of the transistors and the drain of transistor 433 are coupled at the input node of the receiving IRAMPX. The current combiner network 4 1 9 operates to multiply the current IFCOMP by the current IRAMPX divided by the reference current IREF to develop IRX, or IRX = IFCOMP · IRAMPX/IREF. Since IFCOMP = FC0MP/R Therefore, the output ramp current IRX is determined according to the following equation (1): IRX =

FCOMP · IRAMPX R.IREF (Ο where R and IREF are selected to determine the gain of the combiner 400. 21 201236340 This current IR (combination of IR1 and IR2) is based on the voltage between LX and VOUT for the continuous period of the PWM. The difference becomes positive and negative to charge/discharge the chopper capacitor 246, and thus the auxiliary chopping voltage VR is developed. The phase comparator 300 compares the phases of RCLK and PWM to develop FCOMP, the FCOMP The IRAMP1 and IRAMP2 are multiplied to adjust the steady state operating frequency of the regulator 107. Figure 5 is a timing diagram depicting a series of RCLK, PWM, FCOMP, VUP, VR, VDOWN, and VOUT versus time, in accordance with an embodiment. RCLK and PWM are drawn on the upper timing diagram. Together, FCOMP is drawn on the second timing diagram. VUP, VR and VDOWN are drawn together on the third timing diagram, and VOUT is drawn on In the last figure, the timing diagrams generally depict how the regulator 107 responds to the frequency change of RCLK ^ RCLK starts from a lower frequency and then jumps to a higher frequency "after RCLK increases, PWM The frequency is behind, and the FCO The MP system increases in the continuous cycle of PWM in response to the increase of RCLK. The slope of VR increases as FCOMP increases. This increases the frequency of PWM. Both VUP and VDOWN switch up and down with VR. The difference between VUP and VDOWN remains fixed because the window network maintains the overall hysteresis window voltage constant. When the frequency of the PWM becomes substantially equal to the frequency of RCLK, FCOMP eventually settles in A higher voltage level. Figure 6 is a summary timing diagram of a controller 600 that can be utilized to control a multi-phase synthetic chopping voltage 5-cycle 8 with frequency control implemented in accordance with the present invention. 〇〇 (Fig. 8). Although only two phases are depicted, the description below from 22 201236340 will readily recognize that the architecture and functionality of the present invention can be easily extended to additional phases as needed. For the purpose of the complexity of the equation and its accompanying description, a two-phase implementation has been shown as an example of a multi-phase with reduced complexity. The controller 600 includes a top and bottom The main hysteresis comparators formed by the threshold comparators 010 and 620, the outputs of the comparators 61 and 620 are respectively coupled to a reset and set input of a set/reset flip-flop 63〇. The Q output of the 630 provides a main clock signal MCLK 'the main clock signal MCLK is switched at the actual operating frequency of the controller 600. A first, inverted (one) input 6 of the comparator 6 10 Coupling to receive an upper threshold voltage VUPPER, and a first, non-inverting (+) input 621 of the comparator 62 is coupled to receive a lower threshold voltage VLOWER, the lower threshold voltage VL〇WER It is specified to be approximately Δ v/2 lower than the upper threshold voltage VUPPER. Although not shown, an error amplifier is similar to the error amplifier 22 of the regulator 107 to develop a compensation or error signal or the like, which adjusts VUPPER and VL〇WER in a manner similar to Vup and VDOWN, where The voltage window difference between vuppER and VLOWER is maintained at Δ v/2. The second, non-inverting input 6丨2 of the comparator < 510 and the second, inverted (-) input 622 of the comparator 62 are coupled to a node 699, which is coupled to a node 699 An output coupled to a combiner network 691 is also coupled to a chopper capacitor 045, which is referenced to ground. The combiner network 691 is configured in a manner similar to the combiner network 252, with a single input for receiving a bidirectional IRAMp current. Section 23 201236340 Point 6" is developed - chopping voltage VR. The wheeling system of the combiner network 691 is coupled to a common terminal of the open source 64 〇? (4) The controlled switch is controlled by the inverted Q or $ output of the flip-flop 630. The phase comparator 300 is incorporated, which receives the external reference clock signal RCLK and The primary clock signal MCLK provides an input of the frequency compensation voltage FCOMP to the combiner network 691. Switch 640 ❾ - the first input? The 642 system is coupled to the output of a transconductance amplifier (4), and a second input terminal (4) of the switch 64A is coupled to the output of a transconductance amplifier 660. The transimpedance amplifier 65 is configured such that the non-inverted (+) input 65丨 is coupled to receive the input voltage of the controller, and one of the second, inverted (one) inputs (four) is connected to: The output voltage of the controller 600 is ν 〇υ τ. The transimpedance amplifier 65 produces - proportional to the difference between its inputs, that is, the output current proportional to vin v〇ut. The transconductance amplifier 66 is configured such that a first, non-inverting (1) input 661 is coupled to ground and one of the second inputs (6) is coupled to receive the output voltage VOUT. The transconductance amplifier 66 produces a proportional difference to the input current, i.e., the output current proportional to 〇 (ground voltage) _ν 〇υ τ. The flip-flop (4) develops the MCLK signal # Q-round is coupled to an input of the -sequential logic .... The sequential logic (4) that can be implemented as a counter has N outputs corresponding to the number of phases produced. In the example of the two phases, the sequential logic circuit 67 has a first input coupled to the set input of the set-and-reset flip-flop 680: 67丨 and - coupled to - set/reset positive The second input of the setting input of the counter 69〇 201236340 is 672. For this purpose, the sequential logic 67 can be implemented as a flip-flop for applications of two phases, or in applications where more than two phases are implemented. The reset input of the flip-flop 68 is connected to the output of a comparator 601, and the flip-flop of the flip-flop 613 of the flip-flop (4). The 601 & 61 3 series have (in) inputs (five) and 614 respectively consumed to receive the reverse of the upper critical power VUPPER. The non-inverting (+) input 603 of the comparator 6〇1 is connected to receive-cross-capacitance H 6〇5 to develop:: phase i chopping” voltage waveform, the “phase chopping” voltage f chlorine Generated by the current supplied to the capacitor 005 by the phase 1 transconductance amplifier 607. The non-inverting (+) wheel 615 of the comparator 613 is connected to receive the "phase 2 chopping" electric dust developed by the cross-capacitor 606. The "phase 2 chopping" voltage is by one phase. 2 Transconductance amplifier _ generated by the current supplied to capacitor 006. Phase 1 transconductance amplifier 607 is such that the -, non-inverting (1) input 616 is coupled to receive the phase i voltage vpHAsEi and to couple a second, inverted (one) input 617 to receive the output voltage ν 〇υ τ . The phase 1 voltage VPHASE1 corresponds to the phase voltage LX of the node 2〇6 at the single-phase adjustment $1〇7 in addition to the -phase-phase output voltage, and according to the Q at the output flip-flop_ A first phase PWM1 waveform provided by the wheel is controllably gated. Therefore, the transconductance amplifier generates a "phase chopping" voltage proportional to vpHASE1_v〇UT. Similarly, the 'phase 2 transconductance amplifier 6〇8 system makes a first, non-inverting (1) input 6U auxiliary to receive a phase 2 electric house νρΗ·2, and 25 201236340 to make a second, inverted (one) input 6丨9 is coupled to receive the turn-off voltage VOUT. The phase 2 voltage VPHASE2 corresponds to a phase voltage LX at a node of the single phase adjuster 1〇7 in addition to a second phase turn-off voltage, and is based on the Q-round output at the output flip-flop 69〇 A second phase PWM2 waveform is provided and controllably gated. Therefore, the transconductance amplifier 608 produces a "+ Μ phase 2 chopping" voltage proportional to vphasE2-VOUT. In a conventional multiphase composite chopper voltage regulator, the node is directly coupled to 699 without the combiner network 691. The controller 600 is plugged into the combiner network 691, which operates in a substantially similar manner to the prior description. The transimpedance amplifiers 65A and 66B and the switch 64" operate in a substantially similar manner to the transconductance network 254. When MCLK is high, switch 64A selects node 642 at the output of the transconductance amplifier 650, which provides a current proportional to νΐΝ_ν〇υτ, similar to LX-VOUT when LX is pulled to VIN. . When MCLK is degraded, switch 640 selects node 643 at the output of the transconductance amplifier 66A, which absorbs a current proportional to 〇-ν〇υτ, similar to when LX is pulled low to ground. LX_V0U1^ Therefore, a current IRAMp is provided at the input of the combiner network 69A via node 64 1 . The phase comparator 300 operates in a substantially similar manner except that it compares the main clocks MCLK and RCLK, rather than comparing PWM and RCLK, and provides FC〇Mp in a substantially similar manner as further herein. As described, MCLK controls the operation of each of the plurality of pwM signals pwM1 and PWM2 of the controller 6〇〇. The combiner network 691 combines IRAMP and FCOMP (and lREF) as previously described 26 201236340 and produces the adjusted ramp current IR at its output, which is provided for charging and discharging. The chopper capacitor 645 develops the chopping voltage vR. Figure 7 is a simplified timing diagram depicting the operation of the controller 6 with frequency control during steady state operation. The chopping voltage VR is drawn in an overlapping manner with VUPPER and VLOWER, and "phase chopping" and "phase 2 chopping" are drawn in an overlapping manner with VUPPER, and the MCLK, pWM1, and pWM2 signals are plotted with respect to time. VUPPER and VLOWER are shown at fixed levels, where it is understood that they all vary with the compensation or error voltage as previously described. The steady state action is substantially similar to the conventional configuration in which the phase comparator 3A and the action of the combiner network 69j are temporarily ignored. At time t 〇, the comparator 62 〇 detects that it is lower than VLOWER, which sets the flip flop 630 to change the MCLK pull M ^ MCLK to 咼 'the switch 640 selects the output of the transconductance amplifier 650 The capacitor 645 is charged by injecting a positive current, and thus the VR starts to ramp up. Furthermore, the sequence logic 670 sets the flip-flop 680 to pull PWM1 high' to draw the corresponding phase node (not shown) to V[N' which pulls VPHASE1 high. The transconductance amplifier 607 injects a positive current to charge the capacitor 605, so that "phase 1 chopping" begins to ramp up the ramp.

At a subsequent time t1, the VR is either as detected by the comparator 610 or exceeds VUPPER, which resets the flip-flop 630 to pull McLK back low. The switch 640 is switched to select the output of the transconductance amplifier 660, which draws current from the chopper capacitor 645, and thus the VR 27 201236340 ramp down. "Phase 1 Chopping" still increases the ramp as it has not yet reached VIJPPER. At a subsequent time t2, "Phase 1 Wave" arrives or exceeds VUPPER, so the comparator 601 resets the flip 680 to pull PWM1 back low. VR, "Phase 1 Chop" and "Phase 2 Chop" are ramped down after time t2 until the next cycle. At a subsequent time t3, VR is again detected by the comparator 620 below VLOWER, which sets the flip-flop 63〇, which pulls MCLK again. When MCLK goes high, the switch 640 selects the output of the transconductance amplifier 650 to inject a positive current to charge the capacitor 645, and thus vr begins to ramp up. In this example, the sequence logic 67 sets the flip-flop 690 to pull PWM2 high, which pulls the corresponding phase node (not shown) to VIN' which pulls VPHASE2 high. The transconductance amplifier 608 injects a positive current to charge the capacitor 6〇6, so that the "phase 2 chopping" is reversed and the ramp wave starts to increase upward. It should be noted that the "phase 1 涟 wave" continues to decrease the ramp down 'because the sequential logic 670 now selects phase 2 ' instead of phase 1. At the subsequent time t4' VR, the comparator 6 1 0 detects that it has reached again or exceeds VUPPER, which resets the flip-flop 63 to pull MCLK back low. The switch 640 is switched to select the output of the transconductance amplifier 660, which draws current from the chopper capacitor 645, and thus the VR ramps down again. "Phase 2 Chopping" is still increasing the ramp as it has not yet reached VUPPER. At a subsequent time t5, "Phase 2 Chop" arrives or exceeds VUPPER, so the comparator 613 resets the positive 690 to pull PWM2 back low. VR, "Phase! Chop" and "Phase 2 Chop" are ramped down again after time t5 until the next cycle. The next cycle begins at a subsequent time t6, in which the 'MCLK and PWM1 lines become high again. The actions are repeated in this manner, wherein the sequential logic selects the plurality of phases one at a time in a manner of 5%. The VUPPER and VLOWER voltages operate in a manner similar to the window voltages vup and vd〇wn, and although not explicitly shown, these voltages are up and down in a similar manner in response to a change in error or compensation signal Change. In this manner, in response to the output transient, the frequency of MCLK, and thus the frequency of both PWM 1 and PWM 2, changes accordingly to cancel the transient and maintain regulation. Furthermore, the frequencies of MCLK, pWM, and P WM2 will otherwise be responsive to VIN, ν 〇υ τ, steady state load current, and ESR of the output capacitor, among other factors. The mysterious phase comparator 3 00 and the combiner network 69 operate in a manner similar to that previously described to maintain the steady state frequency of MCLK substantially equal to the frequency of HCLK. When, for whatever reason, the frequency of mclk is different from RCLK, for example, when νΐΝ, _τ, steady-state load, or the ESR of the wheel-out capacitor, the shark is changed on the toast, The phase comparator 300 adjusts FCOMP, and the ^ 玄 人 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / During the steady-state condition determined by rCLK, the frequencies of PWM1 and PWM2 below the frequency of MCLK (for example, one and a half) are adjusted accordingly to stabilize at a preset target frequency. Figure 8 is a simplified block diagram of a multi-phase composite chopper voltage regulator 800 implemented with control 29 201236340, 600, in accordance with an exemplary embodiment having "N" phases. The multiphase regulator 800 can be utilized as the regulator 107 shown in FIG. The controller 600 receives RCLK, VIN, and VOUT (or VFB) and N phase voltages VPHASE1_VPHASEN, and provides N PWM signals PWM1, PWM2, . . . , PWMN to N channels of the regulator 800 constituting the multiphase. Individual n gate drivers GDI, GD2, ..., GDN. The number N is a positive integer greater than i, which contains N = 2 for the example of the two phases. For the first channel, the PWM1 signal is provided to the first gate driver GD1, which controls the turn-on and turn-off of a pair of electronic power switching devices or switches ^^ and Q12. In particular, the gate driver Gm generates an upper gate switching signal UG1, and the upper gate switching signal UG1 is supplied to a control terminal (eg, a gate) of the upper (or high side) switch q丨丨, and The gate driver GD1 generates a lower gate switching signal LG1 that is supplied to a control terminal of the lower (or low side) switch Qi2. In the particular configuration shown, 'open Q" and Q12 are depicted as N-channel MOS field effect transistors (m〇sfet) such that their immersed and source current paths are coupled in series-to-pair Between the input power supply terminals, in the configuration shown, the input power supply terminals are developed - reference to the grounding (GND) wheel-in voltage VIN1. Other types of electronically switched shocks have also been considered. The pole of the switch Ql2 is developed to develop the phase node VPHASE1_ of the voltage vpHASE1 to the source of the open source, and the phase node νΡΗΑ_ is lightly connected to one end of the output inductor. The other flaw of the inductor L1 is coupled to a common wheeling node 8 that develops an output signal ν〇υτ 30 201236340 (the remaining channel 2 of the regulator 800 of the H-phase phase The -N is configured in substantially the same manner as the first channel. The PWM2 (or PWMN) signal is provided to the gate driver GD2 (or GDN), which provides a signal υ 〇2 and LG2 (or UGN and LGN) drive the switches q21 and q22 (or qni and QN2) between the input voltage VIN and ground at the phase node VPHASE2 (or VPHASEN). The phase node vphASE2 (or VPHASEN) is coupled to the output node 〇1 that develops ν〇υτ through the output inductor L2 (or LN). The output node 801 is coupled to an output capacitor that is referenced to ground. 803. A load (eg, device circuit m of the electronic device) can be coupled to the output node 801 and ground to receive VOUT. The VIN and VOUT signals are fed back to the controller 600. The multiphase Multiple phases or .channels of regulator 800 are coupled in parallel to regulate VOUT. For the multiphase regulator For 800, each channel contains a different phase node and an output inductor. Each phase of the phase node VPHASE1-VPHASEN (developing the phase voltage VPHASE1 - VPHASEN of each channel) exhibits a large and rapid transition. Effectively switching between VIN and ground or 〇v, the output node 801 that develops the current VOUT signal remains relatively stable. Therefore, each inductor L1-LN develops a fairly large triangle during operation. Wave current signal. As described earlier, the corresponding chopping voltage "phase 1 chopping", "phase 2 chopping", etc. are developed according to the chopping current of the wheeled inductor for controlling each Phase switching. As described herein, a frequency-controlled synthetic chopper regulator 31 201236340 brings a kind of synchronization operation frequency and external application when the regulator is suitable for general purpose. 'Therefore, the phase-locked loop control system is referenced to only the main regulator control loop to lock the switching frequency to a one-shot clock signal. A feedback loop responds to the clock and cut, The difference is to adjust the slope of the resultant current seam wave. This phase comparison can be implemented in any alternative way known to those of ordinary skill in the art. Since the hysteresis window size is fixed, the description herein is fixed. The architecture can be applied to applications where the input voltage is drastically varied. A synthetic chopper regulator is disclosed herein that converts an input voltage into an adjusted output voltage and includes a reference clock based on frequency control. The regulator includes an error network, a slit wave detector, a combination %, a chopper generator, a comparator network, and a phase comparator. The error network provides an error signal indicative of the relative error of the turn-off voltage. The chopper detector provides a ramp control signal based on the input and output voltages and a pulse control signal. The combiner adjusts the ramp control signal based on a frequency compensation signal to provide an adjusted ramp control signal. The chopper generator develops a chopping control signal based on the adjusted ramp control signal. The comparator network develops the pulse control signal to control switching based on the error signal and the dich control signal. The phase comparator compares the pulse wave control signal with the reference clock and provides a frequency compensation signal indicative of the comparison. In one embodiment, the phase comparator compares the reference clock with the actual operating frequency indicated by the pulse control signal and is used to adjust the ramp control signal. The frequency of the pulse control signal can follow the circuit shape

32 201236340 Condition or variable, for example, 'wheeling voltage, output voltage, output capacitance, etc. and culture in a synthetic chopper regulator, the frequency of the pulse control signal can be varied to allow a fast response to the output load Transient. The frequency compensation provided by this phase than plagiarism compensates for the change in operating frequency, and thus the steady-state operating frequency is based on the reference clock and is therefore stable. The synthetic chopper regulator can be implemented as a multi-phase regulator. The integrated chopper regulator can be implemented on an electronic device. For example, the electronic device can include a processor and memory commonly found in many types of computer devices. According to the embodiment, the method of controlling the steady-state switching frequency includes determining the error of the output voltage and providing a compensation signal indicating the error, using The compensation signal develops a window signal having an upper limit and a lower limit, and when a pulse control is detected as a difference, a ramp signal is generated according to a difference between the input and output voltages, and when When the pulse wave control signal is emitted low, the ramp signal is generated according to the output voltage, and the pulse wave control is compared according to the pulse wave control

The signal and the reference clock provide __ 4 mesh I fork 1, frequency compensation value, according to the frequency compensation value to adjust the ramp signal and provide an adjusted ramp signal, and convert the adjusted ramp signal It becomes a chopping signal and compares the chopping number with the window signal and provides a pulse wave control difficulty number indicating the comparison. σ Although the invention has been described in considerable detail with reference to certain preferred versions thereof, other versions and variations are possible and contemplated. Those skilled in the art will recognize that the concepts and embodiments of the disclosure can be readily utilized to design or modify the basis of other structures, for the same purpose of the invention, without departing from the invention. Special 33 201236340 The spirit and vanity defined by the scope of interest. BRIEF DESCRIPTION OF THE DRAWINGS The benefits, features, and advantages of the present invention will become more apparent from the description and the accompanying drawings, wherein: FIG. A block diagram of an electronic device including a DC-DC switching voltage regulator implemented by frequency control (otherwise referred to as a converter or power supply or the like); FIG. 2 is a diagram of a diagram according to an embodiment A schematic block diagram of a frequency controlled synthetic chopper regulator; FIG. 3 is a schematic block diagram of a phase comparator that can be utilized to develop the frequency compensation signal fc mpmp according to an embodiment; A schematic diagram of an exemplary embodiment of a combiner of an example embodiment that can be utilized to implement either or both of the combiners of FIG. 9; FIG. 5 is a depiction of RCL/K, pWM, in accordance with an embodiment. , a timing diagram of fc〇mp, vup, VR, VD0WN, and ν〇υτ versus time series; FIG. 6 is a schematic time-and-time diagram of a controller that can be utilized to control frequency with implementation in accordance with the present invention Controlling multiple phases FIG. 7 is a simplified timing diagram depicting the operation of the controller with frequency control of FIG. 6 during steady state operation; FIG. 8 is an embodiment of a range of 4 columns according to a range of #Ν" A simplified block diagram of a multiphase synthetic chopper voltage regulator implemented using the controller of Figure 6 34 201236340; and Figure 9 is a more detailed configuration of the transconductance network and one of the combiner networks of Figure 2. Simplified outline block diagram. [Main component symbol description] 100 Electronic device 101 Battery 103 Rectifier 105 Voltage selection (VSEL) circuit 106 Phase node 107 Regulator 108 Electronic switch 109 Power bus 111 Device circuit 113 Processor 115 Memory 118 Comparator 202 Input Node 204 Switch or Switching Transistor 206 Phase Node 208 Switch or Switching Transistor 210 Output Inductor 212 Output Node 35 201236340 214 Output Capacitor 216 Horse Block Block 218 PWM Comparator 220 Error Amplifier 222 Center Node 224 Window V current source 226 first window node 228 first window resistance 230 Window D Current Source 232 Node 234 Second Window Resistor 236 々A* Point 238 Switch 240 Inverter 242 Switch 244 Chopper Node 246 Chopper Capacitor 248 Chopper Resistor 250 Common Voltage Node 252 Combiner Network 254 Transconductance network 300 phase comparator 301 D-type flip-flop (DFF) 303 AA· defect

36 201236340 305 D-type flip-flop (DFF) 3 07 Node 309 2 input gates 311 SPST switch 313 SPST switch 3 15 Current source 319 Node 321 Node 323 Current source 400 Combiner 401 Operational amplifier 403 N-type MOS transistor 405 N-type MOS transistor 407 P-type MOS transistor 409 Resistor 411 Resistor 412 Node 413 P-type MOS transistor 415 P-type MOS transistor 417 Node 419 Current combiner network 421 Dual-carrier junction transistor (BJT ) 423 Node 425 Bipolar Contact Transistor (BJT) 37 201236340 427 Bipolar Contact Transistor (BJT) 429 Current Source 431 Bipolar Contact Transistor (B JT) 433 N Type MOS Transistor 435 N MOS transistor 600 controller 601 comparator 602 inverting (-) input 603 non-inverting (+) input 605 capacitor 606 capacitor 607 phase 1 transconductance amplifier 608 phase 2 transconductance amplifier 610 threshold comparator 611 anti Phase (-) input 612 non-inverting (+) input 613 comparator 614 inverting (-) input 615 non-inverting (+) input 616 non-inverting (+) input 617 inverting (- ) Input 618 non-inverting (+) input 619 inverting (-) input threshold comparator 620

38 201236340 62 1 Non-inverting (+) input 622 Inverting (-) input 630 Setting/resetting flip-flop 640 Controlled switch 641 Node 642 First input terminal 643 Second input terminal 645 Chopper capacitor 650 Transconductance amplifier 65 1 non-inverting (+) input 652 inverting (-) input 660 transimpedance amplifier 66 1 non-inverting (+) input 662 inverting (-) input 670 sequential logic circuit 671 first Output 672 Second Output 680 Positive and Negative 690 Positive and Negative 691 Combiner Network 699 Node 800 Multiphase Synthetic Chopper Voltage Regulator 801 Common Output Node 803 Output Capacitor 39 201236340 901 Sample and Hold (SH) Network 903 Mutual Conductor amplifier 905 combiner 907 P-type MOS transistor 909 P-type MOS transistor 911 switch 915 transconductance amplifier 917 combiner Cl~C2 capacitor GDI ~ GDN gate driver Ll-LN inductor Q1 1' - switch Q12 above QN1 ~QN2 under the switch R1 resistor 40

Claims (1)

201236340 VII, the scope of application for patents: 1 · A synthetic chopper regulator, which is the stalk output of the conversion input voltage m contains the reference clock based on the second post-chopper regulator system including: control 'edge' into the error network Road, the sister is his _ /, is the k supply finger should not output the voltage difference signal; the chopping detector for the decision, the choice @, according to the 输入 dedicated input and output voltage and control signals to Providing a ramp control signal; a wave ... combiner, which adjusts the ramp control signal according to the frequency compensation signal to supply the ramped control signal after the trimming; the skin SHI is based on the adjusted ramp control signal Exciting a chopping control signal; an x π comparator network that develops the pulse wave control signal to control switching based on the error signal and the continuous wave control signal; and a phase comparator that compares the pulse wave The control signal is coupled to the reference clock and provides a frequency compensation signal indicative of the frequency. 2 _ The composite chopper regulator of claim 1, wherein: the chopper detector comprises at least one transconductance device, wherein the transconductance device is based on the input and output voltages and the pulse wave control signal Providing a ramp control current; wherein the phase comparator compares the pulse control signal with the reference clock to develop the frequency compensation signal; and wherein the combiner utilizes the frequency compensation signal to adjust the ramp control current An adjusted ramp control current is provided. 41 201236340 3. The composite chopper regulator of claim 2, wherein the chopper generator comprises a chopper capacitor that is charged by the adjusted ramp control current and Discharge. 4. The composite chopper regulator of claim 2, wherein the frequency compensation signal comprises a frequency compensation current, and wherein the combiner comprises a multiplier, the multiplier multiplying the ramp control current by the frequency The compensation current is divided by a reference current. 5. The composite chopper regulator of claim </ RTI> wherein the phase comparator comprises: a flash lock for measuring the edge of the reference clock; the second flash lock is used for Detecting an edge of the pulse control signal; a resistor-capacitor network for developing a frequency compensation voltage; and switching a current network by the first and second latches Controlling for charging and discharging the resistor-capacitor network based on a duration between the reference clock and the edge '彖 of the pulse control signal. 6. The composite chopper regulator of the scope of the patent application, wherein the comparator network comprises: a window network that converts the error signal into a window signal having an upper limit and a lower limit; and a hysteresis comparator, It compares the chopping control signal with the window signal U to develop the pulse wave control signal. 7. The composite chopper regulator of claim 1, further comprising: 42 201236340 a plurality of phase networks, each of which develops a plurality of chopping control signals according to the pulse width modulation signals corresponding to the input and output voltages and the plurality of pulse width modulation signals Corresponding chopping control signal; and "the pulse wave control signal; comprising a main day pulse signal, the main clock signal controlling a switching frequency of each of the plurality of pulse width modulation signals." An electronic device includes: a composite chopper regulator that converts an input voltage into an adjusted output voltage 'and includes a frequency control based on a reference clock, and the synthetic chopper regulator in # includes: σ The network 'provides an error signal indicating the relative error of the output voltage; the chopper detector 'based on the input and output voltages and the pulse wave control signal to provide a ramp control signal; a compensation signal to adjust the ramp control signal to provide an adjusted ramp control signal; a ramp control signal and the chirp control: and chopping Based on the adjusted signal to develop a chopper control signal; the comparator network develops the pulse wave control signal according to the error signal to control the switching phase comparator, which is The pulse wave control signal is coupled to the clock and provides the frequency compensation signal. ^ 9. The electronic device of claim 8 wherein the synthetic chopper 43 201236340 卽 卽 包括 includes multiphase adjustment And wherein the pulse wave control signal comprises a primary clock signal. 10. The electronic device of claim 8, wherein the method comprises: a processor receiving the output voltage as a power supply voltage; The electronic comparator is coupled to the processor and receives the output voltage as a power supply voltage. 11. The electronic device of claim 8 wherein the phase comparator comprises: Receiving the reference clock and providing an up signal; the first flip-flop receiving the pulse control signal and providing a downward signal; Μ controlling the gate' An input C for receiving the upward and downward signals and an output of the clearing input connected to the first and second flip-flops; and a voltage-carrying network for developing a frequency compensation voltage Do not compensate the signal for the frequency; switch the current source-capacitor network; switch the current sink-capacitor network, which charges the resistor when the upward signal is emitted and discharges when the downward signal is emitted The resistor of claim 8, wherein the combiner multiplies the ramp control signal by the frequency compensation signal to provide the adjusted ramp control signal. 8 items of electronic devices, wherein: the phase comparator provides the frequency compensation signal as a frequency compensation 44 201236340 wherein the δ 涟 涟 wave predator comprises a transconductance amplifier that provides the ramp control signal as a ramp control current based on a voltage applied across the output inductor; and wherein the combiner is A multiplier is included that multiplies the frequency compensation voltage by the ramp control current. The electronic device of claim 13, wherein the combiner comprises a converter that converts the frequency compensation voltage into a frequency compensation current, and wherein the multiplier comprises a current multiplier, the current multiplier Multiplying the frequency compensation current by the ramp control current divided by the reference becomes a method for controlling the steady-state switching frequency of the synthesized chopper regulator according to the reference clock, wherein the synthetic chopper regulator is converted An input voltage-adjusted output voltage, the method comprising: determining an error of the output power S and providing a window signal indicating a compensation limit and a lower limit indicating the error, using the compensation signal to develop an upper limit and a field When the wave control signal is emitted as high, according to the interval between the voltages, #佶AA....... Input and output at the 并且 and when the pulse wave controls the signal ramp signal; the clock provides a frequency compensation according to the frequency compensation value to adjust the ramp signal and provides an adjusted ramp signal of 20123634040; after the adjustment is converted The ramp signal becomes a chopping signal; and the ratio is complemented by comparing the concatenated signal with the window signal and providing a ratio of the pulse control signal. 16· The method of claim 15 of the patent application, wherein the providing the frequency compensation value comprises: when the Tianhai reference clock has a higher frequency than the pulse control signal, adding the frequency compensation value And when the Putian ° Hai reference clock has a lower frequency than the pulse control signal, the level of the β Xuan frequency compensation value is lowered. The method of claim 15, wherein the adjusting the ramp signal based on the frequency compensation value comprises multiplying the ramp signal by the frequency compensation value. + 18· The method of claim 15 wherein: the ramp signal generated by the S-hai includes generating a ramp current; and the frequency compensation value of the medium-occurring frequency includes generating a frequency compensation current; wherein the tilt is adjusted The wave signal system includes multiplying the ramp current by the frequency compensation current and dividing by the reference current. 19. The method of claim 15, wherein the converting the adjusted ramp signal comprises charging the chopper capacitor with the adjusted ramp current to provide a chopping voltage. 2. The method of claim 19, wherein: determining the error of the output voltage comprises amplifying a difference between the output voltage 201236340 and a reference voltage to provide a compensation voltage; wherein the window signal is developed The method includes providing an upper voltage by adding an offset voltage to the current compensation voltage, and by applying a voltage from the compensation ink, to provide a lower voltage; and subtracting the bias, wherein the adjusted chopping signal is compared and The window D^ includes comparing the chopping voltage with the upper voltage and the lower voltage. °绿仪包 Eight, schema: (such as the next page) 47