201224696 六、發明說明： 【發明所屬之技術領域】 本發明為一低壓降電壓穩壓器，特別是使用於SoC内 部之電源管理單元與獨立的電源管理晶片之一種低壓降電 壓穩壓器。 【先前技術】 傳統上，為了得到精確的輸出電壓位準，也就是較高 • 的線上穩壓和負載穩壓，低壓降電壓穩壓器必須設計具較 高的迴路增益。目前大部份可攜式電子產品操作在低的供 應電壓，因此傳統以疊揍方式增加誤差放大器增益的方式 已不適合，大多是採用串接方式為主。也就是在誤差放大 器之後串上高擺幅的第二級增益，再串接功率電晶體 (Power PMOS)，形成三級放大的架構，但是低壓降電壓 穩壓器串接愈多級，所產生由寄生電容貢獻的極點會愈 多，使低壓降電壓穩壓器不穩定。 • 習知低壓降線性穩壓器補償的方式是較不理想，其利 用晶片外部大電容的等效串聯電阻達成頻率補償，但是無 法精確的製造與控制晶片外部大電容的等效串聯電阻（ESR) 值；另外，於SoC中使用低壓降電壓穩壓器，穩壓電路輸 出端會有電源金屬層等效寄生電容，因此要滿足穩定度的 補償設計而沒有外部電容與等效串聯電阻（ESR)的輔助是 _ 很困難的。 目前已有將麵合電容〇.6nF整合到SoC内部的技術， 201224696 此種晶片内部電容佔有非常大的面積，不適合s〇c的發 f，於是就有許多研究朝著不需要晶片外部負載電容的穩 壓器發展’例如：利用電路之極零對消（pole-zero201224696 VI. Description of the Invention: [Technical Field] The present invention is a low-dropout voltage regulator, particularly a low-dropout voltage regulator used in a power management unit and a separate power management chip inside the SoC. [Prior Art] Traditionally, in order to obtain accurate output voltage levels, that is, higher on-line regulation and load regulation, the low-dropout voltage regulator must be designed with higher loop gain. At present, most portable electronic products operate at a low supply voltage, so the conventional method of increasing the gain of the error amplifier in a stacked manner is not suitable, and most of them are mainly in series. That is, after the error amplifier, a series of high-swing second-stage gain is connected, and then a power transistor (Power PMOS) is connected in series to form a three-stage amplification structure, but the lower-voltage-down voltage regulator is connected in series, and the resulting The more poles contributed by the parasitic capacitance, the instability of the low dropout voltage regulator. • The conventional low-dropout linear regulator compensation method is less than ideal. It uses the equivalent series resistance of the large external capacitor to achieve frequency compensation, but cannot accurately manufacture and control the equivalent series resistance of the external large capacitor (ESR). In addition, in the SoC, a low-dropout voltage regulator is used, and the output voltage of the voltage regulator circuit has the equivalent parasitic capacitance of the power supply metal layer, so the compensation design to satisfy the stability without external capacitor and equivalent series resistance (ESR) The aid is _ very difficult. At present, there is a technology for integrating the surface capacitance 〇.6nF into the SoC. 201224696 The internal capacitance of this chip occupies a very large area, which is not suitable for the s〇c. Therefore, there are many studies that do not require external load capacitance of the chip. The development of the regulator's example: using the pole zero cancellation of the circuit (pole-zero
CanCellation)技術，或利用 Flipped Voltage Follower 架構 之設計。 低壓降線性穩壓電路的負載穩壓/線上穩壓之精確度 與迴路穩定度的規格常常有互相牴觸的狀態，高的迴路增 益可以提供精確的穩態電壓值，卻會減少相位邊際影響迴 Φ 路的穩疋度。因此，極零對消（pole-zero cancellation)技術 使用於此穩壓電路，以及利用Flipped Voltage F〇ll〇wer的 並聯回授（shunt feedback)技術以減少低壓降線性穩壓電 路的輸出組抗’而得到頻率補償。但使用極零對消（p〇le_zer〇 cancellation)技術的低壓降線性穩壓器不容易達到非常快 速的負载暫態響應，而使用Flipped Voltage Follower的並 聯回授（shunt feedback)技術的低壓降線性穩壓器迴路增 益較低，有不好的負載穩壓/線上穩壓狀況，不易達到高的 # 輸出電流驅動能力。 故而為了能產生製造更佳的低壓降電壓穩壓器，需要 研發新式的低壓降電壓穩壓器技術，藉以提升低壓降電壓 穩壓器效率且能夠降低該低壓降電壓穩壓器的製造成本。 【發明内容】 •本發明之主要目的，係在提供一種低壓降電壓穩壓 器，其係利用快速自我反應電路加速負載暫態變化，當負 201224696 迴路以減少輸出 載陕速1動b$ ’快速自我反應電路形成一 電壓的變化幅度。 II 之另目的’係在提供-種低壓降電壓穩壓 器，=利用頻率補償電路可以在無晶片外大電容情況 下，具有非常高的穩定性，從零負載電流到設定的最大負 载電;^都保持最好的穩定度。 、 本發月之另一目的，係在提供一種低壓降電壓穩壓方 法’其係利用補償網路產生零點與米勒補償效應及快速自 鲁我反應電路增加訊號迴轉率加快負載暫態響應與線上暫雜 響應。 本發明為一種低壓降電壓穩壓器，包括：一回授電路 接收一參考電壓訊號及一回授電壓訊號，回授電路輸出一 控制訊號；一功率傳遞裝置電性連接回授電路並輸出一輸 出電壓，一快速自我反應電路電性連接回授電路及功率傳 遞裝置之輸出端，快速自我反應電路接收輸出電壓，降低 電壓輸出之變化幅度，並輸出一調整訊號至回授電路及控 制訊號；一第一補償電路電性連接回授電路及快速自我反 應電路，第一補償電路接收調整訊號以補償回授電路中的 頻率訊號，以及一第二補償電路電性連接回授電路及功率 傳遞裝置’第二補償電路接收輸出電壓以補償回授電路中 的頻率訊號。 另外，本發明為一種低壓降電壓穩壓器，包括：一誤 差放大器，包含一第一放大器及一第二放大器，第一放大 器接收一參考電壓訊號及一回授電壓訊號，第二放大器串 201224696 聯第一放大器輸出一控制訊號；一功率電晶體電性連接誤 差放大器接收控制訊號以控制一輸入訊號通過並輸出一輸 出電壓；一第二補償電路，包含一第三放大器及一補償電 容’第三放大器及補償電容以並聯方式電性連接回授電路 及功率電晶體，第二補償電路接收調整訊號以補償回授電 路中的頻率訊號；一快速自我反應電路電性連接回授電路 及功率電晶體之輸出端，快速自我反應電路接收輸出電 壓·降低電壓輸出之變化幅度，並輸出一調整訊號至回授 電路及控制訊號，其包含：一第四放大器連接功率電晶體 之輸出以接收輸出電壓；一第六放大器連接第四放大器形 成一第二快速自我反應電路偵測輸出電壓以控制控制訊 號’ 一第二電容位於第四放大器與第六放大器之間；一第 五放大器連接功率電晶體之輸出以接收輸出電壓，第五放 大器之輸出傳送至第六放大器形成一第三快速自我反應電 路偵測輸出電壓以控制控制訊號；以及一第七放大器連接 功率電晶體之輸出以接收輸出電壓，形成一第一快速自我 反應電路偵測輸出電壓以控制控制訊號；一第一電容與第 =放大器並聯；一第一電阻與第一電容串聯並與第六放大 器並聯，第一電容、第一電阻與第六放大器形成第一補償 電路，其電性連接回授電路及功率電晶體，第一補償電路 接收輸出電愿以補償回授電路中的頻率訊號；以及-回授 分壓電路電性連接㈣電路，回授分壓電路接收輸出電壓 以產生回授電壓訊號傳送至回授電路。 再者，本發明為一種低壓降電壓穩壓的方法，包括： 201224696 將工力率傳遞裝置的輪入與輸出兩個極點推到迴路頻寬之 夕卜；在單增益頻率之内留下兩個級點與 一個零點；利用— 補償網路產生零點與米勒補償效應；利用-快速自我反應 電路增加訊號迴轉率；以及使用高增益之回授放大器增加 迴路增益。 故而，關於本發明之優點與精神可以 藉由以下發明詳 述及所附圖式得到進一步的瞭解。 • 【實施方式】 本發明為一低壓降電壓穩壓器及其使用方法，其可以 達到高的迴路增益使其具有高的負載穩壓與高的線上穩壓 之精確度。 請參閱第1圖所示為本發明一實施例之低壓降電壓穩 壓器架構示意圖。低壓降電壓穩壓器包括：回授電路1()接 收參考電壓訊號vref及回授電壓訊號vfeb，在輸出端輸出 控制訊號Vctrl ;功率傳遞裝置11電性連接回授電路1〇並 籲 輸出一輸出電壓Vout;快速自我反應電路12電性連接回授 電路10及功率傳遞裝置11之輸出端，快速自我反應電路 U接收輸出電壓Vout，並降低電壓輸出之變化幅度，其輸 出一調整訊號至回授電路10及控制訊號Vctr丨；第一補償電 路14電性連接回授電路1〇及快速自我反應電路π，第一 補償電路14接收調整訊號以補償回授電路1〇中的頻率訊 7虎，第二補償電路13電性連接回授電路10及功率傳遞裝 置11，第二補償電路13接收輸出電壓Vout以補償回授電 201224696 路10中的頻率訊號；以及回授分壓電路15電性連接回授 電路10，回授分壓電路15接收輸出電壓以產生回授 電壓訊號vfeb傳送至回授電路10。 其中，回授電路10為一高迴路增益之回授電路。第 一補償電路14包含一放大器、一補償電容以及一補償電阻 (圖中未示），補償電容與補償電阻串聯並與放大器並聯。 第二補償電路13包含一放大器及一補償電容（圖中未 示），補償電容與放大器並聯。 • 請參閱第2圖所示為本發明另一實施例之低壓降電壓 穩壓器架構示意圖。低壓降電壓穩壓器包括：回授電路20、 功率傳遞裝置21、第一補償電路24、第二補償電路23、 回授分壓電路25、第一快速自我反應電路221、第二快速 自我反應電路222及第三快速自我反應電路223。第一快 速自我反應電路221偵測輸出電壓以控制控制訊號 Vctrl，第二快速自我反應電路222偵測輸出電壓Vm以控 制控制訊號Vctrl，第三快速自我反應電路223偵測輸出電 籲 壓VQUt以控制控制訊號Vctrl。 另外，在另一實施例中，回授分壓電路25連接回授 電路20及第三快速自我反應電路223，其接收輸出電壓以 產生回授電壓訊號Vfeb傳送至回授電路20，並產生一分壓 訊號至第三快速自我反應電路223，如第3圖所示。 再者，未使用回授分壓電路的另一實施例則如第4圖 所示。 根據上述，回授電路20為一高迴路增益之回授電路。 201224696 第一補償電路24包含一放大器、一補償電容以及一補償電 阻（圖中未示），補償電容與補償電阻串聯並與放大器並 聯。第二補償電路23包含一放大器及一補償電容（圖中未 示），補償電容與放大器並聯。 請參閱第5圖所示為本發明一實施例之低壓降電壓穩 壓器電路元件示意圖。誤差放大器50包含放大器A,及放 大器A2，放大器A〗接收參考電壓訊號VREF及回授電壓訊 號Vfb ’放大器A2串聯放大器A!輸出一控制訊號VCTRL ; 參 功率電晶體MPW電性連接誤差放大器50接收控制訊號 VCTR以控制輸入訊號V丨N (電源訊號VDD)通過並輸出一輸 出電壓VOUT;第二補償電路53包含放大器A3及電容Cm3, 放大器A3及電容Cm3以並聯方式電性連接回授電路50及 功率電晶體MPW，第二補償電路53接收輸出訊號以補償回 授電路50中的頻率訊號；電容cml、電阻Rml與放大器A6 形成第一補償電路54，其電性連接回授電路50及功率電 晶體MPW，第一補償電路54接收輸出電塵νουτ以補償回 馨 授電路50中的頻率訊號；回授分壓電路由電組Rfb1與Rfb2 形成’其電性連接回授電路50並接收輸出電壓V〇ut以產 生回授電壓訊號VFB傳送至回授電路50。 另外’快速自我反應電路包含：放大器A4連接功率電 晶體]viPwi輸出以接收輸出電壓ν〇υτ;放大器&連接放 大器八4形成第二快速自我反應電路522偵測輸出電麼 V0UT以控制控制訊號VcTRL;電容Cm2位於放大器a4與放 大器Αδ之間；放大器八5連接功率電晶體Mpw之輸出以接 201224696 收輸出電壓V0lJT，放大器A5之輸出傳送至放大器A6形成 第三快速自我反應電路523偵測輸出電壓νουτ以控制控制 訊號Vctrl;放大器Α7連接功率電晶體MPW之輸出以接收 輸出電壓V0UT，形成第一快速自我反應電路521偵測輸出 電壓V〇ut以控制控制訊號VCTRL;其中誤差放大器50為一 高迴路增益之回授電路。 在第5圖實施例中，本發明將功率電晶體MPW閘極端 的極點（pole)和穩壓電路輸出端的極點（pole)推往高頻， φ 讓這兩個極點（pole )的位置超過單一增益頻率（Unity Gain Frequency, UGF )。本發明之穩壓電路的主要極點（dominant pole)P!位在放大電路A2的輸入端，第二極點（second pole) P2位於放大電路A6的輸入端，第三極點（third pole) P3 位於低壓降電壓穩壓器的輸出端。 第一快速自我反應電路521會偵測穩壓器的輸出端節 點ηουτ的電壓訊號V0UT，當V0UT突然下降（AVout)時’ 第一快速自我反應電路521會將此Δνουτ放大並且快速地 鲁 控制節點ncTRL的電壓訊號Vctrl下降，於是功率電晶體 MPW會提供更多的功率（與電流）到穩壓器的輸出端節點 ηουτ’穩壓器的輸出端節點的電壓訊號VOUT就會快速的回 復到正常的穩壓狀態。第一快速自我反應電路521提高了 迴轉率（slew rate)並提昇了迴路頻寬（i〇op bandwidth )。 另外’在小訊號分析中，第一快速自我反應電路521 會降低節點nCTRL與節點ηουτ所看進去的阻抗，因此這兩 個卽點的極點（pole )會位在高頻處，節點nCTRL的極點會 201224696 被第一補償電路54推到很高頻的地方，遠大於單位增益頻 率（unity gain bandwidth )，因此節點nCTRL的極點不會影 響系統的穩定性。而節點ηουτ的極點會被第二補償電路53 推到更高頻，高於單位增益頻率形成系統的第三個極點Ρ 3。 第二快速自我反應電路522會偵測穩壓器的輸出端節 點η〇υτ的電壓訊號V〇ut，當V〇ut突然下降（△ V〇ut)時， 第二快速自我反應電路522會將此△V〇ut放大並且快速地 控制節點nCTRL的電壓訊號VCtrl下降’於是功率電晶體 • MPW會提供更多的功率（與電流）到穩壓器的輸出端節點 η〇υτ’穩壓器的輸出端節點的電壓訊號VOUT就會快速的回 復到正常的穩壓狀態。第二快速自我反應電路522提高迴 轉率並提昇迴路頻寬。 第三快速自我反應電路523會偵測穩壓器的輸出端節 點n0UT的電壓訊號νουτ’當V0UT突然下降（AVout)時’ 第三快速自我反應電路523會將此Ανουτ放大並且快速地 控制節點nCTRL的電壓訊號VCTRL下降’於是功率電晶體 鲁 MPW會提供更多的功率（與電流）到穩壓器的輸出端節點 η〇υτ’穩壓器的輸出端節點的電壓訊號V〇ut就會快速的回 復到正常的穩壓狀態。第三快速自我反應電路523提高了 迴轉率並提昇了迴路頻寬。 在第一補償電路54小訊號分析中’由於節點ncTRL所 看到的阻抗較低，於是第一補償電路54會將節點nCTRL的 極點推到非常高頻之處’遠大於單位增益頻率，使得節點 nCTRL的極點不會影響系統的穩定性。由於節點^⑶奶所看 201224696 到的阻抗較局’卽點nc〇M2的極點會被第—補償電路54推 往低頻的位置形成系統的第二個極點P 2。 在第二補償電路53小訊號分折中’由於節點η〇υτ所 看到的阻抗較低’於是第二補償電路53會將節點恥⑽的 極點推到較高頻的地方，高於單位增益頻率形成系統的第 二個極點Ρ3。由於卽點nc〇M i所看到的Ρ且抗較高，於是第 一補償電路53會將節點nC0M1的極點推到較低頻之處，形 成系統的主極點（dominant pole )，也就是第一個極點p!。 鲁 另外’放大電路A?使得放大電路八2的輸出端與功率 電晶體（MPW )的汲極端看到的輸出阻抗（〇utput impedance ) 變付較低’因此當低壓降電壓穩壓器加入了補償電容cm3 和放大電路As之後，放大電路八2輸入端的極點（p〇le)會 被推到更低頻而形成主要極點（dominant pole) P!，而低 壓降電壓穩壓器輸出端的極點反而會被推到較高頻，而形 成迴路的第三極點（third pole) P3。同樣的，電容cml、電 阻Rml和放大電路八6會將功率電晶體Mpw閘極端的極點 馨 （pole)推到更高頻遠離單一增益頻率（UGF)，而將放大 電路A6的輸入端極點推至低頻形成迴路的第二極點 (second pole) P2。第一個零點（zer〇)是由放大電路八4、 電容Cm和放大電路As所產生，用來和第二極點（此⑶⑼ pole)卩2相消’第二零點（second zer〇)心是由電容Cm、 電阻Rml和放大電路A6所產生，可以和第三極點〇hird pole) P3相消，因此穩壓電路整個迴路具有非常好的穩定 度。 “ 201224696 如第6A圖與第6B圖所示為本發明一實施例之頻率響 應（Frequency Response)示意圖，以及第7圖所示為本發 明一實施例之相位邊際（Phase Margin)示意圖。在第6a 圖中為負載電流為零時的頻率響應圖，極點Ρι位在非常低 頻，零點Zi用來與極點I相消（Z2位的頻率稍高於匕）。 在第6B圖中負載電流為1〇〇111八時的頻率響應圖，極點h 位在非吊低頻，零點z〗用來與極點h相消（但心位的頻 率梢低於P3)。帛7圖巾AA’線為帛6A圖的相位邊際圖， 鲁 BB ’線為第6B圖的相位邊際圖。 明參閱第8圖所示為本發明一實施例之低壓降線性穩 壓器電路示意圖，有—偏主要的串聯_並聯（sedal_shunt) 回授路徑與快速自我反應電路路徑，此電路可以加速負載 ^態響應與線上暫態響應。第-快速自我反應電路是由電 日0體μ丨7、μ丨8、μ丨9、m20和功率電晶體Mpwm構成，，當 輸出電壓VOUT瞬間下降時，Imi9偏壓電流固定，因此 下降’進而造成m17的閘極電壓下降，流過M17的電流增 加，使得功率電晶體Mpw的閘極電壓快速下降，因此功率 電晶體Mpw提供更多的電流至輸出負載端，輸出電壓νουτ I·、速回到正常穩壓值。第二快速自我反應電路徑是由電晶 體 Μ17 Μ18、μ19、Μ20、cm2、μ16 和功率電晶體 Mpw 所 構成，當輸出電壓V0UT瞬間下降時，會經由電晶體M17、 M18 M19 M20在m20的閘源極形成一個訊號增量Δν_， 而此訊號增量會經由補償電容Cm2輕合至電晶體Μ16的問 極電曰曰體Μ16因此而產生一個電流増量，此電流增量會CanCellation) technology, or the design of the Flipped Voltage Follower architecture. The low-dropout linear regulator circuit's load regulation / line regulation accuracy and loop stability specifications often have a state of mutual contact, high loop gain can provide accurate steady-state voltage values, but will reduce phase marginal effects Back to the stability of the Φ road. Therefore, the pole-zero cancellation technique uses this voltage regulator circuit, and the shlipped feedback technique of the Flipped Voltage F〇ll〇wer is used to reduce the output group resistance of the low-dropout linear regulator circuit. 'And get frequency compensation. However, low-dropout linear regulators using the zero-zero cancellation (p〇le_zer〇cancellation) technique do not easily achieve very fast load transient response, while the low-dropout linearity of the shlipped feedback technique using the flipped voltage follower The regulator loop gain is low, there is a bad load regulation / online regulation, it is not easy to achieve high # output current drive capability. Therefore, in order to produce a better low-dropout voltage regulator, a new type of low-dropout voltage regulator technology is needed to improve the efficiency of the low-dropout voltage regulator and reduce the manufacturing cost of the low-dropout voltage regulator. SUMMARY OF THE INVENTION The main object of the present invention is to provide a low-dropout voltage regulator that utilizes a fast self-reacting circuit to accelerate load transients, when a negative 201224696 loop is used to reduce the output load of the Shaanxi speed b$ ' The fast self-reactive circuit forms a magnitude of change in voltage. The other purpose of II is to provide a low-dropout voltage regulator, and the frequency compensation circuit can have very high stability in the absence of large external capacitors, from zero load current to the set maximum load power; ^ All maintain the best stability. Another purpose of this month is to provide a low-voltage drop voltage voltage regulation method, which uses the compensation network to generate zero point and Miller compensation effect and fast self-reliance circuit to increase the signal slew rate and accelerate the load transient response. Online miscellaneous response. The present invention is a low voltage drop voltage regulator comprising: a feedback circuit receiving a reference voltage signal and a feedback voltage signal, the feedback circuit outputting a control signal; a power transfer device electrically connecting the feedback circuit and outputting a The output voltage, a fast self-reactive circuit is electrically connected to the output of the feedback circuit and the power transfer device, the fast self-reactive circuit receives the output voltage, reduces the variation range of the voltage output, and outputs an adjustment signal to the feedback circuit and the control signal; A first compensation circuit is electrically connected to the feedback circuit and the fast self-reaction circuit, the first compensation circuit receives the adjustment signal to compensate the frequency signal in the feedback circuit, and the second compensation circuit is electrically connected to the feedback circuit and the power transmission device The second compensation circuit receives the output voltage to compensate for the frequency signal in the feedback circuit. In addition, the present invention is a low-dropout voltage regulator comprising: an error amplifier comprising a first amplifier and a second amplifier, the first amplifier receiving a reference voltage signal and a feedback voltage signal, the second amplifier string 201224696 The first amplifier outputs a control signal; a power transistor is electrically connected to the error amplifier to receive the control signal to control an input signal to pass and output an output voltage; and a second compensation circuit includes a third amplifier and a compensation capacitor The three amplifiers and the compensation capacitors are electrically connected to the feedback circuit and the power transistor in parallel, the second compensation circuit receives the adjustment signal to compensate the frequency signal in the feedback circuit, and the fast self-reaction circuit is electrically connected to the feedback circuit and the power supply. At the output end of the crystal, the fast self-reacting circuit receives the output voltage, reduces the magnitude of the change in the voltage output, and outputs an adjustment signal to the feedback circuit and the control signal, which includes: a fourth amplifier connected to the output of the power transistor to receive the output voltage a sixth amplifier connected to the fourth amplifier to form a second The fast self-reactive circuit detects the output voltage to control the control signal. A second capacitor is located between the fourth amplifier and the sixth amplifier; a fifth amplifier is connected to the output of the power transistor to receive the output voltage, and the output of the fifth amplifier is transmitted to The sixth amplifier forms a third fast self-reactive circuit to detect the output voltage to control the control signal; and a seventh amplifier is connected to the output of the power transistor to receive the output voltage to form a first fast self-reactive circuit to detect the output voltage to control a first capacitor is connected in parallel with the ninth amplifier; a first resistor is connected in series with the first capacitor and is connected in parallel with the sixth amplifier, and the first capacitor, the first resistor and the sixth amplifier form a first compensation circuit, and the electrical connection is a feedback circuit and a power transistor, the first compensation circuit receives the output power to compensate the frequency signal in the feedback circuit; and - the feedback voltage divider circuit is electrically connected (4), and the feedback voltage circuit receives the output voltage A feedback voltage signal is generated and transmitted to the feedback circuit. Furthermore, the present invention is a low voltage drop voltage regulation method, comprising: 201224696 Pushing the two poles of the wheel force input and output of the power rate transmission device to the loop bandwidth; leaving two within the single gain frequency Levels and zeros; use - compensation network to generate zero and Miller compensation effects; use - fast self-reaction circuit to increase signal slew rate; and use high gain feedback amplifier to increase loop gain. Therefore, the advantages and spirit of the present invention can be further understood from the following detailed description of the invention and the accompanying drawings. • [Embodiment] The present invention is a low-dropout voltage regulator and a method of using the same, which can achieve high loop gain for high load regulation and high on-line voltage regulation accuracy. Please refer to FIG. 1 , which is a schematic diagram of a low voltage drop voltage regulator according to an embodiment of the invention. The low-voltage drop voltage regulator includes: the feedback circuit 1 () receives the reference voltage signal vref and the feedback voltage signal vfeb, and outputs the control signal Vctrl at the output end; the power transfer device 11 is electrically connected to the feedback circuit 1 and calls the output one The output voltage Vout; the fast self-reaction circuit 12 is electrically connected to the output of the feedback circuit 10 and the power transfer device 11, and the fast self-reaction circuit U receives the output voltage Vout, and reduces the amplitude of the change of the voltage output, and outputs an adjustment signal to the output. The circuit 10 and the control signal Vctr丨 are provided; the first compensation circuit 14 is electrically connected to the feedback circuit 1〇 and the fast self-reaction circuit π, and the first compensation circuit 14 receives the adjustment signal to compensate the frequency signal in the feedback circuit 1〇7 The second compensation circuit 13 is electrically connected to the feedback circuit 10 and the power transfer device 11, and the second compensation circuit 13 receives the output voltage Vout to compensate the frequency signal in the feedback power 201224696 path 10; and the feedback voltage divider circuit 15 The feedback circuit 10 is connected, and the feedback voltage dividing circuit 15 receives the output voltage to generate a feedback voltage signal vfeb for transmission to the feedback circuit 10. The feedback circuit 10 is a feedback circuit with a high loop gain. The first compensation circuit 14 includes an amplifier, a compensation capacitor, and a compensation resistor (not shown). The compensation capacitor is connected in series with the compensation resistor and in parallel with the amplifier. The second compensation circuit 13 includes an amplifier and a compensation capacitor (not shown), and the compensation capacitor is connected in parallel with the amplifier. • Referring to FIG. 2, a schematic diagram of a low voltage drop voltage regulator architecture according to another embodiment of the present invention is shown. The low-dropout voltage regulator includes: a feedback circuit 20, a power transfer device 21, a first compensation circuit 24, a second compensation circuit 23, a feedback voltage dividing circuit 25, a first fast self-reaction circuit 221, and a second fast self The reaction circuit 222 and the third fast self-reaction circuit 223. The first fast self-reaction circuit 221 detects the output voltage to control the control signal Vctrl, the second fast self-reaction circuit 222 detects the output voltage Vm to control the control signal Vctrl, and the third fast self-reaction circuit 223 detects the output power-off voltage VQUt to Control control signal Vctrl. In addition, in another embodiment, the feedback voltage dividing circuit 25 is connected to the feedback circuit 20 and the third fast self-reaction circuit 223, which receives the output voltage to generate the feedback voltage signal Vfeb and transmits it to the feedback circuit 20, and generates A partial pressure signal to the third fast self-reaction circuit 223, as shown in FIG. Furthermore, another embodiment in which the feedback voltage dividing circuit is not used is as shown in Fig. 4. According to the above, the feedback circuit 20 is a high loop gain feedback circuit. 201224696 The first compensation circuit 24 includes an amplifier, a compensation capacitor, and a compensation resistor (not shown). The compensation capacitor is connected in series with the compensation resistor and is connected in parallel with the amplifier. The second compensation circuit 23 includes an amplifier and a compensation capacitor (not shown), and the compensation capacitor is connected in parallel with the amplifier. Please refer to FIG. 5, which is a schematic diagram showing the circuit components of the low-dropout voltage regulator according to an embodiment of the present invention. The error amplifier 50 includes an amplifier A, and an amplifier A2. The amplifier A receives the reference voltage signal VREF and the feedback voltage signal Vfb. The amplifier A2 series amplifier A! outputs a control signal VCTRL. The reference power transistor MPW is electrically connected to the error amplifier 50. The control signal VCTR controls the input signal V丨N (power signal VDD) to pass and outputs an output voltage VOUT; the second compensation circuit 53 includes an amplifier A3 and a capacitor Cm3, and the amplifier A3 and the capacitor Cm3 are electrically connected to the feedback circuit 50 in parallel. And the power transistor MPW, the second compensation circuit 53 receives the output signal to compensate the frequency signal in the feedback circuit 50; the capacitor cml, the resistor Rml and the amplifier A6 form a first compensation circuit 54, which is electrically connected to the feedback circuit 50 and the power The transistor MPW, the first compensation circuit 54 receives the output electric dust νουτ to compensate the frequency signal in the return circuit 50; the feedback piezoelectric routing group Rfb1 and Rfb2 form the 'electrical connection feedback circuit 50 and receives the output. The voltage V〇ut is transmitted to the feedback circuit 50 in response to the generation of the feedback voltage signal VFB. In addition, the 'fast self-reaction circuit includes: the amplifier A4 is connected to the power transistor] the viPwi output to receive the output voltage ν 〇υ τ; the amplifier & connection amplifier VIII forms a second fast self-reaction circuit 522 to detect the output power V0UT to control the control signal VcTRL; the capacitor Cm2 is located between the amplifier a4 and the amplifier Αδ; the amplifier 8 is connected to the output of the power transistor Mpw to receive the output voltage V0lJT of 201224696, and the output of the amplifier A5 is transmitted to the amplifier A6 to form the third fast self-reaction circuit 523 detecting output. The voltage νουτ is used to control the control signal Vctrl; the amplifier Α7 is connected to the output of the power transistor MPW to receive the output voltage VOUT, and the first fast self-reaction circuit 521 is configured to detect the output voltage V〇ut to control the control signal VCTRL; wherein the error amplifier 50 is a High loop gain feedback circuit. In the embodiment of Fig. 5, the present invention pushes the pole of the power transistor MPW gate terminal and the pole of the voltage regulator circuit output to the high frequency, and φ allows the positions of the two poles to exceed a single Unity Gain Frequency (UGF). The main pole P! of the voltage stabilizing circuit of the present invention is at the input end of the amplifying circuit A2, the second pole P2 is located at the input end of the amplifying circuit A6, and the third pole P3 is located at the low voltage. The output of the voltage reduction regulator. The first fast self-reaction circuit 521 detects the voltage signal VOUT of the output node ηουτ of the voltage regulator. When the VOUT suddenly drops (AVout), the first fast self-reaction circuit 521 amplifies the Δνουτ and quickly controls the node. The voltage signal Vctrl of ncTRL drops, so the power transistor MPW will provide more power (and current) to the output node of the voltage regulator. The voltage signal VOUT of the output node of the regulator will quickly return to normal. Regulated state. The first fast self-reaction circuit 521 increases the slew rate and increases the i〇op bandwidth. In addition, in the small signal analysis, the first fast self-reaction circuit 521 will reduce the impedance seen by the node nCTRL and the node ηουτ, so the poles of the two defects will be at the high frequency, and the pole of the node nCTRL 201224696 is pushed by the first compensation circuit 54 to a very high frequency, much larger than the unity gain bandwidth, so the pole of the node nCTRL does not affect the stability of the system. The pole of the node ηουτ is pushed to a higher frequency by the second compensation circuit 53, above the third pole Ρ 3 of the unity gain frequency forming system. The second fast self-reaction circuit 522 detects the voltage signal V〇ut of the output node η〇υτ of the voltage regulator. When V〇ut suddenly drops (ΔV〇ut), the second fast self-reaction circuit 522 will This ΔV〇ut amplifies and quickly controls the voltage signal VCtrl of the node nCTRL to drop 'so the power transistor• MPW will provide more power (with current) to the output node of the regulator η〇υτ' regulator The voltage signal VOUT of the output node will quickly return to the normal voltage regulation state. The second fast self-reaction circuit 522 increases the return rate and increases the loop bandwidth. The third fast self-reaction circuit 523 detects the voltage signal νουτ' of the output node n0UT of the voltage regulator. When the VOUT suddenly drops (AVout), the third fast self-reaction circuit 523 amplifies the Ανουτ and quickly controls the node nCTRL. The voltage signal VCTRL drops' so the power transistor Lu MPW will provide more power (with current) to the output node of the regulator η〇υτ' the voltage signal of the output node of the regulator V〇ut will be fast The return to the normal steady state. The third fast self-reaction circuit 523 increases the slew rate and increases the loop bandwidth. In the small signal analysis of the first compensation circuit 54, 'the impedance seen by the node ncTRL is low, so the first compensation circuit 54 pushes the pole of the node nCTRL to a very high frequency' much larger than the unity gain frequency, so that the node The pole of nCTRL does not affect the stability of the system. As the node ^3 (3) sees the impedance of 201224696, the pole of the point nc〇M2 will be pushed to the low frequency position by the first compensation circuit 54 to form the second pole P 2 of the system. In the small signal division of the second compensation circuit 53, 'the impedance seen by the node η 〇υ τ is low', so that the second compensation circuit 53 pushes the pole of the node shame (10) to a higher frequency, higher than the unity gain. The second pole of the frequency forming system Ρ3. Since the defect seen by the defect point nc〇M i is high, the first compensation circuit 53 pushes the pole of the node nC0M1 to a lower frequency to form a dominant pole of the system, that is, the first A pole p!. Lu's 'amplifier circuit A' makes the output impedance of the amplifier circuit VIII and the output impedance of the power transistor (MPW) 变utput impedance lower, so when the low-dropout voltage regulator is added After the compensation capacitor cm3 and the amplifier circuit As, the pole (p〇le) of the input terminal of the amplifier circuit is pushed to a lower frequency to form a dominant pole P!, and the pole of the output of the low-dropout voltage regulator is instead It is pushed to a higher frequency to form a third pole P3 of the loop. Similarly, the capacitor cml, the resistor Rml and the amplifying circuit VIII will push the pole of the power transistor Mpw gate extreme to a higher frequency away from the single gain frequency (UGF), and push the input terminal of the amplifying circuit A6. The second pole P2 is formed to the low frequency. The first zero point (zer〇) is generated by the amplifying circuit VIII, the capacitor Cm and the amplifying circuit As, and is used to cancel the second pole (the second zer〇) with the second pole (this (3)(9) pole) 卩2 It is generated by capacitor Cm, resistor Rml and amplifier circuit A6, and can be canceled with the third pole 〇hird pole) P3, so the whole circuit of the voltage regulator circuit has very good stability. 201224696 FIG. 6A and FIG. 6B are schematic diagrams showing a frequency response (Frequency Response) according to an embodiment of the present invention, and FIG. 7 is a schematic diagram showing a phase margin (Phase Margin) according to an embodiment of the present invention. 6a is the frequency response diagram when the load current is zero. The pole Ρι is at very low frequency, and the zero Zi is used to cancel the pole I (the frequency of Z2 is slightly higher than 匕). In Figure 6B, the load current is 1 〇〇111 The frequency response diagram at 8:00, the pole h is in the non-suspended low frequency, and the zero point z is used to cancel the pole h (but the frequency of the heart is lower than P3). 帛7 towel AA' line is 帛6A The phase margin diagram of the graph, Lu BB' line is the phase margin diagram of Figure 6B. See Figure 8 for a schematic diagram of the circuit of the low-dropout linear regulator according to an embodiment of the present invention, which has a partial-series main-parallel connection. (sedal_shunt) feedback path and fast self-reactive circuit path, this circuit can accelerate the load state response and online transient response. The first-fast self-reaction circuit is composed of electric day 0 body μ丨7, μ丨8, μ丨9 , m20 and power transistor Mpwm, when the output voltage VOUT When the moment drops, the Imi9 bias current is fixed, so the drop' further causes the gate voltage of m17 to drop, and the current flowing through M17 increases, so that the gate voltage of the power transistor Mpw drops rapidly, so the power transistor Mpw provides more Current to the output load, the output voltage νουτ I·, the speed returns to the normal regulation value. The second fast self-reactive electrical path is composed of transistors Μ17 Μ18, μ19, Μ20, cm2, μ16 and power transistor Mpw. When the output voltage V0UT drops momentarily, a signal increment Δν_ is formed at the gate of the m20 via the transistors M17, M18, M19 and M20, and the signal increment is lightly coupled to the transistor of the transistor Μ16 via the compensation capacitor Cm2. The body Μ 16 thus produces a current , amount, which will increase
13 S 201224696 快速降低功率㈣Mpw的閘極電屢，因此功率電晶體 *心壓值。第二快速自我反應電路是由電晶體M"、 12 13 Ml4 Ml5、Μ16、功率電晶體MPW和電阻回授 網路RFB1、Rfb2所構成，電晶體‘、Mi2、、13 S 201224696 Fast power reduction (4) Mpw gates are repeated, so the power transistor * core pressure value. The second fast self-reaction circuit is composed of a transistor M", a 12 13 Ml4 Ml5, a Μ16, a power transistor MPW, and a resistance feedback network RFB1, Rfb2, a transistor ‘, Mi2,
m15組成-個誤差放大器，當輸出電壓ν·瞬間下降時， 誤差放大器的輸出端產生—個電壓訊號增量因此流過電 晶體Ml6的電流增加，於是使得功率電晶體MPW的閘極電 壓快速下降，因此功率電晶體、快速地提供更多電流至 輸出負載端’輸出電壓V〇UT快速回到正常穩壓值。 ▲根據上述’本發明利用快速自我反應電路加速負載暫 態變化’當負載快速變動時，快速自我反應電路形成一迴 路以減少輸出電壓的變化幅度，以及利用頻率補償電路可 以在無晶片外大電容情況下，具⑽常高_定性，從零 負載電流到設定的最大負載流都能保持最好的穩定度。 凊參閱第9圖為本發明一實施例之低壓降電壓穩壓方 法，包括.將一功率傳遞裝置的輸入與輸出兩個極點推到 迴路頻寬之外；在單增益頻率之内留τ兩個級點與一個零 點；利用一補償網路產生零點與米勒補償效應；利用一快 速自我反應電路增加訊號迴轉率；以及使用高增益之回授 放大器增加迴路增益。 根據上述，本發明係利用補償網路產生零點與米勒補 侦效應及快速自我反應電路以增加訊號迴轉率，故可加快 負載暫態響應與線上暫態響應。 201224696 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之申請專利範圍；凡其它未脫離本發明所揭示之 精神下所完成之等效改變或修飾，均應包含在下述之申請 專利範圍内。 【圖式簡單說明】 第1圖為本發明一實施例之低壓降電壓穩壓器架構示 意圖。 φ 第2圖為本發明另一實施例之低壓降電壓穩壓器架構 示意圖。 第3圖為本發明另一實施例之低壓降電壓穩壓器架構 示意圖。 第4圖為本發明另一實施例之低壓降電壓穩壓器架構 示意圖。 第5圖為本發明本發明一實施例之低壓降電壓穩壓器 電路元件示意圖。 • 第6A圖與第6B圖所示為本發明一實施例之頻率響應 示意圖。 第7圖為第6A圖與第6B圖之相位邊際示意圖。 第8圖所示為本發明一實施例之低壓降線性穩壓器電 路示意圖。 第9圖為本發明一實施例之低壓降電壓穩壓方法。 15 201224696 【主要元件符號說明】 10、 20回授電路 11、 21功率傳遞裝置 12快速自我反應電路 13、 23第二補償電路 14、 24第一補償電路 15、 25回授分壓電路 221第一快速自我反應電路 • 222第二快速自我反應電路 223第三快速自我反應電路 50誤差放大器 521第一快速自我反應電路 522第二快速自我反應電路 523第三快速自我反應電路 53第二補償電路 54第一補償電路 _ Vref、VrEF參考電壓訊號M15 is composed of an error amplifier. When the output voltage ν· drops instantaneously, the output of the error amplifier generates a voltage signal increment, so the current flowing through the transistor M16 increases, so that the gate voltage of the power transistor MPW drops rapidly. Therefore, the power transistor quickly supplies more current to the output load terminal' output voltage V〇UT quickly returns to the normal regulation value. ▲According to the above-mentioned 'Using the fast self-reaction circuit to accelerate the load transient change', when the load changes rapidly, the fast self-reaction circuit forms a loop to reduce the variation range of the output voltage, and the frequency compensation circuit can be used in the large-capacity outside the wafer. In the case, with (10) constant high _ qualitative, from zero load current to the set maximum load flow can maintain the best stability. 9 is a low voltage drop voltage voltage stabilization method according to an embodiment of the present invention, including: pushing two poles of input and output of a power transmission device to outside the loop bandwidth; leaving τ within a single gain frequency Levels and zeros; use a compensation network to generate zero and Miller compensation effects; use a fast self-reactive circuit to increase signal slew rate; and use high gain feedback amplifiers to increase loop gain. According to the above, the present invention utilizes a compensation network to generate a zero point and Miller replenishment effect and a fast self-reaction circuit to increase the signal slew rate, thereby accelerating the load transient response and the line transient response. 201224696 The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the claims of the present invention; any other equivalent changes or modifications which are not departing from the spirit of the present invention should be included. Within the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram showing the architecture of a low-dropout voltage regulator according to an embodiment of the present invention. φ Fig. 2 is a schematic diagram showing the architecture of a low-dropout voltage regulator according to another embodiment of the present invention. FIG. 3 is a schematic diagram of a low voltage drop voltage regulator architecture according to another embodiment of the present invention. Figure 4 is a schematic diagram showing the architecture of a low voltage drop voltage regulator according to another embodiment of the present invention. Fig. 5 is a schematic view showing the circuit components of the low-dropout voltage regulator according to an embodiment of the present invention. • Figs. 6A and 6B are diagrams showing the frequency response of an embodiment of the present invention. Figure 7 is a schematic diagram of the phase margins of Figures 6A and 6B. Fig. 8 is a circuit diagram showing a circuit of a low-dropout linear regulator according to an embodiment of the present invention. Figure 9 is a diagram of a low voltage drop voltage regulation method according to an embodiment of the present invention. 15 201224696 [Description of main component symbols] 10, 20 feedback circuit 11, 21 power transfer device 12 fast self-reaction circuit 13, 23 second compensation circuit 14, 24 first compensation circuit 15, 25 feedback voltage divider circuit 221 A fast self-reactive circuit • 222 second fast self-reaction circuit 223 third fast self-reaction circuit 50 error amplifier 521 first fast self-reaction circuit 522 second fast self-reaction circuit 523 third fast self-reaction circuit 53 second compensation circuit 54 First compensation circuit _ Vref, VrEF reference voltage signal
Vfeb、VfB回授電壓訊號 Vctrl ' VCTRL 控制訊號 V〇ut、V〇UT輸出電壓 Αι、A2、A3、A4、A5、Αβ、A7 放大益 Cmi、Cm2、Cm3 電容 Μι〜M20電晶體 Mpw功率電晶體 16 201224696Vfeb, VfB feedback voltage signal Vctrl ' VCTRL control signal V〇ut, V〇UT output voltage Αι, A2, A3, A4, A5, Αβ, A7 amplification benefits Cmi, Cm2, Cm3 capacitance Μι~M20 transistor Mpw power Crystal 16 201224696
Rml、RfBI、RfBI 電阻 nCTRL ' nOUT ' nCOM2 ' nCOMl 節點 P,、P2、P3 極點 VlN輸入電壓 Vdd電源訊號 S91 —S95低壓降電壓穩壓方法之步驟Rml, RfBI, RfBI resistance nCTRL 'nOUT 'nCOM2 ' nCOMl node P, P2, P3 pole VlN input voltage Vdd power signal S91 - S95 low voltage drop voltage regulation method steps
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