TW201203248A - Nonvolatile memory device having trasistor connected in parallel with resistance switching device - Google Patents

Abstract

A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in parallel with a resistance switching device. The transistor is switchable between a plurality of different threshold voltages associated with respective memory states. The resistance switching device is configured to be switchable between a plurality of different resistances associated with respective memory states.

Description

201203248 i«/8Uli5 32646twf.doc/I VI. Description of the invention: [Technical field of invention] Combined use as non-volatile memory guide: suitable for [previous technique] Recall:: can be = installed = commonly found in the system _ In the computer and other called * is called computer memory can be =::::=:= to _ bit: m power == have recalled (dram) computer memory "ti power lost the stored data. In contrast, non-volatile electricity == is an example of a non-volatile electronic memory device that can still be used in the absence of an external power source. For example, a camera if the device is called a memory card. Retained two: like 'and even when the memory card is removed from surgery' still * the system using electronic memory devices is getting stronger and stronger, on the data storage 201203248

The demand for J2646twf.doc/I r^oviu capacity is increasing at the same time. For example, if the brain and the software have a large number of images in the _ access record, the camera produces a larger picture, the case and the shadow (4) case, and the ability to survive can accept the money. Therefore, the electronic record (4): only increasing the capacity is not enough, usually the same ideal: holding or even reducing the memory device 换 In other words, the other trend is to increase - the size of the bribe storage capacity, that is, increase the bit density Another consideration is cost. For example, : When the density of the element is increased, the electronic code is maintained or reduced. In other words, the ideal situation is to reduce the cost of the New Zealand dollar (each bit = become a further one, and another - a test # is related to performance, such as providing faster storage and faster access to data stored on the electronic memory device. There is a way to provide increased bit density and reduce the size of individual memory cells. For example, to improve the manufacturing process, to form the structure of ^, so as to allow the creation of smaller memory cells. However, there are inferences on the 22nd The forecast points out that using this method in the future will increase the cost of the bit, 1 because after a certain time point, the process cost increase of the money will start faster than the memory-unit-reduction rate. Therefore, the ideal situation In order to find an alternative method to increase the position and degree of the electronic memory device. [Description of the Invention] The following describes the memory device and the party associated with the memory device 201203248

115 32646twf.doc/I method. According to one aspect of the present disclosure, the present invention provides a memory device comprising an array having a plurality of memory cells, wherein each memory cell includes a transistor and a resistance value switching device in parallel with the transistor. Each of the transistor and resistance value switching devices has the ability to independently store one or more bits of data. The transistor includes a first end, a second end and a gate terminal, and the transistor is used to switch between a plurality of different threshold voltages respectively associated with the multi-memory. The resistor value is clamped in parallel with the transistor to connect the resistance value switching device to the first end and the second end of the transistor. The resistance value switching means is for switching between a plurality of different resistance values respectively associated with the multi-memory state. According to another aspect of the present disclosure, the present invention provides a memory device including a plurality of bit lines, a plurality of word lines, and a first memory string including a first memory group. And a second memory string including a second memory group and a common source line. The first memory bank and the second memory string are connected to one common source line and respectively connected to a plurality of word lines. The plurality of character lines are respectively connected to the memory cells of the first memory group and the memory cells of the memory group respectively connected to the second memory group. Each of the memory cells includes a transistor and a resistance value switching device in parallel with the transistor. Each of the transistor and resistance value switching devices has the ability to independently store one or more bits of data. The first electrical body includes a first end, a second end and a gate terminal. The first transistor is used to connect the first resistance value switching device between the plurality of different threshold voltages associated with the plurality of S-resonance states and the first transistor, and the second transistor; 2 201203248 P980115 32646twf.d 〇c/l resistance switching device is connected to the first-electro-crystal (4): ==================== According to a further aspect of the present disclosure, the present invention provides a method for reading a cell, the method The memory cell for reading and writing the resistor-device connected in parallel with the transistor has the capability of being independent of each of the resistor switching devices. For example, in accordance with one aspect of the present disclosure, a critical electrical circuit comprising a transistor for making the memory cell, wherein the transistor is used to switch between a plurality of critical electrical dusts associated with a plurality of memory states, respectively. The reading method may further include a resistance value of the memory resistance switching, wherein the resistance value of the resistance switching device is used to switch between the plurality of resistance values and the multi-resistance state_ These and the characteristics of the other, difficult to implement the implementation of the following Naxiang towel. The exemplary embodiments of the present invention are described in detail below, and the features, aspects, and embodiments are described in detail with reference to the accompanying drawings. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b; δ has been used to denote the same or similar elements. 1 is a block diagram of a memory array 100 in accordance with an exemplary embodiment of the present disclosure. The memory array 1〇〇 can include a plurality of memory cells

201203248 P980115 32646twf.doc/I 102, a plurality of bit lines BL1-BLm, a plurality of word lines WL1-WLn, a serial selection line SSL, a ground selection line GSL and a common source line SL. The memory array 100 can be configured such that a plurality of memory cells 1 〇 2 are arranged in a memory array having mxn memory cells 1 〇 2, where m and η represent natural numbers, respectively. More precisely, the memory array can be configured such that a plurality of memory cells 102 are arranged in a plurality of memory strings MS1-MSm. Each of the memory strings MS includes a respective tandem selection transistor SST, a group of respective n memory cells 102, and a respective ground selection transistor GST. The memory strings MSI to MSm are connected to the bit lines BL1 to BLm, respectively. The memory strings MSI to MSm are connected in series to the common source line SL. Fig. 2 is a schematic diagram of a memory string MSi as an example which can be used as any of the memory strings MS1 to MSm presented in Fig. 1. The memory string MSi includes a serial selection transistor SST, first to fourth memory cells 110a to i2d, and a ground selection line GSL. The serial selection transistor SST, the first to fourth memory cells i〇2a to 1〇2d, and the ground selection line GSL' are connected in series between the bit line BLi and the common source line SL. The memory string MSi described above includes four memory cells i〇2a~l〇2d, but it may be preferable to include the remaining memory cells 102. The first to fourth memory cells 102a to 102d respectively include resistance value switching devices 111a to 11D and transistors n2a to 112d. The gate terminal of the serial selection transistor SST is coupled to the serial select line SSL. The source terminal of the serial selection transistor SST is coupled to the bit line bu. The 汲 terminal of the tandem selection transistor SST is coupled to the first memory cell 102a. 201203248

P980115 32646twf.doc/I Ground Select Transistor GST GSL. Ground selection transistor GST 102d. Ground selection transistor GST SL. The gate terminal connected to the ground terminal is connected to the source terminal of the fourth memory cell to the common source line. Fig. 3 is a schematic diagram showing the memory cell 1〇2 according to an embodiment of the present disclosure. Memory cells 102a-102d may be configured as shown in FIG. Memory cell 102 includes a plurality of memory cells in parallel. In this embodiment, the memory cell 110 includes a resistance value switching device 110 for use as a first body unit, and a floating gate transistor 112 for use as a second memory unit, and The floating hybrid crystal 112 may be a floating crystal, an -N transistor, a p-type transistor or a (Fin-FET). The transistor 112 can be used such that its gate is connected to one word line WL. The source terminal of the transistor in is connected to the bit line electrocardior 112 by a tandem selection transistor Mi and any intervening memory cell 1G2 as shown in FIG. 2, and the ground selection transistor GST is as shown in FIG. Any of the memory cells 1() 2 in which it is connected to the common source line. The source terminal and the drain terminal of the transistor 112 are also connected to the positive and negative ends of the resistance value switching device 110 such that the transistor 112 is connected in parallel with the resistance value switching device 110. In some embodiments, the resistance value switching device 11 can be as shown in Figure 3 above the transistor 112 and the word line WL. In these embodiments, the memory cell 102 may first form the transistor 112 and the word line WL, and then form a resistance value switching device over the transistor 112 and the word line WL. The transistor 112 may be a floating gate. Crystal, an N-type electric crystal 201203248

Γ> 〇υχ 1 j 32646 twf.doc/I body, a p-type transistor or a fin field effect transistor (Fin_FET), which is used to make the threshold voltage vt of the transistor 112 between two or more values Change 'the exact value of the threshold voltage Vt is related to multiple memory states, respectively. For example, 'the transistor 112 can be a single-element cell (SLC) floating transistor, a multi-level cell (Muiti_ievei ceii, MLC) floating transistor 'a nano crystal fast lightning crystal (nan〇_crystaj flash transistor) Or a nitride trap device. φ Thus, the transistor 112 can be used to store multiple Vt states in one or more locations. For example, in some embodiments, transistor 112 can be used as a 1-bit memory device that can be programmed into any of two distinct threshold voltages Vt. Such an embodiment may include an embodiment of an SLC floating transistor. Further, for example, in some embodiments, the transistor 112 may be used as a 2-bit memory that can be programmed into any of four distinct threshold voltages Vt. Device. Such an embodiment may include an embodiment of an MLC floating transistor. Embodiments of the transistor 112 including a floating gate device can be programmed by hot electron injection techniques and electronically penetrated by F〇wler-Nordheim (FN) (electron tunneling) technology is cleared. The resistance value switching device 110 can be used such that the resistance value of the resistance value switching device 11() can be changed between a plurality of resistance values, wherein the exact values of the resistance values are respectively associated with a plurality of memory states. For example, the transistor 112 can be a resistive memory device as described in U.S. Patent No. 7,524,722, the disclosure of which is incorporated herein by reference. Thus, in some embodiments, memory cell 102 can be used to store one or 201203248

I2646twf.doc/I multiple bits, such as 'in some embodiments, the transistor ιΐ2 can switch between two memory states and the resistance value switching device nG can switch between two memory states, so that The memory cell 1〇2 is a device capable of having a total of four memory cells. As another example, in some embodiments, 'the transistor 112 can be switched between four states of the dragon and the resistance switching device UG can be in the domain between the four states, and the memory cell 102 is capable of A 4-bit memory device with a total of sixteen memory states. Still other embodiments may include that the transistor 112 may be configured to switch between selected N1 threshold voltages associated with a plurality of 5 memory states, and the resistance value switching device 11() may be in plurality The memory state is switched between the selected N2 resistance values, so that the memory cell 1〇2 thus becomes a memory device capable of having a total of N1+N2 memory states. Fig. 4A is a view showing a resistance value switching device 11a according to some embodiments of the resistance value switching device ι1. The resistance value switching device 110a includes a substrate 122, an inter-wire dielectric layer (IMD) layer 124, a first electrode layer 126, an oxidized crane layer 128, and a first dielectric layer 130a. A second dielectric layer 30b> and a second electrode layer 134. The substrate 122 can be a stone substrate and the IMD layer 124 can be an oxide layer or other electrically insulating layer formed on the substrate 122 using conventional techniques such as chemicai vapor deposition (CVD) techniques. The first electrode 126 can be formed by using titanium nitride (TiN) and is deposited by a CVD process or physical vapor deposition (physical vapor 201203248).

The r 32646 twf.doc/I deposition, PVD) process is set on the IMD layer i24. The material of the first electrode 126 may alternatively comprise a doped polysilicon (doped such as 111 (: 〇 11) 'Ming' steel or nitride button (1 shirt & 11111111 1 (^, 1 ^) 〇 tungsten oxide The layer 128 is formed on the first electrode 126. The first dielectric layer 130a and the second dielectric layer i30b are adjacent to the tungsten oxide layer 128, and are also formed on the first electrode 126. The first dielectric layer 13A and The second dielectric layer 13〇b may comprise, for example, germanium dioxide (Si〇2), tantalum nitride (Si3N4) or a similar material of φ. The insulating material 6 comprises a tungsten oxide layer 128, a first dielectric layer 130a and a second dielectric layer. The structure of the electrical layer 130b can be formed by first forming the dielectric layer 130 as a continuous dielectric layer over the first electrode 126 by, for example, a CVD process. [Next] by lithography or etching Etching (etching) to remove a portion of the continuous dielectric layer to create a space between the first dielectric layer 13A and the second dielectric layer 130b. Next, at the first dielectric layer 130a and Forming an oxidized crane layer in the crucible between the two dielectric layers mb More precisely, the tungsten oxide layer 128 may first deposit tungsten in the first dielectric layer 130a and In the interval between the dielectric layers of 13%, an oxygenation process is then performed to oxidize the crane. For example, a thermal oxidation process can be used to diffuse the oxidation process to most or all of the tungsten layer to form an oxide layer. 128. The second electrode layer 134 can be disposed on the oxidized dummy layer 128 by a CVD process or PVD, and the second electrode layer 134 can also extend to the first dielectric layer and the second dielectric layer. Layer i swim ^ The structure of the two electrode layer 134 may include a doped multi-tetra (poly) polysihcon), aluminum, copper or nitride button. Complete oxidation of the oxidized crane layer 128 will result in the formation of an adjustable resistance 201203248

The first interface area 138 and the second interface area i4 of the -------j^646twf.doc/I value. Figure 4B shows the individual locations of the first interface region 138 and the second interface region 14 . The first interface region 138 includes a region between the interface of the first electrode 126 and the tungsten oxide layer 128. The second interface region 140 includes a region in the interface between the second electrode layer 134 and the oxide layer 128. 5A-5E illustrate the resistance switching characteristics of the symmetric two-state embodiment of the resistance value switching device 110a of Figs. 4A and 4B. That is, in the present embodiment, the resistance value switching device 110a includes two interface regions 138, 140, each of which includes two resistance values (memory states) and each interface region is at least substantially symmetrical to each other. Alternative embodiments, including those described herein, may include embodiments that are asymmetric or/and each interface region includes more than two resistance values. Passing through the tungsten oxide layer 128 and the first electrode 126 and the second The resistance value between the electrodes 134 can be adjusted between the two resistance values R1, R2. The resistance switching behavior of the resistance value switching device 110a can occur in the first interface region 138 or the second interface region 140. As further described in more detail, a voltage pulse can be used to select an interface region between the first interface region 138 or the second interface region 14A to control the switching behavior of the resistance value switching device 110a. This is important. Because the voltage level required to switch the resistance value from R1 to R2 will depend on the current interface being controlled by the first interface region 138 or the second interface region 14 Switching behavior of switching device 11a, and vice versa. Returning to Figure 5A, Figure 5A shows 12 of the present embodiment of the resistance value switching device u〇a when the second interface region 14 is controlling the resistance switching characteristic. 201203248

P980115 32646twf.doc/I

Resistance switching characteristics. Here, the resistance value switching means U?a can be controlled to have a reset resistance value R1 or a set resistance value R2. If the resistance value of the resistance value switching device 11a is R1, a negative voltage V2 can be applied to the resistance value switching device 110a between the voltage supply terminal and the ground as shown in FIG. 4B to reduce it by R1. Resistance value ^ R2. Similarly, if the resistance value of the resistance value switching device u〇a is R1, a positive voltage V4 may be applied to the resistance value switching device 11a between the voltage supply terminal and the ground as indicated by @4B. , due to its resistance value to ία. 9 is a flow chart for controlling the switching from the second interface region 14A to the first region 138. More specifically, the resistance switching means for switching the resistance switching characteristic of the present embodiment to the first interface region 138 can be switched by a negative voltage applied to the resistance switching device 11Ga. The result of switching in ® 5B is shown in Figure %, where the first interface ^2 currently controls the resistance value switching device to hide the resistance cut of this embodiment = the behavior described in Figure 5C can be the behavior in Figure 5A Here, it can be observed that when the first interface area 138 is being controlled, the resistance switching characteristic of the present embodiment of the switching device 110a, and the difference of the t === of the resistance value switching device when the domain (10) is being controlled. At present, in the figure, when the voltage is applied, the resistance value is reduced to the phantom by the positive voltage V3 applied to the resistance value switching device 11a, and is applied to the resistance value switching device (10). - a negative voltage V! may 13 201203248 - increase the resistance value from R2 to ri β. Figure 5D depicts the flow of switching from the first interface region 138 to the second interface region Μ0. More precisely, the control of the resistance switching characteristic of the present embodiment of the resistance value switching device (10) & can be switched from the first interface region 138 to the second interface by applying a positive voltage ν4 to the resistance value switching device 11Ga. Area 140. The result of the switching in Fig. 5D is as shown in Fig. 5E, which is the same as the figure, wherein the second interface region 14G re-controls the resistance switching characteristic of the present embodiment of the resistance value switching device_. Therefore, the 'resistance value switching device 11Ga can be set to one of four states' and the four states can be used as four memory states: (1) the first interface control and the resistance value = R1 (state, "-,,"); (2) the first interface control and resistance value = R2 (state '",", (2) the second interface control and resistance value = illusion (like 'R^eset'); and (4) the second interface control and Resistance value =] 12 (state Rset). It is quite difficult to distinguish between state g and Rset; ^ However, the state and Rreset can be reliably distinguished from each other. 'In addition, one of the states and Rreset can be reliably The ground is clearly distinguished from RSET. Therefore, according to the present embodiment, the resistance value is switched Hn〇a ^ ex £ jx ^ ^ (1 )Rreset ; (2) Rreset; A (3) RSET ^

A three-state memory device for Rset. The reading flow of the resistance value switching means U()a according to an embodiment of the three-state memory device will be described below with reference to Figs. 6 and 7. Fig. 6 shows the _ representation of the relationship between the memory state of the resistance value switching device 110a and the applied voltage, and Fig. 7 shows a flow chart of the reading flow. 201203248

115 32646twf.doc/I

First, in block 200, the resistance value switching device u〇a has been programmed into one of the memory states (1) EEE§gx; (2) RRESET; and (3) the guard gET or rset. The remainder of this flow allows reading of the resistance value switching means ll 〇 a to determine which memory state is written to the resistance value switching 置 〇 a. In block 202, the resistance of the resistance value switching device 11A is determined as shown in FIG. 6. Regardless of whether one of the first interface region 138 and the second interface region 14 is under control, the resistance value can be expected to be a comparison. High resistance value SeiseI / Rreset or a lower resistance value & / RSET. If a lower resistance value E group Γ / Rset' is detected, the flow ends at block 204 and it is determined that the memory state of the resistance value switching device 110a is this extension i/rset. Conversely, if a higher resistance value / Rreset is detected, the process continues to distinguish between the memory state fesEL and the memory state by determining that the interface area 138 and the second interface area 140 are currently being determined. - In control, it is possible to distinguish between the memory state and the memory state Rreset. In the flow shown in FIG. 7, since the behavior of the resistance value switching means 11Ga may depend on the fact that the first interface region (3) and the second interface region 14G are different in control, it is possible to apply one (four) V__ To the real society to judge the silk. The voltage level that can be used as the voltage vDETERMINE is a voltage level between Figure 5A and Figure. Before the square 卩 resistance value level 疋 position (for example, in the figure μ to the figure, it can be known that when the money Vdetermine is applied to the resistance value switching device Π0-a wide resistance value switching device brain will depend on the current One of the first-face area 138 and the second interface area 14 is in control 15 201203248

r 7〇ν ιυ J2646twf.doc/I is different. For example, according to Fig. 5A, if it is currently controlled by the second interface region 14A, the applied voltage VDETERMINE does not change the resistance value of the resistance value switching device lla from R1. On the other hand, according to Fig. 5D, as previously controlled by the first interface region 138, the applied voltage VDEra_ changes the resistance value of the resistance value switching device 11a from R1 to R2. Therefore, in block 206, a voltage is applied to the resistance value switching device 110a' and then in block 208, the resistance value of the resistance value switching device 110a is measured. If a higher resistance value / Rreset is still measured, it can be determined that the second interface region 14 is currently being controlled because the resistance value is not affected by the applied voltage Vdetomine. Therefore, the flow ends in block 210, and it is determined that the s-resonance state of the resistance value switching device u〇a is the Rreset memory state. Conversely, if a lower resistance value of I/Rset' is detected, it can be determined that it was previously controlled by the first interface region 138 because the resistance value was once changed by the applied voltage Vdeto. It is worth noting in this case that the applied voltage Vdetermine will control switching from the first interface region 138 to the second interface region 140. Therefore, the flow continues to block 212 where the switching control transitions back to the first interface region 138 so that the resistance value of the resistance value switching device ll 〇 a is not disturbed by the current reading process. Then, the flow ends at block 214, and it is determined that the memory state of the resistance value switching means u 〇 a is the Eredet memory state. 8 to 10 illustrate the resistance switching characteristics of an alternative embodiment of the resistance value switching device u〇a. More precisely, FIG. 8 illustrates the switching characteristics of the symmetric three-state embodiment of the resistance value switching device 110a; FIG. 9 depicts 201203248

* / ... ~ 32646twf.doc / I switching characteristics of the asymmetric two-state embodiment of the resistance value switching device UOa; Figure 10 shows the switching of the asymmetric two-state / three-state embodiment of the resistance value switching device 11A characteristic. These and other similar alternative embodiments can be made by changing the composition of the first electrode 126 and the second electrode 134 or/and the composition of the tungsten oxide layer 128. For example, when the first electrode 126 and the second electrode 134 are composed of titanium nitride, the resistance value associated with the r^set or the embossed state can be increased or decreased according to the nitrogen element content of the titanium nitride. Similarly, the resistance value associated with the state of the orthodontic can be increased or decreased depending on the oxygen element content of the tungsten oxide layer 128. The symmetry tristate of the resistance value switching device u〇a as shown in Fig. 8 includes switching characteristics of two kinds of resistance values (memory state) in each interface region 138/interface region 14A. When controlled by the first interface area 138, these memory states are controlled by the second interface area 140. These memory states are Rset, printed and Rresed. It is quite difficult to distinguish the state ^ from the lamp. However, the state ' RRESET1 and RRESm can be reliably/cut out from each other. In addition, each of the states 'ESSIi, Rreset2' Rreseti and RRESm can be reliably distinguished from the state and RSET. Therefore, according to the present embodiment, the resistance value switching device 110a can be used as a five-state memory device having (1) Ern; (2); (3) Rreseti; (4) RREsm; and (5); or Rset. . The switching characteristic of the asymmetric state embodiment of the resistance value switching device 11A as shown in FIG. 9 includes two resistance values (remembering the dragon state) in each interface region 138/interface region, wherein the resistance value is obviously not ^ 17 201203248

Ryeu i i 3 32646twf.doc/I is at the resistance value ^ESET. When controlled by the first interface region 138, these memory states are the same as Rreset0 when controlled by the second interface region 140, and these memory states are RSET AND. It is quite difficult to distinguish the state clearly from rset. However, the state and Rreset can be reliably distinguished from each other. In addition, each of the state ^ and Rreset can be reliably distinguished from the state gggL and rset. Therefore, according to the present embodiment, the resistance value switching means 11a can be set as a type having (1)

Eee§ei; (2) RreSET; and (3) this extension! Or a tri-state memory device in a state such as RSET. ~ Figure 11 is a flow chart of the read resistance value switching means 110a shown in green according to the asymmetrical embodiment of Figure 9. First, at block 3, the resistance value switching device 110a has been programmed into a memory state (1) Rreset; (2)

EggSEI, and one of (3) or rset. The remainder of the flow will allow reading of the resistance value switching means 11a to determine which memory state is written to the resistance value switching means 11a, as shown in Figure 9, regardless of the current interface area 138 and One of the second interface regions 14A controls one of the first resistance value g^SET, the second resistance value Rreset or the third resistance value Rsu/Rset with the expected resistance value. If a resistance value of 3⁄4iI/RsET is detected, then the flow ends at block 304 and it is determined that the memory state of the resistance value switching device 110a is Rset / Rset » if the resistance value Rreset' is detected, the flow ends at block 306. It is also determined that the memory state of the resistance value switching device 11 〇a is Rreset. If a resistance value is detected, then the flow ends at block 308 and it is determined that the memory state of the resistance value switching device 11 & is Er £ SET.

201203248 P980115 32646twf.doc/I Referring back to the figure, the switching characteristics of the asymmetry/three-state embodiment of the resistance value switching device 11A include two types of electrical shouting (memory verification) when associated with the first interface region 138. And when associated with the second interface region 14A, includes three resistance values (memory shape • when controlled by the first interface region 138, these memory states are ^ and stomach. When controlled by the second interface region 140, These memory states are Rset, and

Rreseh. It is quite difficult to distinguish between the state & RSET. However, the state Rset, Rreseti and RreSET2 can be reliably distinguished from each other. In addition, each of the states Rset, Rreseti and Rreset2 can be reliably distinguished from the states Esil and Rset. Therefore, according to the present embodiment, the resistance value switching means U〇a can be set as one type having

Rreseti; (3) Rreset2; and (4) ^ or rset state of the four-state memory device. ~ Fig. 12 is a schematic diagram of the resistance value switching device 110b shown in accordance with several embodiments of the resistance value switching device ii〇a. The resistance value switching device 11A may include a programmable metallization unit (PMC) 400. More specifically, the resistance value switching device 110b may include a substrate 402, an IMD layer 404, and a first electrode. A layer 406, a conductive plug layer 408, a first dielectric layer 410, a second dielectric layer 412, a solid electrolyte layer 414, and a second electrode layer 416. Substrate 402 can be a stone substrate, and IMD layer 404 can be an oxide layer or other electrically insulating layer formed on substrate 402 using conventional techniques, such as CVD techniques. 19 201203248

ryeuiiD 32646twf.doc/I The first electrode layer 406 T is formed by nitriding and is disposed in the IMD layer 4〇4 by a .cvd process or a PVD process. The material of the first electrode layer 4 〇 6 may alternatively comprise doped (tetra), indium, copper or gasified nucleus. A conductive plug layer 408 is formed over the first electrode layer 406, and the first dielectric layer 410 and the second dielectric layer 412 are adjacent to the conductive plug layer and are also formed on the first electrode layer 406. The first dielectric layer 41A and the second dielectric layer 412 are made of a silicon nitride or a similar insulating material. = The embolic plug layer 408 can include a crane. The first dielectric layer 41 〇 and the second dielectric layer may be formed on the drain layer 406 by first utilizing, for example, a meridian layer 406, and the layer 412 is formed as a continuous dielectric layer to include a conductive plug: 08, The structure of the first dielectric layer 41 and the second dielectric layer 412. Next, an injury of the continuous dielectric layer is removed by, for example, lithography or engraving techniques: to create between the first dielectric layer 41 and the second dielectric layer 412. The first dielectric layer 410 and the second dielectric layer 412 are exposed to the conductive plug layer 408. More precisely, the conductive plug layer 408 can be formed by the deposition of a material of W μ $ 4 〇 8 between the first dielectric layer 410 and the second dielectric layer $, and the electrolyte layer 414 can be deposited by The conductive plug layer 4 (10) may be extended to the first dielectric layer 410 and the layered solid electrolyte layer 414 may include transition metal oxygen, a transition metal oxide comprising at least one medium sulfide element. Example: The electrolyte layer 414 may contain sulfidation/silver or erg/silver. The electrode layer 416 can be formed as an oxidizable electrode by being deposited on the solid electrolyte layer 414. Second electrode

201203248 r^oui i j 32646twf.doc/I ^ 416 may include an oxidizable electrode material, for example, silver (Zn). Ding 蕈 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( The full voltage and current levels can be compared with Figure 13 =: Q. Therefore, the device _ may not be programmed at the beginning; 16 and a lower voltage is applied to the FET layer, and before the second: =2= or __, no current will pass, In the illustrated example, the threshold voltage is set to, for example, approximately g. 7 (frequency s). When the voltage applied by the device exceeds the critical limit Vl, the current is 1w, and can be limited by the stylized circuit (for example, limit). In an embodiment, the voltage may be reduced to 〇V:=amps, and thus the completion of the electric-voltage two=峨 reading to the cell state, a sensing (VS) may be applied to the resistance value switching device u 〇b. Sense voltage

Set the critical power a V1. In the fairness of the clear, the sense light vs Z is 'for example, about G. 3 volts. When the resistance value switching means 11% is programmed (i.e., 'SET') as described above and the sensing · % switching means 11Gb is applied, the operating current Iw may be switched by the resistance value.

201203248 1 32646twf.doc/I 110 If the resistance value switching device 11Gb is not programmed (ie, RESET)', when the sensing voltage vs is applied, little or no current will pass through the resistance value switching device 110b. In the embodiment, a lower voltage can be applied, for example, a negative voltage changing device u clears or resets the stylized state. The second = medium 'reset threshold voltage can be, for example, approximately _ 〇 3 volts. When applying the reset threshold money to the resistance value switching device 11%, the negative current may pass through the resistance device 11%. When the negative voltage drop is lower than the reset threshold voltage, the current may stop flowing (that is, after the ampere is applied, the resistance value switching device 11Gb may have a program, after applying the reset threshold voltage to the resistance device. The high voltage of the operation is such that the value stored in the resistance value switching device 11Gb is cleared or reset. Fig. 14 is a resistance value switching device shown in several embodiments of the resistance value switching device 110c. The resistance value switching device 110c includes a dual PMC structure. The resistance value switching device 11Qe includes a substrate 452, an IMD layer 45, a first electrode layer 456, a conductive plug layer 458, and a first The electric layer 460, the second dielectric layer 462, the first solid-state electrolyte layer 464' - the second electrode layer 466, the second second solid electrolyte layer 468 and the third solid electrolyte layer 47A. It is a germanium substrate, and the IMD layer 454 can be an oxide layer or other electrically insulating layer formed on the substrate 452 using conventional techniques, such as CVD techniques.

The first electrode layer 456 can be formed of titanium nitride and by CVD 22

201203248 ^»υι〇 32646twf.doc/I The process or PVD process is disposed on the IMD layer 454. The material of the first electrode layer 456 may alternatively comprise doped polysilicon, aluminum, copper or tantalum nitride. A conductive plug layer 458 is formed over the first electrode layer 456, and a first dielectric layer 460 and a second dielectric layer 462 are adjacent to the conductive plug layer 458 and are also formed on the first electrode layer 456. The first dielectric layer 460 and the second dielectric layer 462 may include, for example, hafnium oxide, tantalum nitride, or the like. The embolic plug layer 458 can include a crane. The first dielectric layer 460 and the second dielectric can be formed on the first electrode layer 456 by first using, for example, a CVD process: 乂:! A continuous dielectric layer' is formed to include a conductive plug, such as a structure of a second dielectric layer and a second dielectric layer 462. Connect the - part to remove the interval of the continuous dielectric layer at the !===. Next, a material 458 of conductive Sa and a first conductive layer 462 deposited with a conductive plug layer 458 is formed in the space between the reservoir layers 62. Two:: say ' can be made by the interval between the layers ^ ^ in the first dielectric layer _ and the second dielectric flute ml into a conductive plug layer 458. The first solid electrolyte layer 4 W is formed. The solid state is in the conductive plug layer 460 and the second dielectric layer 462. The layer 464 can extend to the first dielectric interlayer oxide, or it can comprise a transition metal. For example, ϋ state electrolysis f / transition metal oxidation / silver of two vulcanization elements. 'may contain barium sulfide/silver or strontium selenide. The first electrode layer 466 can be formed by 464. The first electrolyte layer 466 may be an oxidizable electrode. 23rd

201203248 Fy»Ull3 32646twf.doc/I The two electrode layer 466 may comprise an oxidizable electrode material such as silver, copper, zinc. The first solid electrolyte layer 468 can be formed by being deposited on the second electrode layer 466. The second solid electrolyte layer 咐 may include a transition metal oxide ' or a transition metal oxide containing at least a sulfurized element. For example, the 'second solid electrolyte layer 468 may contain a sulfidation/defect/silver. The third solid electrolyte layer 47G can be formed by being deposited on the second electrode layer 466. The third solid electrolyte layer may also contain a conductive material or a semiconductor material such as titanium nitride. The embodiment of the resistance value switching device (10) shown in Fig. 14 forms a dual PMC structure which includes an upper pMC structure 472 and a lower PMC structure 474. Each of the upper PMC structure 472 and the lower PMC structure 474 is stylized. For the ride to the resistance _ two memory states. The memory state of the upper PMC structure 472 includes the Rreset and RSET memory states, which correspond to relatively high resistance values and lower resistance values, respectively. The memory state of the lower acid structure 474 includes the & ESEL and memory states, which correspond to relatively high resistance values and lower resistance values, respectively. In some implementations, the associated electrical P is valued to be substantially the same as the electrical PJL value associated with Rreset. However, in other embodiments, the resistance values associated with the ruler and the selected red are respectively Different from each other. Similarly, in some embodiments, the resistance value associated with Rset may be substantially equal to the phase _ lightning 佶, while in other embodiments 'the resistance values associated with rset and s red, respectively, may be ^匕24 201203248

P980115 32646twf.doc/I is not the same. Figs. 15A, 15B and 16 are graphs showing the resistance switching characteristics of the symmetric double PMC embodiment of the resistance value switching device 11A. More specifically, FIG. 15A illustrates the resistance switching characteristics of the upper PMC structure 472, FIG. MB illustrates the resistance switching characteristics of the lower PMC structure 474, and FIG. 16 illustrates the double formed by the upper PMC structure 472 and the lower pMC structure 474. Resistance switching characteristics of a symmetric embodiment of a PMC structure. • As shown in Figure 15A, the positive voltage VS1 through the upper PMC structure 472 causes the resistance of the upper PMC structure 472 to switch to the resistance value associated with the memory state Rreset. The negative voltage Vs:2 through the upper PMC structure 472 causes the resistance of the upper PMC structure 472 to switch to the resistance value associated with the memory state Rset. As shown in Figure 15B, a positive voltage VS3 through the lower PMC structure 474 causes the resistance of the lower PMC structure 474 to switch to a resistance value associated with the memory state Rreset. The negative voltage Vs* passing through the lower PMC structure 474 causes the resistance of the lower PMC structure 474 to be switched to the (4) resistance value of the memory state Rset. The combination of the symmetrical embodiments of the upper PMC structure 472 and the lower P MC structure 474 as shown in FIGS. 15A and 15B produces a memory device capable of having four memory states A as shown in FIG. D. Each of the memory states A to D is associated with the sum of the resistance values of the memory states of the upper PMC structure 472 and the lower PMC structure 474, respectively. The memory state A occurs when the upper PMC structure 472 has a resistance value Rset associated with the memory state, and the lower pMC structure 474 has a memory 25 201203248

r>〇viu i2646twf.doc/I. The body state-related resistance value EreSET is such that the overall resistance value of the double P C Μ structure is 6 in the state of the memory, Rset+Rrrsp.t. The memory state D occurs when the upper PMC structure 472 has a resistance value Rreset ' associated with the memory state and the lower PMC structure 474 has a resistance value associated with the memory state such that the overall resistance value of the dual PCM structure is in the memory state d Esu+Rreset. Both the memory state B and the memory state C occur when the upper PMC structure 472 has a resistance value Rreset' associated with the memory state and the lower PMC structure 474 has a resistance value EgESH associated with the memory state, such that the entire dual PCM structure The resistance value is in the memory state B and the buddy state C is Rreset+Rreset. Therefore, it is quite difficult to clearly distinguish between the memory state B and the memory state C, so the dual PMC structure of the resistance value switching device 110c can be implemented as a three-state memory device having the memory states A, B (or C) and D. . Referring to Fig. 17, a reading flow of the resistance value switching means 11c can be described based on an embodiment of the three-state symmetric dual pmc memory device, and a flow chart of the reading flow is shown. First, in block 500, the memory switching device u0c has been programmed into one of the memory states A' B/C or D. The remainder of this flow will allow the memory switching device l1〇c to be read to determine which state is written to the memory switching device 110c. In block 5〇2, the resistance value of the memory switching device 110c is determined. In the present symmetrical embodiment, the resistance value associated with Rset is substantially equal to the resistance value associated with RSET, and the resistance value associated with Rreset is substantially equal to the resistance value associated with this office. Therefore, it can be expected that the resistance value of the memory switching device 11〇c is a 26

201203248 ryeu 115 32646twf.doc/I The resistance value R = Rreset + Rreset or a lower resistance value R = (Rreset + Egii) or (Rset + Rreset). If Y 贞 detects a higher resistance value R = Rreset + Rreset ', then the flow ends at block 504 and it is determined that the memory state of the memory switching device 110c is the memory state B/CffiRESET + Rreset). Conversely, if a lower resistance value is detected, then the flow continues to make a clear distinction between memory state A (RSET + - and D (RreSET + &). Contact 'in block 506' applies voltage In the memory switching device 110c, the resistance value of the memory switching device 110c is then measured in block 508. In this embodiment, the selection is made by ¥7£1^£ The voltage is such that if the memory state is memory state A, the upper PMC structure 472 will be switched from RSET to the (10) lamp' but will not cause any change when the memory state is the memory state D. The voltage of ^_ is a voltage between VS1# VS3. The voltage of 乂_Teng can alternatively be selected between VS2 and Vs#, so that if the memory state is memory state D This causes the upper pMC structure 472 to switch from, but does not cause any change when the memory state is the memory state A. If the lower resistance value is measured in block 508 is equal to Rreset + (and is also equal to rset + to ^) 'You can determine the memory state as the memory state D, because the resistance value and It is changed by the applied voltage ν〇. Therefore, the flow ends at block 51〇, and it is determined that the memory state of the memory switching device UOc is the memory state D. Conversely, if measured in block 508 Compared with the local resistance value, Wang Wang Ding + ^ Zheng Ding, then the memory state 27 201203248

P980115 32646twf.doc/I is the memory state A because the resistance value was once changed by the applied voltage VDETCRMINE. It is worth mentioning in this case that the applied voltage VDE7ERMINE switches the resistance of the upper PMC structure 472 from Rset to Rreset. Thus, the flow continues with block 512 where the resistance of the upper pMc structure 472 is switched back to Rset (e.g., by applying a voltage VS2) such that the memory state of the memory switching device 110c is not disturbed by the current read state. Then, the flow ends at block 514, and it is determined that the memory state of the memory switching device 111c is the memory state A.

18 to 20 are graphs showing the resistance switching characteristics of the asymmetric double PMC embodiment of the resistance value switching device u〇c. More specifically, FIG. 18 illustrates the resistance switching characteristics of the upper PMC structure 472, FIG. 19 illustrates the resistance switching characteristics of the lower PMC structure 474, and FIG. 2B illustrates the non-component composed of the upper structure 472 and the lower PMC structure 474. Resistance switching characteristics of symmetrical dual structures.

As shown in FIG. 18, the positive voltage VS1 applied to the upper PMC structure 472 causes the resistance value of the upper PMC g structure 472 to switch to the resistance value associated with the memory state Rreset. % is added to the upper PMC structure 472. Negative power causes the upper PMC. The resistance value of structure 472 is switched to the resistance value associated with memory state RSET. As shown in Figure 19, the positive voltage VS3 applied to the lower pMC structure causes the electrical resistance of the lower PMC structure 474 to be related to the memory, E§el. Application to the lower pMC structure 474 ^ Negative = S4 causes the resistance value of the lower PMC structure 474 to switch to the resistance value associated with the memory. 28

201203248 113 32646twf.doc/I The combination of the upper PMC structure 472 and the asymmetric embodiment of the lower PMC structure 474 as shown in FIGS. 18 and 19 produces a memory device that can have four as shown in FIG. Memory states A to D. Each of the memory states A to D is associated with the sum of the resistance values of the memory states of the upper pmc structure 472 and the lower PMC structure 474, respectively. The memory state A occurs when the upper PMC structure 472 has a resistance value RSET associated with the memory state, and the lower PMC structure 474 has a resistance value Rreset ' associated with the memory state such that the overall resistance value of the dual PCM structure is in the memory state. A is R~set+Bjieset. The memory state D occurs when the upper PMC structure 472 has a resistance value Rreset associated with the memory state, and the lower PMC structure 474 has a resistance value Esee' associated with the memory state such that the overall resistance value of the dual PCM structure is in the memory state. 〇 is Siii+Rreset. Both the memory state B and the memory state c occur when the upper PMC structure 472 has a resistance value Rreset associated with the memory state, and the lower PMC structure 474 has a resistance value associated with the memory state such that the overall resistance value of the dual PCM structure The memory state B and the memory state C are Rreset+Ereset. Therefore, it is quite difficult to clearly distinguish between the memory state B and the memory state C, so the dual PMC structure of the resistance value switching device 110c can be realized as a three-state memory having memory states A, B (or C), and D. Body device. Figure 21 is an alternative read flow of the resistance value switching device u〇c according to an asymmetric embodiment having asymmetric switching characteristics as shown in Figures 18-20. First, in block 600, the resistance value switching device 110c has been programmed into one of the memory states A, B/C or D.

201203248 ryftuio 32646twf.doc/I -. The rest of the flow is read by the scale changing device (10), and which one of the determined memory states A, Β/C or D is written to the resistance value switching device 110c. In block 6〇2, the resistance value of the resistance value switching device wrist is determined. As shown in Fig. 2G, it is expected that the resistance value is one of a plurality of resistance values corresponding to the memory state AdW+R^), 3 maser +^) or ds§£i+Rreset). If the resistance value Rreset+&isei is detected, the flow ends at block 604 and it is determined that the memory state of the resistance value switching device 110c is the memory state B/c. If the resistance value Sssi+Rreset is detected, the flow ends at block 600 and it is determined that the memory state of the resistance value switching device 110c is the memory state. If the resistance value RSET+Egg^ is detected, the flow is at block 6〇. 8 ends and determines that the memory state of the resistance value switching device 110c is the memory state A. Further embodiments of many other possible resistance value switching devices 11 can be understood in addition to the foregoing embodiments U 〇 a, and 110 c of the resistance value switching device 110. Figure 22 illustrates a block diagram of a more generalized embodiment which is generally referred to as a resistance value switching device 110d. The resistance value switching device 110d includes an upper PMC structure 652 and a lower PMC structure 654, wherein the upper PMC structure 652 and the lower PMC structure 654 each include a semiconductor resistance-switching memory device. For example, the upper PMC structure 652 includes a PMC, a resistive random access memory (RRAM), a magnetoresistive random access memory (MRAM), and a phase change memory. (phase-change memory, PCM) or a ferroelectric random access memory (FRAM). Similar to the class 201203248

P980115 32646twf.doc/I Similarly, the lower PMC structure 654 includes a PCM, a rram, an MRAM or an FRAM. The upper PMC structure 652 and the lower PMC structure 654 may alternatively include any one of the electronic memory devices (corresponding to two memory states) that can be switched between the two resistance values. The memory state of the upper PMC structure 652 includes the memory states labeled Rr £set and Rset, which correspond to higher resistance values and lower resistance values, respectively. A positive reset voltage (+VreSET) switches the resistance of the upper PMC structure 652 to the resistor Rreset, and a negative set voltage (-VSET) switches the resistance of the upper PMC structure 652 to the resistor rset. The memory state of the lower pMC structure 654 includes the memory states labeled Rreset# Ksel, which correspond to higher resistance values and lower resistance values, respectively. A negative reset voltage (_Vr£set) switches the resistance of the lower PMC structure 654 to the resistor, and a positive set voltage (+VSET) switches the resistance of the lower PMC structure 654 to the resistor & The resistance value switching device 110d has two preferred combinations of conditions, and the first combination of conditions satisfies the following conditions (la) and (lb): (la) +Vreset> +Yset

(lb) Bu VSET| > I

The second conditional combination of iYresetI satisfies the following conditions (2a) and (2b):

(2 a) +VreSET < +VgET

(2B) |-Vset| < IiYresetI An embodiment of the resistance value switching device 110d that satisfies the first conditional combination will be described with reference to Figs. 23 to 25 . An embodiment of the resistance value switching device 11〇d that satisfies the first conditional combination will be described with reference to Figs. 27 to 30. 23 to 25 illustrate resistance values satisfying the first combination conditions (丨a) and (lb) 31 201203248

P980115 32646twf.doc/I A graph of the resistance switching characteristics of an embodiment of the switching device llGd. More precisely, FIG. 23 shows the resistance switching characteristic of the upper PMC structure, FIG. 2 shows the resistance switching characteristic of the lower PMC structure 654, and FIG. 25 shows the overall resistance of the resistance value switching device l1Gd according to the present embodiment. Switch characteristics. As shown in Fig. 23, the application of a positive voltage + 乂 fat to the upper structure 652 causes the resistance of the upper PMC structure to switch to 盥.

_ New value... A 贞 peach ^ applied to the upper part ^^^^ 652 causes the resistance of the upper PMC structure (6) to switch to the resistance value associated with the memory state Rset. As shown in FIG. 24, a positive voltage + γ is applied to the lower pMc structure 654, which causes the resistance of the lower pMC to 654 to switch to the resistance value associated with the memory state. A negative voltage - γ ^ ΕΤ lower PMC structure 654 causes the resistance of the lower PMC structure 654 to switch to the state of the memory state.

As shown in Fig. 23 and Fig. 24, the combination of the upper PMC structure 652 and the lower pMC structure 654 generates a resistance value switching device 11 (memory body) capable of having four memories as shown in Fig. 25, states A to D. The parent of states A to D is associated with the sum of the resistance values of the upper PMC structure 652 and the lower PMC structure 654. The memory state A occurs when the upper PMC structure 652 has a resistance associated with the memory state. The value of the lower PMC structure 654 has a resistance value associated with the remember state Eredset such that the overall resistance value of the resistance value switching device 110d is in the memory state A. The memory state b is generated when the upper pMC structure 652 has a memory Body state Rr£set related resistance value, while lower pMc 32 201203248

Γ^ουιιό 32646twf.doc/I Structure 654 has a lightning 檑 associated with the memory state Bj^eset such that the overall resistance value of the resistance value switching device ll 〇d is Seesh+Rreset in the memory state B. The memory state C occurs when the upper pmc structure 652 has a resistance value associated with the memory state RSET, and the lower PMC structure 654 has a resistance value associated with the memory state such that the overall resistance value of the resistance value switching device 110d In the memory state c, the memory state D occurs when the upper pmc structure 652 has a resistance value associated with the memory state rReset and the lower PMC structure 654 has a resistance value associated with the memory state Esm: such that the resistance value The overall resistance value of the switching device 11〇d is in the memory state D. Therefore, the resistance value switching device 110d can be realized as a four-state memory device having the memory states a, B, c, and D. Next, referring to FIG. 26, the read resistance value switching device 110d' will be described based on an embodiment in which the resistance switching characteristic satisfies the first combination condition (1a) and (lb) of the four-state memory device, and FIG. 26 shows the reading flow. flow chart. φ. First, in block 70, the resistance value switching means 11'd has been programmed into one of the memory genres A'B, C or D. The rest of the process allows reading of the resistance value switching means 1HM to determine which of the 2 memory states A to D is written to the resistance value switching means_. In block 702, a resistance value of the resistance value switching device 11 (1) is determined. The resistance value of the device may be one of four resistance values respectively associated with the memory. When the resistance is measured: =SET+Sm, the flow ends at block 7〇4 and it is determined that the memory state of the resistance value switching device 110d is the memory state c(Rset+^).

201203248 ryuviu 32646twf.doc/I The resistance value R^Rreset+Rreset is detected, and the flow ends at block 705 and it is determined that the memory state of the resistance value switching device 11〇d is the memory state BCRRESET+EfiEiEI;). In this embodiment, the resistance value associated with Rset is substantially equal to the resistance value associated with Esil, and the resistance value associated with Rreset is substantially equal to the resistance value associated with Preset. Therefore, the second possibility at block 702 is that the resistance is R = Rreset + Rset = Rset + Ereset. If the third possibility occurs, the flow continues to be clearly distinguished between the memory state A (Rset+Rreset) and the memory state D (Rreset+Eset). Next, in block 706, a voltage VDETERM is applied to the memory switching device 110d, and then the resistance value of the memory switching device 110d is measured in block 708. In this embodiment, the voltage of %^_ is selected such that if the memory state is the memory state A, the lower PMC structure 654 will be switched from Eseset to Rset' but when the memory state is the memory state D, Will cause any change "Therefore, the voltage of the stomach is a voltage between +VreSET. In block 708, the resistance value of the resistance value switching device ii 〇d is again determined. If the resistance detected in block 708 is r = Rr £set + Sssi, then it can be judged that the state of the memory is § the state of the memory D because the resistance value is not changed by the applied voltage vDETERMINE. Therefore, the flow ends at block 71〇, and it is determined that the memory state of the resistance value switching device 11〇d is the memory state D. Conversely, if the resistance value is measured in block 708 as R = Rreset + Esu, the memory state is the memory state a because the resistance value was once changed by the applied voltage VDETERMINE. Worth in this situation 34

201203248 32646twf.d〇c/I It is mentioned that the applied voltage Vdetermine switches the resistance value of the lower pMc structure from the current value to the block 712, wherein the resistance values of the lower pmc and the structure 654 are switched back to ( For example, by applying a voltage, the memory state of the resistance value switching device is not disturbed by the current read state. Then, the flow ends at block 714, and it is determined that the memory shape of the resistance value switching device is a memory. State A. ~ Figures 27 to 29 illustrate the resistance switching characteristics of an embodiment of the resistance value switching device 11 〇d satisfying the second set of conditions (2 &) and (2b) described above. More precisely, Fig. 27 The resistance switching characteristic of the upper memory structure 652 is illustrated, the resistance switching characteristic of the lower memory structure 654 is illustrated in FIG. 28, and the resistance switching characteristic 8 of the resistance value switching device 11〇d according to the present embodiment is illustrated in FIG. As shown in Figure 27, a positive voltage +Vr£set applied to the upper pMC structure 652 causes the resistance of the upper PMC structure 652 to switch to a resistance value associated with the memory state Rreset. A negative voltage -VSET is applied to the upper PMC junction. 652 causes the upper PMC structure ^52 to switch to the resistance value associated with the memory state Rset as shown in Figure 28. As shown in Figure 28, a positive voltage is applied to the lower pMC structure 654 which causes the resistance of the lower PMC structure 654. Switching to the resistance value associated with the memory state Ssel. A negative voltage-Yreset lower PMC structure 654 causes the resistance of the lower PMC structure 654 to switch to the τ resistance value of the memory state.

As shown in Figures 27 and 28, the upper pMC structure 652 and the lower PMC 35 201203248

Ry δυ u 3 J2646twf.doc/I Structure 654 is combined to produce a resistance value switching device capable of having four s-resonance states A to D as shown in FIG. Each of the memory states A to D is associated with the sum of the resistance values of the upper PMC structure 652 and the lower pMC structure 654 memory state, respectively. The memory state a occurs when the upper PMC structure 652 has a resistance value associated with the memory state Rset, and the lower PMC structure 654# has a resistance value associated with the memory state, so that the overall resistance value of the resistance value switching device 11〇d The memory state A is RsET+Eggser memory state b is generated when the upper pMC structure 652 has a resistance value associated with the 5 memory state rset, and the lower PMc structure 654 has a resistance value associated with the § memory state. Therefore, the overall resistance value of the resistance value switching device 110d in the memory state B is the memory state C occurs when the upper PMC structure 652 has the resistance value associated with the memory state Rreset' and the lower PMC structure 654 has the memory state When the resistance value of ^eset^ is off, the overall resistance value of the resistance value switching device 丨1〇d is in the memory state C is the memory state D occurs when the upper PMC structure 652 has a resistance related to the memory state Rr£set The value, while the lower PMC structure 654 has a resistance value associated with the state of the memory, 'the overall resistance value of the resistance value switching device 110d is set to Rset+Rresft. Therefore, the resistance value switching means 110d can be realized as a four-state memory device having the memory states a, B, C and D. Next, referring to FIG. 30, the read resistance value switching device 110d will be described based on an embodiment in which the resistance switching characteristic satisfies the first combination condition (2a) and (2b) of the four-state memory device, and FIG. 30 shows the reading flow. flow chart. 36 201203248

Fysons 32646twf.doc/I First, in block 800, the resistance value switching device u〇d has been programmed into one of the memory states A, B, C or D. The rest of the process allows reading of the resistance value switching means u〇d to determine which of the memory states A to D is written to the resistance value switching means u?d. In block 802, the resistance value of the resistance value switching device u〇d is determined. It is expected that the resistance value of the resistance value switching means 11?d is one of four resistance values respectively associated with the memory states A to D. If the resistance % value R=:Rset+&1I' is detected, the flow ends at block 804 and it is determined that the memory state of the resistance value switching device 110d is the memory state. If the resistance value R=Rreset+ is measured, Rreset, the flow ends at block 805 and determines that the memory state of the resistance value switching device 110d is the memory state C (Rreset+Ereset). In this embodiment, the resistance value associated with RSET is substantially equal to Eeel. The resistance value, and the resistance value associated with RreSET is substantially equal to the resistance value associated with B^eset. Thus, the third combinability at block 802 is that the resistance is R = RreSET + Kset = Rset + Ereset. If a third possibility occurs, then the flow continues to make a clear distinction between the memory state A (Rset + Sbeset) and the delta recall state D (Rrksf. t + Rset). The picker 'in block 806' applies a voltage Vdetermine to the memory switching device 110d, and then measures the resistance value of the memory switching device 110d in the square 808. In this embodiment, the Vdetermine is selected so that if the memory state is the memory state A, the upper PMC structure 652 is switched from RSET to Rreset, but if the memory state is memory 37

201203248 r > 〇υ 11 j J2646twf.doc/I Body state D does not cause any changes. Therefore, the voltage of v__ is a voltage between +V reset and +YsET. In block 808, the resistance value of the resistance value switching device is again determined. If the resistance detected in block 808 is r = Rreset +; ^, then the memory state can be determined to be the memory state D because the resistance value I is not changed by the applied voltage VdetermiNE. Therefore, the flow ends at block 81 ’ and judges that the memory state of the resistance value switching device 11 〇 d is the memory state D. Conversely, if the resistance value is measured in block 808 as R ==Rreset + Ereset, the memory state is memory state A because the resistance value has been changed by the applied voltage VdeterminE. It is worth mentioning in this case that the applied electric grinder VDETErmine switches the resistance value of the upper PMC structure 652 from RSET to Rreset. Thus, the flow continues with block 812 where the resistance value of the upper PMC structure 652 is switched back to Rset (eg, by applying a voltage -VSET) such that the memory state of the resistance value switching device 110d is not being read by the current state. interference. Then, the flow ends at block 814, and it is determined that the memory state of the resistance value switching means H?d is the memory state A. FIG. 31 is a flow chart showing a flow of reading a selected one of the memory cells 102 of FIG. 1 to FIG. This flow is described by reading the example of the memory cell 1 〇 2d shown in FIG. 2; however, any of the processes described herein and illustrated in FIG. 31 can be similarly used to read the memory cell 1 〇 2 One. In short, the reading process can include turning on transistors 112a-112c that are not selected memory cells 102a-102c (block 902), enabling serial selection 38 201203248

Ryovno 32646twf.d〇c/I

The transistor SST and the ground select transistor GST (block 904), the read resistance switching device 110d (blocks 906-910), and the read transistor 112d (blocks 912-914). The read resistance value switching device 1 〇d may include a transistor 112d that turns off the selected memory cell 102d (block 906), and applies a voltage to the bit line associated with the memory string MSi of the selected memory cell 102d. BLi (block 908)' and the resistance value of the resistance value switching device 110d of the selected memory cell i2d. Reading transistor ii2d may include applying a mid-range voltage (reading the polarity of the pole) to word line WL4 (block 912) and determining if the applied threshold voltage turns on transistor U2d (block 914). In block 900, the reading step can be initiated to read the selected memory cell, for example, including using a read enable signal. In block 902, a plurality of word lines WL' of the unselected memory cells, i.e., word lines WL1-WL3, are activated to turn on the transistors 112a-112c of the unselected memory cells 102a-102c. That is, the boost word line WL1-WL3 exceeds the threshold voltage Vte of the transistors ii2a-112c at the transistor 112a-l 12c $ floating gate transistor (or other type that can be switched between a plurality of different threshold voltages Vt) In an embodiment of the transistor, the voltage applied to the word lines WL1-WL3 can be set to a high level, but not the voltage of the unprogrammed level (a pass voltage). The pass voltage applied to the bodies 112a-112e allows the transistor ma_U2e = current limited by the stored data value. The eight towers in block 9〇4, open the tandem selection transistor and the ground selection transistor GST by applying an appropriate threshold voltage to the serial selection 39 201203248 J264^6twf.doc/[line SSL and ground selection line GSL. . In block 906, the transistor of the selected memory cell is turned off. Thereafter, the voltage of word line WL4 is set lower than the threshold voltage Vt of the transistor of memory cell 1〇2. In the case where the transistor 112d is a floating closed-pole transistor (or other type of device that can be switched between a plurality of different threshold voltages Vt), the electrical waste applied to the word line WL4 can be less than a large amount; The lowest value is to turn off the transistor l12d. In block 908, an appropriate read voltage is applied between the word line BLi and the common source limit S1, and the resistance value of the resistance value switching device 110d is measured in block 91. Depending on the type of resistance value switching means as the resistance value switching means, blocks 9〇8 and 9191〇 may be included herein, for example as shown in FIG. 7, FIG. 9, FIG. 17, FIG. 21, FIG. Reading process. In block 912, a mid-range house (read gate voltage) between possibly multiple winter threshold voltages is applied to the character, line WL4. For example, in some embodiments 'The transistor 112d can be programmed (eg, logic state "〇") to the first effective threshold voltage Vtpr. (d) and the gate that is cleared (eg, 'logic state' Γ,) to the second effective threshold voltage v_ Polar crystal. Stylized threshold voltage Vogram in typical conditions It will be higher than the clear threshold voltage vt:. The read gate voltage can be selected between 'ready and ip', so that if it is cleared (storing logic state "Γ"), the transistor 112d is turned off or maintained until it is Stylized (storing logic state "〇"). In block 914 'detects the state of transistor 112d. Block 914 201203248

r^oviu 32646twf.doc/I may include applying an appropriate bias voltage to the bit line BLi and detecting the impedance value of the memory string MSi through the memory cell 102d. If the transistor ii2d has been programmed, then the read voltage ' applied to the intermediate level of the gate of the transistor U2d in block 914 will not be sufficient to turn on the transistor 112d. Therefore, the detected current passes through the resistance value switching device 102d and a portion of the increased resistance value (eg, 'a resistance value greater than the value of the through-resistance when the transistor 112d is turned on). 112 (1 is cleared, then in block 914, the read voltage applied to the intermediate level of the gate of transistor 112d will be sufficient to turn on transistor 112d. In this case, current will pass through transistor 112d because of the resistance value. The transistor ii2d provides almost no resistance compared to the switching device ii 〇 d. In block 916, the read flow ends in a state in which the data of the resistance value switching device 110d and the transistor ii2d are read. Block 916 may include removal. The voltage is connected to the bit line BLi, the word lines WL1 WL WL4, the string selection line SSL, and the gate selection line GSL. FIG. 32 is a diagram showing that one of the memory cells 1 〇 2 shown in FIG. Flowchart of a stylized flow of memory cells. This flow is described by reading an example of the memory cell 〇2d shown in FIG. 2; however, the flow described herein and illustrated in FIG. 32 can be similarly used. To read the memory cell 102 The reading process may include turning on the transistors ll2a-112c that are not selected for the memory cells 102a-102c (block 952), and turning on the tandem selection transistor SST and the ground selection transistor GST (block 954). 'Stylized resistance value switching device 11〇d (blocks 956-958), and stylized transistor 41 201203248

r^ouiij J2646twf.doc/I 112d (block 960-962^ stylized resistance value switching device u〇d can include a transistor 关闭12d (block 956) that closes the selected memory cell 〇2d, applying a program The voltage is applied to the bit line BLi associated with the memory string MSi of the selected memory cell 1〇2d (block 958), and the resistance value of the resistance value switching device 11〇d of the selected memory cell 102d is measured. The transistor 112d can include applying a programmed gate voltage to the word line (block 960) and applying a programmed voltage to the bit line BU (block 962). In block 950, the initial stylization step can be programmed. The selected memory cell, for example, includes a write enable signal, (write_enaWe signal). In block 952, a plurality of word lines WL of the unselected memory cells, that is, word lines WL1-WL3, The transistors Ii2a-ll2c are activated to turn on the unselected memory cells 102a-102c. That is, the boost word lines WL1-WL3 exceed the threshold voltage vt of the transistors ii2a-ii2c. The transistors 112a-12b are floating gates. The transistor (or can be cut between a number of different threshold voltages Vt) In another embodiment of the transistor of the other type, the voltage applied to the word lines WL1 - WL3 can be set to a high level, but the voltage of the unprogrammed level (a pass voltage) can be applied. The pass voltages at the transistors 112a-112c allow the transistors U2a-n2c to transfer currents that are not limited by their stored data values. In block 954, by applying an appropriate threshold voltage to the string select line SSL and the ground select line GSL, The serial selection transistor SST and the ground selection transistor GST are turned on. In block 956, the transistor of the selected memory cell is turned off, that is, 42 201203248

The voltage of the r^6uno 32646twf.doc/I word line WL4 is set lower than the threshold voltage Vt of the transistor U2d of the memory cell 1〇2. In embodiments where the transistor 112d is a floating gate transistor (or other type of transistor that can be switched between different multiple threshold voltages Vt), the voltage applied to the word line AVL4 can be lower than a plurality of thresholds. The lowest value in the voltage is to turn off the transistor 112 (1. In block 958, an appropriate read voltage is applied between the word line BLi and the common source limit spring SL according to the data written to the resistance value switching device. Then, the word line voltage is removed before the programmed transistor ii2d. In block 960, the writing of the data to the transistor 112 (the flow of 1 is started. The word line WL of the memory cell is not selected, and the word line is maintained. Open state. According to the data written to the transistor U2d, an appropriate bias voltage is applied between the bit line BLi and the common source line SL. The bit-programmed electric house is selected to be able to write the logic state to the transistor 112d. Stylized voltage, or write logic state "1" to the stylized voltage of transistor 112d. For example, to achieve stylization, volts (v 〇 ls) can be applied in bit Φ line BLi. Thus, tandem Select line SSL is activated, and The ground select line GST is turned off. In block 962, the Fuller-Norton electron penetration current can be utilized to program/eliminate the transistor 112d. When the volts are applied to the non-selected word lines WL1-WL3, 'apply one High level voltage (programmed gate voltage) to word line WL4. For example, in some embodiments, transistor U2d can be programmed (eg, logic state "〇,") to a first effective threshold voltage Vtpr_ and the gate transistor that is cleared (eg, logic state "1") to the second effective threshold voltage of 43 2012032, - V^rase. The stylized threshold voltage Vtpr〇gram will be higher than the clearing threshold under typical conditions. Voltage Vt-erase. For example, in some embodiments, applying 0 volts to a non-selected character, a 20 volt stylized voltage can be applied to transistor 112d to program transistor 112d. In block 964, The stylization process ends with a state in which the data of the resistance value switching device 110d and the transistor ii2d is written. Block 964 may include removing the voltage to the bit line BLi, the word line, the string selection line SSL, and the gate selection. Line gsl. The embodiments of the present invention and the disclosed embodiments have been described above, and it is to be understood that the described embodiments are merely illustrative and are not intended to limit the embodiments of the invention. The spirit and scope of the present invention should not be limited by the above-described exemplary embodiments disclosed herein. In addition, the advantages and features provided in the described embodiments should not be construed as limiting the practice of the present invention. The scope of protection is in the process and structure to achieve any or all of the above advantages. In addition, the questions in the specification format required by the patent law are for organizational purposes only. These headings should not limit or limit the scope of the protection that can be derived from the disclosure. In particular, the scope of protection of the present invention should not be limited to the "technical field to which the invention pertains". In the prior art of the present invention, the prior art should not be interpreted as a prior matter of the present invention. "Send = = tolerance" does not apply to the limitations of the present invention by consideration. The single-state in the above-mentioned invention is not to be construed as merely a single feature of the present invention. According to the scope of protection extended by the disclosure, multiple hairs can be disclosed 44 201203248

115 32646 twf.doc/I and such protection scopes correspondingly define inventions equivalent to the invention and protect the invention as defined. In all cases, the scope of protection thus set should be interpreted in accordance with the technical content of the present disclosure and should not be limited by the title of the paragraph. The scope of the invention as disclosed herein is intended to be limited only by the scope of the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a memory device according to an exemplary embodiment of the present disclosure. 2 is a schematic diagram showing a memory string of the memory device presented in FIG. 1. Figure 3 is a schematic illustration of the memory cells of the memory device presented in Figure 1. 4A and 4B are schematic diagrams showing a resistance value switching device according to several embodiments of the resistance value switching device of Fig. 3. 5A-5E illustrate the resistance switching characteristics of the symmetric two-state embodiment of the resistance value switching device of FIGS. 4A and 4B, and FIG. 6 illustrates the implementation of the symmetric state of the resistance value switching device of FIGS. 4A and 4B. A graphical representation of the relationship between the memory state and the applied voltage. Figure 7 is a flow chart showing the reading flow of the resistor-switching, non-symmetric two-state embodiment of Figures 4A and 4B. ° f Figure 8 shows the symmetry of the resistance value switching device of Figure 4A and Figure 4B.

>^646twf.doc/I 201203248 The switching characteristics of the embodiment. Asymmetric double-resistance switching device of the two-state changing device performs asymmetric reading of the asymmetry of the sugar display. The drawing shows: 2 resistance = map loading 3::: for (four), 13 A graph of the voltage and current occurring in the staging and reading operations of the resistance value switching device in FIG. Figure J4 is a schematic diagram of a resistance value switching device according to several embodiments of the resistance value switching device of Figure 3. FIG. 15A is a diagram showing the pair of resistance value switching devices of FIG. 14.

= Resistor S of the Programmable Metallization Cell Structure Above the Generating Unit Figure 15B shows the resistance switching characteristics of the programmable metallization cell structure under the symmetrical double 2 metallization unit of the resistance value switching device of Figure 14. Figure 16 illustrates the resistance switching characteristics of the dual programmable metallization cell structure including the upper and lower materialized metallizations having the switching characteristics presented in Figure 15A and the drawings, respectively. . Figure ΠS is a flow chart showing the read flow of the resistance value switching device shown in Fig. 16. 46

201203248 ryouiu 32646twf.doc/I FIG. 2 is a schematic diagram showing the asymmetric double-passage of the resistance-switching device in the resistor-cutting type of the non-element programmable metallization unit structure of the resistance value switching device of FIG. The resistance cut-off diagram 20 of the programmable metallization unit structure in the lower part of the early 70 shows the resistance switching characteristic of the upper and lower programmable metallization == programmable metallization unit structure having the switching characteristics of the top and bottom of the graph . Take the flow chart ΙΪ7. Reading of the root 2 akisaki 1 electric device 吟 - Fig. 3 Μ 城 装置 _ _ 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 。 22 resistor switching device - the upper part of the embodiment of the resistor switching characteristics of the memory structure. Figure 24 is a diagram showing the resistance switching characteristics of the memory structure of one embodiment of the resistance value switching device of Figure 22. Figure 25 is a diagram showing the resistors shown in Figures 23 and 24, respectively, including the upper and lower memory structures. The electric diagram 26 of the memory device is a flow chart of the reading flow of the resistance value switching device shown in Fig. 25. Fig. 27 is a diagram showing the upper memory of one of the resistance value switching devices shown in Fig. 22. Resistance switching characteristics of the structure. 47 201203248

r^oviu -*2646twf.doc/I ^ 28 depicts the resistance switching characteristics of the lower memory structure of one of the resistance value switching devices presented in FIG.乞 Figure 29 shows the resistance of the upper and lower recording structures with switching characteristics in Figures 27 and 28, respectively! The resistance switching characteristic is shown in Fig. 29. Fig. 30 is a flow chart showing the flow of the resistance value switching according to Fig. 29. a "1" FIG. 31 is a flow chart showing the reading flow of the memory cell shown in FIG. 3. FIG. 32 is a flow showing the stylized flow of the memory cell shown in FIG. 3. [Main component symbol description] 100: Memory array 102: memory cell '102a: first memory cell 102b: second memory cell 102c: third memory cell 102d: fourth memory cell 110a to 110d: resistance value switching device 112, 112a to 112d: transistor 122, 402, 452: substrate 124, 404, 454: dielectric inter-metal dielectric layer (IMD layer) 126, 406, 456: first electrode layer 128: tungsten oxide layer 468: second solid electrolyte layer 470: third solid electrolyte layer 472: upper programmable metallization unit structure 474: lower programmable metallization single light structure 652: upper memory structure (upper programmable metallization unit structure) 654: lower memory structure (upper programmable metallization) Unit structure) A, B, C, D: Memory state BL1~BLm: Bit line GSL: Ground selection line 48 201203248

Ry δυ iid 32646twf.doc/I 130 : dielectric layer 130a, 410, 460: first dielectric layer 130b, 412, 462: second dielectric layer 134, 416, 466: second electrode layer 138: first interface Region 140: second interface regions 200-214, 300-308, 500-514, 600-608, 700-714, 800-814, 900-916, 950-964: Step Flow 400: Programmable Metallization Unit ( PMC) 408, 458: conductive plug layer 414: solid electrolyte layer 464: first solid electrolyte layer GST: ground selection transistor MSI~MSm: memory string Rl, R2: resistance value

Rset, Rset, Rreset, Rreset,

Rreseti, BlRESETI, RrESET2, RrJESET2: Memory Status SL: Source Line SSL: Tandem Select Line SST: Tandem Select Transistor "VI, "V2, ν$2, ν§4,·Υ5ΕΤ,

Yreset : Negative voltage V3, V4, V] § i, VS3, +Vreset, +VsET : positive voltage ^DETERMINE : voltage Vt-program · first effective threshold voltage Vt-erase * second effective threshold voltage WL1 ~ WLn: word Yuan line 49

Claims (1)

646 twf.doc/I 201203248 VII. Patent Application Range: L A memory device comprising an array having a plurality of memory cells, and at least one of the memory cells comprises: a first transistor having a first a second terminal and a gate terminal, wherein the transistor is configured to switch between different threshold voltages respectively associated with the plurality of memory states; and a resistance value switching device coupled in parallel with the transistor Connecting the resistance value switching device to the first end and the second end of the transistor, and the resistance value switching device is configured to be between different resistance values respectively associated with the plurality of memory states Switch. 2. The memory device of claim 1, wherein the f resistance switching device comprises a first interface region and a second interface region respectively having no more than one resistance switching characteristic. 3. The memory device of claim 2, wherein the first interface is at least a portion of the tungsten layer of the second interface region. The memory device of claim 2, wherein the resistance switching characteristics of the surface region are symmetrical to the resistance switching characteristics of the second interface region. i. The memory device according to item 2, wherein the resistance switching characteristics of the two-sided area are asymmetrical to the resistance switching characteristics of the second interface area. 6. The memory device according to the above paragraph, wherein the resistance value switching device comprises a first-styltable metallization unit. The memory device of claim 6, wherein the resistance value switching device comprises a second programmable metallization unit. The memory device of claim 7, wherein the first: programmable metallization unit comprises a first solid electrolyte layer, and the second programmable metallization unit comprises a second solid electrolyte layer. 9. The memory device of claim 8, wherein the resistance value switching device comprises an oxidizable electrode layer, the oxidizable electrode layer being disposed on the first solid electrolyte layer and the second solid electrolyte layer between. The memory device of claim 7, wherein the first programmable metallization unit has no different resistance switching characteristics than the second programmable metallization unit. The memory device of claim 10, wherein the electrical (four) switching characteristics of the first programmable metallization unit are symmetric with respect to the resistance switching characteristics of the first programmable metallization unit . 12. The memory device according to the first aspect of the invention, wherein the resistance switching characteristics of the first element are asymmetrical to the resistance switching characteristics of the stylized metallization unit. The device of the present invention, wherein the Φ value switching device comprises a first memory structure and a second memory. 14. The memory device according to claim 13 of the fourth patent scope, the first record « The structure includes - the electric record _ access record dragon, a magnetic = random access memory and - ferroelectric _ access note New 51. 201203248 a n ------- J2646twf.doc / I 15. The memory device of claim 1, wherein the transistor comprises a floating gate. 16. A memory device comprising: a plurality of bit lines; a plurality of word lines; a first memory string comprising a first memory cell group; a second memory string comprising a first a second memory cell; and a common source line connected to the first memory string and the second memory string; wherein the first memory string and the second memory string Columns are respectively connected to the bit lines; wherein the word lines are respectively connected to the memory cells of the first memory cell group and the memory cells connected to the second memory cell group; wherein the first memory The cell group includes a first memory cell connected between the common source line and a first bit line of the bit lines, the first memory cell comprising: a first transistor 'Having - first end, - second end and - gate extreme 'the first electric (10) for switching between different threshold voltages respectively associated with a plurality of memory states; and - first - resistance value switching a device connected in parallel with the first transistor to connect the first resistance value switching device to The first end and the second end of the first transistor and the first residual switching device are configured to switch between different resistance values respectively associated with the plurality of memory states. 52 201203248 ryw ii) 32646twf.doc/I Element 17. As described in claim 16, the gate terminal of the first transistor is connected to one of the word lines. The memory device of claim 16, wherein the line can be controlled to store data to the first-electron M body and store data to the first-resistance value switching device. 19. The memory device of claim 16 and the common source line can be controlled to read data from the third, read data, and read data from the first resistance value switching device. . </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; 2L as claimed in claim 2, wherein the u-interface region and at least a portion of at least one of the tungsten oxide layers of the second interface region. 22. The memory device of claim 16, wherein the I resistance value switching device comprises a first-styltable metallization unit. 23. The memory device of claim 22, wherein the i resistance value switching device comprises a second programmable metallization unit. 24. The memory device of claim 23, wherein the programmable metallization unit comprises a first solid electrolyte layer and the programmable metallization unit comprises a U-state electrolyte layer. 25. The memory device of claim 16, wherein the uf resistance switching device comprises a - memory structure and a second 53 201203248 i2646 twf. doc / I memory structure 26 The memory device of claim 25, wherein the first memory structure comprises a resistive random access memory, a magnetoresistive random access memory and a ferroelectric random access memory. 27. The memory device of claim 16, wherein the first transistor comprises a floating gate. The memory device of claim 16, wherein the second memory material group includes a second memory cell connection between the second bit line and the second bit line, wherein the The second memory cell includes a second transistor and a second resistance value switch device 1 connected in parallel to the second transistor: 'the second transistor of the second transistor is used to be associated with the memory state. Switching between the same plurality of threshold voltages, and wherein the second resistance value switching device is configured to switch between different resistance values associated with the associated memory state. 29. The memory device of claim 28, wherein the first memory cell group comprises a third memory cell connected to the source line and the second bit line, wherein the The three memory cells include a third transistor, a third resistance value switching device of the third transistor, and a second transistor for switching between different threshold voltages respectively associated with the memory state, and Wherein the third resistance value is switched by n with a plurality of different resistance values respectively associated with the state of the memory. 30. The memory device according to claim 29, wherein 54 201203248 ryoviu 32646twf.doc/I = The second transistor is connected in series with the third transistor and the third resistor value is switched between the second transistor and the second resistor value switching device in parallel with the third transistor and the third resistor value switching device. 31. A method of reading a memory cell of a semiconductor memory device, the method comprising: n the memory cell-electricity-critical money, the transistor using f and the memory state of the memory is not more than Switching between threshold voltages; and measuring a resistance value of the memory cell-resistance value switching device, the electrical switching device heart switching between a plurality of different resistance values associated with the plurality of states. The Thunder is said to be the 31st rhyme of the green, and (4) measuring the threshold voltage of the a first voltage to the extremum of the transistor and the -dosal end of the transistor in the memory cell A second voltage is applied such that if the first voltage is insufficient to activate the electrical body, a current passes through the resistance value switching device. 33. The memory device of claim 31, wherein the resistance value of the resistance switching unit is detected to include the transistor. 34. A method of staging memory _, the array array = one word line and a plurality of bit lines, the method of staging the memory array comprising: applying a line; and applying a first voltage to a second ink of the character lines of the selected word line to a selected pure element line, such that the selected 55 J2646 twf.doc/I 201203248 XWXA*/ sub-line is coupled to the bit line A memory unit is programmed. 5. The method of staging a memory array according to claim 34, wherein the memory unit is one of a first memory unit and a second memory unit in the memory array. . 36. The method of staging a memory array according to claim 35, wherein the first memory unit comprises a resistance value switching device (4), the stylized memory barrier described in claim 36 The method of 歹J, wherein the second memory unit comprises an electrical a body. a method of the first memory cell and the second memory cell