201201012 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明涉及一種主機板多硬碟埠測試系統及方法。 [先前技術] [0002] 主機板在裝配完成後，需經過全面的功能測試，其中包 括對主機板上各種埠的測試。目前主機板上一般都有多 個SATA/SAS (SATA : Serial Advanced Technology Attachment，串列高級技術附件，SAS : Serial At-tached SCSI，串列連接SCSI介面）硬碟埠，經過pCI_ E (PCI Express)擴展卡擴展後更是達數十個埠，而網 路儲存裝置的硬碟埠更多。測試這些埠的一般做法是測 試人員將所有硬碟埠都接上硬碟進行功能測試。如果每 個硬碟埠都用硬碟作為測試設備的話，一是由於硬碟的 價格一般較高’二是硬碟作為測試設備體積大不便於維 € ’三是損耗大’四是硬碟容易受到震動而影響測試效 果。同時’測試人員如果對痒進杆遂播侧試，則需每測 武疋一個谭後又重新插拔硬碟1並旦還要重新啟動測試 程式’在大規模生產應用_會造咸成本和時間的浪費。 【發明内容】 _3]蓉於上述内容，有必要提供—種主機板多硬碟瑋測試系 統及方法。 斤述主機板夕硬碟相n統，該系、㈣於測試待測主 機板的夕個硬碟蜂，所述待測主機板的多個硬碟蜂與一 個測域裝置的多個硬碟槔相連接，該測試裝置還包括MUX (Multiplexer，多工器）晶片、儲存設備及指示裝置 099119861 表單編號A0101 第4頁/共22頁 0992035117-0 201201012 ’該系統包括：切換通道模組’用於將制主機板的待 測埠號翻譯成MUX“對應的通道號，以切換·晶片中 與該通道號相對應的通道與儲存設備相連，形成一條從 待測主機板至儲存設備的資料傳輸路徑；寫校驗資料模 組三當错存設備與MUX晶片連接好後，通過上述資料傳輸 /將才父驗資料寫入儲存設備；讀校驗資料模組，用 =從儲存設備中㈣上述資料傳輸路徑，將所述寫入的 校驗資料讀出至制主機板；驗證模組，用於驗證上述 〇 寫人及讀出的的校驗f料是否-致；發送模組，用於當 1入和讀出的校驗資料不-致時’通過I/G痒向脆晶片 發送待測蟑異常的資訊，糊X晶片根據該資訊驅動指示 =置顯示待測埠異常的資訊；該發送模組還用於當寫入 ㈣出的校驗資料-致時，通過Ι/σ埠向Μυχ晶片發送待 /車正常的資讯’该MUX晶片根據該資訊驅動指示裝置顯 不待測蜂正常的資訊；擦除資料模組，當所寫入及讀出 ★驗資料—致時，擦除儲存設備中寫人的校驗資料。 ◎ [_ ^種主機板多硬，埠測試方法，包括以下步驟：⑷從 待測主機板的多硬碟埠中選擇—個待測槔，並將其埠號 ^譯成測試裝置中MUX晶片對應的通道號；⑴隨晶片 切換與該通道號對應的通道與_裝置的儲存設備相連 形成-條從待測主機板至儲存設備的資料傳輸路徑； (C)當健存設備與MX晶片連接好後，繼晶片驅動指示 :置顯示該待測埠的埠號；⑷待測主機板經由上述資 傳輪路彳⑽儲存設備寫人校驗資料並儲存；（e)待測 主機板經由上述資料傳輸路徑從儲存設備中讀出校驗資 099119861 表單蝙號A0101 第5頁/共22頁 0992035117-0 201201012 料；（f)當寫入與讀出的校驗資料不一致時，結束測試 ;(g)當寫入與讀出的校驗資料一致時，擦除寫入儲存 設備的校驗資料；（h )當待測主機板還有未測試的硬碟 琿時，返回步驟（a)，當該待測主機板的所有硬碟埠測 試完畢時’通過指示裝置顯示待測主機板測試成功的資 訊。 [0006] 相較於習知技術’本發明可一次自動測試主機板所有的 SATA/S AS硬碟埠’不會因硬碟在測試中受到震動而影響 測試效果，節約測試的成本和時.間。 【實施方式】 [0007] 如圖1所示，係本發明主機板多硬碟埠測試系統較佳實施 例的架構圖。該主機板多硬碟埠測試系統運行於主機1 上’主機1中待測主機板11與測試裝置2相連接。所述測 試裝置2包括一MUX晶片21、一儲存設備22、一 I/O埠25 、一 I/O琿轉換模組24、一指示裝置23及至少含有一個 ,.；.：：：： : : SATA/SAS埠的SATA/SAS埠組20。所碟指示裝置23由MUX 晶片21驅動。其中，SATA/SAS埠組20中的每個埠都按排 列順序有相應的編號，在圖中以6個埠為例；MUX晶片21 的通道數可根據實際需要測試的’埠數而定制，且晶片通 道按排列順序也有相應的編號。 [0008] 如圖2所示，係待測主機板與測試裝置硬碟埠的連接方式 示意圖。待測主機板11的SATA/SAS埠組12中的所有埠（ 埠也按順序有相應的編號，圖中以6個埠為例）與該測試 裝置2的SATA/SAS埠組20中的埠相連，連接方式為埠號 一一對應，例如，待測主機板11的埠A1與測試裝置2的埠 099119861 表單編號 A0101 第 6 頁/共 22 頁 0992035117-0 201201012 Β1相連，待測主機板11的埠Α2與測試裝置2的埠Β2相連 ，依此類推。所述測試裝置2的SATA/SAS埠組20中的埠 與所述MUX晶片21的通道（圖中以6條通道為例）相連， 連接方式為埠號與通道號--對應，如測試裝置2的埠C1 與MUX晶片21的通道Μ相連，測試裝置2的埠C2與MUX晶 片21的通道D2相連，依此類推。MUX晶片21連接至所述 儲存設備22。 [0009] Ο 如圖1和圖2所示’主機板多硬碟埠測試系統1〇從SATA/ SAS埠組12中選擇待測試的參號，並將該埠號翻譯成mux 晶片21對應的通道號，再將該通道號經待測主機板丨i的 I/O埠13和所述測試裝置2的I/O埠25傳，送到I/O埠轉換模 組24 ’該I/O埠轉換模組24將所接收到的通道號轉換成所 ο [0010] 述MUX晶片21的控制信號，如i2C (Inter — Integrated Circuit ’兩線式串列匯流排）或SPI (Serial Peripheral Interface ’ 串 列外設，介面 ）¾¾¾ ，以切換刖又 晶片21的通道與儲存設備22相連接，形成一條從待測主 機板11傳送資料到儲存設備22的資料傳輸路徑。 主機板多硬碟埠測試系統10將校驗資料經上述所選擇的 埠號及MUX晶片21的通道儲存在儲存設備22中。該儲存設 備22相當於—個硬碟用於儲存校驗資料，其可以是SSD ( S〇Ud’固態硬碟）或HDD (Hard Disk Drive,硬碟驅 動器）。 ' [0011]201201012 VI. Description of the Invention: [Technical Field of the Invention] [0001] The present invention relates to a motherboard hard disk testing system and method. [Prior Art] [0002] After the assembly is completed, the motherboard is subjected to comprehensive functional tests, including testing of various defects on the motherboard. Currently, there are usually multiple SATA/SAS (SATA: Serial Advanced Technology Attachment, SAS: Serial At-tached SCSI, Serial Attached SCSI Interface) hard disk drives on the motherboard, after pCI_E (PCI Express) After the expansion card is expanded, it is dozens of flaws, and the network storage device has more hard drives. The general practice of testing these defects is that the tester attaches all hard drives to the hard drive for functional testing. If each hard disk is using a hard disk as a test device, one is because the price of the hard disk is generally higher. 'The second is that the hard disk is too large for the test device. 'Three is the big loss' and the fourth is the hard disk. It is affected by vibration and affects the test results. At the same time, if the tester squats into the side of the test, it is necessary to re-plug the hard disk 1 after each test, and then restart the test program. Waste of time. SUMMARY OF THE INVENTION _3] In the above content, it is necessary to provide a motherboard-based multi-hard disk test system and method. The main board, the hard disk phase n, the system, (d) in the test of the motherboard to be tested, a hard disk bee, the hard disk bee of the motherboard to be tested and a plurality of hard disk of a range device The test device also includes a MUX (Multiplexer) chip, a storage device, and a pointing device. 099119861 Form No. A0101 Page 4 / Total 22 Page 0992035117-0 201201012 'The system includes: switching channel module' Translating the nickname of the motherboard to be translated into the corresponding channel number of the MUX, and switching the channel corresponding to the channel number in the wafer to the storage device to form a data transmission from the motherboard to be tested to the storage device Path; write verification data module 3. When the faulty device is connected to the MUX chip, the above data transmission/writing data will be written into the storage device; read the verification data module, use the = from the storage device (4) a data transmission path, the read verification data is read out to the motherboard; the verification module is configured to verify whether the above-mentioned writer and the read verification material are-induced; the transmission module is used for When 1 check in and read out If the material is not - when it is sent, the information of the abnormality to be tested is sent to the chip by I/G, and the paste X chip displays the information of the abnormality to be tested according to the information; the transmitting module is also used for writing (4) Verification data issued - when the Ι/σ埠 is sent to the Μυχ wafer, the normal information of the waiting/car is transmitted. 'The MUX chip drives the indicating device according to the information to display the normal information of the bee; the erasing data module When the data is written and read, the data of the writer in the storage device is erased. ◎ [_ ^ The type of motherboard is hard, the test method includes the following steps: (4) From the host to be tested Select one of the hard disk of the board to be tested, and translate the nickname into the channel number corresponding to the MUX chip in the test device; (1) switch the channel corresponding to the channel number to the storage device of the device Forming a data transmission path from the motherboard to be tested to the storage device; (C) when the storage device is connected to the MX chip, following the wafer driving instruction: displaying the nickname of the to-be-tested device; (4) the motherboard to be tested Write verification data via the above-mentioned asset transmission wheel (10) storage device (e) The board to be tested reads the verification resource from the storage device via the above data transmission path. 099119861 Form bat number A0101 Page 5 / Total 22 page 0992035117-0 201201012 material; (f) When writing and reading When the verification data is inconsistent, the test is ended; (g) when the verification data written and read is consistent, the verification data written to the storage device is erased; (h) when the motherboard to be tested still has untested When the hard disk is ,, return to step (a), when all the hard disks of the motherboard to be tested are tested, the information indicating the success of the test board to be tested is displayed by the pointing device. [0006] Compared with the prior art The invention can automatically test all the SATA/S AS hard disks of the motherboard at one time, which will not affect the test results due to the vibration of the hard disk during the test, saving the cost and time of the test. [Embodiment] FIG. 1 is a block diagram showing a preferred embodiment of a multi-hard disk test system for a motherboard of the present invention. The motherboard multi-hard disk test system runs on the host 1. The host board 11 to be tested in the host 1 is connected to the test device 2. The test device 2 includes a MUX chip 21, a storage device 22, an I/O port 25, an I/O port conversion module 24, a pointing device 23, and at least one, .;.:::: : : SATA/SAS埠 SATA/SAS埠 20. The disc indicating device 23 is driven by the MUX wafer 21. Each of the SATA/SAS group 20 has a corresponding number in the order of arrangement. In the figure, six 埠 are taken as an example; the number of channels of the MUX chip 21 can be customized according to the number of turns required for the actual test. And the wafer channels are also numbered in the order of arrangement. [0008] As shown in FIG. 2, it is a schematic diagram of a connection manner between a motherboard to be tested and a hard disk of the test device. All the SATA in the SATA/SAS group 12 of the motherboard 11 to be tested (there are corresponding numbers in the order, 6 埠 in the figure) and the SATA/SAS group 20 of the test device 2 Connected, the connection mode is the one-to-one correspondence. For example, the 埠A1 of the motherboard 11 to be tested is connected to the 埠099119861 form number A0101 of the test device 2, and the host board 11 is to be tested. The 埠Α 2 is connected to the 埠Β 2 of the test device 2, and so on. The SATA in the SATA/SAS group 20 of the test device 2 is connected to the channel of the MUX chip 21 (the six channels in the figure are taken as an example), and the connection mode is the nickname and the channel number--corresponding to, for example, the test device The 埠C1 of 2 is connected to the channel M of the MUX wafer 21, the 埠C2 of the test device 2 is connected to the channel D2 of the MUX wafer 21, and so on. The MUX wafer 21 is connected to the storage device 22. [0009] As shown in FIG. 1 and FIG. 2, the motherboard hard disk test system selects the parameter to be tested from the SATA/SAS group 12 and translates the code into the corresponding mux chip 21. The channel number is transmitted to the I/O埠25 of the test device 2 via the I/O埠13 of the motherboard 丨i to be tested, and sent to the I/O埠 conversion module 24'. The conversion module 24 converts the received channel number into a control signal of the MUX chip 21, such as i2C (Inter- Integrated Circuit 'two-wire serial bus) or SPI (Serial Peripheral Interface ' The serial peripheral device, interface 3b, is connected to the storage device 22 by switching the channel of the chip 21 to form a data transmission path for transferring data from the motherboard 11 to be tested to the storage device 22. The motherboard multi-drive test system 10 stores the verification data in the storage device 22 via the selected nickname and the channel of the MUX wafer 21. The storage device 22 is equivalent to a hard disk for storing verification data, which may be an SSD (S〇Ud' solid state hard disk) or an HDD (Hard Disk Drive). ' [0011]
MUX 099119861 阳片21的控制信號在切換通道成功後，控制所述的指 不裝置23指示當前正在測試的埠號，並根據主機板多硬 碟璋測試系統1 〇對校驗資料的驗證結果指示當前正在測 表單編號A0101 第7頁/共22頁 0992035117-0 201201012 試的埠是否正常，還可以控制指示裝置2 3顯示全部埠都 測試完畢的資訊。在本實施例中，該指示裝置2 3可以是 七段LED (Light Emitting Diode，發光二極體）數位 管’通過顯示的數值指示正在測試的埠號，例如，顯示 數值閃爍則指示當前正在測試的埠異常，顯示數值穩定 指示埠正常，再如顯示“L”或其它非數值記號表示全 部埠已測試完畢。 [0012] 如圖3所示，是本發明主機板多硬碟埠測試系統的功能模 組圖。所述主機板多硬碟埠測試系統1〇包括：切換通道 模組101、檢測通道模組102、寫校驗資料模組103、讀 校驗資料模组1〇4、驗證模組105、發送模組、擦除 資料模組107。 [0013] 切換通道模組1 〇 1用於切換與待測埠相連的M U X晶片21的 相應通道與儲存設備22連接。在本實施例中，該切換通 道模組1 01將從S A T A / S A S埠組12中所選擇的待測埠號翻 譯成MUX晶片21對應的通道號，經由待測主機板11的I /〇 ' .... 埠13及測試裝置2的I/O埠25雖ΐ該道號傳送到所述I/O 埠轉換模組24，該I/O埠轉換模組24將該通道號轉換成所 述MUX晶片21的控制信號’如12C或SPI控制信號，以控 制MUX晶片21切換該通道與儲存設備22連接。從而形成_ 條從待測主機板11到儲存設備2 2的資料傳輸路徑。 [0014] 檢測通道模組102用於檢測測試裝置2的儲存設備22是否 連接好，在本較佳實施例中’若已連接好則主機i會指示 多一㈣移動磁片，繼續測試；若未連接好則主機W 任何指示，測試失敗。在其它實施例中，可用其它方式 0992035117-0 099119861 表單編號Α0101 第8頁/共22頁 201201012 表示該儲存設備22是否與MUX晶片21連接好。當儲存設備 22與MUX晶片21連接好後，該MUX晶片21驅動指示裝置23 顯示該當前正在測試的埠號。 [0015]寫校驗資料模組103用於向儲存設備22發送一寫入命令， 所述寫入命令通過上述形成的資料傳輸路徑，也即從 S A T A / S A S埠組12所選擇的一個待測埠以及對應的測試裝 置2的SATA/SAS埠’再經由MUX晶片21切換後的通道，將 校驗資料傳送至所述儲存設備22並儲存。 〇 [0016]讀校驗資料模組104用於向儲存設備22發送一讀出命令以 讀出剛剛寫入儲存設備22的校驗資料，該讀出命令通過 上述資料傳輸路徑將校驗資料從儲存設備22中讀出。 [0017] 驗證模組105通過比對從儲存設備22中讀出的校驗資料與 寫入儲存設備22的校驗資料是否一致來驗證待測埠是否 正常。 [0018] 發送模組106用於向MUX晶片21發送當前正在測試的埠正 q 常或異常的資訊。在本實施例中，當驗證模組105驗證寫MUX 099119861 The control signal of the positive film 21 controls the finger device 23 to indicate the nickname currently being tested after the switching channel is successful, and according to the verification result of the calibration data of the motherboard multi-hard disk test system 1 〇 The current test form number A0101 Page 7 / Total 22 page 0992035117-0 201201012 Whether the test is normal, you can also control the indicator device 2 3 to display the information that all the tests have been completed. In this embodiment, the indicating device 2 3 may be a seven-segment LED (Light Emitting Diode) digital tube' indicating the nickname being tested by the displayed value, for example, the display value flashing indicates that the indicator is currently being tested. The 埠 anomaly indicates that the value stability indicator is normal, and the display “L” or other non-numeric token indicates that all 埠 has been tested. [0012] As shown in FIG. 3, it is a functional block diagram of the multi-hard disk test system of the motherboard of the present invention. The motherboard multi-hard disk test system 1 includes: a switch channel module 101, a detection channel module 102, a write verification data module 103, a read verification data module 1〇4, a verification module 105, and a transmission Module, erase data module 107. [0013] The switching channel module 1 〇 1 is used to switch the corresponding channel of the M U X wafer 21 connected to the 待 to be connected to the storage device 22. In this embodiment, the switching channel module 101 translates the to-be-measured nickname selected from the SATA/SAS group 12 into the channel number corresponding to the MUX chip 21, and passes the I/〇' of the motherboard 11 to be tested. The I13 and the I/O 埠25 of the test device 2 are transferred to the I/O 埠 conversion module 24, and the I/O 埠 conversion module 24 converts the channel number into a The control signal of the MUX chip 21, such as 12C or SPI control signal, is controlled to switch the MUX chip 21 to switch the channel to the storage device 22. Thereby, a data transmission path from the motherboard 11 to be tested to the storage device 22 is formed. [0014] The detection channel module 102 is configured to detect whether the storage device 22 of the testing device 2 is connected. In the preferred embodiment, if the connection is good, the host i will instruct one (four) mobile magnetic disk to continue testing; If it is not connected, the host W will give any indication and the test will fail. In other embodiments, other methods may be used. 0992035117-0 099119861 Form No. 1010101 Page 8 of 22 201201012 indicates whether the storage device 22 is connected to the MUX wafer 21. When the storage device 22 is connected to the MUX wafer 21, the MUX chip 21 drives the pointing device 23 to display the nickname currently being tested. [0015] The write verification data module 103 is configured to send a write command to the storage device 22, and the write command passes through the formed data transmission path, that is, one selected from the SATA / SAS group 12 to be tested. The SATA/SAS 埠' of the corresponding test device 2 is then transferred to the storage device 22 via the channel switched by the MUX chip 21 and stored. [0016] The read check data module 104 is configured to send a read command to the storage device 22 to read the check data just written to the storage device 22, and the read command passes the check data from the data transfer path. Read out in storage device 22. [0017] The verification module 105 verifies whether the defect to be tested is normal by comparing whether the verification data read from the storage device 22 and the verification data written to the storage device 22 are identical. [0018] The transmitting module 106 is configured to send the MUX chip 21 the information that is currently being tested or abnormal. In this embodiment, when the verification module 105 verifies the write
入與讀出的校驗資料一致時，該¥送模組106通過I/O埠 13和I/O埠25，傳送當前測試埠正常的資訊至I/O埠轉換 模組24，該I/O埠轉換模組24將資訊轉換成所述MUX晶片 21的控制信號以控制MIIX晶片21驅動指示裝置23將當前 正在測試的埠號穩定顯示來指示當前測試埠正常。反之 ’當驗證模組105驗證寫入與讀出的校驗資料不一致時， 該發送模組106傳送該當前測試埠異常的資訊至I/O埠轉 換模組24，該I/O槔轉換模組24將該資訊轉換成所述MUX 0992035117-0 099119861 表單編號A0101 第9頁/共22頁 201201012 晶片21的控制信號，以驅動指示裝置23將當前正在測試 的埠號閃爍顯示來指示當前測試埠異常。當切換通道模 組1 〇1已切換過所有的*41^晶片21的通道後，發送模組 1 〇6通過上述待測主機板Π的I/O埠13和測試裝置2的 埠2 5，發送一個結束信號至I / 0埠轉換模組2 4，該I / 〇蜂 轉換模組24將該結束信號轉換成所述MUX晶片21的控制信 號，控制MUX晶片21驅動指示裝置23顯示一個非數值記號 如符號表示全部埠已測試完畢。 [0019] [0020] [0021] [0022] 擦除資料模組107用於擦除儲存設備22中的校驗資料。當 驗證模組105驗證寫入與讀出的校驗資料一致時，即當前 測試埠功能正常後，擦除資料模组107發送一刪除命令， 擦除儲存設備22中寫入及儲存的校驗資料》 如圖4所示，係本發明主機板多硬碟埠測試方法較佳實施 例的流程圖。 步驟S201 ’切換通道模組101從待;:測..主機..扳I!的sata/ S A S埠組1 2中選擇一個待測試埠，讀g換通道模組丨〇 j將 该待測試瑋號翻譯成M U X晶片21對應的通道號，再經由待 測主機板11的I/O埠13及測試裝置2的I/O埠25將該通道 號傳送到所述I/O埠轉換模組24，該I/O埠轉換模組24將 該通道號轉換成所述MUX晶片21的控制信號，如I2C或 SPI控制信號，以切換該MUX晶片21的通道與儲存設備22 連接，形成一條從待測主機板11到儲存設備2 2傳輸資料 的路徑。 步驟S202，檢測通道模組1〇2檢測錯存設備22與mux晶片 099119861 表單編號A0101 第10頁/共22頁 0992035117-0 201201012 [0023] 21是否連接好。在本實施例中’若已連接好則主機指示 多一個可移動磁片，進入步驟S203 ;若未連接好，則主 機無任何指不’進入步驟S 2 0 8，測試失敗。 步驟S203 ’ MUX晶片21驅動指示裝置23顯示該待測淳的 埠號。 [0024] 步驟S204，寫校驗資料模組103向儲存設備22發送一寫 入命令，所述寫入命令通過步驟S201形成的資料傳輸路 徑向儲存設備22寫入校驗資料並儲存。 Ο [0025] 步驟S205，讀校驗資料模組104向儲存設備22發送一讀 出命令，所述讀出命令’經由步驟S201形成的傳輸資料 的路徑’將剛剛寫入儲存設備22的校驗資料再從該儲存 設備22讀出到待測主機板11。 [0026] 步驟S206 ’驗證模組1〇5通過比對從儲存設備22中讀出 的校驗資料與寫入儲存設備22的校驗資料是否一致來驗 G [0027] 證該待測埠是否正常，當驗證模組1〇5驗證寫入與讀出的 校驗資料不一致，進入步驟S2Q7 ;如一致’即當前所測 試的埠功能正常後，進入步驟S209 » 步驟S207，發送模組1〇6將當前測試埠異常的資訊通過 I/O埠13、I/O埠25，發送到I/O埠轉換模組24，I/O埠 轉換模組24將該資訊轉換成所述Μυχ晶片21的控制信號， 以驅動指示裝置23將當前正在測試的埠號閃爍顯示來指 示當則測試埠異常，並進入步驟S208，表明測試失敗， 結束測試。 [0028] 099119861 步驟S209 ’發送模組1 〇6將當前測試埠正常的資訊通過 表早編號A0101 第11頁/共22頁 0992035117-0 201201012 [0029] [0030] [0031] [0032] [0033] [0034] I/O埠13、I/O埠25，發送到I/O埠轉換模組24，1/〇埠 轉換模組24將該資訊轉換成所述晶片21的控制信號， 以驅動指示裝置23將當前正在測試的埠號穩定顯示來指 示當前測試埠正常。 步驟S210，擦除資料模組107發送一刪除命令，擦除儲存 設備22中寫入及儲存的校驗資料。 步驟S211，若SATA/SAS埠組12中還有未測試的埠，則返 回步驟S201，若SATA/SAS埠組12中所有的埠均測試完畢 時，進入步驟S212，測試成功，發送模組1〇6將測試完畢 的資訊通過1/〇埠13和1/〇埠25，發送到1/〇璋轉換模組 24，該I/O埠轉換模組24將該資訊轉換成所述Μυχ晶片21 的控制信號，以驅動指示裝置23指示全部埠已測試完畢 的資訊。 在步驟S204中，當不能寫入校驗資料時，退出測試系統 ，測試失敗。 在步驟S205中，當不能讀出校，^料時，退出測試系統 ，測試失敗。 在步驟S210中，當不能擦除校驗資料時，退出測試系統 ，測試失敗。 最後應說明的是，以上實施方式僅用以說明本發明的技 術方案而非限制，儘管參照較佳實施方式對本發明進行 了詳細說明’本領域的普通技術人員應當理解，可以對 本發明的技術方案進行修改或等同替換，而不脫離本發 明技術方案的精神和範圍。 099119861 表單編號Α0101 第12頁/共22頁 0992035117-0 201201012 【圖式簡單說明】 [0035] 圖1係為本發明主機板多硬碟埠測試系統較佳實施例的架 構圖。 [0036] 圖2係為待測主機板與測試裝置硬碟埠的連接方式示意圖 [0037] 圖3係為本發明主機板多硬碟埠測試系統的功能模組圖。 [0038] 圖4係為本發明主機板多硬碟埠測試方法較佳實施例的流 程圖。When the checksum data is the same as the read verification data, the ¥ send module 106 transmits the current test normal information to the I/O埠 conversion module 24 through the I/O埠13 and the I/O埠25, the I/ The O埠 conversion module 24 converts the information into control signals of the MUX wafer 21 to control the MIIX wafer 21 drive instructing device 23 to stably display the nickname currently being tested to indicate that the current test is normal. Conversely, when the verification module 105 verifies that the written and read verification data are inconsistent, the transmission module 106 transmits the current test anomaly information to the I/O conversion module 24, and the I/O conversion module The group 24 converts the information into the control signal of the MUX 0992035117-0 099119861 Form No. A0101, page 9 / page 22 2010201012, to drive the pointing device 23 to flash the currently-tested nickname to indicate the current test埠abnormal. After the switching channel module 1 〇1 has switched all the channels of the *41^ chip 21, the transmitting module 1 〇6 passes through the I/O 埠 13 of the motherboard to be tested and the 埠 2 5 of the testing device 2, Sending an end signal to the I/O conversion module 24, the I/〇 conversion module 24 converts the end signal into a control signal of the MUX chip 21, and controls the MUX chip 21 to drive the indication device 23 to display a non- Numeric tokens such as symbols indicate that all have been tested. [0022] [0022] The erasure data module 107 is used to erase the verification data in the storage device 22. When the verification module 105 verifies that the written and read verification data are consistent, that is, after the current test function is normal, the erase data module 107 sends a delete command to erase the write and store verification in the storage device 22. As shown in FIG. 4, it is a flowchart of a preferred embodiment of the multi-hard disk test method for the motherboard of the present invention. In step S201, the switching channel module 101 selects a to-be-tested one from the sata/SAS group 1 2 of the test.. The number is translated into the channel number corresponding to the MUX chip 21, and the channel number is transmitted to the I/O埠 conversion module 24 via the I/O port 13 of the motherboard 11 to be tested and the I/O port 25 of the test device 2. The I/O conversion module 24 converts the channel number into a control signal of the MUX chip 21, such as an I2C or SPI control signal, to switch the channel of the MUX chip 21 to the storage device 22 to form a slave station. The path of the data transfer from the motherboard 11 to the storage device 2 is measured. Step S202, the detection channel module 1〇2 detects the faulty device 22 and the mux chip. 099119861 Form No. A0101 Page 10 of 22 0992035117-0 201201012 [0023] 21 is connected. In the present embodiment, if the host is connected, the host indicates one more removable disk, and the process proceeds to step S203; if not, the host does not have any indications. The process proceeds to step S208, and the test fails. Step S203' MUX wafer 21 drives the pointing device 23 to display the nickname of the test to be tested. [0024] Step S204, the write verification data module 103 sends a write command to the storage device 22, and the write command writes the verification data and stores it through the data transmission path radial storage device 22 formed in step S201. [0025] Step S205, the read verification data module 104 sends a read command to the storage device 22, and the read command 'path of the transmission data formed via step S201' will be written to the verification of the storage device 22. The data is then read from the storage device 22 to the motherboard 11 to be tested. [0026] Step S206 'The verification module 1〇5 verifies whether the test data is verified by comparing whether the check data read from the storage device 22 and the check data written to the storage device 22 are identical. Normally, when the verification module 1〇5 verifies that the written data is inconsistent with the read verification data, the process proceeds to step S2Q7; if the same, that is, the currently tested 埠 function is normal, the process proceeds to step S209: Step S207, the transmission module 1〇 The information of the current test 埠 abnormality is sent to the I/O 埠 conversion module 24 through the I/O 埠 13, I/O 埠 25, and the I/O 埠 conversion module 24 converts the information into the Μυχ wafer 21 . The control signal is used to drive the pointing device 23 to flash the nickname currently being tested to indicate that the test 埠 is abnormal, and proceeds to step S208 to indicate that the test has failed and ends the test. [0028] 099119861 Step S209 'Transmission module 1 〇6 will be the current test 埠 normal information through the table early number A0101 page 11 / total 22 page 0992035117-0 201201012 [0029] [0031] [0032] [0033 [0034] I/O埠13, I/O埠25, sent to the I/O埠 conversion module 24, and the 1/〇埠 conversion module 24 converts the information into a control signal of the wafer 21 to drive The pointing device 23 displays the nickname currently being tested stably to indicate that the current test is normal. In step S210, the erasure data module 107 sends a delete command to erase the verification data written and stored in the storage device 22. In step S211, if there are untested defects in the SATA/SAS group 12, the process returns to step S201. If all the ports in the SATA/SAS group 12 are tested, the process proceeds to step S212, and the test is successful, and the module 1 is sent. 〇6 sends the tested information to the 1/〇璋 conversion module 24 through 1/〇埠13 and 1/〇埠25, and the I/O埠 conversion module 24 converts the information into the silicon wafer 21. The control signal is used to drive the pointing device 23 to indicate all the information that has been tested. In step S204, when the verification data cannot be written, the test system is exited and the test fails. In step S205, when the calibration cannot be read, the test system is exited and the test fails. In step S210, when the verification data cannot be erased, the test system is exited and the test fails. It should be noted that the above embodiments are only for explaining the technical solutions of the present invention, and are not intended to be limiting, although the present invention has been described in detail with reference to the preferred embodiments. Modifications or equivalents are made without departing from the spirit and scope of the invention. 099119861 Form No. Α0101 Page 12 of 22 0992035117-0 201201012 [Simplified Schematic] [0035] FIG. 1 is a block diagram of a preferred embodiment of a multi-hard disk test system for a motherboard of the present invention. 2 is a schematic diagram of a connection mode between a motherboard to be tested and a hard disk of a test device. [0037] FIG. 3 is a functional block diagram of a multi-hard disk test system for a motherboard of the present invention. 4 is a flow chart of a preferred embodiment of a multi-hard disk test method for a motherboard of the present invention.
【主要元件符號說明】 [0039] 主機1 [0040] 待測主機板11 [0041] SATA/SAS 槔組 12，20 [0042] I/O埠 13，25 [0043] 測試裝置2 [0044] MUX晶片21 & [0045] 儲存設備2 2 [0046] 指示裝置23 [0047] I/O埠轉換模組 24 [0048] 主機板多硬碟埠測試系統10 [0049] 切換通道模組 101 [0050] 檢測通道模組 102 表單編號A0101 第13頁/共22頁 '.a ： 099119861 0992035117-0 201201012 [0051] 寫校驗資料模組103 [0052] 讀校驗資料模組104 [0053] 驗證模組105 [0054] 發送模組106 [0055] 擦除資料模組107 099119861 表單編號A0101 第14頁/共22頁 0992035117-0[Main component symbol description] [0039] Host 1 [0040] Test board to be tested 11 [0041] SATA/SAS 槔 group 12, 20 [0042] I/O 埠 13, 25 [0043] Test device 2 [0044] MUX Wafer 21 & [0045] Storage device 2 2 [0046] Indication device 23 [0047] I/O conversion module 24 [0048] Motherboard multi-hard disk test system 10 [0049] Switching channel module 101 [0050] ] Detection Channel Module 102 Form No. A0101 Page 13 of 22 '.a : 099119861 0992035117-0 201201012 [0051] Write Calibration Data Module 103 [0052] Read Calibration Data Module 104 [0053] Verification Module Group 105 [0054] Transmitting Module 106 [0055] Erasing Data Module 107 099119861 Form Number A0101 Page 14 of 22 0992035117-0