TWI309779B - Testing system and testing method for link control card - Google Patents
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- TWI309779B TWI309779B TW94127460A TW94127460A TWI309779B TW I309779 B TWI309779 B TW I309779B TW 94127460 A TW94127460 A TW 94127460A TW 94127460 A TW94127460 A TW 94127460A TW I309779 B TWI309779 B TW I309779B
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1309779 九、發明說明: 【發明所屬之技術領域】 本發明涉及一種鏈結控制卡測試系統及方法。 【先前技術】 隨著資訊技術之發展,磁碟陣列越來越多應用於企 J用土統中。它開始只是簡單作爲某台主機或伺服器之附加外牙 存儲设備,主要用於擴展單台主機或伺服器之永久 般透過 SCSI (Small computer System Interface,小 二 面)或其他介面與主機直接相s;後來隨光纖通 ^ 技術之發展,磁碟陣列透過光纖通道介面接入到(sa annel) 蝴,— 拓ϊΐϊ架型光纖通道存儲設備通常由兩片鏈結控制卡、中間 磁碟陣列及電馳成,在光_道存儲設備 7、= 成磁碟陣列讀寫測試,記錚測•士旲,二L透過廷種方式來完 能,酬試絲需大量光纖 長期’且磁碟也容易在受到震動d 功/二;議早―’其無法測試麟控制卡之另一 準電愿上下浮動日猶結控制卡有可能;J =^工_壓偏離標 2傳輸之光纖通道峨會失真,無法確^ 傳輸,則該産品不能滿足客戶之測試要/丄滅通道-虎可祕 7 1309779 於測麟㈣相辦賊方法,用 —,鏈結控制卡測試系統,其包括: —帶有主機匯流排適配器之主機; 鍵結控制卡’其第一端連接至主機,兮 流排適配器發送光纖通訊號 ^ ,仏 —中間板,其第-端與該鏈結控制卡 一測試裝置陣列,额射㈣夕—弟—&相連接,及 :亥測4裝置陣列相連接以發送測試 。 该測試裝置陣列由複數測辦¥έΒ 士—魏測之'°果’ -微控 裝置組成,每—賴裝置包括·· 纖通道訊 1該微控ϋ連接之介面連姑,祕接收光 -與該介面連接料接之光_道躲器,餘 收之光纖通道訊號進行訊號完整性測試.、. -與該微㈣n連接之錢姉 鏈結控制卡之工作電壓極限;』早凡職控制。亥 一與該微控制器連接之位址設定單元.及 該每一測試裝置透過該第-串列糊 種鏈結控制卡測試方法,其用於測試—鏈結 罪性,該鏈結控制卡測試方法包括以下步驟:、、卫 ,定二測試裝置陣列中每-測試裝置之各別位址; 偵測每一測試裝置所設定之位址, 1 —之每-測試裝置之微控制器中;工將料位址保存在對應 —主機發送1_道職_鏈結㈣卡 該光纖通道訊號到每-測試裝置; 由中間板刀 遠主機發送一測試命令至該測試裝置陣列中其中一測試裝 8 1309779 置; ’ 該一測試裝置偵測該測試命令中之所包含的位址與其所 之位址是否一致; 若一致’則該一測試裝置設置該鏈結控制卡工作電壓模式; 該:測試裝置對所接收之光纖通道訊號進行訊號完整 試,並將測試結果傳給主機。 、 相較習知測試裝置’由於本發明在鏈結 置陣列來替代磁碟陣列,透過對 通道訊號進行完整性測試,來間接測試鏈 =確絲纖通道訊號可靠性傳輸,採用本發明=試== 法^則试過程快速而效,滿足客戶之測試要求。… 【實施方式】1309779 IX. Description of the Invention: [Technical Field] The present invention relates to a link control card test system and method. [Prior Art] With the development of information technology, disk arrays are increasingly used in enterprise systems. It started as a simple external storage device for a host or server. It is mainly used to extend the permanent SCSI (Small Computer System Interface) or other interface directly to the host. Phase s; later with the development of fiber-optic technology, the disk array is connected to the (sa annel) through the fiber channel interface. - The top-of-rack Fibre Channel storage device usually consists of two link control cards and an intermediate disk array. And electricity, in the light_channel storage device 7, = into the disk array read and write test, record • test • gentry, two L through the way to complete the performance, the test wire requires a large number of fiber long-term and disk It is also easy to be subjected to vibration d / 2; early - "It is impossible to test the other control of the Lin control card. It is possible to freeze the control card. J = ^ _ _ pressure deviation from the standard 2 transmission of the Fibre Channel 峨Will be distorted, can not be confirmed ^ transmission, then the product can not meet the customer's test / annihilation channel - Tiger can be secret 7 1309779 in the measurement of the Lin (four) phased thief method, with -, link control card test system, which includes: - With host bus The host of the adapter; the junction control card 'the first end is connected to the host, the bus bar adapter sends the fiber communication number ^, the 中间-intermediate board, the first end and the link control card are a test device array, the front shot (four) Xi-Di-& is connected, and: the Hai 4 device array is connected to send the test. The test device array is composed of a plurality of measurement and control devices, such as the '° fruit'-micro control device, and each of the devices includes: · fiber channel communication 1 the micro-control device is connected to the interface, the secret receiving light - The light source _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ . An address setting unit connected to the microcontroller, and each test device passes the first-series paste chain control card test method, which is used for testing-linking crime, the link control card The test method comprises the following steps:, wei, and the respective addresses of each test device in the test device array; detecting the address set by each test device, 1 - each per-test device in the microcontroller The worker saves the material address in the corresponding--the host sends the 1_Tao_link (four) card to the Fibre Channel signal to each-test device; the intermediate board sends the remote command to the host to send one test command to one of the test device arrays. 8 1309779; 'The test device detects whether the address included in the test command is consistent with the address of the test command; if it is consistent', the test device sets the link control card working voltage mode; The test device performs a complete signal test on the received Fibre Channel signal and transmits the test result to the host. Compared with the conventional test device, since the present invention replaces the disk array in the chain array array, through the integrity test of the channel signal, the indirect test chain = the fiber channel signal reliability transmission, using the present invention = test == Method ^ The test process is fast and effective, meeting the customer's testing requirements. ... [Embodiment]
Bus Adaptor)之主機 100、一由複 -°。 A (Host ,、-中間板3。、一第一: 50、一第一電源6〇及一第二 弟一鏈、.,。控制卡 該測試裝㈣肋G相連用於透過—串列埠與 該主機觸透過兩根光纖結果, 二鏈結控制卡50之第一端,用、、^第;;鍵、、Ά制卡40、第 之第-端與該第—鏈結控制卡4〇 x ^纖通道訊號,該中間板30 連接,該中間板30之第二端轉控制卡5〇之第二端 HBA輸出兩路標準光纖 =序串接而成。邊主機100經 40、該第二鏈結控制卡50後,由過該第一鏈結控制卡 配給測試裝置陣列中每―取裝^板3G將該光纖通道訊號分 請-併參考圖第二圖,其爲;發明^控制卡測試系統中每 9 1309779 一測試置1之原理框圖,每一測試裝置丨包括: 一微控制器10,該微控制器10採用PIC18F6520晶片,其内 部存儲一韌體(Firmware) ’該晶片内部設有寄存器,該晶片支援 兩個RS232串列埠、一個HC匯流排; 一介面連接器 SCA2 ( Single Connector Attach 2 ) 11,其與微 控=ίο連接’該介面連接器u滿足光纖通道硬碟介面sff_8〇45 ,範,並具熱插拔功能,在第一圖中測試裝置陣列2〇〇之每一測 試裝置1均透過該介面連接器n與中間板3〇之第二端相連接, 來接收中間板30所分配之光纖通道訊號; 一光纖通道集線器12,其與該介面連接器u相連接,用於對 所接收之光纖通道訊號進行測試,該光纖通道集線器採用 BCM8422 ; ’該晶片内财寄存^,同輕w具有檢測訊號Bus Adaptor) host 100, one by -°. A (Host, - intermediate plate 3., first: 50, a first power supply 6〇 and a second brother, a chain, .. control card, the test device (four) rib G is connected for transmission - serial 埠The first end of the two-link control card 50 is used to contact the host, and the first end of the two-link control card 50 is used to make a key, the card 40, the first end, and the first link control card 4中间x ^ fiber channel signal, the intermediate board 30 is connected, the second end of the intermediate board 30 is controlled by the second end HBA of the control card 5 输出 output two standard optical fibers = serially connected. The side host 100 passes 40, the After the second link control card 50, the first link control card is assigned to each of the pick-up boards 3G in the test device array to separate the fiber channel signals - and refer to the second figure of the figure, which is the invention ^ A control block diagram of every test set in the control card test system, each test device includes: a microcontroller 10, which uses a PIC18F6520 chip, which internally stores a firmware (Firmware) There are registers inside the chip, the chip supports two RS232 serial ports, one HC bus bar; one interface connector SCA2 ( Single Co Nnector Attach 2 ) 11, which is connected with the micro control = ίο 'the interface connector u meets the Fibre Channel hard disk interface sff_8 〇 45, and has a hot plug function. In the first figure, the test device array 2 Each test device 1 is connected to the second end of the intermediate board 3 through the interface connector n to receive the fiber channel signal allocated by the intermediate board 30; a fiber channel hub 12, which is connected to the interface connector u Connection, used to test the received Fibre Channel signal, the Fibre Channel hub uses BCM8422; 'The internal memory of the chip ^, the same light w has a detection signal
完整性 SI (SignalIntegrity),框起始 s〇F(Start OfFrame),訊轳P 耗 LOS(Loss Of Signal)等功能; 0 儿貝 :I2C電平轉換單元13 ’其連接於該微控制器1〇與該光 ^線器12之間’該微控制器1G與該光纖通道集線器12透過1 ^排傳輸資料,該I2C電平轉換單元13用於爲既 傳輸之訊號進行電平轉換; 卩上所 二極if 繼料狀^ (吻如―,發光 兮LE^單早W f於對每—測試裝置1之測試狀態進行顯示, Λ 燈,該每—職㈣1在對先纖通道可 束時’若該每一測試裝置丨侧出錯誤,該紅产 二控制器1G連接之電壓極限控制單元15,用ϋ制第 2結控制卡4G或第二鏈結控制卡5G之工二於^弟 该苐-鏈結控制卡40或第二鏈結控制卡50之工作可=末驗通 一,該微控制器10連接之位址設定單元16 ; 傳出;第—串列璋〗7 ’其爲則2串列埠,其用於將測試結果 10 1309779 一第二串列埠18 ,其亦爲RS232串列埠。 接方Si圖= 過串列埠與測試裝置陣列之連 接方式如下.主機1〇〇透過串列4與第 埠17相連,第-測試裝置i之第二 =置/一之第一串列 其他測縣置丨均_接,法_置陣列中 口月併參考第二圖’其爲本發明鏈結 、^ ^ — 測試裝置丨之位址設定料電路圖,每—測糸統中= 單元16與該微控制器10連接,該定:之位址汉疋 連接時’ A0設定爲1 ”;當j〇 二之腳位1和2 ‘oour、“〇011,’、 “1000” 、 “1001” 、 '1Η〇” ,即每一測 “0”,該j W2、J3設置方法與J〇相^故==0 =定爲 輸入值依次可選取“0000”、“〇〇〇1 ” 再重禝,則位址 “0100” ' “0101” 、 “0110” 、 “〇111” “1010” 、 “1011” 、 “1100” 、 “11〇1 試裝置1可設定之位址範圍爲0至14。 測j =參考細圖,其爲本發明鏈結控制卡測試祕中每-圖,V、㈣厂之電壓極限控制單元15在本發明測試系统中之干音 了結控制卡,第= 高模式時工作鮮 靠度,在偏 標準之-5%,如下表丨所示。 在偏低核式蚪工作電壓偏離 -~電壓模式之工作雷懕Integrity SI (SignalIntegrity), frame start s〇F (Start OfFrame), 轳 LS (Loss Of Signal) and other functions; 0 儿贝: I2C level conversion unit 13 ' is connected to the microcontroller 1 Between the 光 and the optical line controller 12, the microcontroller 1G and the Fibre Channel hub 12 transmit data through 1 排, and the I2C level converting unit 13 is configured to perform level conversion for the transmitted signal; The second pole if the material shape ^ (kiss like ", the light 兮 LE ^ single early W f in the test state of each test device 1 is displayed, Λ light, the each - (4) 1 in the fiber channel can be bundled 'If there is an error in the side of each test device, the voltage limit control unit 15 connected to the red controller 2G is used to control the second junction control card 4G or the second link control card 5G. The operation of the 苐-link control card 40 or the second link control card 50 can be = the last pass, the address 10 of the microcontroller 10 is connected; the outgoing; the first - the serial 璋 7 ' For the 2 series, it is used to test the result 10 1309779 a second string 埠18, which is also RS232 serial 埠. Si Si diagram = over series 埠 测The connection mode of the test device array is as follows. The host 1 is connected to the third node through the serial 4, and the first test device i is the second = set/one of the first series. In the array of the mouth and month and refer to the second figure 'which is the link of the invention, ^ ^ - test device 设定 address setting material circuit diagram, each - 糸 = = unit 16 is connected with the microcontroller 10, the : When the address is connected, 'A0 is set to 1'; when j〇2's feet 1 and 2 'oour, '〇011,', '1000', '1001', '1Η〇', ie each Measure "0", the j W2, J3 setting method and J 〇 phase = 0 = set as the input value, then select "0000", "〇〇〇1" and then repeat, then the address "0100" “0101”, “0110”, “〇111” “1010”, “1011”, “1100”, “11〇1 test device 1 can be set to address from 0 to 14. Measure j = reference fine picture, For the link control card test secret of the present invention, the voltage limit control unit 15 of the V and (4) plants in the test system of the present invention has a dry sound control card, and the work is fresh in the first mode. Degrees, 5% vinylidene standards, as shown in the lower core sheet formula tadpole operating voltage departing Shu -. ~ Mine working voltage mode of Yan
2.5V 〜模式 土2.5V ~ mode
5* (1+5%) =5.25V5* (1+5%) = 5.25V
2-5* ( 1+5%) =2.625V 5* ( 1-5%) =4.75v2-5* ( 1+5%) = 2.625V 5* ( 1-5%) =4.75v
^ 阳丄---——^… 2·5* (1-5%) =2_37W 四θ 中每- 1309779 紐控鮮元15爲麵議1G所發出之 i ^ 繼訊號分別 margin m N B ' margin-^〇-N_b ^ 制卡4〇之電壓極限,MARGIN L0 N B、 Γ可是控制第二鍵結控制卡50之電壓極限:第四圖 ΐ第[鏈結控制卡4〇 卡40或該第二鏈結控:現控_—鍵結控制 圖,其爲本發明鏈結控制卡測試方法之流程 S” ======?驟 一測試震置i所設定下置之位址是“_”,每 編號 111¾¾ 置 0110 1001 弟十一測試紫罡T~77^r~t~— 〜Α~~μ上州 哭 立對應之每一測試裝置1之微控制器10之寄存 2 10之寄存器中’第二測試装置 =在: 控制器10之寄存器中,第三測物 保 微控制器10之寄街,同理其他測試裝置W將對應 12 1309779 在其微控制器10之寄存器中; 機100透過HBA發送標準光纖通道訊號到第一鏈結控制卡 或第二鍵結控制卡5〇,由中間板3〇分配該標準光纖通道訊號 到母一測試裝置1(步驟S3); 豆φί機2〇〇透過其串列埠發送一測試命令至該測試陣列20〇中 i 式裝置Κ步驟弘)’該測試命令包含一設置第一鏈結控制 :人入或第二鏈結控制卡5〇工作電壓模式命令、一測試訊號完整 卩々、一預設光纖通道訊號之標準相位資料及一預設置位址, 该預設^位址爲“〇_,,至“ 111〇”中任何一個位址; 哕制置1之第一串列槔17接收到上述測試命令,憤測 s^、;e °卩中所包含之位址與其所保存之位址是否一致(步驟 另一 3==該—測試裝置1將該測試命令傳至與其串接之 5,,、斤〇3之位址與其所保存之位址是否一致(步驟S5),若一 褒置=彳不—致’廳續進行倾S6,依此該測試 矛置陣列200中其它測試裝置1逐一進行偵測;當一致眭,# 測試裝置i直接進行步驟S7。進订制,田料,该- 測試ί :存之位址與該測試命令中所包含之位址-致之 壓ίίί 第—鏈結控制卡40或第二鏈結控制卡50卫作電 作電Τ置第’結控制卡4G或第二鏈結控制卡50工 朗試裝置1之光纖通道集線器12對所接收之光 S3號進了喊完整_試,其具體如下:_錄置1之微 二2為之命令巾所包含之標準相位資料寫人光纖通道集i i所接收通,曾1=戴通道集線器12設定一框格式,然後 資料做比#,/〜進仃_ ’將雜#之資料與標準相位 他认右兩者不_,職錯誤,若兩者_,關正確, 13 1309779 .時’測财置1將測試結果傳給主機,若測試裝置1 貞/貝]到錯误,則紅燈亮起(步驟S8)。 在步驟S4中,可透過一根線境將該一測試裝置i辦 或丨Γ字工作電顧式命令傳送給第一鏈結控制卡奶 ^ j 制卡5G之工作電壓。本發明實補選取第一測試聲^ Yangshuo----^... 2·5* (1-5%) =2_37W Four θ per -1309779 New control fresh element 15 is negotiable 1G issued by i ^ relay signal respectively margin m NB ' margin -^〇-N_b ^ The voltage limit of the card 4〇, MARGIN L0 NB, Γ can control the voltage limit of the second bond control card 50: the fourth figure ΐ [link control card 4 〇 card 40 or the second Chain control: the current control _-key control chart, which is the flow of the test method of the link control card of the invention S" ======? The address set by the test set i is "_ ", each number 1113⁄43⁄4 set 0110 1001 brother eleven test purple 罡T~77^r~t~-~Α~~μ Shangzhou crying corresponding to each test device 1 of the microcontroller 10 register 2 10 register In the 'second test device=in: the register of the controller 10, the third test object holds the street of the microcontroller 10, and the other test device W will correspond to the register of 12 1309779 in its microcontroller 10; 100 sends a standard Fibre Channel signal to the first link control card or the second bond control card 5 through the HBA, and the standard Fibre Channel signal is distributed by the intermediate board 3 to the parent test device 1 (step S3); Bean φ 机 2 〇〇 through its serial 埠 send a test command to the test array 20 i i i device Κ step 弘) 'The test command contains a set first link control: human into or second The link control card 5 〇 working voltage mode command, a test signal complete 卩々, a preset phase channel data of a preset Fibre Channel signal, and a preset address, the preset ^ address is “〇_,, to “111任何 任何 任何 任何 任何 ; ; ; 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收The other 3 == the test device 1 transmits the test command to the 5 connected thereto, and the address of the battery 3 matches the address it holds (step S5), if a device = not - To the 'room continues to tilt S6, according to which the other test devices 1 in the test spear array 200 are detected one by one; when consistent, the # test device i directly proceeds to step S7. Order, field, the test ί : the address of the save and the address contained in the test command - the exact number of the link control card 40 or Two-link control card 50 Guardian electric power device No. 'Just control card 4G or second link control card 50 Industrial test device 1 Fibre Channel hub 12 to the received light S3 number shouted complete _ test The specifics are as follows: _ Recording 1 of the micro 2 2 for the standard phase data contained in the command towel written by the Fibre Channel set ii received, Zeng 1 = wearing a channel hub 12 to set a frame format, and then the data to do than # , / ~ 进仃_ '将杂# The data and the standard phase he recognizes the right two are not _, job error, if both _, off correctly, 13 1309779. When 'measure the wealth set 1 to pass the test results to the host, If the test device 1 is erroneous, the red light is on (step S8). In step S4, the test device i or the 工作 word work mode command can be transmitted to the working voltage of the first link control card milk card 5G through a line. The invention complements the first test sound
St中間板3G相連接(第—圖未示出)。步㈣中ί 一 式 或弟:鏈結控制卡50是在標準、高、低三種工作電壓模 > i打=則第一測試裂置1之電壓極限控制單元15在標準· 气%測5式,即设置5ν、2·5ν電壓來測試;在電壓偏高模式下例 tl =置5.25V、2·625ν電壓來測試;_在電壓偏低模式下, Ρ 口又置4.75 V、2.375 V電壓來測試。 壯罢^步驟S8巾,該測試絲係經由該最先接㈣試命令之測試 j傳給主機1〇〇。#光纖通道職完整性測·由最先接收測試 二二測試裝置完成時,制試絲係直接_最先接收測試命 二《測,裝置傳給主機歐若職結果係非_最先接收測試命 二測巧置完成時’則完成該測試結果之測試裝置將測試結果 八运到該最先接收測試命令之測試裝置,再由該最先接收測試命 7之測試裝置傳給主機100。 在上述本發明之實施例中,主機100經HBA發送兩路標準光 40通、3^訊號,該兩路標準光纖通道訊號分別透過第一鏈結控制卡 、―或ί—鍵結控制卡50 ’由中間板30分配給丨5個測試裝置1 ’ 蚪先測透過其中一片鏈結控制卡之一路光纖通道訊號,再測 過另一片鏈結控制卡之另一路光纖通道訊號,設在測試透過第 測,了控制卡40之一路光纖通道訊號時’若主機1〇0讀到15個 貝°式波置1之介面連接器11所接收之光纖通道訊號之測試結果都 a害。玄主機1 〇〇顯示測試成功,表明第一鏈結控制卡40工作正 吊’若其中有任何一測試裝置1之測試結果不正確,主機〗〇〇顯 14 1309779 3試2 ’表明第一鏈結控制卡4〇工作不正常 過第一鏈結控制卡5Q之另—路光纖通道訊號時,^ 透 15個測試結果都正確,主機1GG顯示測試成功,表明^到 :卡5〇工作正常,若其中有任何一測試:置力丨控 確’ 示測試失敗,表明第二鏈結控制卡5q =正 ,冰上所述,本發明確已符合發明專利之要件 ^书。The St intermediate plate 3G is connected (not shown). Step (4) in ί 一式或弟: The link control card 50 is in the standard, high and low three working voltage modes > i hit = then the first test split 1 voltage limit control unit 15 in the standard · gas % test 5 That is, set the voltage of 5ν, 2·5ν to test; in the high voltage mode, tl = 5.25V, 2.625ν voltage is tested; _ in the low voltage mode, the port is set to 4.75 V, 2.375 V To test. Step S8, the test wire is transmitted to the host 1 via the test j of the first (four) test command. #Fiber channel job integrity test · When the first test test device is completed, the test wire system is directly _ the first to receive the test life second "test, the device is transmitted to the host Ou Ruo job results are not _ the first to receive the test When the test is completed, the test device that completes the test result transports the test result to the test device that first receives the test command, and then passes the test device that first receives the test command 7 to the host device 100. In the above embodiment of the present invention, the host 100 transmits two standard optical 40-channel and 3^ signals via the HBA, and the two standard Fibre Channel signals are respectively transmitted through the first link control card, or the ί-key control card 50. 'Assigned to the 5 test devices 1 by the intermediate board 30', the first fiber channel signal through one of the link control cards is measured, and the other fiber channel signal of the other link control card is measured. In the first measurement, when the one-way Fibre Channel signal of the control card 40 is used, the test result of the Fibre Channel signal received by the interface connector 11 of the host 1 〇 0 read to 15 °-wave type 1 is a harm. Xuan host 1 〇〇 shows that the test is successful, indicating that the first link control card 40 is working properly. If any of the test devices 1 have incorrect test results, the host 〇〇 14 14 1309779 3 test 2 ' indicates the first chain When the control card 4 is not working properly, the other link of the first link control card 5Q is the same as the Fibre Channel signal. The test result is correct. The host 1GG shows that the test is successful, indicating that the card is working properly. If there is any test in it: the force control does not indicate that the test fails, indicating that the second link control card 5q = positive, as described on the ice, the invention has indeed met the requirements of the invention patent.
Si士^上僅為本發明之較佳實施例,舉凡熟習本ίΪS :下之精神所作之等效修飾或變化,皆應 【圖式簡單說明】 Ϊ 一圖係本發明鏈結控制卡測試㈣之方框圖。 弟ίΓ本發明鏈結控制卡測财統中每—戦裝置之原理 第結控制卡_統中每 第=圖係本發明鏈結控制卡測試系統中每一 極限控制單元在本發明測試系統中之示意圖。、置之電壓 【主要法之流程圖。 主機 測試裝置 第一鏈結控制卡 第一電源 微控制器 光纖通道集線器 LED單元 位址設定單元 第二串列埠 100 1 40 60 10 12 14 16 18 置陣列2〇〇 中間板 30 第二鏈結控制卡 ;二電源 7; "面連接器 u I2C電平轉換單元 電壓極限控制單元15 第—串列埠 门 15The present invention is only a preferred embodiment of the present invention, and equivalent modifications or changes made by the spirit of the present invention should be [simplified description of the drawing] Ϊ a picture of the link control card test of the present invention (4) Block diagram. Brother Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Schematic diagram. , set the voltage [main flow chart. Host Test Device First Link Control Card First Power Microcontroller Fibre Channel Hub LED Unit Address Setting Unit Second Serial 埠100 1 40 60 10 12 14 16 18 Array 2 〇〇 Intermediate Board 30 Second Link Control card; two power supply 7; " surface connector u I2C level conversion unit voltage limit control unit 15 first - tandem trick 15
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| TW94127460A TWI309779B (en) | 2005-08-12 | 2005-08-12 | Testing system and testing method for link control card |
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| TW94127460A TWI309779B (en) | 2005-08-12 | 2005-08-12 | Testing system and testing method for link control card |
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| TWI309779B true TWI309779B (en) | 2009-05-11 |
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| TWI482016B (en) * | 2013-03-05 | 2015-04-21 | Wistron Corp | Test method for a storage device and computer program product executing the same |
| US11338586B2 (en) | 2018-12-03 | 2022-05-24 | Hewlett-Packard Development Company, L.P. | Logic circuitry |
| AU2019392181A1 (en) | 2018-12-03 | 2021-06-24 | Hewlett-Packard Development Company, L.P. | Logic circuitry package |
| EP3688636B1 (en) | 2018-12-03 | 2023-07-19 | Hewlett-Packard Development Company, L.P. | Logic circuitry |
| WO2020117776A1 (en) | 2018-12-03 | 2020-06-11 | Hewlett-Packard Development Company, L.P. | Logic circuitry package |
| EP3687815B1 (en) | 2018-12-03 | 2021-11-10 | Hewlett-Packard Development Company, L.P. | Logic circuitry |
| EP3718039B1 (en) | 2018-12-03 | 2021-08-18 | Hewlett-Packard Development Company, L.P. | Logic circuitry |
| US11250146B2 (en) | 2018-12-03 | 2022-02-15 | Hewlett-Packard Development Company, L.P. | Logic circuitry |
| EP3681723B1 (en) | 2018-12-03 | 2021-07-28 | Hewlett-Packard Development Company, L.P. | Logic circuitry |
| WO2020117198A1 (en) | 2018-12-03 | 2020-06-11 | Hewlett-Packard Development Company, L.P. | Logic circuitry |
| US10894423B2 (en) | 2018-12-03 | 2021-01-19 | Hewlett-Packard Development Company, L.P. | Logic circuitry |
| EP3844000B1 (en) | 2019-10-25 | 2023-04-12 | Hewlett-Packard Development Company, L.P. | Logic circuitry package |
| EP4031997A1 (en) | 2020-04-30 | 2022-07-27 | Hewlett-Packard Development Company, L.P. | Logic circuitry package for print apparatus |
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