TW201133826A - Power device with self-aligned silicide contact and method of fabricating thereof - Google Patents

Abstract

Catheters having a pre-shaped tip configuration are disclosed. A catheter in accordance with an illustrative embodiment of the present invention can include an elongated tubular shaft equipped with a distal tip section having a pre-shaped tip configuration that can be used to facilitate tracking of the device through particular locations of the vasculature. The catheter may include a number of features that transition the stiffness and flexibility characteristics of the device and provide a means to radiographically visualize the catheter within the body.

Description

201133826 VI. Description of the Invention: [Technical Field of the Invention] [_1] The present invention relates to a semiconductor device and a process thereof, and more particularly, to a power device and its manufacture. [Prior Art] [0002] Power devices, such as metal germanide semiconductor field effect transistors (MOS-FETs), insulated gate bipolar transistors (UGBT), super-junction MOSFETs, vertical structure double-diffused metal oxide semiconductor devices (VDMOS) ,vertical

Structured metal oxide semiconductor devices (VMOS) and the like generally have a number of excellent device characteristics such as a high breakdown voltage, a large safe operating area (SOA), and a low on-resistance. In addition, power devices have lower production costs and higher yields. A typical VDMOS device (not shown) may include a P-type body region that is aligned with the polysilicon grid. An N+ type source region and a p + type body contact region may be formed in the P type body region. The safe working area of a typical VDMOS is the same as that of the N + type source area. The length is inversely proportional, that is, the longer the length of the N+ type source region, the larger the safe working area. However, the length of a typical Nf type source region is limited by the tolerance of masking (e.g., photolithography) and alignment processes. Typical VDMOS fabrication processes include the step of multi-step lithography to mask the wafer prior to other process steps and/or other process steps (e.g., deposition, diffusion, engraving, etc.). Thus, conventional VDMOS devices make it difficult to obtain a large safe working area. In U, reducing the masking step will help reduce costs and increase production. SUMMARY OF THE INVENTION [0003] For one or more problems in the prior art, the present invention - a purpose 099130674 form number A0101 page 3 / 29 pages 0993417350-0 201133826 is provided - a kind of self-aligned social contact Power device and method of manufacturing the same. In one aspect of the invention, a power device is provided comprising: an initial layer; __; _ formed on the initial layer, and the initial layer separated by a gate oxide layer; isolation _, at least substantially Between the gate region and the edge of the contact region; a gate material layer formed on the gate region 4 and a body money foreign matter layer formed on the body contact region. In another aspect of the invention, another power device is provided comprising: a semiconductor substrate; an epitaxial layer on the surface of the casting body, the epitaxial layer having a first surface 'and (d) including at least one body contact a region, a source region, and a body region, the body region at least substantially including the body contact region and the gate field on the first surface ' gate (four) gate dielectric layer Separating from the epitaxial layer; the isolation sidewall is substantially aligned between the escape region and the edge of the body contact region; a chemical layer is formed on the grid; the body contact (8) The layer 'is formed on the substrate _ (on; and the electrode that is transferred over the contact bismuth layer. In a further aspect of the invention, a method of manufacturing a power device is proposed) includes: Forming an epitaxial layer; forming a gate gas layer on the epitaxial layer; fabricating a plurality of (four) gate regions on the gate oxide layer; and fabricating an isolation spacer wall at least substantially self-aligned with the polysilicon The edge of the reading zone; and one of the following steps (a), (b), (C) ^; (a) being formed on the solar crystal 7 gate region and the epitaxial layer; the chemical layer is at least substantially self-aligned with the isolation side; (b) at the epitaxial layer Forming a body contact zone; 099130674

0993417350-0 Form No. A0101 Page 4 of 29 201133826 The surname is carried out in the epitaxial layer, which is at least substantially self-aligned to the isolated sidewall. U. With the embodiment of the present invention, the power device is provided to increase the self-alignment process step and reduce the masking: η art step, thereby improving the control precision of the power device, increasing the output of the power device and reducing the production cost thereof. [Embodiment] [0004] Ο

G 099130674 Embodiment (4) of the present invention provides an improved power device having self-aligned debris contact and a method of fabricating the power device. In the following, the embodiment of the present invention describes the power device and the method of the vertical structure power device as an example. However, the skilled person in the art understands that the following description is also applicable to other power devices. The vertical structure force rate device includes contacts formed on the gate region and the body contact region, the step of forming the contact being performed by at least substantially a self-aligned material (e.g., self-aligned telluride). The vertical structure power device can also include one or more isolated sidewalls, each of which is aligned at least between the gate region and the edge of the body contact region. The body contact pads can be formed by at least substantially self-aligning the spacer side walls into the interior of the device. The method can also include a germanium etch process that is at least substantially self-aligned. 1 is a schematic cross-sectional view of a vertical structure power device 100. The vertical structure power device 1〇〇 may be a vertical double-diffused metal oxide semiconductor power device (VDMOS) having a planar gate structure. The vertical structure power device 100 can also be other power plants with higher breakdown voltage, lower on-resistance, and larger safe operating area. As shown in Fig. 1, the vertical structure power device 1A includes a type epitaxial layer formed on the N+ type substrate 105, and a gate oxide layer separating the polysilicon gate region 120 from the N- epitaxial layer 110. 115. Vertical Structure Power Device Form No. A0101 Page 5 of 29 0993417350-0 201133826 1〇〇 Also includes a ?_body region 125 formed in an epitaxial layer 11〇, a family source region 130 and a P+ type Body contact region 135. The p_type body region 125 includes at least substantially (eg, within a process tolerance range) an N + -type source region 13 (^〇p + body contact region 135. Further, the vertical structure power device 1 The crucible further includes an isolation sidewall 14 〇, wherein the isolation sidewall 140 is at least substantially aligned between the edges of the polysilicon gate region 2 〇 and the ρ + body contact region 135, and the germanide layer 145 formed thereafter A portion of at least substantially self-aligned with the polysilicon gate region 12 and another portion of the vaporization layer 145 is at least substantially self-aligned to the p+ body contact region 135. As shown in Figure 1, the vertical structure power is set to 1〇〇. Also included is an interlayer dielectric layer (ILD) 150 in contact with the germanide layer 145 and a metal electrode 155, The filled metal electrode 155 is coupled to a portion of the germanide layer 145 located above the germanium + body contact region 135 and is also in contact with the interlayer dielectric layer 15〇, although the first figure uses a cross-sectional schematic view of the vertical structure power. The device 丨〇〇 will be described, but those skilled in the art will appreciate that the components of the vertical structure power device 100 may also form a ring structure. For example, the gate oxide layer 115, the polysilicon gate region 120, and the Ρ-type body region 丨25. The Ν+-type source region 130, a portion of the germanide layer ι45 and the interlayer dielectric layer (ILD) 150 over the polysilicon gate region 12A may form a ring structure (relative to the metal electrode 155 and the ρ + body contact region 135) A portion of the germanide layer 145 above, etc.) In one embodiment 'using the isolation sidewall 140 and the described techniques, the masking process steps required to fabricate the vertical power device 100 can be made less than that required by conventional methods. Masking the process steps and reducing the dependence on the masking tolerance, thereby shortening the length of the Ν + source region, increasing the safety of 0993417350-0 099130674 Form No. Α0101 Page 6 of 2 Page 9 of 201133826.

The vertical structure power device 100 can also have a greater contact to the polycrystalline length (contact-t〇_p〇lysilic〇n length ' LCP) and a smaller N + source length than the device manufactured by the conventional process ( LSC). The greater contact to polysilicon length (LCP) can effectively reduce the dependence of the metal electrode 155 and polysilicon gate region 120 on the process variations of the mask-based alignment process. The smaller source length (LSC) reduces the likelihood that the vertical structure power device will be damaged by parasitic bipolar effects. In the embodiment shown in Figure 1, the shorter source length LSC makes the safe working area approximately three to five times larger than conventionally manufactured devices. For example, using the isolation sidewall 140 and the described techniques can shorten the length of the N+ source region of the fabricated vertical structure power device 1〇〇 to 〇. J micron to 0.3 micron, which is less than the fabrication based on the masking process. The length of the source area of the source '/ increases the safe working area. In addition, the cost of the masking process step 'the manufacturing cost of the vertical structure power device 1' is reduced due to the increased number of self-aligned process steps compared to conventionally fabricated devices.

Can be reduced. Although FIG. 1 only shows a VDMOS device, those skilled in the art will appreciate that the techniques described herein are equally applicable to other devices such as the MOSFET, IGBT, superjunction MOSFET, VDMOS, and VMOS described above. Other planar gate devices, lateral power devices, N-channel devices, P-channel devices, and/or the like. The remaining details of the vertical structure power unit 1 〇 将 will be described in detail below with reference to Figure 2A-2. Fig. 2-2 shows a method of fabricating the vertical structure power device 100 shown in Fig. 1. The second drawing is to form a germanium-epitaxial layer 11 on the germanium + substrate 105, respectively, and a gate oxide layer 115 is formed on the 099130674 form number Α0101 page 7 / 29 page 0993417350-0 201133826 N outer layer 110 And the structure of the vertical structure power device (10) after the polycrystalline (10) region 120 on the gate oxide layer 115 shows that the process of forming the polysilicon gate region 120 can include forming a layer of doping, a masking station. The polycrystalline 7 layer and the engraved #unmasked region. The gate oxide layer 115 can be formed using an oxide layer growth technique and has a thickness such that the vertical structure power device 100 is optimized in the foregoing. For example, for a high breakdown voltage VDM 〇s transistor, the thickness may be between 400 angstroms and 1 000 angstroms. However, those skilled in the art will appreciate that other processes may be used to form the gate oxide layer 115. At the same time, other suitable dielectric materials may be substituted for the gate oxide layer and/or similar oxide layer. In at least one embodiment, the N- epitaxial layer 110 may have a characteristic based on the breakdown voltage or other suitable standard requirements. The thickness and/or doping concentration. For example, an epitaxial layer having a doping concentration of 1x1014cnT3 and a thickness of 50 microns may be suitable for fabricating a VDMOS device having a breakdown voltage of 700 V. Also, the polycrystalline germanium gate region 120 may be a relatively thick polycrystalline germanium. The layers (e.g., thicknesses from 6,000 angstroms to 100 angstroms angstroms) act to block/self-mask in subsequent ion implantation, diffusion, and/or the like (e.g., implantation to form the tantalum contact regions 135). In one example, the polysilicon gate region 120 has a thickness of about 7000 angstroms. However, those skilled in the art will appreciate that any other suitable thickness or additional layer of material (e.g., as referred to in FIG. 3) may be used. As will be described later, in one embodiment, the initial thickness of the polysilicon gate region 120 is determined by the final thickness required for the polysilicon gate region 12 and the thickness of the polysilicon that is etched away in the germanium etching process described below. And determined ° In one embodiment, in addition to the above described process, you can also choose to form 099130674 Form No. A0101 0993417350-0 Page 8 / Total 29 Page 201133826 Field Gas Zone ( Go to - mountain, not to make (for example, using a masking process) boundary isolation region. For 2 Ν Λ %, in the N-type epitaxial layer 110, optional placement, soft-masking (not * out ), it is possible to reduce the adjacent buckling body position. The resistance of the formed junction field effect transistor (JEFT). 2BFig. + & + M , 俨., ion implantation in the _ epitaxial layer 11〇 A step of forming a p-type = 125. In the ion injection process, the performance of the device can be optimized by selecting N-:, 4吏. For example, when boron ions are implanted into the epitaxial layer 11 ,, the implantation dose can be 2χ1〇13'2 to 8χ.

~ between and its energy is between 20keV and 80keV, and then into: diffusion (for example, the lateral diffusion of the body region 125 to the polycrystalline slab area i Z0 below the real side, to form the vertical power device 100 Conductive sermon). In this example, in order to form a channel having a length of 1.5 μm to 3.0 μm, the temperature at the time of pushing 12 〇 is about U 〇〇 ° C, and the diffusion time is 60 minutes to 120 ° ° as shown in the figure (10). It is shown that the edges of the P_type body region 125 and the polycrystalline spine region are at least substantially self-aligned. The method of the present invention can avoid a special masking step when forming the P~type body region 125. In the illustrated embodiment, the D-type-type region 125 is formed by an ion implantation technique and is self-aligned with the polysilicon gate region 12 (1, however, those skilled in the art should understand that the P~dust region 125 may also be aligned with other components of the power device or by other suitable techniques. As shown in the figure, the N+ source region 130 and the P+ body contact region 135 are subsequently > 2 In the trench layer 110. As shown, both the N+ source region 130 and the P+ body contact region 135 are at least substantially self aligned with the polysilicon gate region 120. In one embodiment, the N+ source region 130 is used. Arsenic ion implantation is formed in which the ion implantation energy is between 100 keV and 15 〇 keV, and the implantation dose is between 2 x 10 cm and 5 x 1 ο 15 cm 2 . In other embodiments, it can also be 099130674. Form number A0101 page 9 / total 29 pages 0993417350-0 201133826 to use other suitable impurity species, implant dose and implant energy. Prior to ion implantation, the gate oxide layer 115 can be thinned to facilitate more dopant injection into the stone material. +type source region 130 and P+ body contact region 135 The diffusion step may simultaneously perform 'or N + -type source region 13 推进 propagating diffusion before ion implantation in the p + -type body contact region 135 (eg, when the n + -type source region 130 is diffused) 'avoiding the P + -type body contact region The diffusion of ι35 also occurs. The ion implantation dose and energy of the P + -type body contact region 135 can be higher (for example, the dose range of boron implantation is lxl0Hcm-2 to 1><1〇16(^-2, energy range) Any other suitable dose and energy may be used between 100 keV and 200 keV. In one embodiment, the implantation dose of the p+ type body contact region ^35 is about lxl 〇 15 cm 2 and the implantation energy is about 15 〇 keV. The high implant dose and energy can have a lower on-resistance of the portion of the P-type body region 25 below the N+ source region 130, thereby expanding the safe working area range as described above. In addition, a higher implant dose And energy can also reduce the reproducibility of lateral diffusion of implanted impurities into the channel, thereby reducing the negative impact on the threshold voltage or other parameters of the power device 100. In other embodiments, the implantation process step of the P+ body contact region 135 can This is done late (for example, after forming the isolation sidewall 145 or after the ruthenium etching process). Such an embodiment will be described in detail below although the 'P-type body regions 125 and P are as shown in Figures 2B and 2C. The +-body contact regions 13 5 are formed separately by separate steps. However, in other embodiments, the P-type body regions 125 and the P + -type body contact regions 135 may be replaced with a reverse-commutated P-plate structure. Next, as shown in FIG. 2D, the process step is to build a dielectric layer on the polycrystalline ridge region 12〇, the hall 099130674, wherein a part of the dielectric layer of the form number A0101 is used to form a page 10/29 0993417350-0 201133826 From the side wall 140. In one embodiment, the isolation sidewalls 140 may be formed from silica, yttrium, and/or other suitable dielectric materials. In addition, the dielectric layer can also serve as a conformal layer. In one embodiment, the thickness of the conformal layer may thereafter determine the width of the isolation sidewall 140 and the N+ source region 130, and may range from 2000 angstroms to 7000 angstroms. However, those skilled in the art will appreciate that the conformal layer can also have other suitable thicknesses. The process step as shown in FIG. 2E is to etch the dielectric layer along the polysilicon gate region 120 to form the isolation spacer 140, wherein the etching should at least cause the isolation sidewall 140 and the edge of the polysilicon gate region 120 to be substantially opposite. quasi. In one embodiment, an anisotropic dielectric etch process can be selected. The anisotropic dielectric etch process has an etch rate to the dielectric that is greater than the etch rate of the ruthenium, such that the polysilicon gate region 120 and the N- epitaxial layer 110 are substantially unaffected during formation of the isolation sidewall 140. influences. During the etching process, a suitable etching time can also be selected to form the isolation sidewall 140 of any suitable height. As shown in Fig. 2E, the height of the isolation sidewall 140 is lower than the top of the polysilicon gate region 120. In the present embodiment, the process steps shown in Fig. 2F will further reduce the thickness of the polysilicon gate region 120 to be substantially flush with the top end of the spacer sidewall 140. As an alternative to the process steps corresponding to FIG. 2C, the P+ type body contact region 135 may be implanted before or after the etching step of FIG. 2E after the dielectric layer deposition process shown in FIG. 2D is completed. In this embodiment, the P+ body contact region 135 can be at least substantially self-aligned with the isolation sidewall 140 without having to be self-aligned with the polysilicon gate region 120. The alternative can increase the lateral spacing between the P+ body contact region 135 and the conductive channel, reducing the negative impact on the threshold voltage and other parameters of the power device 100. 099130674 Form No. A0101 Page 11 of 29 0993417350-0 201133826 The process step shown in Figure 2F is to engrave the polysilicon gate region 1 2 〇 and the N-epitaxial layer 11 0. In the engraving process, the engraving rate for Shi Xi is greater than the etching rate for oxygen 4 such as the first material (or other material forming the isolation spacer 140). As shown in Fig. 2F, the etch of germanium is deep into the N- epitaxial layer 11 〇 such that the N + source 130 and the P + body contact region 135 are exposed. The illustrated trench etch is substantially self-aligned with the isolated sidewall 140. Due to the self-aligned nature of the trench etch, the N + source region length LSC in Figure 1 can be more accurately controlled without being affected by the masking process tolerance. This results in a smaller LSC length and a lesser parasitic transistor effect. 4 As shown in FIG. 2F, the polysilicon gate region 120 may be etched to the same degree as the N-epitaxial layer 110, depending on the relative orientation of the polycrystalline sapphire region 1 20 and the N- epitaxial layer 11 〇. In the present embodiment, the thickness of the previously generated polysilicon layer 120 (corresponding to the polysilicon layer 120 shown in FIG. 2A) may take into account the influence of the etching effect, so that the polycrystalline grid The final thickness required for the region 12 is equal to the difference between the initial thickness of the polysilicon gate region 120 and the thickness of the polycrystalline spine etched away in the germanium etching process described herein. In addition, as shown in the embodiment in FIG. 3, a protective layer may be formed on the multi-b mash gate region 12 , to prevent the polysilicon etch region 12 受到 from being etched in the 矽 etch process, such that the polysilicon The final thickness of the gate region 12A is substantially the same as the initial thickness required for the polymorphic gate region 120. As an alternative to the process steps corresponding to the 2nd C circle, the implantation of the p + -type body contact region 135 may be performed after the 矽 etch process step corresponding to the 2F map, and before the formation of the lithium compound process step corresponding to the 2G map get on. In this embodiment, the P+ body contact region 135 will at least substantially self-align with the isolation sidewall 140 without having to be self-aligned with the polysilicon gate region 12. This alternative enables a greater lateral direction between the P+ body contact region 135 and the conductive channel. 099130674 Form No. A0101 Page 12 of 29, 0993417350-0 201133826

The pitch' thus reduces the negative impact on the threshold electrical μ and other parameters of the power skirt 1(10). In the case of further steps, the injection of the Ρ+-type contact area 135 after cutting the number of arts also has the advantage of reducing the energy requirement of the injection. For example, 'the overlapping of the Ν + source region 130 is removed, so that a portion of the body region 125 can be exposed to the injection of Ρ + material. For example, in the process of injecting the ρ + body contact region 135 through the overlapping Ν + source region 13 所示 shown in Fig. 2C, the ion implantation energy needs to be 1 〇〇 keV to 2 〇〇 keV. In the present embodiment, the ion implantation energy of 2 〇 ke D, j 8 〇 keV can achieve a similar effect. In this embodiment, after injecting the P+ type body contact region 135, rapid thermal annealing (RTA) or other suitable furnace annealing process may be used to initiate P+ impurities and to allow lateral diffusion of impurities under the N+ source region 130. '

Figure 2G shows a j-step of forming a lithiation layer 1^5: the step--the at least substantially parallel to the isolated sidewall 14 is self-aligned. Because the germanide is not formed on the isolation side step 140, the isolation spacer 140 can isolate the portion of the germanide layer 145 above the polysilicon gate region 丨2〇 from the portion of the germanide layer 145 above the P+ body contact region 135. Open. The f-telluride layer 145 also provides a low resistance interconnect between the N + source region 130' > + body contact region 135 and the metal electrode 155 to be formed. In some embodiments, the low resistance interconnect can increase the safe working area and improve switching performance. In one embodiment, the dream compound 14 includes a multilayer structure. For example, the telluride 145 includes titanium telluride having a thickness between 200 angstroms and 6 angstroms and titanium nitride having a thickness between 100 angstroms and 2 angstroms. In the embodiment, the sheet resistance of the telluride layer 145 (the sheet resistance refers to the resistance of the semiconductor material having the same length and width, which is ideally equal to the resistivity of the material divided by the thickness. The electrical conductivity of the semiconductor material is equal to the sheet resistance. Multiply by the number of blocks 099130674 Form No. A0101 Page 13 / 29 pages 0993417350-0 201133826, where the number of blocks is the ratio of the length to the width of the semiconductor material ^ - Generally speaking, the resistivity and thickness of the semiconductor material are fixed, can The resistance value is set by flexibly setting the length and width of the semiconductor material) between approximately 3 Ω/□ and 5 Ω/□ (where the character represents the unit square resistance). The telluride layer 145 in this embodiment can provide about a lower gate resistance than a typical polysilicon gate material having a sheet resistance between 10 □ and 20 Q/μ. However, it will be understood by those skilled in the art that other suitable values and values can be used in other embodiments. The process steps shown in Fig. 2H include deposition, masking, and 'interstitial interlayer 150 to form contact holes for metal electrode 155. The material of the interlayer dielectric layer 15 can be a single material or a composite dielectric material formed using other interlayer dielectric layer processes. For example, the material of the interlayer dielectric layer 150 may be undoped or doped dioxide having a thickness between 1 micrometer and 2 micrometers. Compared with the conventional manufacturing process, the importance of the alignment of the contact hole 矽 矽 gate region 120 in the process of the present embodiment is reduced because the bismuth compound layer 145 is provided to the N+ type source Zen 130 and P + type splicing. Lin 135 low contact resistance. Thereafter, a metallization process step can be performed to form the metal gate 155 in %, thereby completing the vertical structure power device 1 shown in Fig. 1. In one embodiment, achieving metallization can include killing a 2 micron to 5 micron thick alloy of the title, followed by masking and occupational techniques. However, in the technical field: the surgeon should understand that in other implementations, other techniques can also be used. In addition, it is also possible to use a temple, a mask, and a mask to form a passivation layer (not shown). Figure 3 is a diagram of "the material of the vertical structure power device is intended to be compared with the second layer AA, and the a099130674 figure further includes the polysilicon protective layer 305 and oxidation.

The form number is deleted 1 ^ 14 i / # 29 M M 099341 201133826, 蒦 layer 31 〇. In the apparatus shown in Fig. 3, the thickness of the polysilicon gate region 120, which is substantially unchanged in the step of *, is such that the initial thickness at the time of formation can be equal to or close to the final desired thickness. The ruthenium layer 3 〇 5 and the oxide protective layer 31 〇 may be formed of any suitable thickness of nitride, cerium oxide, tantalum nitride, and/or other suitable materials. When the device is fabricated, the polysilicon protective layer 305 protects the oxide protective layer 310 and the polycrystalline gate region 120 from the engraving process as shown in FIG. 2E and the polycrystalline oxide layer 305 can then be used as Part of the 矽0 etching process shown in Figure 2F is removed. The oxide protective layer 31 can also protect the polysilicon gate region 丨2〇 in the germanium etching process shown in Fig. 2F. For example, the germanide protective layer 310 may be composed of a material which can be etched slowly in the germanium etching process shown in Fig. 2F, thereby protecting the polysilicon gate region 12 from strong etching. The oxide protective layer 310 may be removed prior to the depletion process illustrated in the second figure. For example, the oxide protective layer 310 may be etched by selective wet etching, such as hydrofluoric acid etching or any other suitable The process is removed. In one embodiment, the nitride may be used to form the isolation sidewall 140, or an anisotropic etch may be used to remove the oxide protection layer 31 while leaving the isolation sidewall 140 substantially unaffected. In one embodiment, the oxide protective layer 31 is <RTI ID=0.0>"""""""""""""" The method for self-aligning telluride contact and the method of manufacturing the same according to embodiments of the present invention are described in an exemplary manner, and are not intended to limit the scope of the present invention. Variations and modifications are made to the disclosed embodiments. Possible, other feasible 099130674 Form No. A010J No. 5 page / Total 29 page 0993417350-0 201133826 Alternative embodiments and equivalent variations to the elements in the embodiment can be used by the present technology Other variations and modifications of the disclosed embodiments of the present invention are beyond the spirit and scope of the invention. [FIG. Brief Description] [0005] The following drawings relate to the present invention without limitation. The same reference numerals are used throughout the drawings to refer to the same parts in the drawings. The figures are not necessarily drawn to scale. The dimensions of the vertical structure power device in accordance with one embodiment of the present invention are provided for reference for a better understanding of the present invention. 2A-2 is a schematic view showing a process of fabricating a vertical structure power device shown in Fig. 1 according to an embodiment of the present invention. Fig. 3 is another view showing a vertical structure power device according to another embodiment of the present invention. Schematic diagram of process method. [Main component symbol description] [0006] LCP polysilicon length LSC source region length 100 vertical structure power device 1 05 substrate 11 0Ν-type epitaxial layer 115 gate oxide layer 1 2 0 polycrystalline chopping gate region 099130674 Form number Α0101 Page 16 / 29 pages 0993417350-0 201133826 125P-type body region 130N + type source region 135P + body contact region 140 isolation Side wall 14 5 seconds layer 150 interlayer dielectric layer 155 metal electrode 305 polysilicon protective layer 310 oxide protective layer ❹ 0993417350-0 099130674 Form No. A0101 Page 17 of 29

Claims (1)

201133826 VII. Patent application scope: 1. A power device, comprising: an initial layer; a body contact region formed on the initial layer; a gate region, and the initial layer separated by a gate oxide layer; a sidewall spacer aligned between the gate region and an edge of the body contact region; a gate germanide layer formed over the gate region; and a body contact germanide layer formed in the body contact region on. 2. The device of claim 1, further comprising: a metal electrode coupled to the body contact telluride layer; a semiconductor substrate, wherein the initial layer is formed in the An epitaxial layer on a semiconductor substrate; an interlayer dielectric layer in contact with the gate germanide layer, the body contact germanide layer and the metal electrode; a source region formed in the initial layer; The body region formed in the initial layer includes at least the source region and the body contact region. 3. The device of claim 2, wherein the initial layer is an N-type epitaxial layer, the gate region is formed of polysilicon, and the body contact region is a P+ implant region. The body region is a P-type implant region, and the source region is an N + -type implant region. 4. The device of claim 1, wherein the gate region and the gate germanide layer are both annular regions. 099130674 Form No. A0101 Page 18 of 29 0993417350-0 201133826 5 ·=Application of the patent scope of the invention, wherein the isolated spacer is from a cerium oxide conformal layer or a nitride layer Layer. 6. If you apply for a patent scope! The device of the item wherein the device is at least one of an N-channel or P-channel device and has a planar thumb structure. 7. The agricultural device of claim i, wherein the device is at least a metal oxide semiconductor field effect transistor, an insulated gate bipolar transistor, a super junction metal oxide semiconductor field effect transistor, and a vertical A double-diffused metal oxide semiconductor device or a germanium in a vertical structure metal oxide semiconductor device. 8. If you apply for a patent scope! The device of claim 7, wherein the barrier layer is self-aligned to the isolated sidewall, and wherein the body contact region is self-aligned to the isolated sidewall and the body contact region is dosed It is formed by an ion implantation process of lxl016cm 2 and an energy range of 1 〇〇 ke 2 〇〇 keV. 9. A power device comprising: a semiconductor substrate; Q an epitaxial layer on the semiconductor substrate, the epitaxial layer having a first surface, and the interior comprising at least - an individual contact region, a source region, and a body region Wherein the body region includes the body contact region and the source region; a gate region on the first surface, wherein the gate region is separated from the epitaxial layer by a gate dielectric layer; Aligning between the gate region and an edge of the body contact region; a gate silicide layer formed over the gate region; a body contact vaporization layer formed over the body contact region; Lightly connecting the electrodes above the body contacting the layer of debris. 10. The device of claim 9, wherein the gate 099130674 form number A0101 page 19/29 pages 0993417350-0 201133826 region and the gate germanide layer are in the body contact region Around the production 11 12 13 14 . 15 . 16 . 17 . 18 . 19 . 099130674 clothing v'cr structure. The device of claim 9, wherein the device is a vertical double-diffused metal oxide semiconductor device having a planar gate and structure, such as the device of claim 9 of the patent application, characterized in that The isolation sidewall is derived from a ceria conformal layer or a tantalum nitride conformal layer, and the gate chelate layer and the bulk contact chelate layer are self-aligned to the spacer sidewall. The device of claim 9, wherein the body contact region is self-aligned to the edge of the gate region and/or the spacer sidewall. The device of claim 9, wherein there is a channel in the epitaxial layer, the channel extending perpendicularly from the first surface into the epitaxial layer 'the channel The depth is greater than the depth of the source region and the 'transverse portion of the channel is self-aligned to the isolated sidewall. The device of claim 14, wherein the body contact hairsing layer is located at the -4 end of the channel opposite to the first surface, as in the device of claim 14 of the patent application, It is characterized in that the side walls of the two channels and the source region are adjacent to each other and that the body contact werews make electrical contact with a portion of the source region exposed. The device of claim 16, wherein the source region is self-aligned between the edge of the gate H and the edge of the channel. The device of claim U, which is characterized in that the contact area is self-contained at the edge of the side wall of the channel region. A method of fabricating a power device, comprising: '' fabricating an epitaxial layer on a substrate; forming a gate oxide layer on the epitaxial layer; Form No. A0101 Page 20 of 29 0993417350-0 201133826 Ο ❹ 1 Forming a polycrystalline germanium gate region on the oxygen layer; : separating the isolated sidewall spacer from self-aligned to the plurality of steps: one step in (c) or forming a layer of the dazzling layer on the polycrystalline germanium gate region and the epitaxial layer Self-aligning to the isolated sidewall; s, (b) forming a body contact zone in the exposed layer; Performing (4) in the delamination layer, the method described in claim 19, wherein the isolation sidewall comprises: depositing a dioxide dioxide layer or Gasifying the hair-protecting layer; and engraving the (4) layered money from the side wall, the side wall being aligned with the edge of the polycrystalline grid region. The method of claim 19, wherein the method comprises at least forming the lithiation layer 'and the method further comprises: j, at the telluride layer and Depositing an interlayer dielectric layer on the isolation sidewall; etching the deposited interlayer dielectric layer to expose at least a portion of the vaporization layer on the epitaxial layer; and forming an electrode, wherein An electrode is in contact with the exposed portion of the litchi layer. The method of claim 19, wherein the method comprises at least implanting the body contact region, and the method further comprises: performing ion implantation on the epitaxial layer to form Body region, the body region self-aligned form number A0101 » 〇! _ n〇Qf 20 21 on 099130674 page 21 / 29 pages 0993417350-0 201133826 in the polycrystalline stone slab region; The layer is ion implanted to form a source region that is self-aligned to the polysilicon gate region, and the body region includes the body contact region and the source region. The method of claim 22, wherein the method comprises implanting the body contact region such that the body contact region is vertically below the source region. The method of claim 19, wherein the method comprises at least engraving in the epitaxial layer, and the method further comprises: performing etching in the epitaxial layer The implant is then formed to form the body contact region. The method of claim 19, wherein the method comprises at least implanting the body contact region, and the method further comprises: injecting before forming the isolated sidewall The body contact region is formed such that the body contact region is self-aligned to the polysilicon gate region. The method of claim 19, wherein the method comprises at least implanting the body contact region, and the method further comprises: injecting after forming the isolated sidewall The body contact region is formed such that the body contact region is self-aligned to the isolated sidewall spacer. The method of claim 19, wherein the method comprises at least forming the telluride layer and etching in the epitaxial layer, and the method further comprises: After performing etching in the epitaxial layer, forming the germanide layer; and forming a source region, wherein the germanide layer on the epitaxial layer is etched to form 099130674 Form No. A0101 Page 22 / 29 Page 0993417350- 0 201133826 28 . 29 . The bottom of the channel and in contact with the isolated sidewall in the channel. The method of claim 19, wherein the method comprises at least engraving in the epitaxial layer, wherein the method further comprises: forming an oxide protective layer on the polysilicon gate region When performing epitaxial layer etching, the protective layer can at least partially protect the polysilicon gate region. The method of claim 28, wherein the method further comprises: forming a polysilicon protective layer on the oxide protective layer, wherein the polysilicon protective layer at least partially protects the polysilicon when etching the isolated sidewall spacer a gate region; and removing the polysilicon protective layer while performing epitaxial layer etching. ο 099130674 Form number Α0101 Page 23 of 29 0993417350-0